X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fmips%2Fbearch_mips.c;h=62b946b8f649b179ef673b33c1453ce8e44c1f1c;hb=39cb52264857d7c21c7141ba82bb55adaa78064d;hp=8ef88ef2e38fa55140f3913a747b77f1d1e3fa4f;hpb=816e7e0779021990465292820aa997d2af768c72;p=libfirm diff --git a/ir/be/mips/bearch_mips.c b/ir/be/mips/bearch_mips.c index 8ef88ef2e..62b946b8f 100644 --- a/ir/be/mips/bearch_mips.c +++ b/ir/be/mips/bearch_mips.c @@ -23,9 +23,7 @@ * @author Matthias Braun, Mehdi * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif #include "pseudo_irg.h" #include "irgwalk.h" @@ -44,10 +42,12 @@ #include "bitset.h" #include "debug.h" -#include "../bearch_t.h" -#include "../benode_t.h" +#include "../bearch.h" +#include "../benode.h" #include "../belower.h" -#include "../besched_t.h" +#include "../besched.h" +#include "../beblocksched.h" +#include "../beirg.h" #include "be.h" #include "../beabi.h" #include "../bemachine.h" @@ -82,139 +82,12 @@ static set *cur_reg_set = NULL; * |___/ **************************************************/ -/** - * Return register requirements for a mips node. - * If the node returns a tuple (mode_T) then the proj's - * will be asked for this information. - */ -static const -arch_register_req_t *mips_get_irn_reg_req(const void *self, - const ir_node *node, int pos) -{ - long node_pos = pos == -1 ? 0 : pos; - ir_mode *mode = get_irn_mode(node); - (void) self; - - if (is_Block(node) || mode == mode_X || mode == mode_M) { - return arch_no_register_req; - } - - if (mode == mode_T && pos < 0) { - return arch_no_register_req; - } - - if (is_Proj(node)) { - /* in case of a proj, we need to get the correct OUT slot */ - /* of the node corresponding to the proj number */ - if (pos == -1) { - node_pos = mips_translate_proj_pos(node); - } - else { - node_pos = pos; - } - - node = skip_Proj_const(node); - } - - /* get requirements for our own nodes */ - if (is_mips_irn(node)) { - const arch_register_req_t *req; - if (pos >= 0) { - req = get_mips_in_req(node, pos); - } else { - req = get_mips_out_req(node, node_pos); - } - - return req; - } - - /* unknown should be translated by now */ - assert(!is_Unknown(node)); - - return arch_no_register_req; -} - -static void mips_set_irn_reg(const void *self, ir_node *irn, - const arch_register_t *reg) -{ - int pos = 0; - (void) self; - - if (is_Proj(irn)) { - - if (get_irn_mode(irn) == mode_X) { - return; - } - - pos = mips_translate_proj_pos(irn); - irn = skip_Proj(irn); - } - - if (is_mips_irn(irn)) { - const arch_register_t **slots; - - slots = get_mips_slots(irn); - slots[pos] = reg; - } else { - /* here we set the registers for the Phi nodes */ - mips_set_firm_reg(irn, reg, cur_reg_set); - } -} - -static const arch_register_t *mips_get_irn_reg(const void *self, - const ir_node *irn) -{ - int pos = 0; - const arch_register_t *reg = NULL; - (void) self; - - if (is_Proj(irn)) { - - if (get_irn_mode(irn) == mode_X) { - return NULL; - } - - pos = mips_translate_proj_pos(irn); - irn = skip_Proj_const(irn); - } - - if (is_mips_irn(irn)) { - const arch_register_t **slots; - slots = get_mips_slots(irn); - reg = slots[pos]; - } - else { - reg = mips_get_firm_reg(irn, cur_reg_set); - } - - return reg; -} - -static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) +static arch_irn_class_t mips_classify(const ir_node *irn) { - (void) self; - irn = skip_Proj_const(irn); - - if (is_cfop(irn)) { - return arch_irn_class_branch; - } else if (is_mips_irn(irn)) { - return arch_irn_class_normal; - } - + (void) irn; return 0; } -static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) -{ - (void) self; - irn = skip_Proj_const(irn); - - if (!is_mips_irn(irn)) - return 0; - - return get_mips_flags(irn); -} - int mips_is_Load(const ir_node *node) { return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) || @@ -226,10 +99,9 @@ int mips_is_Store(const ir_node *node) return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node); } -static ir_entity *mips_get_frame_entity(const void *self, const ir_node *node) +static ir_entity *mips_get_frame_entity(const ir_node *node) { const mips_load_store_attr_t *attr; - (void) self; if(!is_mips_irn(node)) return NULL; @@ -240,17 +112,15 @@ static ir_entity *mips_get_frame_entity(const void *self, const ir_node *node) return attr->stack_entity; } -static void mips_set_frame_entity(const void *self, ir_node *node, - ir_entity *entity) +static void mips_set_frame_entity(ir_node *node, ir_entity *entity) { mips_load_store_attr_t *attr; - (void) self; if(!is_mips_irn(node)) { - panic("trying to set frame entity on non load/store node %+F\n", node); + panic("trying to set frame entity on non load/store node %+F", node); } if(!mips_is_Load(node) && !mips_is_Store(node)) { - panic("trying to set frame entity on non load/store node %+F\n", node); + panic("trying to set frame entity on non load/store node %+F", node); } attr = get_irn_generic_attr(node); @@ -261,16 +131,15 @@ static void mips_set_frame_entity(const void *self, ir_node *node, * This function is called by the generic backend to correct offsets for * nodes accessing the stack. */ -static void mips_set_frame_offset(const void *self, ir_node *node, int offset) +static void mips_set_frame_offset(ir_node *node, int offset) { mips_load_store_attr_t *attr; - (void) self; if(!is_mips_irn(node)) { - panic("trying to set frame offset on non load/store node %+F\n", node); + panic("trying to set frame offset on non load/store node %+F", node); } if(!mips_is_Load(node) && !mips_is_Store(node)) { - panic("trying to set frame offset on non load/store node %+F\n", node); + panic("trying to set frame offset on non load/store node %+F", node); } attr = get_irn_generic_attr(node); @@ -281,21 +150,18 @@ static void mips_set_frame_offset(const void *self, ir_node *node, int offset) } } -static int mips_get_sp_bias(const void *self, const ir_node *irn) +static int mips_get_sp_bias(const ir_node *irn) { - (void) self; (void) irn; return 0; } /* fill register allocator interface */ -static const arch_irn_ops_if_t mips_irn_ops_if = { - mips_get_irn_reg_req, - mips_set_irn_reg, - mips_get_irn_reg, +static const arch_irn_ops_t mips_irn_ops = { + get_mips_in_req, + get_mips_out_req, mips_classify, - mips_get_flags, mips_get_frame_entity, mips_set_frame_entity, mips_set_frame_offset, @@ -306,13 +172,6 @@ static const arch_irn_ops_if_t mips_irn_ops_if = { NULL, /* perform_memory_operand */ }; -mips_irn_ops_t mips_irn_ops = { - &mips_irn_ops_if, - NULL -}; - - - /************************************************** * _ _ __ * | | (_)/ _| @@ -324,174 +183,35 @@ mips_irn_ops_t mips_irn_ops = { * |___/ **************************************************/ - -typedef struct { - ir_node *start; - ir_node *end; - unsigned cnt; -} anchor; - -/** - * Ext-Block walker: create a block schedule - */ -static void create_block_list(ir_extblk *blk, void *env) { - anchor *list = env; - int i, n; - - for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) { - ir_node *block = get_extbb_block(blk, i); - - set_irn_link(block, NULL); - if (list->start) - set_irn_link(list->end, block); - else - list->start = block; - - list->end = block; - list->cnt += 1; - } -} - -/* return the scheduled block at position pos */ -ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) { - if (0 <= pos && pos < ARR_LEN(cg->bl_list)) - return cg->bl_list[pos]; - return NULL; -} - -/* return the number of scheduled blocks */ -int mips_get_sched_n_blocks(const mips_code_gen_t *cg) { - return ARR_LEN(cg->bl_list); -} - -/* set a block schedule number */ -void mips_set_block_sched_nr(ir_node *block, int nr) { - set_irn_link(block, INT_TO_PTR(nr)); -} - -/* get a block schedule number */ -int mips_get_block_sched_nr(ir_node *block) { - return PTR_TO_INT(get_irn_link(block)); -} - -/** - * Creates a block schedule for the given graph. - */ -static void mips_create_block_sched(mips_code_gen_t *cg) { - anchor list; - ir_node **bl_list, *block; - unsigned i; - - if (cg->bl_list) { - DEL_ARR_F(cg->bl_list); - free_survive_dce(cg->bl_list_sdce); - } - - /* calculate the block schedule here */ - compute_extbb(cg->irg); - - list.start = NULL; - list.end = NULL; - list.cnt = 0; - irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list); - - - bl_list = NEW_ARR_F(ir_node *, list.cnt); - cg->bl_list_sdce = new_survive_dce(); - for (i = 0, block = list.start; block; block = get_irn_link(block)) { - bl_list[i] = block; - survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]); - i++; - } - - cg->bl_list = bl_list; -} - -#if 0 -typedef struct _wenv_t { - ir_node *list; -} wenv_t; - -/** - * Walker: link all CopyB nodes - */ -static void collect_copyb_nodes(ir_node *node, void *env) { - wenv_t *wenv = env; - - if (get_irn_op(node) == op_CopyB) { - set_irn_link(node, wenv->list); - wenv->list = node; - } -} -#endif - -static void replace_copyb_nodes(mips_code_gen_t *cg) { -#if 0 - wenv_t env; - ir_node *copy, *next; - ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem; - const ir_edge_t *edge; - - /* build code for all copyB */ - env.list = NULL; - irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env); - - for (copy = env.list; copy; copy = next) { - next = get_irn_link(copy); - - old_bl = get_nodes_block(copy); - part_block(copy); - jmp = get_Block_cfgpred(old_bl, 0); - new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy)); - - new_bl = new_r_Block(cg->irg, 1, &new_jmp); - set_nodes_block(jmp, new_bl); - - mem = gen_code_for_CopyB(new_bl, copy); - - /* fix copyB's out edges */ - foreach_out_edge(copy, edge) { - ir_node *succ = get_edge_src_irn(edge); - - assert(is_Proj(succ)); - switch (get_Proj_proj(succ)) { - case pn_CopyB_M_regular: - case pn_CopyB_M_except: - exchange(succ, mem); - break; - default: - exchange(succ, get_irg_bad(cg->irg)); - } - } - } -#endif - (void) cg; -} - /** * Transforms the standard firm graph into * a mips firm graph */ static void mips_prepare_graph(void *self) { mips_code_gen_t *cg = self; - int bl_nr, n; - - // replace all copyb nodes in the block with a loop - // and mips store/load nodes - replace_copyb_nodes(cg); - // Calculate block schedule - mips_create_block_sched(cg); + /* do local optimizations */ + optimize_graph_df(cg->irg); - /* enter the block number into every blocks link field */ - for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) { - ir_node *bl = mips_get_sched_block(cg, bl_nr); - mips_set_block_sched_nr(bl, bl_nr); - } + /* TODO: we often have dead code reachable through out-edges here. So for + * now we rebuild edges (as we need correct user count for code selection) + */ +#if 1 + edges_deactivate(cg->irg); + edges_activate(cg->irg); +#endif // walk the graph and transform firm nodes into mips nodes where possible mips_transform_graph(cg); dump_ir_block_graph_sched(cg->irg, "-transformed"); + + /* do local optimizations (mainly CSE) */ + optimize_graph_df(cg->irg); + + /* do code placement, to optimize the position of constants */ + place_code(cg->irg); + + be_dump(cg->irg, "-place", dump_ir_block_graph_sched); } /** @@ -501,18 +221,14 @@ static void mips_finish_irg(void *self) { mips_code_gen_t *cg = self; ir_graph *irg = cg->irg; + /* create block schedule, this also removes empty blocks which might + * produce critical edges */ + cg->block_schedule = be_create_block_schedule(irg, cg->birg->exec_freq); + dump_ir_block_graph_sched(irg, "-mips-finished"); } -/** - * These are some hooks which must be filled but are probably not needed. - */ -static void mips_before_sched(void *self) -{ - (void) self; -} - static void mips_before_ra(void *self) { (void) self; @@ -541,10 +257,6 @@ static void mips_emit_and_done(void *self) /* de-allocate code generator */ del_set(cg->reg_set); - if (cg->bl_list) { - DEL_ARR_F(cg->bl_list); - free_survive_dce(cg->bl_list_sdce); - } free(cg); } @@ -556,7 +268,6 @@ static const arch_code_generator_if_t mips_code_gen_if = { NULL, /* before abi introduce */ mips_prepare_graph, NULL, /* spill */ - mips_before_sched, /* before scheduling hook */ mips_before_ra, /* before register allocation hook */ mips_after_ra, mips_finish_irg, @@ -569,21 +280,17 @@ static const arch_code_generator_if_t mips_code_gen_if = { static void *mips_cg_init(be_irg_t *birg) { const arch_env_t *arch_env = be_get_birg_arch_env(birg); - mips_isa_t *isa = (mips_isa_t *) arch_env->isa; - mips_code_gen_t *cg = xmalloc(sizeof(*cg)); + mips_isa_t *isa = (mips_isa_t *) arch_env; + mips_code_gen_t *cg = XMALLOCZ(mips_code_gen_t); cg->impl = &mips_code_gen_if; cg->irg = be_get_birg_irg(birg); cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024); - cg->arch_env = arch_env; cg->isa = isa; cg->birg = birg; - cg->bl_list = NULL; cur_reg_set = cg->reg_set; - mips_irn_ops.cg = cg; - isa->cg = cg; return (arch_code_generator_t *)cg; @@ -605,8 +312,9 @@ static mips_isa_t mips_isa_template = { &mips_isa_if, &mips_gp_regs[REG_SP], &mips_gp_regs[REG_FP], + &mips_reg_classes[CLASS_mips_gp], -1, /* stack direction */ - 1, /* stack alignment for calls */ + 2, /* power of two stack alignment for calls, 2^2 == 4 */ NULL, /* main environment */ 7, /* spill costs */ 5, /* reload costs */ @@ -617,7 +325,7 @@ static mips_isa_t mips_isa_template = { /** * Initializes the backend ISA and opens the output file. */ -static void *mips_init(FILE *file_handle) { +static arch_env_t *mips_init(FILE *file_handle) { static int inited = 0; mips_isa_t *isa; @@ -625,13 +333,13 @@ static void *mips_init(FILE *file_handle) { return NULL; inited = 1; - isa = xcalloc(1, sizeof(isa[0])); + isa = XMALLOC(mips_isa_t); memcpy(isa, &mips_isa_template, sizeof(isa[0])); be_emit_init(file_handle); mips_register_init(); - mips_create_opcodes(); + mips_create_opcodes(&mips_irn_ops); // mips_init_opcode_transforms(); /* we mark referenced global entities, so we can only emit those which @@ -640,7 +348,7 @@ static void *mips_init(FILE *file_handle) { */ inc_master_type_visited(); - return isa; + return &isa->arch_env; } /** @@ -650,22 +358,19 @@ static void mips_done(void *self) { mips_isa_t *isa = self; - be_gas_emit_decls(isa->arch_isa.main_env, 1); + be_gas_emit_decls(isa->arch_env.main_env, 1); be_emit_exit(); free(isa); } -static unsigned mips_get_n_reg_class(const void *self) +static unsigned mips_get_n_reg_class(void) { - (void) self; return N_CLASSES; } -static const arch_register_class_t *mips_get_reg_class(const void *self, - unsigned i) +static const arch_register_class_t *mips_get_reg_class(unsigned i) { - (void) self; assert(i < N_CLASSES); return &mips_reg_classes[i]; } @@ -678,10 +383,8 @@ static const arch_register_class_t *mips_get_reg_class(const void *self, * @param mode The mode in question. * @return A register class which can hold values of the given mode. */ -const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, - const ir_mode *mode) +const arch_register_class_t *mips_get_reg_class_for_mode(const ir_mode *mode) { - (void) self; (void) mode; ASSERT_NO_FLOAT(mode); return &mips_reg_classes[CLASS_mips_gp]; @@ -689,7 +392,6 @@ const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, typedef struct { be_abi_call_flags_bits_t flags; - const arch_isa_t *isa; const arch_env_t *arch_env; ir_graph *irg; // do special handling to support debuggers @@ -698,34 +400,27 @@ typedef struct { static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg) { - mips_abi_env_t *env = xmalloc(sizeof(env[0])); + mips_abi_env_t *env = XMALLOC(mips_abi_env_t); be_abi_call_flags_t fl = be_abi_call_get_flags(call); env->flags = fl.bits; env->irg = irg; env->arch_env = arch_env; - env->isa = arch_env->isa; env->debug = 1; return env; } -static void mips_abi_dont_save_regs(void *self, pset *s) -{ - mips_abi_env_t *env = self; - - if(env->flags.try_omit_fp) - pset_insert_ptr(s, env->isa->bp); -} - -static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map) +static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map, int *stack_bias) { mips_abi_env_t *env = self; ir_graph *irg = env->irg; - ir_node *block = get_irg_start_block(env->irg); + ir_node *block = get_irg_start_block(irg); ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]); ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); int initialstackframesize; - if(env->debug) { + (void) stack_bias; + + if (env->debug) { /* * The calling conventions wants a stack frame of at least 24bytes size with * a0-a3 saved in offset 0-12 @@ -737,16 +432,16 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap initialstackframesize = 24; // - setup first part of stackframe - sp = new_rd_mips_addu(NULL, irg, block, sp, + sp = new_bd_mips_addu(NULL, block, sp, mips_create_Immediate(initialstackframesize)); - mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]); - set_mips_flags(sp, arch_irn_flags_ignore); + arch_set_irn_register(sp, &mips_gp_regs[REG_SP]); + panic("FIXME Use IncSP or set register requirement with ignore"); /* TODO: where to get an edge with a0-a3 int i; for(i = 0; i < 4; ++i) { ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]); - ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T); + ir_node *store = new_bd_mips_store_r(dbg, block, *mem, sp, reg, mode_T); attr = get_mips_attr(store); attr->load_store_mode = mode_Iu; attr->tv = new_tarval_from_long(i * 4, mode_Is); @@ -756,41 +451,41 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap */ reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); - store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 16); + store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 16); mm[4] = store; reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]); - store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 20); + store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 20); mm[5] = store; /* Note: ideally we would route these mem edges directly towards the * epilogue, but this is currently not supported so we sync all mems * together */ - sync = new_r_Sync(irg, block, 2, mm+4); + sync = new_r_Sync(block, 2, mm+4); *mem = sync; } else { ir_node *reg, *store; initialstackframesize = 4; // save old framepointer - sp = new_rd_mips_addu(NULL, irg, block, sp, + sp = new_bd_mips_addu(NULL, block, sp, mips_create_Immediate(-initialstackframesize)); - mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]); - set_mips_flags(sp, arch_irn_flags_ignore); + arch_set_irn_register(sp, &mips_gp_regs[REG_SP]); + panic("FIXME Use IncSP or set register requirement with ignore"); reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); - store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 0); + store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 0); *mem = store; } // setup framepointer - fp = new_rd_mips_addu(NULL, irg, block, sp, + fp = new_bd_mips_addu(NULL, block, sp, mips_create_Immediate(-initialstackframesize)); - mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]); - set_mips_flags(fp, arch_irn_flags_ignore); + arch_set_irn_register(fp, &mips_gp_regs[REG_FP]); + panic("FIXME Use IncSP or set register requirement with ignore"); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp); @@ -802,7 +497,6 @@ static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *r { mips_abi_env_t *env = self; - ir_graph *irg = env->irg; ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]); ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); ir_node *load; @@ -810,18 +504,18 @@ static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *r int fp_save_offset = env->debug ? 16 : 0; // copy fp to sp - sp = new_rd_mips_or(NULL, irg, block, fp, mips_create_zero()); - mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]); - set_mips_flags(sp, arch_irn_flags_ignore); + sp = new_bd_mips_or(NULL, block, fp, mips_create_zero()); + arch_set_irn_register(sp, &mips_gp_regs[REG_SP]); + panic("FIXME Use be_Copy or set register requirement with ignore"); // 1. restore fp - load = new_rd_mips_lw(NULL, irg, block, sp, *mem, NULL, + load = new_bd_mips_lw(NULL, block, sp, *mem, NULL, fp_save_offset - initial_frame_size); - set_mips_flags(load, arch_irn_flags_ignore); + panic("FIXME register requirement with ignore"); - fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res); - *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M); - arch_set_irn_register(env->arch_env, fp, &mips_gp_regs[REG_FP]); + fp = new_r_Proj(block, load, mode_Iu, pn_mips_lw_res); + *mem = new_r_Proj(block, load, mode_Iu, pn_mips_lw_M); + arch_set_irn_register(fp, &mips_gp_regs[REG_FP]); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp); @@ -879,7 +573,6 @@ static const be_abi_callbacks_t mips_abi_callbacks = { mips_abi_init, free, mips_abi_get_between_type, - mips_abi_dont_save_regs, mips_abi_prologue, mips_abi_epilogue, }; @@ -914,7 +607,7 @@ static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks); /* collect the mode for each type */ - modes = alloca(n * sizeof(modes[0])); + modes = ALLOCAN(ir_mode*, n); for (i = 0; i < n; i++) { tp = get_method_param_type(method_type, i); modes[i] = get_type_mode(tp); @@ -947,24 +640,6 @@ static void mips_get_call_abi(const void *self, ir_type *method_type, } } -static const void *mips_get_irn_ops(const arch_irn_handler_t *self, - const ir_node *irn) -{ - (void) self; - (void) irn; - return &mips_irn_ops; -} - -const arch_irn_handler_t mips_irn_handler = { - mips_get_irn_ops -}; - -const arch_irn_handler_t *mips_get_irn_handler(const void *self) -{ - (void) self; - return &mips_irn_handler; -} - /** * Initializes the code generator interface. */ @@ -977,30 +652,25 @@ static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) /** * Returns the necessary byte alignment for storing a register of given class. */ -static int mips_get_reg_class_alignment(const void *self, - const arch_register_class_t *cls) +static int mips_get_reg_class_alignment(const arch_register_class_t *cls) { ir_mode *mode = arch_register_class_mode(cls); - (void) self; return get_mode_size_bytes(mode); } static const be_execution_unit_t ***mips_get_allowed_execution_units( - const void *self, const ir_node *irn) + const ir_node *irn) { - (void) self; (void) irn; /* TODO */ - assert(0); - return NULL; + panic("Unimplemented mips_get_allowed_execution_units()"); } static const be_machine_t *mips_get_machine(const void *self) { (void) self; /* TODO */ - assert(0); - return NULL; + panic("Unimplemented mips_get_machine()"); } /** @@ -1020,24 +690,40 @@ static const backend_params *mips_get_libfirm_params(void) { static backend_params p = { 1, /* need dword lowering */ 0, /* don't support inline assembler yet */ - NULL, /* no additional opcodes */ NULL, /* will be set later */ NULL, /* but yet no creator function */ NULL, /* context for create_intrinsic_fkt */ NULL, /* no if conversion settings */ + NULL, /* float arithmetic mode (TODO) */ + 0, /* no trampoline support: size 0 */ + 0, /* no trampoline support: align 0 */ + NULL, /* no trampoline support: no trampoline builder */ + 4 /* alignment of stack parameter */ }; return &p; } +static asm_constraint_flags_t mips_parse_asm_constraint(const char **c) +{ + (void) c; + return ASM_CONSTRAINT_FLAG_INVALID; +} + +static int mips_is_valid_clobber(const char *clobber) +{ + (void) clobber; + return 0; +} + const arch_isa_if_t mips_isa_if = { mips_init, mips_done, + NULL, /* handle intrinsics */ mips_get_n_reg_class, mips_get_reg_class, mips_get_reg_class_for_mode, mips_get_call_abi, - mips_get_irn_handler, mips_get_code_generator_if, mips_get_list_sched_selector, mips_get_ilp_sched_selector, @@ -1046,6 +732,9 @@ const arch_isa_if_t mips_isa_if = { mips_get_allowed_execution_units, mips_get_machine, mips_get_irg_list, + NULL, /* mark remat */ + mips_parse_asm_constraint, + mips_is_valid_clobber }; void be_init_arch_mips(void)