X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fmips%2Fbearch_mips.c;h=62b946b8f649b179ef673b33c1453ce8e44c1f1c;hb=39cb52264857d7c21c7141ba82bb55adaa78064d;hp=52dd52a187ccefa98f5b58ca5de99e5985b31b28;hpb=e07b61c6ed5d198a484761f8a40a4f26520d964d;p=libfirm diff --git a/ir/be/mips/bearch_mips.c b/ir/be/mips/bearch_mips.c index 52dd52a18..62b946b8f 100644 --- a/ir/be/mips/bearch_mips.c +++ b/ir/be/mips/bearch_mips.c @@ -23,9 +23,7 @@ * @author Matthias Braun, Mehdi * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif #include "pseudo_irg.h" #include "irgwalk.h" @@ -44,12 +42,12 @@ #include "bitset.h" #include "debug.h" -#include "../bearch_t.h" -#include "../benode_t.h" +#include "../bearch.h" +#include "../benode.h" #include "../belower.h" -#include "../besched_t.h" +#include "../besched.h" #include "../beblocksched.h" -#include "../beirg_t.h" +#include "../beirg.h" #include "be.h" #include "../beabi.h" #include "../bemachine.h" @@ -84,131 +82,12 @@ static set *cur_reg_set = NULL; * |___/ **************************************************/ -/** - * Return register requirements for a mips node. - * If the node returns a tuple (mode_T) then the proj's - * will be asked for this information. - */ -static const -arch_register_req_t *mips_get_irn_reg_req(const ir_node *node, int pos) -{ - long node_pos = pos == -1 ? 0 : pos; - ir_mode *mode = get_irn_mode(node); - - if (is_Block(node) || mode == mode_X || mode == mode_M) { - return arch_no_register_req; - } - - if (mode == mode_T && pos < 0) { - return arch_no_register_req; - } - - if (is_Proj(node)) { - /* in case of a proj, we need to get the correct OUT slot */ - /* of the node corresponding to the proj number */ - if (pos == -1) { - node_pos = mips_translate_proj_pos(node); - } - else { - node_pos = pos; - } - - node = skip_Proj_const(node); - } - - /* get requirements for our own nodes */ - if (is_mips_irn(node)) { - const arch_register_req_t *req; - if (pos >= 0) { - req = get_mips_in_req(node, pos); - } else { - req = get_mips_out_req(node, node_pos); - } - - return req; - } - - /* unknown should be translated by now */ - assert(!is_Unknown(node)); - - return arch_no_register_req; -} - -static void mips_set_irn_reg(ir_node *irn, const arch_register_t *reg) -{ - int pos = 0; - - if (is_Proj(irn)) { - - if (get_irn_mode(irn) == mode_X) { - return; - } - - pos = mips_translate_proj_pos(irn); - irn = skip_Proj(irn); - } - - if (is_mips_irn(irn)) { - const arch_register_t **slots; - - slots = get_mips_slots(irn); - slots[pos] = reg; - } else { - /* here we set the registers for the Phi nodes */ - mips_set_firm_reg(irn, reg, cur_reg_set); - } -} - -static const arch_register_t *mips_get_irn_reg(const ir_node *irn) -{ - int pos = 0; - const arch_register_t *reg = NULL; - - if (is_Proj(irn)) { - - if (get_irn_mode(irn) == mode_X) { - return NULL; - } - - pos = mips_translate_proj_pos(irn); - irn = skip_Proj_const(irn); - } - - if (is_mips_irn(irn)) { - const arch_register_t **slots; - slots = get_mips_slots(irn); - reg = slots[pos]; - } - else { - reg = mips_get_firm_reg(irn, cur_reg_set); - } - - return reg; -} - static arch_irn_class_t mips_classify(const ir_node *irn) { - irn = skip_Proj_const(irn); - - if (is_cfop(irn)) { - return arch_irn_class_branch; - } else if (is_mips_irn(irn)) { - return arch_irn_class_normal; - } - + (void) irn; return 0; } -static arch_irn_flags_t mips_get_flags(const ir_node *irn) -{ - irn = skip_Proj_const(irn); - - if (!is_mips_irn(irn)) - return 0; - - return get_mips_flags(irn); -} - int mips_is_Load(const ir_node *node) { return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) || @@ -280,11 +159,9 @@ static int mips_get_sp_bias(const ir_node *irn) /* fill register allocator interface */ static const arch_irn_ops_t mips_irn_ops = { - mips_get_irn_reg_req, - mips_set_irn_reg, - mips_get_irn_reg, + get_mips_in_req, + get_mips_out_req, mips_classify, - mips_get_flags, mips_get_frame_entity, mips_set_frame_entity, mips_set_frame_offset, @@ -352,14 +229,6 @@ static void mips_finish_irg(void *self) { } -/** - * These are some hooks which must be filled but are probably not needed. - */ -static void mips_before_sched(void *self) -{ - (void) self; -} - static void mips_before_ra(void *self) { (void) self; @@ -399,7 +268,6 @@ static const arch_code_generator_if_t mips_code_gen_if = { NULL, /* before abi introduce */ mips_prepare_graph, NULL, /* spill */ - mips_before_sched, /* before scheduling hook */ mips_before_ra, /* before register allocation hook */ mips_after_ra, mips_finish_irg, @@ -418,7 +286,6 @@ static void *mips_cg_init(be_irg_t *birg) cg->impl = &mips_code_gen_if; cg->irg = be_get_birg_irg(birg); cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024); - cg->arch_env = arch_env; cg->isa = isa; cg->birg = birg; @@ -445,6 +312,7 @@ static mips_isa_t mips_isa_template = { &mips_isa_if, &mips_gp_regs[REG_SP], &mips_gp_regs[REG_FP], + &mips_reg_classes[CLASS_mips_gp], -1, /* stack direction */ 2, /* power of two stack alignment for calls, 2^2 == 4 */ NULL, /* main environment */ @@ -496,16 +364,13 @@ static void mips_done(void *self) free(isa); } -static unsigned mips_get_n_reg_class(const void *self) +static unsigned mips_get_n_reg_class(void) { - (void) self; return N_CLASSES; } -static const arch_register_class_t *mips_get_reg_class(const void *self, - unsigned i) +static const arch_register_class_t *mips_get_reg_class(unsigned i) { - (void) self; assert(i < N_CLASSES); return &mips_reg_classes[i]; } @@ -518,10 +383,8 @@ static const arch_register_class_t *mips_get_reg_class(const void *self, * @param mode The mode in question. * @return A register class which can hold values of the given mode. */ -const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, - const ir_mode *mode) +const arch_register_class_t *mips_get_reg_class_for_mode(const ir_mode *mode) { - (void) self; (void) mode; ASSERT_NO_FLOAT(mode); return &mips_reg_classes[CLASS_mips_gp]; @@ -546,19 +409,11 @@ static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env return env; } -static void mips_abi_dont_save_regs(void *self, pset *s) -{ - mips_abi_env_t *env = self; - - if(env->flags.try_omit_fp) - pset_insert_ptr(s, env->arch_env->bp); -} - static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map, int *stack_bias) { mips_abi_env_t *env = self; ir_graph *irg = env->irg; - ir_node *block = get_irg_start_block(env->irg); + ir_node *block = get_irg_start_block(irg); ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]); ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); int initialstackframesize; @@ -577,16 +432,16 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap initialstackframesize = 24; // - setup first part of stackframe - sp = new_rd_mips_addu(NULL, irg, block, sp, + sp = new_bd_mips_addu(NULL, block, sp, mips_create_Immediate(initialstackframesize)); - mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]); - set_mips_flags(sp, arch_irn_flags_ignore); + arch_set_irn_register(sp, &mips_gp_regs[REG_SP]); + panic("FIXME Use IncSP or set register requirement with ignore"); /* TODO: where to get an edge with a0-a3 int i; for(i = 0; i < 4; ++i) { ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]); - ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T); + ir_node *store = new_bd_mips_store_r(dbg, block, *mem, sp, reg, mode_T); attr = get_mips_attr(store); attr->load_store_mode = mode_Iu; attr->tv = new_tarval_from_long(i * 4, mode_Is); @@ -596,41 +451,41 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap */ reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); - store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 16); + store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 16); mm[4] = store; reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]); - store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 20); + store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 20); mm[5] = store; /* Note: ideally we would route these mem edges directly towards the * epilogue, but this is currently not supported so we sync all mems * together */ - sync = new_r_Sync(irg, block, 2, mm+4); + sync = new_r_Sync(block, 2, mm+4); *mem = sync; } else { ir_node *reg, *store; initialstackframesize = 4; // save old framepointer - sp = new_rd_mips_addu(NULL, irg, block, sp, + sp = new_bd_mips_addu(NULL, block, sp, mips_create_Immediate(-initialstackframesize)); - mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]); - set_mips_flags(sp, arch_irn_flags_ignore); + arch_set_irn_register(sp, &mips_gp_regs[REG_SP]); + panic("FIXME Use IncSP or set register requirement with ignore"); reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); - store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 0); + store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 0); *mem = store; } // setup framepointer - fp = new_rd_mips_addu(NULL, irg, block, sp, + fp = new_bd_mips_addu(NULL, block, sp, mips_create_Immediate(-initialstackframesize)); - mips_set_irn_reg(fp, &mips_gp_regs[REG_FP]); - set_mips_flags(fp, arch_irn_flags_ignore); + arch_set_irn_register(fp, &mips_gp_regs[REG_FP]); + panic("FIXME Use IncSP or set register requirement with ignore"); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp); @@ -642,7 +497,6 @@ static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *r { mips_abi_env_t *env = self; - ir_graph *irg = env->irg; ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]); ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); ir_node *load; @@ -650,18 +504,18 @@ static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *r int fp_save_offset = env->debug ? 16 : 0; // copy fp to sp - sp = new_rd_mips_or(NULL, irg, block, fp, mips_create_zero()); - mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]); - set_mips_flags(sp, arch_irn_flags_ignore); + sp = new_bd_mips_or(NULL, block, fp, mips_create_zero()); + arch_set_irn_register(sp, &mips_gp_regs[REG_SP]); + panic("FIXME Use be_Copy or set register requirement with ignore"); // 1. restore fp - load = new_rd_mips_lw(NULL, irg, block, sp, *mem, NULL, + load = new_bd_mips_lw(NULL, block, sp, *mem, NULL, fp_save_offset - initial_frame_size); - set_mips_flags(load, arch_irn_flags_ignore); + panic("FIXME register requirement with ignore"); - fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res); - *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M); - arch_set_irn_register(env->arch_env, fp, &mips_gp_regs[REG_FP]); + fp = new_r_Proj(block, load, mode_Iu, pn_mips_lw_res); + *mem = new_r_Proj(block, load, mode_Iu, pn_mips_lw_M); + arch_set_irn_register(fp, &mips_gp_regs[REG_FP]); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp); @@ -719,7 +573,6 @@ static const be_abi_callbacks_t mips_abi_callbacks = { mips_abi_init, free, mips_abi_get_between_type, - mips_abi_dont_save_regs, mips_abi_prologue, mips_abi_epilogue, }; @@ -754,7 +607,7 @@ static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks); /* collect the mode for each type */ - modes = alloca(n * sizeof(modes[0])); + modes = ALLOCAN(ir_mode*, n); for (i = 0; i < n; i++) { tp = get_method_param_type(method_type, i); modes[i] = get_type_mode(tp); @@ -799,18 +652,15 @@ static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) /** * Returns the necessary byte alignment for storing a register of given class. */ -static int mips_get_reg_class_alignment(const void *self, - const arch_register_class_t *cls) +static int mips_get_reg_class_alignment(const arch_register_class_t *cls) { ir_mode *mode = arch_register_class_mode(cls); - (void) self; return get_mode_size_bytes(mode); } static const be_execution_unit_t ***mips_get_allowed_execution_units( - const void *self, const ir_node *irn) + const ir_node *irn) { - (void) self; (void) irn; /* TODO */ panic("Unimplemented mips_get_allowed_execution_units()"); @@ -840,29 +690,28 @@ static const backend_params *mips_get_libfirm_params(void) { static backend_params p = { 1, /* need dword lowering */ 0, /* don't support inline assembler yet */ - 0, /* no immediate floating point mode. */ - NULL, /* no additional opcodes */ NULL, /* will be set later */ NULL, /* but yet no creator function */ NULL, /* context for create_intrinsic_fkt */ NULL, /* no if conversion settings */ - NULL /* no immediate fp mode */ + NULL, /* float arithmetic mode (TODO) */ + 0, /* no trampoline support: size 0 */ + 0, /* no trampoline support: align 0 */ + NULL, /* no trampoline support: no trampoline builder */ + 4 /* alignment of stack parameter */ }; return &p; } -static asm_constraint_flags_t mips_parse_asm_constraint(const void *self, - const char **c) +static asm_constraint_flags_t mips_parse_asm_constraint(const char **c) { - (void) self; (void) c; return ASM_CONSTRAINT_FLAG_INVALID; } -static int mips_is_valid_clobber(const void *self, const char *clobber) +static int mips_is_valid_clobber(const char *clobber) { - (void) self; (void) clobber; return 0; } @@ -870,6 +719,7 @@ static int mips_is_valid_clobber(const void *self, const char *clobber) const arch_isa_if_t mips_isa_if = { mips_init, mips_done, + NULL, /* handle intrinsics */ mips_get_n_reg_class, mips_get_reg_class, mips_get_reg_class_for_mode,