X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fmips%2Fbearch_mips.c;h=19ad6e7f5cddb090dd5be86bf041507948499f18;hb=e7ba741cdd9599ce05d7989bff60a1c6137ee0b5;hp=2ac831157b64297a911aef1f5f8a153126d44ef5;hpb=205396c4f4f5abe7abd6dc2350c8c398a7623afc;p=libfirm diff --git a/ir/be/mips/bearch_mips.c b/ir/be/mips/bearch_mips.c index 2ac831157..19ad6e7f5 100644 --- a/ir/be/mips/bearch_mips.c +++ b/ir/be/mips/bearch_mips.c @@ -1,5 +1,28 @@ -/* The main mips backend driver file. */ -/* $Id$ */ +/* + * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. + * + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. + * + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +/** + * @file + * @brief The main mips backend driver file. + * @author Matthias Braun, Mehdi + * @version $Id$ + */ #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -15,24 +38,28 @@ #include "iredges.h" #include "irdump.h" #include "irextbb.h" +#include "irtools.h" +#include "error.h" #include "bitset.h" #include "debug.h" -#include "../bearch_t.h" /* the general register allocator interface */ +#include "../bearch_t.h" #include "../benode_t.h" #include "../belower.h" #include "../besched_t.h" -#include "../be.h" +#include "be.h" #include "../beabi.h" #include "../bemachine.h" #include "../bemodule.h" +#include "../bespillslots.h" +#include "../beemitter.h" +#include "../begnuas.h" #include "bearch_mips_t.h" -#include "mips_new_nodes.h" /* mips nodes interface */ -#include "gen_mips_regalloc_if.h" /* the generated interface (register type and class defenitions) */ -#include "mips_gen_decls.h" /* interface declaration emitter */ +#include "mips_new_nodes.h" +#include "gen_mips_regalloc_if.h" #include "mips_transform.h" #include "mips_emitter.h" #include "mips_map_regs.h" @@ -62,9 +89,11 @@ static set *cur_reg_set = NULL; */ static const arch_register_req_t *mips_get_irn_reg_req(const void *self, - const ir_node *node, int pos) { + const ir_node *node, int pos) +{ long node_pos = pos == -1 ? 0 : pos; ir_mode *mode = get_irn_mode(node); + (void) self; if (is_Block(node) || mode == mode_X || mode == mode_M) { return arch_no_register_req; @@ -105,8 +134,11 @@ arch_register_req_t *mips_get_irn_reg_req(const void *self, return arch_no_register_req; } -static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) { +static void mips_set_irn_reg(const void *self, ir_node *irn, + const arch_register_t *reg) +{ int pos = 0; + (void) self; if (is_Proj(irn)) { @@ -123,16 +155,18 @@ static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register slots = get_mips_slots(irn); slots[pos] = reg; - } - else { + } else { /* here we set the registers for the Phi nodes */ mips_set_firm_reg(irn, reg, cur_reg_set); } } -static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) { +static const arch_register_t *mips_get_irn_reg(const void *self, + const ir_node *irn) +{ int pos = 0; const arch_register_t *reg = NULL; + (void) self; if (is_Proj(irn)) { @@ -156,7 +190,9 @@ static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node * return reg; } -static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) { +static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) +{ + (void) self; irn = skip_Proj_const(irn); if (is_cfop(irn)) { @@ -168,47 +204,87 @@ static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) { return 0; } -static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) { +static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) +{ + (void) self; irn = skip_Proj_const(irn); - if (is_mips_irn(irn)) { - return get_mips_flags(irn); - } - else if (is_Unknown(irn)) { - return arch_irn_flags_ignore; - } + if (!is_mips_irn(irn)) + return 0; - return 0; + return get_mips_flags(irn); } -static ir_entity *mips_get_frame_entity(const void *self, const ir_node *irn) { - if(is_mips_load_r(irn) || is_mips_store_r(irn)) { - mips_attr_t *attr = get_mips_attr(irn); +int mips_is_Load(const ir_node *node) +{ + return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) || + is_mips_lb(node) || is_mips_lbu(node); +} - return attr->stack_entity; - } +int mips_is_Store(const ir_node *node) +{ + return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node); +} - return NULL; +static ir_entity *mips_get_frame_entity(const void *self, const ir_node *node) +{ + const mips_load_store_attr_t *attr; + (void) self; + + if(!is_mips_irn(node)) + return NULL; + if(!mips_is_Load(node) && !mips_is_Store(node)) + return NULL; + + attr = get_mips_load_store_attr_const(node); + return attr->stack_entity; } -static void mips_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) { - mips_attr_t *attr = get_mips_attr(irn); - assert(is_mips_load_r(irn) || is_mips_store_r(irn)); - attr->stack_entity = ent; +static void mips_set_frame_entity(const void *self, ir_node *node, + ir_entity *entity) +{ + mips_load_store_attr_t *attr; + (void) self; + + if(!is_mips_irn(node)) { + panic("trying to set frame entity on non load/store node %+F\n", node); + } + if(!mips_is_Load(node) && !mips_is_Store(node)) { + panic("trying to set frame entity on non load/store node %+F\n", node); + } + + attr = get_irn_generic_attr(node); + attr->stack_entity = entity; } /** * This function is called by the generic backend to correct offsets for * nodes accessing the stack. */ -static void mips_set_frame_offset(const void *self, ir_node *irn, int offset) { - mips_attr_t *attr = get_mips_attr(irn); - assert(is_mips_load_r(irn) || is_mips_store_r(irn)); +static void mips_set_frame_offset(const void *self, ir_node *node, int offset) +{ + mips_load_store_attr_t *attr; + (void) self; + + if(!is_mips_irn(node)) { + panic("trying to set frame offset on non load/store node %+F\n", node); + } + if(!mips_is_Load(node) && !mips_is_Store(node)) { + panic("trying to set frame offset on non load/store node %+F\n", node); + } + + attr = get_irn_generic_attr(node); + attr->offset += offset; - attr->stack_entity_offset = offset; + if(attr->offset < -32768 || attr->offset > 32767) { + panic("Out of stack space! (mips supports only 16bit offsets)"); + } } -static int mips_get_sp_bias(const void *self, const ir_node *irn) { +static int mips_get_sp_bias(const void *self, const ir_node *irn) +{ + (void) self; + (void) irn; return 0; } @@ -331,6 +407,7 @@ static void mips_create_block_sched(mips_code_gen_t *cg) { cg->bl_list = bl_list; } +#if 0 typedef struct _wenv_t { ir_node *list; } wenv_t; @@ -346,8 +423,10 @@ static void collect_copyb_nodes(ir_node *node, void *env) { wenv->list = node; } } +#endif static void replace_copyb_nodes(mips_code_gen_t *cg) { +#if 0 wenv_t env; ir_node *copy, *next; ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem; @@ -385,6 +464,8 @@ static void replace_copyb_nodes(mips_code_gen_t *cg) { } } } +#endif + (void) cg; } /** @@ -409,8 +490,7 @@ static void mips_prepare_graph(void *self) { } // walk the graph and transform firm nodes into mips nodes where possible - irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg); - + mips_transform_graph(cg); dump_ir_block_graph_sched(cg->irg, "-transformed"); } @@ -428,16 +508,20 @@ static void mips_finish_irg(void *self) { /** * These are some hooks which must be filled but are probably not needed. */ -static void mips_before_sched(void *self) { - /* Some stuff you need to do after scheduling but before register allocation */ +static void mips_before_sched(void *self) +{ + (void) self; } -static void mips_before_ra(void *self) { - /* Some stuff you need to do immediately after register allocation */ +static void mips_before_ra(void *self) +{ + (void) self; } -static void mips_after_ra(void* self) { +static void mips_after_ra(void* self) +{ mips_code_gen_t *cg = self; + be_coalesce_spillslots(cg->birg); irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self); } @@ -445,19 +529,13 @@ static void mips_after_ra(void* self) { * Emits the code, closes the output file and frees * the code generator interface. */ -static void mips_emit_and_done(void *self) { - mips_code_gen_t *cg = self; - ir_graph *irg = cg->irg; - FILE *out = cg->isa->out; - - mips_register_emitters(); - - if (cg->emit_decls) { - mips_gen_decls(out); - cg->emit_decls = 0; - } +static void mips_emit_and_done(void *self) +{ + mips_code_gen_t *cg = self; + ir_graph *irg = cg->irg; + (void) self; - mips_gen_routine(out, irg, cg); + mips_gen_routine(cg, irg); cur_reg_set = NULL; @@ -487,10 +565,11 @@ static const arch_code_generator_if_t mips_code_gen_if = { /** * Initializes the code generator. */ -static void *mips_cg_init(be_irg_t *birg) { +static void *mips_cg_init(be_irg_t *birg) +{ const arch_env_t *arch_env = be_get_birg_arch_env(birg); - mips_isa_t *isa = (mips_isa_t *) arch_env->isa; - mips_code_gen_t *cg = xmalloc(sizeof(*cg)); + mips_isa_t *isa = (mips_isa_t *) arch_env->isa; + mips_code_gen_t *cg = xmalloc(sizeof(*cg)); cg->impl = &mips_code_gen_if; cg->irg = be_get_birg_irg(birg); @@ -499,19 +578,13 @@ static void *mips_cg_init(be_irg_t *birg) { cg->isa = isa; cg->birg = birg; cg->bl_list = NULL; - FIRM_DBG_REGISTER(cg->mod, "firm.be.mips.cg"); - - isa->num_codegens++; - - if (isa->num_codegens > 1) - cg->emit_decls = 0; - else - cg->emit_decls = 1; cur_reg_set = cg->reg_set; mips_irn_ops.cg = cg; + isa->cg = cg; + return (arch_code_generator_t *)cg; } @@ -527,12 +600,17 @@ static void *mips_cg_init(be_irg_t *birg) { *****************************************************************/ static mips_isa_t mips_isa_template = { - &mips_isa_if, - &mips_gp_regs[REG_SP], - &mips_gp_regs[REG_FP], - -1, // stack direction - 0, // num codegens?!? TODO what is this? - NULL + { + &mips_isa_if, + &mips_gp_regs[REG_SP], + &mips_gp_regs[REG_FP], + -1, /* stack direction */ + NULL, /* main environment */ + 7, /* spill costs */ + 5, /* reload costs */ + }, + NULL_EMITTER, /* emitter environment */ + NULL, /* cg */ }; /** @@ -544,17 +622,22 @@ static void *mips_init(FILE *file_handle) { if(inited) return NULL; + inited = 1; - isa = xcalloc(1, sizeof(*isa)); - memcpy(isa, &mips_isa_template, sizeof(*isa)); + isa = xcalloc(1, sizeof(isa[0])); + memcpy(isa, &mips_isa_template, sizeof(isa[0])); - isa->out = file_handle; + be_emit_init_env(&isa->emit, file_handle); - mips_register_init(isa); + mips_register_init(); mips_create_opcodes(); - mips_init_opcode_transforms(); + // mips_init_opcode_transforms(); - inited = 1; + /* we mark referenced global entities, so we can only emit those which + * are actually referenced. (Note: you mustn't use the type visited flag + * elsewhere in the backend) + */ + inc_master_type_visited(); return isa; } @@ -562,15 +645,25 @@ static void *mips_init(FILE *file_handle) { /** * Closes the output file and frees the ISA structure. */ -static void mips_done(void *self) { - free(self); +static void mips_done(void *self) +{ + mips_isa_t *isa = self; + + be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1); + + be_emit_destroy_env(&isa->emit); + free(isa); } -static int mips_get_n_reg_class(const void *self) { +static int mips_get_n_reg_class(const void *self) +{ + (void) self; return N_CLASSES; } -static const arch_register_class_t *mips_get_reg_class(const void *self, int i) { +static const arch_register_class_t *mips_get_reg_class(const void *self, int i) +{ + (void) self; assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested."); return &mips_reg_classes[i]; } @@ -583,14 +676,17 @@ static const arch_register_class_t *mips_get_reg_class(const void *self, int i) * @param mode The mode in question. * @return A register class which can hold values of the given mode. */ -const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) { +const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, + const ir_mode *mode) +{ + (void) self; ASSERT_NO_FLOAT(mode); return &mips_reg_classes[CLASS_mips_gp]; } typedef struct { be_abi_call_flags_bits_t flags; - const mips_isa_t *isa; + const arch_isa_t *isa; const arch_env_t *arch_env; ir_graph *irg; // do special handling to support debuggers @@ -601,28 +697,27 @@ static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env { mips_abi_env_t *env = xmalloc(sizeof(env[0])); be_abi_call_flags_t fl = be_abi_call_get_flags(call); - env->flags = fl.bits; - env->irg = irg; - env->arch_env = arch_env; - env->isa = (const mips_isa_t*) arch_env->isa; - env->debug = 1; + env->flags = fl.bits; + env->irg = irg; + env->arch_env = arch_env; + env->isa = arch_env->isa; + env->debug = 1; return env; } static void mips_abi_dont_save_regs(void *self, pset *s) { mips_abi_env_t *env = self; + if(env->flags.try_omit_fp) - pset_insert_ptr(s, env->isa->fp); + pset_insert_ptr(s, env->isa->bp); } static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map) { mips_abi_env_t *env = self; ir_graph *irg = env->irg; - dbg_info *dbg = NULL; // TODO where can I get this from? ir_node *block = get_irg_start_block(env->irg); - mips_attr_t *attr; ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]); ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); int initialstackframesize; @@ -639,11 +734,10 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap initialstackframesize = 24; // - setup first part of stackframe - sp = new_rd_mips_addiu(dbg, irg, block, sp); - attr = get_mips_attr(sp); - attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is); + sp = new_rd_mips_addu(NULL, irg, block, sp, + mips_create_Immediate(initialstackframesize)); mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]); - //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]); + set_mips_flags(sp, arch_irn_flags_ignore); /* TODO: where to get an edge with a0-a3 int i; @@ -659,22 +753,18 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap */ reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); - store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T); - attr = get_mips_attr(store); - attr->modes.load_store_mode = mode_Iu; - attr->tv = new_tarval_from_long(16, mode_Is); + store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 16); - mm[4] = new_r_Proj(irg, block, store, mode_M, pn_Store_M); + mm[4] = store; reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]); - store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T); - attr = get_mips_attr(store); - attr->modes.load_store_mode = mode_Iu; - attr->tv = new_tarval_from_long(20, mode_Is); + store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 20); - mm[5] = new_r_Proj(irg, block, store, mode_M, pn_Store_M); + mm[5] = store; - // TODO ideally we would route these mem edges directly towards the epilogue + /* Note: ideally we would route these mem edges directly towards the + * epilogue, but this is currently not supported so we sync all mems + * together */ sync = new_r_Sync(irg, block, 2, mm+4); *mem = sync; } else { @@ -682,27 +772,22 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap initialstackframesize = 4; // save old framepointer - sp = new_rd_mips_addiu(dbg, irg, block, sp); - attr = get_mips_attr(sp); - attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is); + sp = new_rd_mips_addu(NULL, irg, block, sp, + mips_create_Immediate(-initialstackframesize)); mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]); - //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]); + set_mips_flags(sp, arch_irn_flags_ignore); reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); - store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T); - attr = get_mips_attr(store); - attr->modes.load_store_mode = mode_Iu; - attr->tv = new_tarval_from_long(0, mode_Is); + store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 0); - *mem = new_r_Proj(irg, block, store, mode_M, pn_Store_M); + *mem = store; } // setup framepointer - fp = new_rd_mips_addiu(dbg, irg, block, sp); - attr = get_mips_attr(fp); - attr->tv = new_tarval_from_long(initialstackframesize, mode_Is); + fp = new_rd_mips_addu(NULL, irg, block, sp, + mips_create_Immediate(-initialstackframesize)); mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]); - //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]); + set_mips_flags(fp, arch_irn_flags_ignore); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp); @@ -712,10 +797,9 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map) { - mips_abi_env_t *env = self; + mips_abi_env_t *env = self; + ir_graph *irg = env->irg; - dbg_info *dbg = NULL; // TODO where can I get this from? - mips_attr_t *attr; ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]); ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); ir_node *load; @@ -723,20 +807,18 @@ static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *r int fp_save_offset = env->debug ? 16 : 0; // copy fp to sp - sp = new_rd_mips_move(dbg, irg, block, fp); + sp = new_rd_mips_or(NULL, irg, block, fp, mips_create_zero()); mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]); - //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]); + set_mips_flags(sp, arch_irn_flags_ignore); // 1. restore fp - load = new_rd_mips_load_r(dbg, irg, block, *mem, sp, mode_T); - attr = get_mips_attr(load); - attr->modes.load_store_mode = mode_Iu; - // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size - attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Is); + load = new_rd_mips_lw(NULL, irg, block, sp, *mem, NULL, + fp_save_offset - initial_frame_size); + set_mips_flags(load, arch_irn_flags_ignore); - fp = new_r_Proj(irg, block, load, mode_Iu, pn_Load_res); - mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]); - //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]); + fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res); + *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M); + arch_set_irn_register(env->arch_env, fp, &mips_gp_regs[REG_FP]); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp); @@ -805,7 +887,9 @@ static const be_abi_callbacks_t mips_abi_callbacks = { * @param method_type The type of the method (procedure) in question. * @param abi The abi object to be modified */ -static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) { +static void mips_get_call_abi(const void *self, ir_type *method_type, + be_abi_call_t *abi) +{ ir_type *tp; ir_mode *mode; int n = get_method_n_params(method_type); @@ -814,6 +898,7 @@ static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_cal ir_mode **modes; const arch_register_t *reg; be_abi_call_flags_t call_flags; + (void) self; memset(&call_flags, 0, sizeof(call_flags)); call_flags.bits.left_to_right = 0; @@ -859,7 +944,11 @@ static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_cal } } -static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) { +static const void *mips_get_irn_ops(const arch_irn_handler_t *self, + const ir_node *irn) +{ + (void) self; + (void) irn; return &mips_irn_ops; } @@ -867,32 +956,45 @@ const arch_irn_handler_t mips_irn_handler = { mips_get_irn_ops }; -const arch_irn_handler_t *mips_get_irn_handler(const void *self) { +const arch_irn_handler_t *mips_get_irn_handler(const void *self) +{ + (void) self; return &mips_irn_handler; } /** * Initializes the code generator interface. */ -static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) { +static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) +{ + (void) self; return &mips_code_gen_if; } /** * Returns the necessary byte alignment for storing a register of given class. */ -static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) { +static int mips_get_reg_class_alignment(const void *self, + const arch_register_class_t *cls) +{ ir_mode *mode = arch_register_class_mode(cls); + (void) self; return get_mode_size_bytes(mode); } -static const be_execution_unit_t ***mips_get_allowed_execution_units(const void *self, const ir_node *irn) { +static const be_execution_unit_t ***mips_get_allowed_execution_units( + const void *self, const ir_node *irn) +{ + (void) self; + (void) irn; /* TODO */ assert(0); return NULL; } -static const be_machine_t *mips_get_machine(const void *self) { +static const be_machine_t *mips_get_machine(const void *self) +{ + (void) self; /* TODO */ assert(0); return NULL; @@ -901,7 +1003,10 @@ static const be_machine_t *mips_get_machine(const void *self) { /** * Return irp irgs in the desired order. */ -static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list) { +static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list) +{ + (void) self; + (void) irg_list; return NULL; } @@ -909,7 +1014,7 @@ static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list) { * Returns the libFirm configuration parameter for this backend. */ static const backend_params *mips_get_libfirm_params(void) { - static arch_dep_params_t ad = { + static ir_settings_arch_dep_t ad = { 1, /* allow subs */ 0, /* Muls are fast enough on Mips */ 31, /* shift would be ok */ @@ -918,11 +1023,13 @@ static const backend_params *mips_get_libfirm_params(void) { 32, /* Mulhs & Mulhu available for 32 bit */ }; static backend_params p = { + 1, /* need dword lowering */ + 0, /* don't support inlien assembler yet */ NULL, /* no additional opcodes */ NULL, /* will be set later */ - 1, /* need dword lowering */ NULL, /* but yet no creator function */ NULL, /* context for create_intrinsic_fkt */ + NULL, /* no if conversion settings */ }; p.dep_param = &ad;