X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fmips%2Fbearch_mips.c;h=18cb60d3b190bb7949d2fb2e4b1c8eefb5dd2d84;hb=97c6f4665bc5071a86ece7fd9d6eaeeb30581bd3;hp=6371ec8145cd141bb88118843bc7fd1f4e8765c3;hpb=21ae21f548b3d01d84d48820bee9429a608c621e;p=libfirm diff --git a/ir/be/mips/bearch_mips.c b/ir/be/mips/bearch_mips.c index 6371ec814..18cb60d3b 100644 --- a/ir/be/mips/bearch_mips.c +++ b/ir/be/mips/bearch_mips.c @@ -1,6 +1,28 @@ -/* The main mips backend driver file. */ -/* $Id$ */ +/* + * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. + * + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. + * + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ +/** + * @file + * @brief The main mips backend driver file. + * @author Matthias Braun, Mehdi + * @version $Id$ + */ #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -16,22 +38,27 @@ #include "iredges.h" #include "irdump.h" #include "irextbb.h" +#include "error.h" #include "bitset.h" #include "debug.h" -#include "../bearch.h" /* the general register allocator interface */ +#include "../bearch_t.h" #include "../benode_t.h" #include "../belower.h" #include "../besched_t.h" -#include "../be.h" +#include "be.h" #include "../beabi.h" +#include "../bemachine.h" +#include "../bemodule.h" +#include "../bespillslots.h" +#include "../beemitter.h" +#include "../begnuas.h" #include "bearch_mips_t.h" -#include "mips_new_nodes.h" /* mips nodes interface */ -#include "gen_mips_regalloc_if.h" /* the generated interface (register type and class defenitions) */ -#include "mips_gen_decls.h" /* interface declaration emitter */ +#include "mips_new_nodes.h" +#include "gen_mips_regalloc_if.h" #include "mips_transform.h" #include "mips_emitter.h" #include "mips_map_regs.h" @@ -54,101 +81,54 @@ static set *cur_reg_set = NULL; * |___/ **************************************************/ -static ir_node *my_skip_proj(const ir_node *n) { - while (is_Proj(n)) - n = get_Proj_pred(n); - return (ir_node *)n; -} - /** * Return register requirements for a mips node. * If the node returns a tuple (mode_T) then the proj's * will be asked for this information. */ -static const arch_register_req_t *mips_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) { - const mips_register_req_t *irn_req; +static const +arch_register_req_t *mips_get_irn_reg_req(const void *self, + const ir_node *node, int pos) { long node_pos = pos == -1 ? 0 : pos; - ir_mode *mode = get_irn_mode(irn); - FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE); + ir_mode *mode = get_irn_mode(node); - if (is_Block(irn) || mode == mode_X || mode == mode_M) { - DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn)); - return NULL; + if (is_Block(node) || mode == mode_X || mode == mode_M) { + return arch_no_register_req; } if (mode == mode_T && pos < 0) { - DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn)); - return NULL; + return arch_no_register_req; } - DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn)); - - if (is_Proj(irn)) { + if (is_Proj(node)) { /* in case of a proj, we need to get the correct OUT slot */ /* of the node corresponding to the proj number */ if (pos == -1) { - node_pos = mips_translate_proj_pos(irn); + node_pos = mips_translate_proj_pos(node); } else { node_pos = pos; } - irn = my_skip_proj(irn); - - DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos)); + node = skip_Proj_const(node); } /* get requirements for our own nodes */ - if (is_mips_irn(irn)) { + if (is_mips_irn(node)) { + const arch_register_req_t *req; if (pos >= 0) { - irn_req = get_mips_in_req(irn, pos); - } - else { - irn_req = get_mips_out_req(irn, node_pos); - } - - DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos)); - - memcpy(req, &(irn_req->req), sizeof(*req)); - - if (arch_register_req_is(&(irn_req->req), should_be_same)) { - assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI"); - req->other_same = get_irn_n(irn, irn_req->same_pos); + req = get_mips_in_req(node, pos); + } else { + req = get_mips_out_req(node, node_pos); } - if (arch_register_req_is(&(irn_req->req), should_be_different)) { - assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI"); - req->other_different = get_irn_n(irn, irn_req->different_pos); - } + return req; } - /* get requirements for FIRM nodes */ - else { - /* treat Phi like Const with default requirements */ - if (is_Phi(irn)) { - DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn)); - if (mode_is_float(mode)) { - //memcpy(req, &(mips_default_req_mips_floating_point.req), sizeof(*req)); - assert(0 && "floating point not supported (yet)"); - } - else if (mode_is_int(mode) || mode_is_reference(mode)) { - memcpy(req, &(mips_default_req_mips_gp.req), sizeof(*req)); - } - else if (mode == mode_T || mode == mode_M) { - DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn)); - return NULL; - } - else { - assert(0 && "unsupported Phi-Mode"); - } - } - else { - DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn)); - req = NULL; - } - } + /* unknown should be translated by now */ + assert(!is_Unknown(node)); - return req; + return arch_no_register_req; } static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) { @@ -161,7 +141,7 @@ static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register } pos = mips_translate_proj_pos(irn); - irn = my_skip_proj(irn); + irn = skip_Proj(irn); } if (is_mips_irn(irn)) { @@ -187,7 +167,7 @@ static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node * } pos = mips_translate_proj_pos(irn); - irn = my_skip_proj(irn); + irn = skip_Proj_const(irn); } if (is_mips_irn(irn)) { @@ -203,7 +183,7 @@ static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node * } static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) { - irn = my_skip_proj(irn); + irn = skip_Proj_const(irn); if (is_cfop(irn)) { return arch_irn_class_branch; @@ -215,7 +195,7 @@ static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) { } static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) { - irn = my_skip_proj(irn); + irn = skip_Proj_const(irn); if (is_mips_irn(irn)) { return get_mips_flags(irn); @@ -227,25 +207,38 @@ static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) { return 0; } -static entity *mips_get_frame_entity(const void *self, const ir_node *irn) { - if(is_mips_load_r(irn) || is_mips_store_r(irn)) { - mips_attr_t *attr = get_mips_attr(irn); +static +ir_entity *mips_get_frame_entity(const void *self, const ir_node *node) { + const mips_attr_t *attr; - return attr->stack_entity; - } + if(!is_mips_irn(node)) + return NULL; - return NULL; + attr = get_mips_attr_const(node); + return attr->stack_entity; +} + +static +void mips_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) { + mips_attr_t *attr = get_mips_attr(irn); + attr->stack_entity = ent; } /** * This function is called by the generic backend to correct offsets for * nodes accessing the stack. */ -static void mips_set_frame_offset(const void *self, ir_node *irn, int offset) { +static void mips_set_frame_offset(const void *self, ir_node *irn, int offset) +{ + panic("TODO"); +#if 0 mips_attr_t *attr = get_mips_attr(irn); - assert(is_mips_load_r(irn) || is_mips_store_r(irn)); - attr->stack_entity_offset = offset; +#endif +} + +static int mips_get_sp_bias(const void *self, const ir_node *irn) { + return 0; } /* fill register allocator interface */ @@ -257,7 +250,13 @@ static const arch_irn_ops_if_t mips_irn_ops_if = { mips_classify, mips_get_flags, mips_get_frame_entity, - mips_set_frame_offset + mips_set_frame_entity, + mips_set_frame_offset, + mips_get_sp_bias, + NULL, /* get_inverse */ + NULL, /* get_op_estimated_cost */ + NULL, /* possible_memory_operand */ + NULL, /* perform_memory_operand */ }; mips_irn_ops_t mips_irn_ops = { @@ -361,6 +360,7 @@ static void mips_create_block_sched(mips_code_gen_t *cg) { cg->bl_list = bl_list; } +#if 0 typedef struct _wenv_t { ir_node *list; } wenv_t; @@ -376,8 +376,10 @@ static void collect_copyb_nodes(ir_node *node, void *env) { wenv->list = node; } } +#endif static void replace_copyb_nodes(mips_code_gen_t *cg) { +#if 0 wenv_t env; ir_node *copy, *next; ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem; @@ -415,6 +417,8 @@ static void replace_copyb_nodes(mips_code_gen_t *cg) { } } } +#endif + (void) cg; } /** @@ -447,10 +451,11 @@ static void mips_prepare_graph(void *self) { /** * Called immediately before emit phase. */ -static void mips_finish_irg(ir_graph *irg, mips_code_gen_t *cg) { - /* TODO: - fix offsets for nodes accessing stack - - ... - */ +static void mips_finish_irg(void *self) { + mips_code_gen_t *cg = self; + ir_graph *irg = cg->irg; + + dump_ir_block_graph_sched(irg, "-mips-finished"); } @@ -467,6 +472,7 @@ static void mips_before_ra(void *self) { static void mips_after_ra(void* self) { mips_code_gen_t *cg = self; + be_coalesce_spillslots(cg->birg); irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self); } @@ -475,20 +481,10 @@ static void mips_after_ra(void* self) { * the code generator interface. */ static void mips_emit_and_done(void *self) { - mips_code_gen_t *cg = self; - ir_graph *irg = cg->irg; - FILE *out = cg->isa->out; - - mips_register_emitters(); + mips_code_gen_t *cg = self; + ir_graph *irg = cg->irg; - if (cg->emit_decls) { - mips_gen_decls(out); - cg->emit_decls = 0; - } - - mips_finish_irg(irg, cg); - dump_ir_block_graph_sched(irg, "-mips-finished"); - mips_gen_routine(out, irg, cg); + mips_gen_routine(cg, irg); cur_reg_set = NULL; @@ -501,40 +497,35 @@ static void mips_emit_and_done(void *self) { free(cg); } -static void *mips_cg_init(const be_irg_t *birg); +static void *mips_cg_init(be_irg_t *birg); static const arch_code_generator_if_t mips_code_gen_if = { mips_cg_init, NULL, /* before abi introduce */ mips_prepare_graph, + NULL, /* spill */ mips_before_sched, /* before scheduling hook */ mips_before_ra, /* before register allocation hook */ mips_after_ra, + mips_finish_irg, mips_emit_and_done }; /** * Initializes the code generator. */ -static void *mips_cg_init(const be_irg_t *birg) { - mips_isa_t *isa = (mips_isa_t *)birg->main_env->arch_env->isa; - mips_code_gen_t *cg = xmalloc(sizeof(*cg)); +static void *mips_cg_init(be_irg_t *birg) { + const arch_env_t *arch_env = be_get_birg_arch_env(birg); + mips_isa_t *isa = (mips_isa_t *) arch_env->isa; + mips_code_gen_t *cg = xmalloc(sizeof(*cg)); cg->impl = &mips_code_gen_if; - cg->irg = birg->irg; + cg->irg = be_get_birg_irg(birg); cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024); - cg->arch_env = birg->main_env->arch_env; + cg->arch_env = arch_env; cg->isa = isa; cg->birg = birg; cg->bl_list = NULL; - FIRM_DBG_REGISTER(cg->mod, "firm.be.mips.cg"); - - isa->num_codegens++; - - if (isa->num_codegens > 1) - cg->emit_decls = 0; - else - cg->emit_decls = 1; cur_reg_set = cg->reg_set; @@ -555,12 +546,16 @@ static void *mips_cg_init(const be_irg_t *birg) { *****************************************************************/ static mips_isa_t mips_isa_template = { - &mips_isa_if, - &mips_gp_regs[REG_SP], - &mips_gp_regs[REG_FP], - -1, // stack direction - 0, // num codegens?!? TODO what is this? - NULL + { + &mips_isa_if, + &mips_gp_regs[REG_SP], + &mips_gp_regs[REG_FP], + -1, /* stack direction */ + NULL, /* main environment */ + 7, /* spill costs */ + 5, /* reload costs */ + }, + { NULL, }, /* emitter environment */ }; /** @@ -572,17 +567,22 @@ static void *mips_init(FILE *file_handle) { if(inited) return NULL; + inited = 1; - isa = xcalloc(1, sizeof(*isa)); - memcpy(isa, &mips_isa_template, sizeof(*isa)); + isa = xcalloc(1, sizeof(isa[0])); + memcpy(isa, &mips_isa_template, sizeof(isa[0])); - isa->out = file_handle; + be_emit_init_env(&isa->emit, file_handle); mips_register_init(isa); mips_create_opcodes(); - mips_init_opcode_transforms(); + // mips_init_opcode_transforms(); - inited = 1; + /* we mark referenced global entities, so we can only emit those which + * are actually referenced. (Note: you mustn't use the type visited flag + * elsewhere in the backend) + */ + inc_master_type_visited(); return isa; } @@ -591,7 +591,12 @@ static void *mips_init(FILE *file_handle) { * Closes the output file and frees the ISA structure. */ static void mips_done(void *self) { - free(self); + mips_isa_t *isa = self; + + be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1); + + be_emit_destroy_env(&isa->emit); + free(isa); } static int mips_get_n_reg_class(const void *self) { @@ -618,7 +623,7 @@ const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const typedef struct { be_abi_call_flags_bits_t flags; - const mips_isa_t *isa; + const arch_isa_t *isa; const arch_env_t *arch_env; ir_graph *irg; // do special handling to support debuggers @@ -629,19 +634,20 @@ static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env { mips_abi_env_t *env = xmalloc(sizeof(env[0])); be_abi_call_flags_t fl = be_abi_call_get_flags(call); - env->flags = fl.bits; - env->irg = irg; - env->arch_env = arch_env; - env->isa = (const mips_isa_t*) arch_env->isa; - env->debug = 1; + env->flags = fl.bits; + env->irg = irg; + env->arch_env = arch_env; + env->isa = arch_env->isa; + env->debug = 1; return env; } static void mips_abi_dont_save_regs(void *self, pset *s) { mips_abi_env_t *env = self; + if(env->flags.try_omit_fp) - pset_insert_ptr(s, env->isa->fp); + pset_insert_ptr(s, env->isa->bp); } static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map) @@ -667,7 +673,7 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap initialstackframesize = 24; // - setup first part of stackframe - sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is); + sp = new_rd_mips_addiu(dbg, irg, block, sp); attr = get_mips_attr(sp); attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is); mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]); @@ -687,20 +693,18 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap */ reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); - store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T); + store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg); attr = get_mips_attr(store); - attr->modes.load_store_mode = mode_Iu; - attr->tv = new_tarval_from_long(16, mode_Is); + attr->tv = new_tarval_from_long(16, mode_Hs); - mm[4] = new_r_Proj(irg, block, store, mode_M, pn_Store_M); + mm[4] = store; reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]); - store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T); + store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg); attr = get_mips_attr(store); - attr->modes.load_store_mode = mode_Iu; - attr->tv = new_tarval_from_long(20, mode_Is); + attr->tv = new_tarval_from_long(20, mode_Hs); - mm[5] = new_r_Proj(irg, block, store, mode_M, pn_Store_M); + mm[5] = store; // TODO ideally we would route these mem edges directly towards the epilogue sync = new_r_Sync(irg, block, 2, mm+4); @@ -710,23 +714,22 @@ static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap initialstackframesize = 4; // save old framepointer - sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is); + sp = new_rd_mips_addiu(dbg, irg, block, sp); attr = get_mips_attr(sp); attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is); mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]); //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]); reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]); - store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T); + store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg); attr = get_mips_attr(store); - attr->modes.load_store_mode = mode_Iu; - attr->tv = new_tarval_from_long(0, mode_Is); + attr->tv = new_tarval_from_long(0, mode_Hs); - *mem = new_r_Proj(irg, block, store, mode_M, pn_Store_M); + *mem = store; } // setup framepointer - fp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is); + fp = new_rd_mips_addiu(dbg, irg, block, sp); attr = get_mips_attr(fp); attr->tv = new_tarval_from_long(initialstackframesize, mode_Is); mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]); @@ -750,24 +753,20 @@ static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *r int initial_frame_size = env->debug ? 24 : 4; int fp_save_offset = env->debug ? 16 : 0; - // restore sp - //sp = be_new_IncSP(&mips_gp_regs[REG_SP], irg, block, sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_against); - // copy fp to sp - sp = new_rd_mips_move(dbg, irg, block, fp, mode_Iu); + sp = new_rd_mips_move(dbg, irg, block, fp); mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]); //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]); // 1. restore fp - load = new_rd_mips_load_r(dbg, irg, block, *mem, sp, mode_T); + load = new_rd_mips_lw(dbg, irg, block, *mem, sp); attr = get_mips_attr(load); - attr->modes.load_store_mode = mode_Iu; // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size - attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Is); + attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Hs); - fp = new_r_Proj(irg, block, load, mode_Iu, pn_Load_res); - mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]); - //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]); + fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res); + *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M); + arch_set_irn_register(env->arch_env, fp, &mips_gp_regs[REG_FP]); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp); be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp); @@ -783,11 +782,11 @@ static ir_type *mips_abi_get_between_type(void *self) { static ir_type *debug_between_type = NULL; static ir_type *opt_between_type = NULL; - static entity *old_fp_ent = NULL; + static ir_entity *old_fp_ent = NULL; if(env->debug && debug_between_type == NULL) { - entity *a0_ent, *a1_ent, *a2_ent, *a3_ent; - entity *ret_addr_ent; + ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent; + ir_entity *ret_addr_ent; ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P); ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P); ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu); @@ -800,21 +799,21 @@ static ir_type *mips_abi_get_between_type(void *self) { old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type); ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type); - set_entity_offset_bytes(a0_ent, 0); - set_entity_offset_bytes(a1_ent, 4); - set_entity_offset_bytes(a2_ent, 8); - set_entity_offset_bytes(a3_ent, 12); - set_entity_offset_bytes(old_fp_ent, 16); - set_entity_offset_bytes(ret_addr_ent, 20); + set_entity_offset(a0_ent, 0); + set_entity_offset(a1_ent, 4); + set_entity_offset(a2_ent, 8); + set_entity_offset(a3_ent, 12); + set_entity_offset(old_fp_ent, 16); + set_entity_offset(ret_addr_ent, 20); set_type_size_bytes(debug_between_type, 24); } else if(!env->debug && opt_between_type == NULL) { ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P); - entity *old_fp_ent; + ir_entity *old_fp_ent; opt_between_type = new_type_class(new_id_from_str("mips_between_type")); old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type); - set_entity_offset_bytes(old_fp_ent, 0); + set_entity_offset(old_fp_ent, 0); set_type_size_bytes(opt_between_type, 4); } @@ -917,11 +916,51 @@ static int mips_get_reg_class_alignment(const void *self, const arch_register_cl return get_mode_size_bytes(mode); } -#ifdef WITH_LIBCORE -static void mips_register_options(lc_opt_entry_t *ent) -{ +static const be_execution_unit_t ***mips_get_allowed_execution_units(const void *self, const ir_node *irn) { + /* TODO */ + assert(0); + return NULL; +} + +static const be_machine_t *mips_get_machine(const void *self) { + /* TODO */ + assert(0); + return NULL; +} + +/** + * Return irp irgs in the desired order. + */ +static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list) { + return NULL; +} + +/** + * Returns the libFirm configuration parameter for this backend. + */ +static const backend_params *mips_get_libfirm_params(void) { + static arch_dep_params_t ad = { + 1, /* allow subs */ + 0, /* Muls are fast enough on Mips */ + 31, /* shift would be ok */ + 0, /* no Mulhs */ + 0, /* no Mulhu */ + 32, /* Mulhs & Mulhu available for 32 bit */ + }; + static backend_params p = { + 1, /* need dword lowering */ + 0, /* don't support inlien assembler yet */ + 0, /* no different calling conventions */ + NULL, /* no additional opcodes */ + NULL, /* will be set later */ + NULL, /* but yet no creator function */ + NULL, /* context for create_intrinsic_fkt */ + NULL, /* no if conversion settings */ + }; + + p.dep_param = &ad; + return &p; } -#endif /* WITH_LIBCORE */ const arch_isa_if_t mips_isa_if = { mips_init, @@ -933,8 +972,17 @@ const arch_isa_if_t mips_isa_if = { mips_get_irn_handler, mips_get_code_generator_if, mips_get_list_sched_selector, + mips_get_ilp_sched_selector, mips_get_reg_class_alignment, -#ifdef WITH_LIBCORE - mips_register_options -#endif + mips_get_libfirm_params, + mips_get_allowed_execution_units, + mips_get_machine, + mips_get_irg_list, }; + +void be_init_arch_mips(void) +{ + be_register_isa_if("mips", &mips_isa_if); +} + +BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);