X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_x87.c;h=ca09d3b407a8dad9c3dd07548415b9017ab88ec0;hb=366e963a782fe9549838fd3492438ea6ea1f19ad;hp=de964f4bb00ed64b7aeca68e8ce0fcbab5b1a0d5;hpb=0b5901405ecbbd5429a131530d921609fd812527;p=libfirm diff --git a/ir/be/ia32/ia32_x87.c b/ir/be/ia32/ia32_x87.c index de964f4bb..ca09d3b40 100644 --- a/ir/be/ia32/ia32_x87.c +++ b/ir/be/ia32/ia32_x87.c @@ -1,10 +1,28 @@ -/** - * This file implements the x87 support and virtual to stack - * register translation for the ia32 backend. +/* + * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. + * + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. * - * @author: Michael Beck + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. * - * $Id$ + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +/** + * @file + * @brief This file implements the x87 support and virtual to stack + * register translation for the ia32 backend. + * @author Michael Beck + * @version $Id$ */ #ifdef HAVE_CONFIG_H #include "config.h" @@ -87,7 +105,7 @@ typedef struct _x87_state { } x87_state; /** An empty state, used for blocks without fp instructions. */ -static x87_state _empty = { { {0, NULL}, }, 0, 0 }; +static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL }; static x87_state *empty = (x87_state *)&_empty; enum { @@ -427,10 +445,10 @@ static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, co */ static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) { ir_node *fxch; - ia32_attr_t *attr; + ia32_x87_attr_t *attr; fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block, mode_E); - attr = get_ia32_attr(fxch); + attr = get_ia32_x87_attr(fxch); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -457,11 +475,16 @@ static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) { * * @return state */ -static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, x87_state *state, ir_node *dst_block, const x87_state *dst_state) { +static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, + x87_state *state, ir_node *dst_block, + const x87_state *dst_state) +{ int i, n_cycles, k, ri; unsigned cycles[4], all_mask; char cycle_idx[4][8]; ir_node *fxch, *before, *after; + (void) sim; + (void) dst_block; assert(state->depth == dst_state->depth); @@ -582,20 +605,20 @@ static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, x87_state *sta * @param state the x87 state * @param n the node after the fxch * @param pos exchange st(pos) with st(0) - * @param op_idx if >= 0, replace input op_idx of n with the fxch result * * @return the fxch */ -static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos, int op_idx) { - ir_node *fxch; - ia32_attr_t *attr; - ir_graph *irg = get_irn_irg(n); - ir_node *block = get_nodes_block(n); +static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos) +{ + ir_node *fxch; + ia32_x87_attr_t *attr; + ir_graph *irg = get_irn_irg(n); + ir_node *block = get_nodes_block(n); x87_fxch(state, pos); fxch = new_rd_ia32_fxch(NULL, irg, block, mode_E); - attr = get_ia32_attr(fxch); + attr = get_ia32_x87_attr(fxch); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -616,13 +639,13 @@ static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos, int op_id */ static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) { ir_node *fpush, *pred = get_irn_n(n, op_idx); - ia32_attr_t *attr; + ia32_x87_attr_t *attr; const arch_register_t *out = x87_get_irn_register(state->sim, pred); x87_push_dbl(state, arch_register_get_index(out), pred); fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n), mode_E); - attr = get_ia32_attr(fpush); + attr = get_ia32_x87_attr(fpush); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -638,20 +661,18 @@ static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) * @param state the x87 state * @param n the node after the fpop * @param num pop 1 or 2 values - * @param pred node to use as predecessor of the fpop * * @return the fpop node */ -static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num, ir_node *pred) { - ir_node *fpop = pred; - ia32_attr_t *attr; +static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num) +{ + ir_node *fpop; + ia32_x87_attr_t *attr; while (num > 0) { - keep_alive(pred); - x87_pop(state); fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n), mode_E); - attr = get_ia32_attr(fpop); + attr = get_ia32_x87_attr(fpop); attr->x87[0] = &ia32_st_regs[0]; attr->x87[1] = &ia32_st_regs[0]; attr->x87[2] = &ia32_st_regs[0]; @@ -660,7 +681,6 @@ static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num, ir_node * sched_add_before(n, fpop); DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name)); - pred = fpop; --num; } return fpop; @@ -710,9 +730,22 @@ static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_ const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp]; const arch_env_t *arch_env = sim->arch_env; + if (get_irn_mode(irn) == mode_T) { + const ir_edge_t *edge; + + foreach_out_edge(irn, edge) { + ir_node *proj = get_edge_src_irn(edge); + + if (arch_irn_consider_in_reg_alloc(arch_env, cls, proj)) { + const arch_register_t *reg = x87_get_irn_register(sim, proj); + live &= ~(1 << arch_register_get_index(reg)); + } + } + } + if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) { - const arch_register_t *reg = x87_get_irn_register(sim, irn); - live &= ~(1 << arch_register_get_index(reg)); + const arch_register_t *reg = x87_get_irn_register(sim, irn); + live &= ~(1 << arch_register_get_index(reg)); } for (i = 0, n = get_irn_arity(irn); i < n; ++i) { @@ -834,6 +867,15 @@ static void vfp_dump_live(vfp_liveness live) { #define XCHG(a, b) do { int t = (a); (a) = (b); (b) = t; } while (0) +/* Pseudocode: + + + + + + +*/ + /** * Simulate a virtual binop. * @@ -846,36 +888,53 @@ static void vfp_dump_live(vfp_liveness live) { static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { int op2_idx = 0, op1_idx; int out_idx, do_pop = 0; - ia32_attr_t *attr; + ia32_x87_attr_t *attr; ir_node *patched_insn; ir_op *dst; - x87_simulator *sim = state->sim; - const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1)); - const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2)); - const arch_register_t *out = x87_get_irn_register(sim, n); - int reg_index_1 = arch_register_get_index(op1); - int reg_index_2 = arch_register_get_index(op2); - vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out)); + x87_simulator *sim = state->sim; + ir_node *op1 = get_irn_n(n, BINOP_IDX_1); + ir_node *op2 = get_irn_n(n, BINOP_IDX_2); + const arch_register_t *op1_reg = x87_get_irn_register(sim, op1); + const arch_register_t *op2_reg = x87_get_irn_register(sim, op2); + const arch_register_t *out = x87_get_irn_register(sim, n); + int reg_index_1 = arch_register_get_index(op1_reg); + int reg_index_2 = arch_register_get_index(op2_reg); + vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out)); + int op1_live_after; + int op2_live_after; DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n, - arch_register_get_name(op1), arch_register_get_name(op2), + arch_register_get_name(op1_reg), arch_register_get_name(op2_reg), arch_register_get_name(out))); DEBUG_ONLY(vfp_dump_live(live)); DB((dbg, LEVEL_1, "Stack before: ")); DEBUG_ONLY(x87_dump_stack(state)); - op1_idx = x87_on_stack(state, reg_index_1); - assert(op1_idx >= 0); + if(reg_index_1 == REG_VFP_UKNWN) { + op1_idx = 0; + op1_live_after = 1; + } else { + op1_idx = x87_on_stack(state, reg_index_1); + assert(op1_idx >= 0); + op1_live_after = is_vfp_live(arch_register_get_index(op1_reg), live); + } if (reg_index_2 != REG_VFP_NOREG) { - /* second operand is a vfp register */ - op2_idx = x87_on_stack(state, reg_index_2); - assert(op2_idx >= 0); + if(reg_index_2 == REG_VFP_UKNWN) { + op2_idx = 0; + op2_live_after = 1; + } else { + /* second operand is a vfp register */ + op2_idx = x87_on_stack(state, reg_index_2); + assert(op2_idx >= 0); + op2_live_after + = is_vfp_live(arch_register_get_index(op2_reg), live); + } - if (is_vfp_live(arch_register_get_index(op2), live)) { + if (op2_live_after) { /* Second operand is live. */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* Both operands are live: push the first one. This works even for op1 == op2. */ x87_create_fpush(state, n, op1_idx, BINOP_IDX_2); @@ -887,7 +946,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } else { /* Second live, first operand is dead here, bring it to tos. */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); if (op2_idx == 0) op2_idx = op1_idx; op1_idx = 0; @@ -898,10 +957,10 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } } else { /* Second operand is dead. */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* First operand is live: bring second to tos. */ if (op2_idx != 0) { - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); if (op1_idx == 0) op1_idx = op2_idx; op2_idx = 0; @@ -931,7 +990,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { out_idx = op2_idx; } else { /* Bring the second on top. */ - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); if (op1_idx == op2_idx) { /* Both are identically and on tos now, no pop needed. */ op1_idx = 0; @@ -952,7 +1011,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } } else { /* second operand is an address mode */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* first operand is live: push it here */ x87_create_fpush(state, n, op1_idx, BINOP_IDX_1); op1_idx = 0; @@ -962,7 +1021,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } else { /* first operand is dead: bring it to tos */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } @@ -979,20 +1038,20 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } /* patch the operation */ - attr = get_ia32_attr(n); - attr->x87[0] = op1 = &ia32_st_regs[op1_idx]; + attr = get_ia32_x87_attr(n); + attr->x87[0] = op1_reg = &ia32_st_regs[op1_idx]; if (reg_index_2 != REG_VFP_NOREG) { - attr->x87[1] = op2 = &ia32_st_regs[op2_idx]; + attr->x87[1] = op2_reg = &ia32_st_regs[op2_idx]; } attr->x87[2] = out = &ia32_st_regs[out_idx]; if (reg_index_2 != REG_VFP_NOREG) { DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n), - arch_register_get_name(op1), arch_register_get_name(op2), + arch_register_get_name(op1_reg), arch_register_get_name(op2_reg), arch_register_get_name(out))); } else { DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n), - arch_register_get_name(op1), + arch_register_get_name(op1_reg), arch_register_get_name(out))); } @@ -1013,7 +1072,7 @@ static int sim_unop(x87_state *state, ir_node *n, ir_op *op) { x87_simulator *sim = state->sim; const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, UNOP_IDX)); const arch_register_t *out = x87_get_irn_register(sim, n); - ia32_attr_t *attr; + ia32_x87_attr_t *attr; unsigned live = vfp_live_args_after(sim, n, REGMASK(out)); DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name)); @@ -1029,14 +1088,14 @@ static int sim_unop(x87_state *state, ir_node *n, ir_op *op) { else { /* operand is dead, bring it to tos */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, UNOP_IDX); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } } x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op)); out_idx = 0; - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); attr->x87[0] = op1 = &ia32_st_regs[0]; attr->x87[2] = out = &ia32_st_regs[0]; DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name)); @@ -1055,12 +1114,12 @@ static int sim_unop(x87_state *state, ir_node *n, ir_op *op) { */ static int sim_load(x87_state *state, ir_node *n, ir_op *op) { const arch_register_t *out = x87_get_irn_register(state->sim, n); - ia32_attr_t *attr; + ia32_x87_attr_t *attr; DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out))); x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op)); assert(out == x87_get_irn_register(state->sim, n)); - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); attr->x87[2] = out = &ia32_st_regs[0]; DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out))); @@ -1109,7 +1168,7 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { const arch_register_t *op2 = x87_get_irn_register(sim, val); unsigned live = vfp_live_args_after(sim, n, 0); int insn = NO_NODE_ADDED; - ia32_attr_t *attr; + ia32_x87_attr_t *attr; int op2_reg_idx, op2_idx, depth; int live_after_node; ir_mode *mode; @@ -1131,8 +1190,8 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { } else { op2_idx = x87_on_stack(state, op2_reg_idx); live_after_node = is_vfp_live(arch_register_get_index(op2), live); - assert(op2_idx >= 0); DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2))); + assert(op2_idx >= 0); } mode = get_ia32_ls_mode(n); @@ -1161,13 +1220,12 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { block = get_nodes_block(n); irg = get_irn_irg(n); - vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg)); + vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg), get_ia32_ls_mode(n)); /* copy all attributes */ set_ia32_frame_ent(vfld, get_ia32_frame_ent(n)); if (is_ia32_use_frame(n)) set_ia32_use_frame(vfld); - set_ia32_am_flavour(vfld, get_ia32_am_flavour(n)); set_ia32_op_type(vfld, ia32_am_Source); add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n)); set_ia32_am_sc(vfld, get_ia32_am_sc(n)); @@ -1197,7 +1255,7 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { } else { /* we can only store the tos to memory */ if (op2_idx != 0) - x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX); + x87_create_fxch(state, n, op2_idx); /* mode != mode_E -> use normal fst */ x87_patch_insn(n, op); @@ -1205,38 +1263,19 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { } else { /* we can only store the tos to memory */ if (op2_idx != 0) - x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX); + x87_create_fxch(state, n, op2_idx); x87_pop(state); x87_patch_insn(n, op_p); } - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); attr->x87[1] = op2 = &ia32_st_regs[0]; DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2))); return insn; } /* sim_store */ -/** - * Simulate a virtual Phi. - * Just for cosmetic reasons change the mode of Phi nodes to mode_E. - * - * @param state the x87 state - * @param n the node that should be simulated (and patched) - * @param arch_env the architecture environment - * - * @return NO_NODE_ADDED - */ -static int sim_Phi(x87_state *state, ir_node *n, const arch_env_t *arch_env) { - ir_mode *mode = get_irn_mode(n); - - if (mode_is_float(mode)) - set_irn_mode(n, mode_E); - - return NO_NODE_ADDED; -} /* sim_Phi */ - #define _GEN_BINOP(op, rev) \ static int sim_##op(x87_state *state, ir_node *n) { \ exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \ @@ -1272,9 +1311,6 @@ GEN_BINOP(fprem) GEN_UNOP(fabs) GEN_UNOP(fchs) -GEN_UNOP(fsin) -GEN_UNOP(fcos) -GEN_UNOP(fsqrt) GEN_LOAD(fld) GEN_LOAD(fild) @@ -1292,15 +1328,17 @@ GEN_STORE(fist) * * @return NO_NODE_ADDED */ -static int sim_fCondJmp(x87_state *state, ir_node *n) { +static int sim_fCmpJmp(x87_state *state, ir_node *n) { int op1_idx; int op2_idx = -1; int pop_cnt = 0; - ia32_attr_t *attr; + ia32_x87_attr_t *attr; ir_op *dst; x87_simulator *sim = state->sim; - const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1)); - const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2)); + ir_node *op1_node = get_irn_n(n, n_ia32_vfCmpJmp_left); + ir_node *op2_node = get_irn_n(n, n_ia32_vfCmpJmp_right); + const arch_register_t *op1 = x87_get_irn_register(sim, op1_node); + const arch_register_t *op2 = x87_get_irn_register(sim, op2_node); int reg_index_1 = arch_register_get_index(op1); int reg_index_2 = arch_register_get_index(op2); unsigned live = vfp_live_args_after(sim, n, 0); @@ -1334,7 +1372,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { dst = op_ia32_fcomrJmp; } else { /* bring the first one to tos */ - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); if (op2_idx == 0) op2_idx = op1_idx; op1_idx = 0; @@ -1346,7 +1384,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { This means further, op1_idx != op2_idx. */ assert(op1_idx != op2_idx); if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); if (op2_idx == 0) op2_idx = op1_idx; op1_idx = 0; @@ -1362,7 +1400,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { This means further, op1_idx != op2_idx. */ assert(op1_idx != op2_idx); if (op2_idx != 0) { - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); if (op1_idx == 0) op1_idx = op2_idx; op2_idx = 0; @@ -1375,7 +1413,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { if (op1_idx == op2_idx) { /* identically, one pop needed */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; op2_idx = 0; } @@ -1389,7 +1427,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { /* good, second operand is already in the right place, move the first */ if (op1_idx != 0) { /* bring the first on top */ - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); assert(op2_idx != 0); op1_idx = 0; } @@ -1400,7 +1438,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { /* good, first operand is already in the right place, move the second */ if (op2_idx != 0) { /* bring the first on top */ - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); assert(op1_idx != 0); op2_idx = 0; } @@ -1410,31 +1448,31 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { /* if one is already the TOS, we need two fxch */ if (op1_idx == 0) { /* first one is TOS, move to st(1) */ - x87_create_fxch(state, n, 1, BINOP_IDX_1); + x87_create_fxch(state, n, 1); assert(op2_idx != 1); op1_idx = 1; - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); op2_idx = 0; /* res = op X tos, pop, pop */ dst = op_ia32_fcomrppJmp; pop_cnt = 2; } else if (op2_idx == 0) { /* second one is TOS, move to st(1) */ - x87_create_fxch(state, n, 1, BINOP_IDX_2); + x87_create_fxch(state, n, 1); assert(op1_idx != 1); op2_idx = 1; - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; /* res = tos X op, pop, pop */ dst = op_ia32_fcomppJmp; pop_cnt = 2; } else { /* none of them is either TOS or st(1), 3 fxch needed */ - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); assert(op1_idx != 0); - x87_create_fxch(state, n, 1, BINOP_IDX_2); + x87_create_fxch(state, n, 1); op2_idx = 1; - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; /* res = tos X op, pop, pop */ dst = op_ia32_fcomppJmp; @@ -1448,14 +1486,14 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { if (is_vfp_live(arch_register_get_index(op1), live)) { /* first operand is live: bring it to TOS */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } dst = op_ia32_fcomJmp; } else { /* first operand is dead: bring it to tos */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } dst = op_ia32_fcompJmp; @@ -1471,7 +1509,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { x87_pop(state); /* patch the operation */ - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); op1 = &ia32_st_regs[op1_idx]; attr->x87[0] = op1; if (op2_idx >= 0) { @@ -1490,6 +1528,61 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { return NO_NODE_ADDED; } /* sim_fCondJmp */ +static +int sim_Keep(x87_state *state, ir_node *node) +{ + const ir_node *op; + const arch_register_t *op_reg; + int reg_id; + int op_stack_idx; + unsigned live; + int i, arity; + int node_added = NO_NODE_ADDED; + + DB((dbg, LEVEL_1, ">>> %+F\n", node)); + + arity = get_irn_arity(node); + for(i = 0; i < arity; ++i) { + op = get_irn_n(node, i); + op_reg = arch_get_irn_register(state->sim->arch_env, op); + if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp]) + continue; + + reg_id = arch_register_get_index(op_reg); + live = vfp_live_args_after(state->sim, node, 0); + + op_stack_idx = x87_on_stack(state, reg_id); + if(op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) { + x87_create_fpop(state, sched_next(node), 1); + node_added = NODE_ADDED; + } + } + + DB((dbg, LEVEL_1, "Stack after: ")); + DEBUG_ONLY(x87_dump_stack(state)); + + return node_added; +} + +static +void keep_float_node_alive(x87_state *state, ir_node *node) +{ + ir_graph *irg; + ir_node *block; + ir_node *in[1]; + ir_node *keep; + const arch_register_class_t *cls; + + irg = get_irn_irg(node); + block = get_nodes_block(node); + cls = arch_get_irn_reg_class(state->sim->arch_env, node, -1); + in[0] = node; + keep = be_new_Keep(cls, irg, block, 1, in); + + assert(sched_is_scheduled(node)); + sched_add_after(node, keep); +} + /** * Create a copy of a node. Recreate the node if it's a constant. * @@ -1509,7 +1602,7 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) { ir_node *res; const arch_register_t *out; const arch_register_t *op1; - ia32_attr_t *attr; + ia32_x87_attr_t *attr; /* Do not copy constants, recreate them. */ switch (get_ia32_irn_opcode(pred)) { @@ -1548,7 +1641,7 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) { x87_push(state, arch_register_get_index(out), res); - attr = get_ia32_attr(res); + attr = get_ia32_x87_attr(res); attr->x87[2] = &ia32_st_regs[0]; } else { int op1_idx = x87_on_stack(state, arch_register_get_index(op1)); @@ -1557,7 +1650,7 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) { x87_push(state, arch_register_get_index(out), res); - attr = get_ia32_attr(res); + attr = get_ia32_x87_attr(res); attr->x87[0] = &ia32_st_regs[op1_idx]; attr->x87[2] = &ia32_st_regs[0]; } @@ -1575,24 +1668,23 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) { * @return NO_NODE_ADDED */ static int sim_Copy(x87_state *state, ir_node *n) { - x87_simulator *sim; - ir_node *pred; - const arch_register_t *out; - const arch_register_t *op1; - ir_node *node, *next; - ia32_attr_t *attr; - int op1_idx, out_idx; - unsigned live; - - ir_mode *mode = get_irn_mode(n); - - if (!mode_is_float(mode)) + x87_simulator *sim = state->sim; + ir_node *pred; + const arch_register_t *out; + const arch_register_t *op1; + const arch_register_class_t *class; + ir_node *node, *next; + ia32_x87_attr_t *attr; + int op1_idx, out_idx; + unsigned live; + + class = arch_get_irn_reg_class(sim->arch_env, n, -1); + if (class->regs != ia32_vfp_regs) return 0; - sim = state->sim; pred = get_irn_n(n, 0); - out = x87_get_irn_register(sim, n); - op1 = x87_get_irn_register(sim, pred); + out = x87_get_irn_register(sim, n); + op1 = x87_get_irn_register(sim, pred); live = vfp_live_args_after(sim, n, REGMASK(out)); DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, @@ -1619,14 +1711,27 @@ static int sim_Copy(x87_state *state, ir_node *n) { op1_idx = x87_on_stack(state, arch_register_get_index(op1)); if (is_vfp_live(arch_register_get_index(op1), live)) { + ir_node *pred = get_irn_n(n, 0); + /* Operand is still live, a real copy. We need here an fpush that can hold a a register, so use the fpushCopy or recreate constants */ node = create_Copy(state, n); + /* We have to make sure the old value doesn't go dead (which can happen + * when we recreate constants). As the simulator expected that value in + * the pred blocks. This is unfortunate as removing it would save us 1 + * instruction, but we would have to rerun all the simulation to get + * this correct... + */ next = sched_next(n); sched_remove(n); exchange(n, node); sched_add_before(next, node); + + if(get_irn_n_edges(pred) == 0) { + keep_float_node_alive(state, pred); + } + DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name, arch_get_irn_register(sim->arch_env, node)->name)); } else { @@ -1640,7 +1745,7 @@ static int sim_Copy(x87_state *state, ir_node *n) { if (out_idx == 0) { /* best case, simple remove and rename */ x87_patch_insn(n, op_ia32_Pop); - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); attr->x87[0] = op1 = &ia32_st_regs[0]; x87_pop(state); @@ -1648,11 +1753,11 @@ static int sim_Copy(x87_state *state, ir_node *n) { } else { /* move op1 to tos, store and pop it */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, 0); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } x87_patch_insn(n, op_ia32_Pop); - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); attr->x87[0] = op1 = &ia32_st_regs[out_idx]; x87_pop(state); @@ -1675,11 +1780,10 @@ static int sim_Copy(x87_state *state, ir_node *n) { } /* sim_Copy */ /** - * Returns the result proj of the call, or NULL if the result is not used + * Returns the result proj of the call */ static ir_node *get_call_result_proj(ir_node *call) { const ir_edge_t *edge; - ir_node *resproj = NULL; /* search the result proj */ foreach_out_edge(call, edge) { @@ -1687,23 +1791,10 @@ static ir_node *get_call_result_proj(ir_node *call) { long pn = get_Proj_proj(proj); if (pn == pn_be_Call_first_res) { - resproj = proj; - break; - } - } - if (resproj == NULL) { - return NULL; - } - - /* the result proj is connected to a Keep and maybe other nodes */ - foreach_out_edge(resproj, edge) { - ir_node *pred = get_edge_src_irn(edge); - if (!be_is_Keep(pred)) { - return resproj; + return proj; } } - /* only be_Keep found, so result is not used */ return NULL; } /* get_call_result_proj */ @@ -1716,18 +1807,22 @@ static ir_node *get_call_result_proj(ir_node *call) { * * @return NO_NODE_ADDED */ -static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) { +static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) +{ ir_type *call_tp = be_Call_get_type(n); ir_type *res_type; ir_mode *mode; ir_node *resproj; const arch_register_t *reg; + (void) arch_env; + + DB((dbg, LEVEL_1, ">>> %+F\n", n)); /* at the begin of a call the x87 state should be empty */ assert(state->depth == 0 && "stack not empty before call"); if (get_method_n_ress(call_tp) <= 0) - return NO_NODE_ADDED; + goto end_call; /* * If the called function returns a float, it is returned in st(0). @@ -1738,15 +1833,18 @@ static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) { mode = get_type_mode(res_type); if (mode == NULL || !mode_is_float(mode)) - return NO_NODE_ADDED; + goto end_call; resproj = get_call_result_proj(n); - if (resproj == NULL) - return NO_NODE_ADDED; + assert(resproj != NULL); reg = x87_get_irn_register(state->sim, resproj); x87_push(state, arch_register_get_index(reg), resproj); +end_call: + DB((dbg, LEVEL_1, "Stack after: ")); + DEBUG_ONLY(x87_dump_stack(state)); + return NO_NODE_ADDED; } /* sim_Call */ @@ -1860,6 +1958,42 @@ static int sim_Perm(x87_state *state, ir_node *irn) { return NO_NODE_ADDED; } /* sim_Perm */ +static int sim_Barrier(x87_state *state, ir_node *node) { + //const arch_env_t *arch_env = state->sim->arch_env; + int i, arity; + + /* materialize unknown if needed */ + arity = get_irn_arity(node); + for(i = 0; i < arity; ++i) { + const arch_register_t *reg; + ir_node *zero; + ir_node *block; + ia32_x87_attr_t *attr; + ir_node *in = get_irn_n(node, i); + + if(!is_ia32_Unknown_VFP(in)) + continue; + + /* TODO: not completely correct... */ + reg = &ia32_vfp_regs[REG_VFP_UKNWN]; + + /* create a zero */ + block = get_nodes_block(node); + zero = new_rd_ia32_fldz(NULL, current_ir_graph, block, mode_E); + x87_push(state, arch_register_get_index(reg), zero); + + attr = get_ia32_x87_attr(zero); + attr->x87[2] = &ia32_st_regs[0]; + + sched_add_before(node, zero); + + set_irn_n(node, i, zero); + } + + return NO_NODE_ADDED; +} + + /** * Kill any dead registers at block start by popping them from the stack. * @@ -1909,10 +2043,8 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * if (keep) x87_set_st(state, -1, keep, i); - keep = x87_create_fxch(state, first_insn, i, -1); + x87_create_fxch(state, first_insn, i); } - else if (! keep) - keep = x87_get_st_node(state, 0); if ((kill_mask & 3) == 3) { /* we can do a double-pop */ @@ -1925,13 +2057,50 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * depth -= num_pop; kill_mask >>= num_pop; - keep = x87_create_fpop(state, first_insn, num_pop, keep); + keep = x87_create_fpop(state, first_insn, num_pop); } keep_alive(keep); } return state; } /* x87_kill_deads */ +/** + * If we have PhiEs with unknown operands then we have to make sure that some + * value is actually put onto the stack. + */ +static void fix_unknown_phis(x87_state *state, ir_node *block, + ir_node *pred_block, int pos) +{ + ir_node *node, *op; + + sched_foreach(block, node) { + ir_node *zero; + const arch_register_t *reg; + ia32_x87_attr_t *attr; + + if(!is_Phi(node)) + break; + + op = get_Phi_pred(node, pos); + if(!is_ia32_Unknown_VFP(op)) + continue; + + reg = arch_get_irn_register(state->sim->arch_env, node); + + /* create a zero at end of pred block */ + zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E); + x87_push(state, arch_register_get_index(reg), zero); + + attr = get_ia32_x87_attr(zero); + attr->x87[2] = &ia32_st_regs[0]; + + assert(is_ia32_fldz(zero)); + sched_add_before(sched_last(pred_block), zero); + + set_Phi_pred(node, pos, zero); + } +} + /** * Run a simulation and fix all virtual instructions for a block. * @@ -1956,6 +2125,8 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { /* at block begin, kill all dead registers */ state = x87_kill_deads(sim, block, state); + /* create a new state, will be changed */ + state = x87_clone_state(sim, state); /* beware, n might change */ for (n = sched_first(block); !sched_is_end(n); n = next) { @@ -1969,12 +2140,6 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { func = (sim_func)op->ops.generic; - /* have work to do */ - if (state == bl_state->begin) { - /* create a new state, will be changed */ - state = x87_clone_state(sim, state); - } - /* simulate it */ node_inserted = (*func)(state, n); @@ -1990,6 +2155,8 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { start_block = get_irg_start_block(get_irn_irg(block)); + DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state)); + /* check if the state must be shuffled */ foreach_block_succ(block, edge) { ir_node *succ = get_edge_src_irn(edge); @@ -2000,10 +2167,16 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { succ_state = x87_get_bl_state(sim, succ); + fix_unknown_phis(state, succ, block, get_edge_src_pos(edge)); + if (succ_state->begin == NULL) { + DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ)); + DEBUG_ONLY(x87_dump_stack(state)); succ_state->begin = state; + waitq_put(sim->worklist, succ); } else { + DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ)); /* There is already a begin state for the successor, bad. Do the necessary permutations. Note that critical edges are removed, so this is always possible: @@ -2014,8 +2187,6 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { } } bl_state->end = state; - - DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state)); } /* x87_simulate_block */ /** @@ -2054,19 +2225,17 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg, ASSOC_IA32(fprem); ASSOC_IA32(fabs); ASSOC_IA32(fchs); - ASSOC_IA32(fsin); - ASSOC_IA32(fcos); - ASSOC_IA32(fsqrt); ASSOC_IA32(fist); ASSOC_IA32(fst); - ASSOC_IA32(fCondJmp); + ASSOC_IA32(fCmpJmp); ASSOC_BE(Copy); ASSOC_BE(Call); ASSOC_BE(Spill); ASSOC_BE(Reload); ASSOC_BE(Return); ASSOC_BE(Perm); - ASSOC(Phi); + ASSOC_BE(Keep); + ASSOC_BE(Barrier); #undef ASSOC_BE #undef ASSOC_IA32 #undef ASSOC @@ -2110,7 +2279,7 @@ void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) { x87_init_simulator(&sim, irg, arch_env); start_block = get_irg_start_block(irg); - bl_state = x87_get_bl_state(&sim, start_block); + bl_state = x87_get_bl_state(&sim, start_block); /* start with the empty state */ bl_state->begin = empty; @@ -2119,9 +2288,10 @@ void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) { sim.worklist = new_waitq(); waitq_put(sim.worklist, start_block); - be_invalidate_liveness(birg); be_assure_liveness(birg); sim.lv = be_get_birg_liveness(birg); +// sim.lv = be_liveness(be_get_birg_irg(birg)); + be_liveness_assure_sets(sim.lv); /* Calculate the liveness for all nodes. We must precalculate this info, * because the simulator adds new nodes (possible before Phi nodes) which