X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_x87.c;h=ca09d3b407a8dad9c3dd07548415b9017ab88ec0;hb=366e963a782fe9549838fd3492438ea6ea1f19ad;hp=9df86db77f95fe2595eaaea778c6529c9b91ea60;hpb=d57f9cb50b17f54d2a63a190b285467519a2af26;p=libfirm diff --git a/ir/be/ia32/ia32_x87.c b/ir/be/ia32/ia32_x87.c index 9df86db77..ca09d3b40 100644 --- a/ir/be/ia32/ia32_x87.c +++ b/ir/be/ia32/ia32_x87.c @@ -730,7 +730,6 @@ static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_ const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp]; const arch_env_t *arch_env = sim->arch_env; -#ifndef SCHEDULE_PROJS if (get_irn_mode(irn) == mode_T) { const ir_edge_t *edge; @@ -743,7 +742,6 @@ static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_ } } } -#endif if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) { const arch_register_t *reg = x87_get_irn_register(sim, irn); @@ -869,6 +867,15 @@ static void vfp_dump_live(vfp_liveness live) { #define XCHG(a, b) do { int t = (a); (a) = (b); (b) = t; } while (0) +/* Pseudocode: + + + + + + +*/ + /** * Simulate a virtual binop. * @@ -884,33 +891,50 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { ia32_x87_attr_t *attr; ir_node *patched_insn; ir_op *dst; - x87_simulator *sim = state->sim; - const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1)); - const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2)); - const arch_register_t *out = x87_get_irn_register(sim, n); - int reg_index_1 = arch_register_get_index(op1); - int reg_index_2 = arch_register_get_index(op2); - vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out)); + x87_simulator *sim = state->sim; + ir_node *op1 = get_irn_n(n, BINOP_IDX_1); + ir_node *op2 = get_irn_n(n, BINOP_IDX_2); + const arch_register_t *op1_reg = x87_get_irn_register(sim, op1); + const arch_register_t *op2_reg = x87_get_irn_register(sim, op2); + const arch_register_t *out = x87_get_irn_register(sim, n); + int reg_index_1 = arch_register_get_index(op1_reg); + int reg_index_2 = arch_register_get_index(op2_reg); + vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out)); + int op1_live_after; + int op2_live_after; DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n, - arch_register_get_name(op1), arch_register_get_name(op2), + arch_register_get_name(op1_reg), arch_register_get_name(op2_reg), arch_register_get_name(out))); DEBUG_ONLY(vfp_dump_live(live)); DB((dbg, LEVEL_1, "Stack before: ")); DEBUG_ONLY(x87_dump_stack(state)); - op1_idx = x87_on_stack(state, reg_index_1); - assert(op1_idx >= 0); + if(reg_index_1 == REG_VFP_UKNWN) { + op1_idx = 0; + op1_live_after = 1; + } else { + op1_idx = x87_on_stack(state, reg_index_1); + assert(op1_idx >= 0); + op1_live_after = is_vfp_live(arch_register_get_index(op1_reg), live); + } if (reg_index_2 != REG_VFP_NOREG) { - /* second operand is a vfp register */ - op2_idx = x87_on_stack(state, reg_index_2); - assert(op2_idx >= 0); + if(reg_index_2 == REG_VFP_UKNWN) { + op2_idx = 0; + op2_live_after = 1; + } else { + /* second operand is a vfp register */ + op2_idx = x87_on_stack(state, reg_index_2); + assert(op2_idx >= 0); + op2_live_after + = is_vfp_live(arch_register_get_index(op2_reg), live); + } - if (is_vfp_live(arch_register_get_index(op2), live)) { + if (op2_live_after) { /* Second operand is live. */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* Both operands are live: push the first one. This works even for op1 == op2. */ x87_create_fpush(state, n, op1_idx, BINOP_IDX_2); @@ -933,7 +957,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } } else { /* Second operand is dead. */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* First operand is live: bring second to tos. */ if (op2_idx != 0) { x87_create_fxch(state, n, op2_idx); @@ -987,7 +1011,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } } else { /* second operand is an address mode */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* first operand is live: push it here */ x87_create_fpush(state, n, op1_idx, BINOP_IDX_1); op1_idx = 0; @@ -1015,19 +1039,19 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { /* patch the operation */ attr = get_ia32_x87_attr(n); - attr->x87[0] = op1 = &ia32_st_regs[op1_idx]; + attr->x87[0] = op1_reg = &ia32_st_regs[op1_idx]; if (reg_index_2 != REG_VFP_NOREG) { - attr->x87[1] = op2 = &ia32_st_regs[op2_idx]; + attr->x87[1] = op2_reg = &ia32_st_regs[op2_idx]; } attr->x87[2] = out = &ia32_st_regs[out_idx]; if (reg_index_2 != REG_VFP_NOREG) { DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n), - arch_register_get_name(op1), arch_register_get_name(op2), + arch_register_get_name(op1_reg), arch_register_get_name(op2_reg), arch_register_get_name(out))); } else { DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n), - arch_register_get_name(op1), + arch_register_get_name(op1_reg), arch_register_get_name(out))); } @@ -1202,7 +1226,6 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { set_ia32_frame_ent(vfld, get_ia32_frame_ent(n)); if (is_ia32_use_frame(n)) set_ia32_use_frame(vfld); - set_ia32_am_flavour(vfld, get_ia32_am_flavour(n)); set_ia32_op_type(vfld, ia32_am_Source); add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n)); set_ia32_am_sc(vfld, get_ia32_am_sc(n)); @@ -1305,15 +1328,15 @@ GEN_STORE(fist) * * @return NO_NODE_ADDED */ -static int sim_fCondJmp(x87_state *state, ir_node *n) { +static int sim_fCmpJmp(x87_state *state, ir_node *n) { int op1_idx; int op2_idx = -1; int pop_cnt = 0; ia32_x87_attr_t *attr; ir_op *dst; x87_simulator *sim = state->sim; - ir_node *op1_node = get_irn_n(n, n_ia32_vfCondJmp_left); - ir_node *op2_node = get_irn_n(n, n_ia32_vfCondJmp_right); + ir_node *op1_node = get_irn_n(n, n_ia32_vfCmpJmp_left); + ir_node *op2_node = get_irn_n(n, n_ia32_vfCmpJmp_right); const arch_register_t *op1 = x87_get_irn_register(sim, op1_node); const arch_register_t *op2 = x87_get_irn_register(sim, op2_node); int reg_index_1 = arch_register_get_index(op1); @@ -1513,22 +1536,32 @@ int sim_Keep(x87_state *state, ir_node *node) int reg_id; int op_stack_idx; unsigned live; + int i, arity; + int node_added = NO_NODE_ADDED; - op = get_irn_n(node, 0); - op_reg = arch_get_irn_register(state->sim->arch_env, op); - if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp]) - return NO_NODE_ADDED; + DB((dbg, LEVEL_1, ">>> %+F\n", node)); + + arity = get_irn_arity(node); + for(i = 0; i < arity; ++i) { + op = get_irn_n(node, i); + op_reg = arch_get_irn_register(state->sim->arch_env, op); + if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp]) + continue; - reg_id = arch_register_get_index(op_reg); - live = vfp_live_args_after(state->sim, node, 0); + reg_id = arch_register_get_index(op_reg); + live = vfp_live_args_after(state->sim, node, 0); - op_stack_idx = x87_on_stack(state, reg_id); - if(op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) { - x87_create_fpop(state, sched_next(node), 1); - return NODE_ADDED; + op_stack_idx = x87_on_stack(state, reg_id); + if(op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) { + x87_create_fpop(state, sched_next(node), 1); + node_added = NODE_ADDED; + } } - return NO_NODE_ADDED; + DB((dbg, LEVEL_1, "Stack after: ")); + DEBUG_ONLY(x87_dump_stack(state)); + + return node_added; } static @@ -1635,24 +1668,23 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) { * @return NO_NODE_ADDED */ static int sim_Copy(x87_state *state, ir_node *n) { - x87_simulator *sim; - ir_node *pred; - const arch_register_t *out; - const arch_register_t *op1; - ir_node *node, *next; - ia32_x87_attr_t *attr; - int op1_idx, out_idx; - unsigned live; - - ir_mode *mode = get_irn_mode(n); - - if (!mode_is_float(mode)) + x87_simulator *sim = state->sim; + ir_node *pred; + const arch_register_t *out; + const arch_register_t *op1; + const arch_register_class_t *class; + ir_node *node, *next; + ia32_x87_attr_t *attr; + int op1_idx, out_idx; + unsigned live; + + class = arch_get_irn_reg_class(sim->arch_env, n, -1); + if (class->regs != ia32_vfp_regs) return 0; - sim = state->sim; pred = get_irn_n(n, 0); - out = x87_get_irn_register(sim, n); - op1 = x87_get_irn_register(sim, pred); + out = x87_get_irn_register(sim, n); + op1 = x87_get_irn_register(sim, pred); live = vfp_live_args_after(sim, n, REGMASK(out)); DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, @@ -1748,11 +1780,10 @@ static int sim_Copy(x87_state *state, ir_node *n) { } /* sim_Copy */ /** - * Returns the result proj of the call, or NULL if the result is not used + * Returns the result proj of the call */ static ir_node *get_call_result_proj(ir_node *call) { const ir_edge_t *edge; - ir_node *resproj = NULL; /* search the result proj */ foreach_out_edge(call, edge) { @@ -1760,23 +1791,10 @@ static ir_node *get_call_result_proj(ir_node *call) { long pn = get_Proj_proj(proj); if (pn == pn_be_Call_first_res) { - resproj = proj; - break; - } - } - if (resproj == NULL) { - return NULL; - } - - /* the result proj is connected to a Keep and maybe other nodes */ - foreach_out_edge(resproj, edge) { - ir_node *pred = get_edge_src_irn(edge); - if (!be_is_Keep(pred)) { - return resproj; + return proj; } } - /* only be_Keep found, so result is not used */ return NULL; } /* get_call_result_proj */ @@ -1798,11 +1816,13 @@ static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) const arch_register_t *reg; (void) arch_env; + DB((dbg, LEVEL_1, ">>> %+F\n", n)); + /* at the begin of a call the x87 state should be empty */ assert(state->depth == 0 && "stack not empty before call"); if (get_method_n_ress(call_tp) <= 0) - return NO_NODE_ADDED; + goto end_call; /* * If the called function returns a float, it is returned in st(0). @@ -1813,15 +1833,18 @@ static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) mode = get_type_mode(res_type); if (mode == NULL || !mode_is_float(mode)) - return NO_NODE_ADDED; + goto end_call; resproj = get_call_result_proj(n); - if (resproj == NULL) - return NO_NODE_ADDED; + assert(resproj != NULL); reg = x87_get_irn_register(state->sim, resproj); x87_push(state, arch_register_get_index(reg), resproj); +end_call: + DB((dbg, LEVEL_1, "Stack after: ")); + DEBUG_ONLY(x87_dump_stack(state)); + return NO_NODE_ADDED; } /* sim_Call */ @@ -1935,6 +1958,42 @@ static int sim_Perm(x87_state *state, ir_node *irn) { return NO_NODE_ADDED; } /* sim_Perm */ +static int sim_Barrier(x87_state *state, ir_node *node) { + //const arch_env_t *arch_env = state->sim->arch_env; + int i, arity; + + /* materialize unknown if needed */ + arity = get_irn_arity(node); + for(i = 0; i < arity; ++i) { + const arch_register_t *reg; + ir_node *zero; + ir_node *block; + ia32_x87_attr_t *attr; + ir_node *in = get_irn_n(node, i); + + if(!is_ia32_Unknown_VFP(in)) + continue; + + /* TODO: not completely correct... */ + reg = &ia32_vfp_regs[REG_VFP_UKNWN]; + + /* create a zero */ + block = get_nodes_block(node); + zero = new_rd_ia32_fldz(NULL, current_ir_graph, block, mode_E); + x87_push(state, arch_register_get_index(reg), zero); + + attr = get_ia32_x87_attr(zero); + attr->x87[2] = &ia32_st_regs[0]; + + sched_add_before(node, zero); + + set_irn_n(node, i, zero); + } + + return NO_NODE_ADDED; +} + + /** * Kill any dead registers at block start by popping them from the stack. * @@ -2066,6 +2125,8 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { /* at block begin, kill all dead registers */ state = x87_kill_deads(sim, block, state); + /* create a new state, will be changed */ + state = x87_clone_state(sim, state); /* beware, n might change */ for (n = sched_first(block); !sched_is_end(n); n = next) { @@ -2079,12 +2140,6 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { func = (sim_func)op->ops.generic; - /* have work to do */ - if (state == bl_state->begin) { - /* create a new state, will be changed */ - state = x87_clone_state(sim, state); - } - /* simulate it */ node_inserted = (*func)(state, n); @@ -2100,6 +2155,8 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { start_block = get_irg_start_block(get_irn_irg(block)); + DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state)); + /* check if the state must be shuffled */ foreach_block_succ(block, edge) { ir_node *succ = get_edge_src_irn(edge); @@ -2113,10 +2170,13 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { fix_unknown_phis(state, succ, block, get_edge_src_pos(edge)); if (succ_state->begin == NULL) { + DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ)); + DEBUG_ONLY(x87_dump_stack(state)); succ_state->begin = state; waitq_put(sim->worklist, succ); } else { + DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ)); /* There is already a begin state for the successor, bad. Do the necessary permutations. Note that critical edges are removed, so this is always possible: @@ -2127,8 +2187,6 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { } } bl_state->end = state; - - DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state)); } /* x87_simulate_block */ /** @@ -2169,7 +2227,7 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg, ASSOC_IA32(fchs); ASSOC_IA32(fist); ASSOC_IA32(fst); - ASSOC_IA32(fCondJmp); + ASSOC_IA32(fCmpJmp); ASSOC_BE(Copy); ASSOC_BE(Call); ASSOC_BE(Spill); @@ -2177,6 +2235,7 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg, ASSOC_BE(Return); ASSOC_BE(Perm); ASSOC_BE(Keep); + ASSOC_BE(Barrier); #undef ASSOC_BE #undef ASSOC_IA32 #undef ASSOC @@ -2220,7 +2279,7 @@ void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) { x87_init_simulator(&sim, irg, arch_env); start_block = get_irg_start_block(irg); - bl_state = x87_get_bl_state(&sim, start_block); + bl_state = x87_get_bl_state(&sim, start_block); /* start with the empty state */ bl_state->begin = empty;