X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_x87.c;h=ca09d3b407a8dad9c3dd07548415b9017ab88ec0;hb=366e963a782fe9549838fd3492438ea6ea1f19ad;hp=5eebfe0b642034cadaad3a552aa42388fdce6a8b;hpb=2adf84106c02caf097c2d6cf1764706bdc437bcc;p=libfirm diff --git a/ir/be/ia32/ia32_x87.c b/ir/be/ia32/ia32_x87.c index 5eebfe0b6..ca09d3b40 100644 --- a/ir/be/ia32/ia32_x87.c +++ b/ir/be/ia32/ia32_x87.c @@ -1,10 +1,28 @@ -/** - * This file implements the x87 support and virtual to stack - * register translation for the ia32 backend. +/* + * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. * - * @author: Michael Beck + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. * - * $Id$ + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +/** + * @file + * @brief This file implements the x87 support and virtual to stack + * register translation for the ia32 backend. + * @author Michael Beck + * @version $Id$ */ #ifdef HAVE_CONFIG_H #include "config.h" @@ -87,10 +105,23 @@ typedef struct _x87_state { } x87_state; /** An empty state, used for blocks without fp instructions. */ -static x87_state _empty = { { {0, NULL}, }, 0, 0 }; +static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL }; static x87_state *empty = (x87_state *)&_empty; -/** The type of an instruction simulator function. */ +enum { + NO_NODE_ADDED = 0, /**< No node was added. */ + NODE_ADDED = 1 /**< A node was added by the simulator in the schedule. */ +}; + +/** + * The type of an instruction simulator function. + * + * @param state the x87 state + * @param n the node to be simulated + * + * @return NODE_ADDED if a node was added AFTER n in schedule, + * NO_NODE_ADDED else + */ typedef int (*sim_func)(x87_state *state, ir_node *n); /** @@ -116,7 +147,7 @@ struct _x87_simulator { be_lv_t *lv; /**< intrablock liveness. */ vfp_liveness *live; /**< Liveness information. */ unsigned n_idx; /**< The cached get_irg_last_idx() result. */ - waitq *worklist; /**< list of blocks to process. */ + waitq *worklist; /**< Worklist of blocks that must be processed. */ }; /** @@ -128,20 +159,7 @@ struct _x87_simulator { */ static int x87_get_depth(const x87_state *state) { return state->depth; -} - -#if 0 -/** - * Check if the state is empty. - * - * @param state the x87 state - * - * returns non-zero if the x87 stack is empty - */ -static int x87_state_is_empty(const x87_state *state) { - return state->depth == 0; -} -#endif +} /* x87_get_depth */ /** * Return the virtual register index at st(pos). @@ -154,7 +172,7 @@ static int x87_state_is_empty(const x87_state *state) { static int x87_get_st_reg(const x87_state *state, int pos) { assert(pos < state->depth); return state->st[MASK_TOS(state->tos + pos)].reg_idx; -} +} /* x87_get_st_reg */ /** * Return the node at st(pos). @@ -214,18 +232,6 @@ static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node) { x87_set_st(state, reg_idx, node, 0); } /* x87_set_tos */ -#if 0 -/** - * Flush the x87 stack. - * - * @param state the x87 state - */ -static void x87_flush(x87_state *state) { - state->depth = 0; - state->tos = 0; -} /* x87_flush */ -#endif - /** * Swap st(0) with st(pos). * @@ -280,7 +286,7 @@ static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) { } /* x87_push_dbl */ /** - * Push a virtual Register onto the stack, double pushes are NOT allowed.. + * Push a virtual Register onto the stack, double pushes are NOT allowed. * * @param state the x87 state * @param reg_idx the register vfp index @@ -295,6 +301,8 @@ static void x87_push(x87_state *state, int reg_idx, ir_node *node) { /** * Pop a virtual Register from the stack. + * + * @param state the x87 state */ static void x87_pop(x87_state *state) { assert(state->depth > 0 && "stack underrun"); @@ -342,22 +350,6 @@ static x87_state *x87_alloc_state(x87_simulator *sim) { return res; } /* x87_alloc_state */ -#if 0 -/** - * Create a new empty x87 state. - * - * @param sim the x87 simulator handle - * - * @return a new empty x87 state - */ -static x87_state *x87_alloc_empty_state(x87_simulator *sim) { - x87_state *res = x87_alloc_state(sim); - - x87_flush(res); - return res; -} /* x87_alloc_empty_state */ -#endif - /** * Clone a x87 state. * @@ -375,7 +367,7 @@ static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) { /** * Patch a virtual instruction into a x87 one and return - * the value node. + * the node representing the result value. * * @param n the IR node to patch * @param op the x87 opcode to patch in @@ -400,8 +392,7 @@ static ir_node *x87_patch_insn(ir_node *n, ir_op *op) { } } } - } - else if (mode_is_float(mode)) + } else if (mode_is_float(mode)) set_irn_mode(n, mode_E); return res; } /* x87_patch_insn */ @@ -436,7 +427,7 @@ static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, co res = arch_get_irn_register(sim->arch_env, irn); assert(res->reg_class->regs == ia32_vfp_regs); return res; -} +} /* x87_get_irn_register */ /* -------------- x87 perm --------------- */ @@ -452,13 +443,12 @@ static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, co * * @return the fxch node */ -static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) -{ +static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) { ir_node *fxch; - ia32_attr_t *attr; + ia32_x87_attr_t *attr; fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block, mode_E); - attr = get_ia32_attr(fxch); + attr = get_ia32_x87_attr(fxch); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -485,11 +475,16 @@ static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) * * @return state */ -static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, x87_state *state, ir_node *dst_block, const x87_state *dst_state) { +static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, + x87_state *state, ir_node *dst_block, + const x87_state *dst_state) +{ int i, n_cycles, k, ri; unsigned cycles[4], all_mask; char cycle_idx[4][8]; ir_node *fxch, *before, *after; + (void) sim; + (void) dst_block; assert(state->depth == dst_state->depth); @@ -610,20 +605,20 @@ static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, x87_state *sta * @param state the x87 state * @param n the node after the fxch * @param pos exchange st(pos) with st(0) - * @param op_idx if >= 0, replace input op_idx of n with the fxch result * * @return the fxch */ -static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos, int op_idx) { - ir_node *fxch; - ia32_attr_t *attr; - ir_graph *irg = get_irn_irg(n); - ir_node *block = get_nodes_block(n); +static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos) +{ + ir_node *fxch; + ia32_x87_attr_t *attr; + ir_graph *irg = get_irn_irg(n); + ir_node *block = get_nodes_block(n); x87_fxch(state, pos); fxch = new_rd_ia32_fxch(NULL, irg, block, mode_E); - attr = get_ia32_attr(fxch); + attr = get_ia32_x87_attr(fxch); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -644,13 +639,13 @@ static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos, int op_id */ static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) { ir_node *fpush, *pred = get_irn_n(n, op_idx); - ia32_attr_t *attr; + ia32_x87_attr_t *attr; const arch_register_t *out = x87_get_irn_register(state->sim, pred); x87_push_dbl(state, arch_register_get_index(out), pred); fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n), mode_E); - attr = get_ia32_attr(fpush); + attr = get_ia32_x87_attr(fpush); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -666,20 +661,18 @@ static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) * @param state the x87 state * @param n the node after the fpop * @param num pop 1 or 2 values - * @param pred node to use as predecessor of the fpop * * @return the fpop node */ -static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num, ir_node *pred) { - ir_node *fpop = pred; - ia32_attr_t *attr; +static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num) +{ + ir_node *fpop; + ia32_x87_attr_t *attr; while (num > 0) { - keep_alive(pred); - x87_pop(state); fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n), mode_E); - attr = get_ia32_attr(fpop); + attr = get_ia32_x87_attr(fpop); attr->x87[0] = &ia32_st_regs[0]; attr->x87[1] = &ia32_st_regs[0]; attr->x87[2] = &ia32_st_regs[0]; @@ -688,7 +681,6 @@ static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num, ir_node * sched_add_before(n, fpop); DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name)); - pred = fpop; --num; } return fpop; @@ -738,9 +730,22 @@ static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_ const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp]; const arch_env_t *arch_env = sim->arch_env; + if (get_irn_mode(irn) == mode_T) { + const ir_edge_t *edge; + + foreach_out_edge(irn, edge) { + ir_node *proj = get_edge_src_irn(edge); + + if (arch_irn_consider_in_reg_alloc(arch_env, cls, proj)) { + const arch_register_t *reg = x87_get_irn_register(sim, proj); + live &= ~(1 << arch_register_get_index(reg)); + } + } + } + if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) { - const arch_register_t *reg = x87_get_irn_register(sim, irn); - live &= ~(1 << arch_register_get_index(reg)); + const arch_register_t *reg = x87_get_irn_register(sim, irn); + live &= ~(1 << arch_register_get_index(reg)); } for (i = 0, n = get_irn_arity(irn); i < n; ++i) { @@ -862,46 +867,74 @@ static void vfp_dump_live(vfp_liveness live) { #define XCHG(a, b) do { int t = (a); (a) = (b); (b) = t; } while (0) +/* Pseudocode: + + + + + + +*/ + /** * Simulate a virtual binop. * * @param state the x87 state * @param n the node that should be simulated (and patched) * @param tmpl the template containing the 4 possible x87 opcodes + * + * @return NO_NODE_ADDED */ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { int op2_idx = 0, op1_idx; int out_idx, do_pop = 0; - ia32_attr_t *attr; + ia32_x87_attr_t *attr; ir_node *patched_insn; ir_op *dst; - x87_simulator *sim = state->sim; - const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1)); - const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2)); - const arch_register_t *out = x87_get_irn_register(sim, n); - int reg_index_1 = arch_register_get_index(op1); - int reg_index_2 = arch_register_get_index(op2); - vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out)); + x87_simulator *sim = state->sim; + ir_node *op1 = get_irn_n(n, BINOP_IDX_1); + ir_node *op2 = get_irn_n(n, BINOP_IDX_2); + const arch_register_t *op1_reg = x87_get_irn_register(sim, op1); + const arch_register_t *op2_reg = x87_get_irn_register(sim, op2); + const arch_register_t *out = x87_get_irn_register(sim, n); + int reg_index_1 = arch_register_get_index(op1_reg); + int reg_index_2 = arch_register_get_index(op2_reg); + vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out)); + int op1_live_after; + int op2_live_after; DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n, - arch_register_get_name(op1), arch_register_get_name(op2), + arch_register_get_name(op1_reg), arch_register_get_name(op2_reg), arch_register_get_name(out))); DEBUG_ONLY(vfp_dump_live(live)); DB((dbg, LEVEL_1, "Stack before: ")); DEBUG_ONLY(x87_dump_stack(state)); - op1_idx = x87_on_stack(state, reg_index_1); - assert(op1_idx >= 0); + if(reg_index_1 == REG_VFP_UKNWN) { + op1_idx = 0; + op1_live_after = 1; + } else { + op1_idx = x87_on_stack(state, reg_index_1); + assert(op1_idx >= 0); + op1_live_after = is_vfp_live(arch_register_get_index(op1_reg), live); + } if (reg_index_2 != REG_VFP_NOREG) { - /* second operand is a vfp register */ - op2_idx = x87_on_stack(state, reg_index_2); - assert(op2_idx >= 0); + if(reg_index_2 == REG_VFP_UKNWN) { + op2_idx = 0; + op2_live_after = 1; + } else { + /* second operand is a vfp register */ + op2_idx = x87_on_stack(state, reg_index_2); + assert(op2_idx >= 0); + op2_live_after + = is_vfp_live(arch_register_get_index(op2_reg), live); + } - if (is_vfp_live(arch_register_get_index(op2), live)) { + if (op2_live_after) { /* Second operand is live. */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* Both operands are live: push the first one. This works even for op1 == op2. */ x87_create_fpush(state, n, op1_idx, BINOP_IDX_2); @@ -913,7 +946,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } else { /* Second live, first operand is dead here, bring it to tos. */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); if (op2_idx == 0) op2_idx = op1_idx; op1_idx = 0; @@ -924,10 +957,10 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } } else { /* Second operand is dead. */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* First operand is live: bring second to tos. */ if (op2_idx != 0) { - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); if (op1_idx == 0) op1_idx = op2_idx; op2_idx = 0; @@ -957,7 +990,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { out_idx = op2_idx; } else { /* Bring the second on top. */ - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); if (op1_idx == op2_idx) { /* Both are identically and on tos now, no pop needed. */ op1_idx = 0; @@ -978,7 +1011,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } } else { /* second operand is an address mode */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* first operand is live: push it here */ x87_create_fpush(state, n, op1_idx, BINOP_IDX_1); op1_idx = 0; @@ -988,7 +1021,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } else { /* first operand is dead: bring it to tos */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } @@ -1005,24 +1038,24 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } /* patch the operation */ - attr = get_ia32_attr(n); - attr->x87[0] = op1 = &ia32_st_regs[op1_idx]; + attr = get_ia32_x87_attr(n); + attr->x87[0] = op1_reg = &ia32_st_regs[op1_idx]; if (reg_index_2 != REG_VFP_NOREG) { - attr->x87[1] = op2 = &ia32_st_regs[op2_idx]; + attr->x87[1] = op2_reg = &ia32_st_regs[op2_idx]; } attr->x87[2] = out = &ia32_st_regs[out_idx]; if (reg_index_2 != REG_VFP_NOREG) { DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n), - arch_register_get_name(op1), arch_register_get_name(op2), + arch_register_get_name(op1_reg), arch_register_get_name(op2_reg), arch_register_get_name(out))); } else { DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n), - arch_register_get_name(op1), + arch_register_get_name(op1_reg), arch_register_get_name(out))); } - return 0; + return NO_NODE_ADDED; } /* sim_binop */ /** @@ -1031,13 +1064,15 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { * @param state the x87 state * @param n the node that should be simulated (and patched) * @param op the x87 opcode that will replace n's opcode + * + * @return NO_NODE_ADDED */ static int sim_unop(x87_state *state, ir_node *n, ir_op *op) { int op1_idx, out_idx; x87_simulator *sim = state->sim; const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, UNOP_IDX)); const arch_register_t *out = x87_get_irn_register(sim, n); - ia32_attr_t *attr; + ia32_x87_attr_t *attr; unsigned live = vfp_live_args_after(sim, n, REGMASK(out)); DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name)); @@ -1053,19 +1088,19 @@ static int sim_unop(x87_state *state, ir_node *n, ir_op *op) { else { /* operand is dead, bring it to tos */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, UNOP_IDX); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } } x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op)); out_idx = 0; - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); attr->x87[0] = op1 = &ia32_st_regs[0]; attr->x87[2] = out = &ia32_st_regs[0]; DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name)); - return 0; + return NO_NODE_ADDED; } /* sim_unop */ /** @@ -1074,19 +1109,21 @@ static int sim_unop(x87_state *state, ir_node *n, ir_op *op) { * @param state the x87 state * @param n the node that should be simulated (and patched) * @param op the x87 opcode that will replace n's opcode + * + * @return NO_NODE_ADDED */ static int sim_load(x87_state *state, ir_node *n, ir_op *op) { const arch_register_t *out = x87_get_irn_register(state->sim, n); - ia32_attr_t *attr; + ia32_x87_attr_t *attr; DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out))); x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op)); assert(out == x87_get_irn_register(state->sim, n)); - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); attr->x87[2] = out = &ia32_st_regs[0]; DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out))); - return 0; + return NO_NODE_ADDED; } /* sim_load */ /** @@ -1130,21 +1167,21 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { ir_node *val = get_irn_n(n, STORE_VAL_IDX); const arch_register_t *op2 = x87_get_irn_register(sim, val); unsigned live = vfp_live_args_after(sim, n, 0); - int insn = 0; - ia32_attr_t *attr; + int insn = NO_NODE_ADDED; + ia32_x87_attr_t *attr; int op2_reg_idx, op2_idx, depth; int live_after_node; ir_mode *mode; op2_reg_idx = arch_register_get_index(op2); if (op2_reg_idx == REG_VFP_UKNWN) { - // just take any value from stack + /* just take any value from stack */ if(state->depth > 0) { op2_idx = 0; DEBUG_ONLY(op2 = NULL); live_after_node = 1; } else { - // produce a new value which we will consume imediately + /* produce a new value which we will consume immediately */ x87_create_fldz(state, n, op2_reg_idx); live_after_node = 0; op2_idx = x87_on_stack(state, op2_reg_idx); @@ -1153,8 +1190,8 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { } else { op2_idx = x87_on_stack(state, op2_reg_idx); live_after_node = is_vfp_live(arch_register_get_index(op2), live); - assert(op2_idx >= 0); DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2))); + assert(op2_idx >= 0); } mode = get_ia32_ls_mode(n); @@ -1173,8 +1210,7 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { x87_create_fpush(state, n, op2_idx, STORE_VAL_IDX); x87_pop(state); x87_patch_insn(n, op_p); - } - else { + } else { ir_node *vfld, *mem, *block, *rproj, *mproj; ir_graph *irg; @@ -1184,13 +1220,12 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { block = get_nodes_block(n); irg = get_irn_irg(n); - vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg)); + vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg), get_ia32_ls_mode(n)); /* copy all attributes */ set_ia32_frame_ent(vfld, get_ia32_frame_ent(n)); if (is_ia32_use_frame(n)) set_ia32_use_frame(vfld); - set_ia32_am_flavour(vfld, get_ia32_am_flavour(n)); set_ia32_op_type(vfld, ia32_am_Source); add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n)); set_ia32_am_sc(vfld, get_ia32_am_sc(n)); @@ -1215,51 +1250,32 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { /* rewire all users, scheduled after the store, to the loaded value */ collect_and_rewire_users(n, val, rproj); - insn = 1; + insn = NODE_ADDED; } - } - else { + } else { /* we can only store the tos to memory */ - if(op2_idx != 0) - x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX); + if (op2_idx != 0) + x87_create_fxch(state, n, op2_idx); /* mode != mode_E -> use normal fst */ x87_patch_insn(n, op); } - } - else { + } else { /* we can only store the tos to memory */ - if(op2_idx != 0) - x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX); + if (op2_idx != 0) + x87_create_fxch(state, n, op2_idx); x87_pop(state); x87_patch_insn(n, op_p); } - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); attr->x87[1] = op2 = &ia32_st_regs[0]; DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2))); return insn; } /* sim_store */ -/** - * Simulate a virtual Phi. - * Just for cosmetic reasons change the mode of Phi nodes to mode_E. - * - * @param state the x87 state - * @param n the node that should be simulated (and patched) - * @param arch_env the architecture environment - */ -static int sim_Phi(x87_state *state, ir_node *n, const arch_env_t *arch_env) { - ir_mode *mode = get_irn_mode(n); - - if (mode_is_float(mode)) - set_irn_mode(n, mode_E); - - return 0; -} /* sim_Phi */ - #define _GEN_BINOP(op, rev) \ static int sim_##op(x87_state *state, ir_node *n) { \ exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \ @@ -1295,9 +1311,6 @@ GEN_BINOP(fprem) GEN_UNOP(fabs) GEN_UNOP(fchs) -GEN_UNOP(fsin) -GEN_UNOP(fcos) -GEN_UNOP(fsqrt) GEN_LOAD(fld) GEN_LOAD(fild) @@ -1312,16 +1325,20 @@ GEN_STORE(fist) * * @param state the x87 state * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED */ -static int sim_fCondJmp(x87_state *state, ir_node *n) { +static int sim_fCmpJmp(x87_state *state, ir_node *n) { int op1_idx; int op2_idx = -1; int pop_cnt = 0; - ia32_attr_t *attr; + ia32_x87_attr_t *attr; ir_op *dst; x87_simulator *sim = state->sim; - const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1)); - const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2)); + ir_node *op1_node = get_irn_n(n, n_ia32_vfCmpJmp_left); + ir_node *op2_node = get_irn_n(n, n_ia32_vfCmpJmp_right); + const arch_register_t *op1 = x87_get_irn_register(sim, op1_node); + const arch_register_t *op2 = x87_get_irn_register(sim, op2_node); int reg_index_1 = arch_register_get_index(op1); int reg_index_2 = arch_register_get_index(op2); unsigned live = vfp_live_args_after(sim, n, 0); @@ -1355,7 +1372,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { dst = op_ia32_fcomrJmp; } else { /* bring the first one to tos */ - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); if (op2_idx == 0) op2_idx = op1_idx; op1_idx = 0; @@ -1367,7 +1384,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { This means further, op1_idx != op2_idx. */ assert(op1_idx != op2_idx); if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); if (op2_idx == 0) op2_idx = op1_idx; op1_idx = 0; @@ -1383,7 +1400,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { This means further, op1_idx != op2_idx. */ assert(op1_idx != op2_idx); if (op2_idx != 0) { - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); if (op1_idx == 0) op1_idx = op2_idx; op2_idx = 0; @@ -1396,7 +1413,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { if (op1_idx == op2_idx) { /* identically, one pop needed */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; op2_idx = 0; } @@ -1410,7 +1427,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { /* good, second operand is already in the right place, move the first */ if (op1_idx != 0) { /* bring the first on top */ - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); assert(op2_idx != 0); op1_idx = 0; } @@ -1421,7 +1438,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { /* good, first operand is already in the right place, move the second */ if (op2_idx != 0) { /* bring the first on top */ - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); assert(op1_idx != 0); op2_idx = 0; } @@ -1431,31 +1448,31 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { /* if one is already the TOS, we need two fxch */ if (op1_idx == 0) { /* first one is TOS, move to st(1) */ - x87_create_fxch(state, n, 1, BINOP_IDX_1); + x87_create_fxch(state, n, 1); assert(op2_idx != 1); op1_idx = 1; - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); op2_idx = 0; /* res = op X tos, pop, pop */ dst = op_ia32_fcomrppJmp; pop_cnt = 2; } else if (op2_idx == 0) { /* second one is TOS, move to st(1) */ - x87_create_fxch(state, n, 1, BINOP_IDX_2); + x87_create_fxch(state, n, 1); assert(op1_idx != 1); op2_idx = 1; - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; /* res = tos X op, pop, pop */ dst = op_ia32_fcomppJmp; pop_cnt = 2; } else { /* none of them is either TOS or st(1), 3 fxch needed */ - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); assert(op1_idx != 0); - x87_create_fxch(state, n, 1, BINOP_IDX_2); + x87_create_fxch(state, n, 1); op2_idx = 1; - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; /* res = tos X op, pop, pop */ dst = op_ia32_fcomppJmp; @@ -1469,14 +1486,14 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { if (is_vfp_live(arch_register_get_index(op1), live)) { /* first operand is live: bring it to TOS */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } dst = op_ia32_fcomJmp; } else { /* first operand is dead: bring it to tos */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } dst = op_ia32_fcompJmp; @@ -1492,7 +1509,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { x87_pop(state); /* patch the operation */ - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); op1 = &ia32_st_regs[op1_idx]; attr->x87[0] = op1; if (op2_idx >= 0) { @@ -1508,9 +1525,72 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n), arch_register_get_name(op1))); - return 0; + return NO_NODE_ADDED; } /* sim_fCondJmp */ +static +int sim_Keep(x87_state *state, ir_node *node) +{ + const ir_node *op; + const arch_register_t *op_reg; + int reg_id; + int op_stack_idx; + unsigned live; + int i, arity; + int node_added = NO_NODE_ADDED; + + DB((dbg, LEVEL_1, ">>> %+F\n", node)); + + arity = get_irn_arity(node); + for(i = 0; i < arity; ++i) { + op = get_irn_n(node, i); + op_reg = arch_get_irn_register(state->sim->arch_env, op); + if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp]) + continue; + + reg_id = arch_register_get_index(op_reg); + live = vfp_live_args_after(state->sim, node, 0); + + op_stack_idx = x87_on_stack(state, reg_id); + if(op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) { + x87_create_fpop(state, sched_next(node), 1); + node_added = NODE_ADDED; + } + } + + DB((dbg, LEVEL_1, "Stack after: ")); + DEBUG_ONLY(x87_dump_stack(state)); + + return node_added; +} + +static +void keep_float_node_alive(x87_state *state, ir_node *node) +{ + ir_graph *irg; + ir_node *block; + ir_node *in[1]; + ir_node *keep; + const arch_register_class_t *cls; + + irg = get_irn_irg(node); + block = get_nodes_block(node); + cls = arch_get_irn_reg_class(state->sim->arch_env, node, -1); + in[0] = node; + keep = be_new_Keep(cls, irg, block, 1, in); + + assert(sched_is_scheduled(node)); + sched_add_after(node, keep); +} + +/** + * Create a copy of a node. Recreate the node if it's a constant. + * + * @param state the x87 state + * @param n the node to be copied + * + * @return the copy of n + */ static ir_node *create_Copy(x87_state *state, ir_node *n) { x87_simulator *sim = state->sim; ir_graph *irg = get_irn_irg(n); @@ -1522,7 +1602,7 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) { ir_node *res; const arch_register_t *out; const arch_register_t *op1; - ia32_attr_t *attr; + ia32_x87_attr_t *attr; /* Do not copy constants, recreate them. */ switch (get_ia32_irn_opcode(pred)) { @@ -1548,19 +1628,21 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) { case iro_ia32_fldln2: cnstr = new_rd_ia32_fldln2; break; + default: + break; } out = x87_get_irn_register(sim, n); op1 = x87_get_irn_register(sim, pred); - if(cnstr != NULL) { + if (cnstr != NULL) { /* copy a constant */ res = (*cnstr)(n_dbg, irg, block, mode); x87_push(state, arch_register_get_index(out), res); - attr = get_ia32_attr(res); - attr->x87[2] = out = &ia32_st_regs[0]; + attr = get_ia32_x87_attr(res); + attr->x87[2] = &ia32_st_regs[0]; } else { int op1_idx = x87_on_stack(state, arch_register_get_index(op1)); @@ -1568,40 +1650,41 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) { x87_push(state, arch_register_get_index(out), res); - attr = get_ia32_attr(res); - attr->x87[0] = op1 = &ia32_st_regs[op1_idx]; - attr->x87[2] = out = &ia32_st_regs[0]; + attr = get_ia32_x87_attr(res); + attr->x87[0] = &ia32_st_regs[op1_idx]; + attr->x87[2] = &ia32_st_regs[0]; } arch_set_irn_register(sim->arch_env, res, out); return res; -} +} /* create_Copy */ /** * Simulate a be_Copy. * * @param state the x87 state * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED */ static int sim_Copy(x87_state *state, ir_node *n) { - x87_simulator *sim; - ir_node *pred; - const arch_register_t *out; - const arch_register_t *op1; - ir_node *node, *next; - ia32_attr_t *attr; - int op1_idx, out_idx; - unsigned live; - - ir_mode *mode = get_irn_mode(n); - - if (!mode_is_float(mode)) + x87_simulator *sim = state->sim; + ir_node *pred; + const arch_register_t *out; + const arch_register_t *op1; + const arch_register_class_t *class; + ir_node *node, *next; + ia32_x87_attr_t *attr; + int op1_idx, out_idx; + unsigned live; + + class = arch_get_irn_reg_class(sim->arch_env, n, -1); + if (class->regs != ia32_vfp_regs) return 0; - sim = state->sim; pred = get_irn_n(n, 0); - out = x87_get_irn_register(sim, n); - op1 = x87_get_irn_register(sim, pred); + out = x87_get_irn_register(sim, n); + op1 = x87_get_irn_register(sim, pred); live = vfp_live_args_after(sim, n, REGMASK(out)); DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, @@ -1622,20 +1705,33 @@ static int sim_Copy(x87_state *state, ir_node *n) { DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name, arch_get_irn_register(sim->arch_env, node)->name)); - return 0; + return NO_NODE_ADDED; } op1_idx = x87_on_stack(state, arch_register_get_index(op1)); if (is_vfp_live(arch_register_get_index(op1), live)) { + ir_node *pred = get_irn_n(n, 0); + /* Operand is still live, a real copy. We need here an fpush that can hold a a register, so use the fpushCopy or recreate constants */ node = create_Copy(state, n); + /* We have to make sure the old value doesn't go dead (which can happen + * when we recreate constants). As the simulator expected that value in + * the pred blocks. This is unfortunate as removing it would save us 1 + * instruction, but we would have to rerun all the simulation to get + * this correct... + */ next = sched_next(n); sched_remove(n); exchange(n, node); sched_add_before(next, node); + + if(get_irn_n_edges(pred) == 0) { + keep_float_node_alive(state, pred); + } + DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name, arch_get_irn_register(sim->arch_env, node)->name)); } else { @@ -1649,7 +1745,7 @@ static int sim_Copy(x87_state *state, ir_node *n) { if (out_idx == 0) { /* best case, simple remove and rename */ x87_patch_insn(n, op_ia32_Pop); - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); attr->x87[0] = op1 = &ia32_st_regs[0]; x87_pop(state); @@ -1657,11 +1753,11 @@ static int sim_Copy(x87_state *state, ir_node *n) { } else { /* move op1 to tos, store and pop it */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, 0); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } x87_patch_insn(n, op_ia32_Pop); - attr = get_ia32_attr(n); + attr = get_ia32_x87_attr(n); attr->x87[0] = op1 = &ia32_st_regs[out_idx]; x87_pop(state); @@ -1671,48 +1767,36 @@ static int sim_Copy(x87_state *state, ir_node *n) { } else { /* just a virtual copy */ x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx); + /* don't remove the node to keep the verifier quiet :), + the emitter won't emit any code for the node */ +#if 0 sched_remove(n); DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n))); exchange(n, get_unop_op(n)); +#endif } } - - return 0; + return NO_NODE_ADDED; } /* sim_Copy */ /** - * Returns the result proj of the call, or NULL if the result is not used + * Returns the result proj of the call */ -static ir_node *get_call_result_proj(ir_node *call) -{ +static ir_node *get_call_result_proj(ir_node *call) { const ir_edge_t *edge; - ir_node *resproj = NULL; /* search the result proj */ foreach_out_edge(call, edge) { ir_node *proj = get_edge_src_irn(edge); long pn = get_Proj_proj(proj); - if(pn == pn_be_Call_first_res) { - resproj = proj; - break; - } - } - if(resproj == NULL) { - return NULL; - } - - /* the result proj is connected to a Keep and maybe other nodes */ - foreach_out_edge(resproj, edge) { - ir_node *pred = get_edge_src_irn(edge); - if(!be_is_Keep(pred)) { - return resproj; + if (pn == pn_be_Call_first_res) { + return proj; } } - /* only be_Keep found, so result is not used */ return NULL; -} +} /* get_call_result_proj */ /** * Simulate a be_Call. @@ -1720,19 +1804,25 @@ static ir_node *get_call_result_proj(ir_node *call) * @param state the x87 state * @param n the node that should be simulated * @param arch_env the architecture environment + * + * @return NO_NODE_ADDED */ -static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) { +static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) +{ ir_type *call_tp = be_Call_get_type(n); ir_type *res_type; ir_mode *mode; ir_node *resproj; const arch_register_t *reg; + (void) arch_env; + + DB((dbg, LEVEL_1, ">>> %+F\n", n)); /* at the begin of a call the x87 state should be empty */ assert(state->depth == 0 && "stack not empty before call"); if (get_method_n_ress(call_tp) <= 0) - return 0; + goto end_call; /* * If the called function returns a float, it is returned in st(0). @@ -1743,16 +1833,19 @@ static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) { mode = get_type_mode(res_type); if (mode == NULL || !mode_is_float(mode)) - return 0; + goto end_call; resproj = get_call_result_proj(n); - if (resproj == NULL) - return 0; + assert(resproj != NULL); reg = x87_get_irn_register(state->sim, resproj); x87_push(state, arch_register_get_index(reg), resproj); - return 0; +end_call: + DB((dbg, LEVEL_1, "Stack after: ")); + DEBUG_ONLY(x87_dump_stack(state)); + + return NO_NODE_ADDED; } /* sim_Call */ /** @@ -1786,6 +1879,8 @@ static int sim_Reload(x87_state *state, ir_node *n) { * * @param state the x87 state * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED */ static int sim_Return(x87_state *state, ir_node *n) { int n_res = be_Return_get_n_rets(n); @@ -1804,7 +1899,7 @@ static int sim_Return(x87_state *state, ir_node *n) { for (i = n_float_res - 1; i >= 0; --i) x87_pop(state); - return 0; + return NO_NODE_ADDED; } /* sim_Return */ typedef struct _perm_data_t { @@ -1817,6 +1912,8 @@ typedef struct _perm_data_t { * * @param state the x87 state * @param irn the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED */ static int sim_Perm(x87_state *state, ir_node *irn) { int i, n; @@ -1827,7 +1924,7 @@ static int sim_Perm(x87_state *state, ir_node *irn) { /* handle only floating point Perms */ if (! mode_is_float(get_irn_mode(pred))) - return 0; + return NO_NODE_ADDED; DB((dbg, LEVEL_1, ">>> %+F\n", irn)); @@ -1858,8 +1955,44 @@ static int sim_Perm(x87_state *state, ir_node *irn) { } DB((dbg, LEVEL_1, "<<< %+F\n", irn)); - return 0; -} /* be_Perm */ + return NO_NODE_ADDED; +} /* sim_Perm */ + +static int sim_Barrier(x87_state *state, ir_node *node) { + //const arch_env_t *arch_env = state->sim->arch_env; + int i, arity; + + /* materialize unknown if needed */ + arity = get_irn_arity(node); + for(i = 0; i < arity; ++i) { + const arch_register_t *reg; + ir_node *zero; + ir_node *block; + ia32_x87_attr_t *attr; + ir_node *in = get_irn_n(node, i); + + if(!is_ia32_Unknown_VFP(in)) + continue; + + /* TODO: not completely correct... */ + reg = &ia32_vfp_regs[REG_VFP_UKNWN]; + + /* create a zero */ + block = get_nodes_block(node); + zero = new_rd_ia32_fldz(NULL, current_ir_graph, block, mode_E); + x87_push(state, arch_register_get_index(reg), zero); + + attr = get_ia32_x87_attr(zero); + attr->x87[2] = &ia32_st_regs[0]; + + sched_add_before(node, zero); + + set_irn_n(node, i, zero); + } + + return NO_NODE_ADDED; +} + /** * Kill any dead registers at block start by popping them from the stack. @@ -1867,6 +2000,8 @@ static int sim_Perm(x87_state *state, ir_node *irn) { * @param sim the simulator handle * @param block the current block * @param start_state the x87 state at the begin of the block + * + * @return the x87 state after dead register killed */ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state) { x87_state *state = start_state; @@ -1908,10 +2043,8 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * if (keep) x87_set_st(state, -1, keep, i); - keep = x87_create_fxch(state, first_insn, i, -1); + x87_create_fxch(state, first_insn, i); } - else if (! keep) - keep = x87_get_st_node(state, 0); if ((kill_mask & 3) == 3) { /* we can do a double-pop */ @@ -1924,21 +2057,55 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * depth -= num_pop; kill_mask >>= num_pop; - keep = x87_create_fpop(state, first_insn, num_pop, keep); + keep = x87_create_fpop(state, first_insn, num_pop); } keep_alive(keep); } return state; } /* x87_kill_deads */ +/** + * If we have PhiEs with unknown operands then we have to make sure that some + * value is actually put onto the stack. + */ +static void fix_unknown_phis(x87_state *state, ir_node *block, + ir_node *pred_block, int pos) +{ + ir_node *node, *op; + + sched_foreach(block, node) { + ir_node *zero; + const arch_register_t *reg; + ia32_x87_attr_t *attr; + + if(!is_Phi(node)) + break; + + op = get_Phi_pred(node, pos); + if(!is_ia32_Unknown_VFP(op)) + continue; + + reg = arch_get_irn_register(state->sim->arch_env, node); + + /* create a zero at end of pred block */ + zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E); + x87_push(state, arch_register_get_index(reg), zero); + + attr = get_ia32_x87_attr(zero); + attr->x87[2] = &ia32_st_regs[0]; + + assert(is_ia32_fldz(zero)); + sched_add_before(sched_last(pred_block), zero); + + set_Phi_pred(node, pos, zero); + } +} + /** * Run a simulation and fix all virtual instructions for a block. * * @param sim the simulator handle * @param block the current block - * - * @return non-zero if simulation is complete, - * zero if the simulation must be rerun */ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { ir_node *n, *next; @@ -1948,18 +2115,18 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { ir_node *start_block; assert(state != NULL); - // already processed? - if(bl_state->end != NULL) + /* already processed? */ + if (bl_state->end != NULL) return; - //update_liveness(sim, block); - DB((dbg, LEVEL_1, "Simulate %+F\n", block)); DB((dbg, LEVEL_2, "State at Block begin:\n ")); DEBUG_ONLY(x87_dump_stack(state)); /* at block begin, kill all dead registers */ state = x87_kill_deads(sim, block, state); + /* create a new state, will be changed */ + state = x87_clone_state(sim, state); /* beware, n might change */ for (n = sched_first(block); !sched_is_end(n); n = next) { @@ -1973,50 +2140,53 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { func = (sim_func)op->ops.generic; - /* have work to do */ - if (state == bl_state->begin) { - /* create a new state, will be changed */ - state = x87_clone_state(sim, state); - } - /* simulate it */ node_inserted = (*func)(state, n); /* - sim_func might have added additional nodes after n, + sim_func might have added an additional node after n, so update next node beware: n must not be changed by sim_func (i.e. removed from schedule) in this case */ - if (node_inserted) + if (node_inserted != NO_NODE_ADDED) next = sched_next(n); } start_block = get_irg_start_block(get_irn_irg(block)); + DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state)); + /* check if the state must be shuffled */ foreach_block_succ(block, edge) { ir_node *succ = get_edge_src_irn(edge); blk_state *succ_state; - if(succ == start_block) + if (succ == start_block) continue; succ_state = x87_get_bl_state(sim, succ); + fix_unknown_phis(state, succ, block, get_edge_src_pos(edge)); + if (succ_state->begin == NULL) { + DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ)); + DEBUG_ONLY(x87_dump_stack(state)); succ_state->begin = state; + waitq_put(sim->worklist, succ); } else { + DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ)); /* There is already a begin state for the successor, bad. Do the necessary permutations. - Note that critical edges are removed, so this is always possible. */ + Note that critical edges are removed, so this is always possible: + If the successor has more than one possible input, then it must + be the only one. + */ x87_shuffle(sim, block, state, succ, succ_state->begin); } } bl_state->end = state; - - DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state)); } /* x87_simulate_block */ /** @@ -2035,8 +2205,6 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg, sim->n_idx = get_irg_last_idx(irg); sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx); - FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87"); - DB((dbg, LEVEL_1, "--------------------------------\n" "x87 Simulator started for %+F\n", irg)); @@ -2057,19 +2225,17 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg, ASSOC_IA32(fprem); ASSOC_IA32(fabs); ASSOC_IA32(fchs); - ASSOC_IA32(fsin); - ASSOC_IA32(fcos); - ASSOC_IA32(fsqrt); ASSOC_IA32(fist); ASSOC_IA32(fst); - ASSOC_IA32(fCondJmp); + ASSOC_IA32(fCmpJmp); ASSOC_BE(Copy); ASSOC_BE(Call); ASSOC_BE(Spill); ASSOC_BE(Reload); ASSOC_BE(Return); ASSOC_BE(Perm); - ASSOC(Phi); + ASSOC_BE(Keep); + ASSOC_BE(Barrier); #undef ASSOC_BE #undef ASSOC_IA32 #undef ASSOC @@ -2086,11 +2252,14 @@ static void x87_destroy_simulator(x87_simulator *sim) { DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n")); } /* x87_destroy_simulator */ -static void update_liveness_walker(ir_node *block, void *data) -{ +/** + * Pre-block walker: calculate the liveness information for the block + * and store it into the sim->live cache. + */ +static void update_liveness_walker(ir_node *block, void *data) { x87_simulator *sim = data; update_liveness(sim, block); -} +} /* update_liveness_walker */ /** * Run a simulation and fix all virtual instructions for a graph. @@ -2104,13 +2273,13 @@ void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) { ir_node *block, *start_block; blk_state *bl_state; x87_simulator sim; - ir_graph *irg = birg->irg; + ir_graph *irg = be_get_birg_irg(birg); /* create the simulator */ x87_init_simulator(&sim, irg, arch_env); start_block = get_irg_start_block(irg); - bl_state = x87_get_bl_state(&sim, start_block); + bl_state = x87_get_bl_state(&sim, start_block); /* start with the empty state */ bl_state->begin = empty; @@ -2119,9 +2288,10 @@ void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) { sim.worklist = new_waitq(); waitq_put(sim.worklist, start_block); - be_invalidate_liveness(birg); be_assure_liveness(birg); - sim.lv = birg->lv; + sim.lv = be_get_birg_liveness(birg); +// sim.lv = be_liveness(be_get_birg_irg(birg)); + be_liveness_assure_sets(sim.lv); /* Calculate the liveness for all nodes. We must precalculate this info, * because the simulator adds new nodes (possible before Phi nodes) which @@ -2135,9 +2305,13 @@ void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) { do { block = waitq_get(sim.worklist); x87_simulate_block(&sim, block); - } while (! pdeq_empty(sim.worklist)); + } while (! waitq_empty(sim.worklist)); /* kill it */ del_waitq(sim.worklist); x87_destroy_simulator(&sim); } /* x87_simulate_graph */ + +void ia32_init_x87(void) { + FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87"); +} /* ia32_init_x87 */