X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_x87.c;h=c724764d4b77c9d152e6cbaa39ae1db24e55ec33;hb=1872920c09708b361d06c0dc9f4c1fd0a03544f5;hp=4bbd9bdca3be9ed2adbd3483cd96b9240edf4f51;hpb=07ccf5c739e1a0627ad3fc2f732b9b5612add654;p=libfirm diff --git a/ir/be/ia32/ia32_x87.c b/ir/be/ia32/ia32_x87.c index 4bbd9bdca..c724764d4 100644 --- a/ir/be/ia32/ia32_x87.c +++ b/ir/be/ia32/ia32_x87.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -47,10 +47,12 @@ #include "../belive_t.h" #include "../besched_t.h" #include "../benode_t.h" +#include "bearch_ia32_t.h" #include "ia32_new_nodes.h" #include "gen_ia32_new_nodes.h" #include "gen_ia32_regalloc_if.h" #include "ia32_x87.h" +#include "ia32_architecture.h" #define N_x87_REGS 8 @@ -141,6 +143,7 @@ struct _x87_simulator { vfp_liveness *live; /**< Liveness information. */ unsigned n_idx; /**< The cached get_irg_last_idx() result. */ waitq *worklist; /**< Worklist of blocks that must be processed. */ + ia32_isa_t *isa; /**< the ISA object */ }; /** @@ -167,6 +170,7 @@ static int x87_get_st_reg(const x87_state *state, int pos) { return state->st[MASK_TOS(state->tos + pos)].reg_idx; } /* x87_get_st_reg */ +#ifdef DEBUG_libfirm /** * Return the node at st(pos). * @@ -180,7 +184,6 @@ static ir_node *x87_get_st_node(const x87_state *state, int pos) { return state->st[MASK_TOS(state->tos + pos)].node; } /* x87_get_st_node */ -#ifdef DEBUG_libfirm /** * Dump the stack for debugging. * @@ -306,6 +309,16 @@ static void x87_pop(x87_state *state) { DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state)); } /* x87_pop */ +/** + * Empty the fpu stack + * + * @param state the x87 state + */ +static void x87_emms(x87_state *state) { + state->depth = 0; + state->tos = 0; +} + /** * Returns the block state of a block. * @@ -440,7 +453,7 @@ static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) { ir_node *fxch; ia32_x87_attr_t *attr; - fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block, mode_E); + fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block); attr = get_ia32_x87_attr(fxch); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -610,7 +623,7 @@ static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos) x87_fxch(state, pos); - fxch = new_rd_ia32_fxch(NULL, irg, block, mode_E); + fxch = new_rd_ia32_fxch(NULL, irg, block); attr = get_ia32_x87_attr(fxch); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -637,7 +650,7 @@ static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) x87_push_dbl(state, arch_register_get_index(out), pred); - fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n), mode_E); + fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n)); attr = get_ia32_x87_attr(fpush); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -659,12 +672,16 @@ static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) */ static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num) { - ir_node *fpop; + ir_node *fpop = NULL; ia32_x87_attr_t *attr; + assert(num > 0); while (num > 0) { x87_pop(state); - fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n), mode_E); + if (ia32_cg_config.use_ffreep) + fpop = new_rd_ia32_ffreep(NULL, get_irn_irg(n), get_nodes_block(n)); + else + fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n)); attr = get_ia32_x87_attr(fpop); attr->x87[0] = &ia32_st_regs[0]; attr->x87[1] = &ia32_st_regs[0]; @@ -1196,8 +1213,9 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { Solution: - stack not full: push value and fstp - stack full: fstp value and load again + Note that we cannot test on mode_E, because floats might be 96bit ... */ - if (mode == mode_E) { + if (get_mode_size_bits(mode) > 64 || mode == mode_Ls) { if (depth < N_x87_REGS) { /* ok, we have a free register: push + fstp */ x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val); @@ -1314,27 +1332,114 @@ GEN_STORE(fst) GEN_STORE(fist) /** - * Simulate a fCondJmp. - * +* Simulate a virtual fisttp. +* +* @param state the x87 state +* @param n the node that should be simulated (and patched) +*/ +static int sim_fisttp(x87_state *state, ir_node *n) { + x87_simulator *sim = state->sim; + ir_node *val = get_irn_n(n, n_ia32_vfst_val); + const arch_register_t *op2 = x87_get_irn_register(sim, val); + int insn = NO_NODE_ADDED; + ia32_x87_attr_t *attr; + int op2_reg_idx, op2_idx, depth; + + op2_reg_idx = arch_register_get_index(op2); + if (op2_reg_idx == REG_VFP_UKNWN) { + /* just take any value from stack */ + if (state->depth > 0) { + op2_idx = 0; + DEBUG_ONLY(op2 = NULL); + } else { + /* produce a new value which we will consume immediately */ + x87_create_fldz(state, n, op2_reg_idx); + op2_idx = x87_on_stack(state, op2_reg_idx); + assert(op2_idx >= 0); + } + } else { + op2_idx = x87_on_stack(state, op2_reg_idx); + DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2))); + assert(op2_idx >= 0); + } + + depth = x87_get_depth(state); + + /* Note: although the value is still live here, it is destroyed because + of the pop. The register allocator is aware of that and introduced a copy + if the value must be alive. */ + + /* we can only store the tos to memory */ + if (op2_idx != 0) + x87_create_fxch(state, n, op2_idx); + + x87_pop(state); + x87_patch_insn(n, op_ia32_fisttp); + + attr = get_ia32_x87_attr(n); + attr->x87[1] = op2 = &ia32_st_regs[0]; + DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2))); + + return insn; +} /* sim_fisttp */ + +static int sim_FtstFnstsw(x87_state *state, ir_node *n) { + x87_simulator *sim = state->sim; + ia32_x87_attr_t *attr = get_ia32_x87_attr(n); + ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left); + const arch_register_t *reg1 = x87_get_irn_register(sim, op1_node); + int reg_index_1 = arch_register_get_index(reg1); + int op1_idx = x87_on_stack(state, reg_index_1); + unsigned live = vfp_live_args_after(sim, n, 0); + + DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1))); + DEBUG_ONLY(vfp_dump_live(live)); + DB((dbg, LEVEL_1, "Stack before: ")); + DEBUG_ONLY(x87_dump_stack(state)); + assert(op1_idx >= 0); + + if (op1_idx != 0) { + /* bring the value to tos */ + x87_create_fxch(state, n, op1_idx); + op1_idx = 0; + } + + /* patch the operation */ + x87_patch_insn(n, op_ia32_FtstFnstsw); + reg1 = &ia32_st_regs[op1_idx]; + attr->x87[0] = reg1; + attr->x87[1] = NULL; + attr->x87[2] = NULL; + + if(!is_vfp_live(reg_index_1, live)) { + x87_create_fpop(state, sched_next(n), 1); + return NODE_ADDED; + } + + return NO_NODE_ADDED; +} + +/** * @param state the x87 state * @param n the node that should be simulated (and patched) - * - * @return NO_NODE_ADDED */ -static int sim_fCmpJmp(x87_state *state, ir_node *n) { +static int sim_Fucom(x87_state *state, ir_node *n) { int op1_idx; int op2_idx = -1; - int pop_cnt = 0; - ia32_x87_attr_t *attr; + ia32_x87_attr_t *attr = get_ia32_x87_attr(n); ir_op *dst; x87_simulator *sim = state->sim; - ir_node *op1_node = get_irn_n(n, n_ia32_vfCmpJmp_left); - ir_node *op2_node = get_irn_n(n, n_ia32_vfCmpJmp_right); + ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left); + ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right); const arch_register_t *op1 = x87_get_irn_register(sim, op1_node); const arch_register_t *op2 = x87_get_irn_register(sim, op2_node); int reg_index_1 = arch_register_get_index(op1); int reg_index_2 = arch_register_get_index(op2); unsigned live = vfp_live_args_after(sim, n, 0); + int permuted = attr->attr.data.ins_permuted; + int xchg = 0; + int pops = 0; + int node_added = NO_NODE_ADDED; DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n, arch_register_get_name(op1), arch_register_get_name(op2))); @@ -1351,18 +1456,18 @@ static int sim_fCmpJmp(x87_state *state, ir_node *n) { op2_idx = x87_on_stack(state, reg_index_2); assert(op2_idx >= 0); - if (is_vfp_live(arch_register_get_index(op2), live)) { + if (is_vfp_live(reg_index_2, live)) { /* second operand is live */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (is_vfp_live(reg_index_1, live)) { /* both operands are live */ if (op1_idx == 0) { /* res = tos X op */ - dst = op_ia32_fcomJmp; } else if (op2_idx == 0) { /* res = op X tos */ - dst = op_ia32_fcomrJmp; + permuted = !permuted; + xchg = 1; } else { /* bring the first one to tos */ x87_create_fxch(state, n, op1_idx); @@ -1370,7 +1475,6 @@ static int sim_fCmpJmp(x87_state *state, ir_node *n) { op2_idx = op1_idx; op1_idx = 0; /* res = tos X op */ - dst = op_ia32_fcomJmp; } } else { /* second live, first operand is dead here, bring it to tos. @@ -1383,12 +1487,11 @@ static int sim_fCmpJmp(x87_state *state, ir_node *n) { op1_idx = 0; } /* res = tos X op, pop */ - dst = op_ia32_fcompJmp; - pop_cnt = 1; + pops = 1; } } else { /* second operand is dead */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (is_vfp_live(reg_index_1, live)) { /* first operand is live: bring second to tos. This means further, op1_idx != op2_idx. */ assert(op1_idx != op2_idx); @@ -1399,8 +1502,9 @@ static int sim_fCmpJmp(x87_state *state, ir_node *n) { op2_idx = 0; } /* res = op X tos, pop */ - dst = op_ia32_fcomrpJmp; - pop_cnt = 1; + pops = 1; + permuted = !permuted; + xchg = 1; } else { /* both operands are dead here, check first for identity. */ if (op1_idx == op2_idx) { @@ -1411,8 +1515,7 @@ static int sim_fCmpJmp(x87_state *state, ir_node *n) { op2_idx = 0; } /* res = tos X op, pop */ - dst = op_ia32_fcompJmp; - pop_cnt = 1; + pops = 1; } /* different, move them to st and st(1) and pop both. The tricky part is to get one into st(1).*/ @@ -1425,8 +1528,7 @@ static int sim_fCmpJmp(x87_state *state, ir_node *n) { op1_idx = 0; } /* res = tos X op, pop, pop */ - dst = op_ia32_fcomppJmp; - pop_cnt = 2; + pops = 2; } else if (op1_idx == 1) { /* good, first operand is already in the right place, move the second */ if (op2_idx != 0) { @@ -1435,8 +1537,10 @@ static int sim_fCmpJmp(x87_state *state, ir_node *n) { assert(op1_idx != 0); op2_idx = 0; } - dst = op_ia32_fcomrppJmp; - pop_cnt = 2; + /* res = op X tos, pop, pop */ + permuted = !permuted; + xchg = 1; + pops = 2; } else { /* if one is already the TOS, we need two fxch */ if (op1_idx == 0) { @@ -1447,8 +1551,9 @@ static int sim_fCmpJmp(x87_state *state, ir_node *n) { x87_create_fxch(state, n, op2_idx); op2_idx = 0; /* res = op X tos, pop, pop */ - dst = op_ia32_fcomrppJmp; - pop_cnt = 2; + pops = 2; + permuted = !permuted; + xchg = 1; } else if (op2_idx == 0) { /* second one is TOS, move to st(1) */ x87_create_fxch(state, n, 1); @@ -1457,8 +1562,7 @@ static int sim_fCmpJmp(x87_state *state, ir_node *n) { x87_create_fxch(state, n, op1_idx); op1_idx = 0; /* res = tos X op, pop, pop */ - dst = op_ia32_fcomppJmp; - pop_cnt = 2; + pops = 2; } else { /* none of them is either TOS or st(1), 3 fxch needed */ x87_create_fxch(state, n, op2_idx); @@ -1468,41 +1572,66 @@ static int sim_fCmpJmp(x87_state *state, ir_node *n) { x87_create_fxch(state, n, op1_idx); op1_idx = 0; /* res = tos X op, pop, pop */ - dst = op_ia32_fcomppJmp; - pop_cnt = 2; + pops = 2; } } } } } else { /* second operand is an address mode */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (is_vfp_live(reg_index_1, live)) { /* first operand is live: bring it to TOS */ if (op1_idx != 0) { x87_create_fxch(state, n, op1_idx); op1_idx = 0; } - dst = op_ia32_fcomJmp; } else { /* first operand is dead: bring it to tos */ if (op1_idx != 0) { x87_create_fxch(state, n, op1_idx); op1_idx = 0; } - dst = op_ia32_fcompJmp; - pop_cnt = 1; + pops = 1; + } + } + + /* patch the operation */ + if (is_ia32_vFucomFnstsw(n)) { + int i; + + switch(pops) { + case 0: dst = op_ia32_FucomFnstsw; break; + case 1: dst = op_ia32_FucompFnstsw; break; + case 2: dst = op_ia32_FucomppFnstsw; break; + default: panic("invalid popcount in sim_Fucom"); + } + + for(i = 0; i < pops; ++i) { + x87_pop(state); + } + } else if(is_ia32_vFucomi(n)) { + switch(pops) { + case 0: dst = op_ia32_Fucomi; break; + case 1: dst = op_ia32_Fucompi; x87_pop(state); break; + case 2: + dst = op_ia32_Fucompi; + x87_pop(state); + x87_create_fpop(state, sched_next(n), 1); + node_added = NODE_ADDED; + break; + default: panic("invalid popcount in sim_Fucom"); } + } else { + panic("invalid operation %+F in sim_FucomFnstsw", n); } x87_patch_insn(n, dst); - assert(pop_cnt < 3); - if (pop_cnt >= 2) - x87_pop(state); - if (pop_cnt >= 1) - x87_pop(state); + if(xchg) { + int tmp = op1_idx; + op1_idx = op2_idx; + op2_idx = tmp; + } - /* patch the operation */ - attr = get_ia32_x87_attr(n); op1 = &ia32_st_regs[op1_idx]; attr->x87[0] = op1; if (op2_idx >= 0) { @@ -1510,19 +1639,20 @@ static int sim_fCmpJmp(x87_state *state, ir_node *n) { attr->x87[1] = op2; } attr->x87[2] = NULL; + attr->attr.data.ins_permuted = permuted; - if (op2_idx >= 0) + if (op2_idx >= 0) { DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n), arch_register_get_name(op1), arch_register_get_name(op2))); - else + } else { DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n), arch_register_get_name(op1))); + } - return NO_NODE_ADDED; -} /* sim_fCondJmp */ + return node_added; +} -static -int sim_Keep(x87_state *state, ir_node *node) +static int sim_Keep(x87_state *state, ir_node *node) { const ir_node *op; const arch_register_t *op_reg; @@ -1665,14 +1795,14 @@ static int sim_Copy(x87_state *state, ir_node *n) { ir_node *pred; const arch_register_t *out; const arch_register_t *op1; - const arch_register_class_t *class; + const arch_register_class_t *cls; ir_node *node, *next; ia32_x87_attr_t *attr; int op1_idx, out_idx; unsigned live; - class = arch_get_irn_reg_class(sim->arch_env, n, -1); - if (class->regs != ia32_vfp_regs) + cls = arch_get_irn_reg_class(sim->arch_env, n, -1); + if (cls->regs != ia32_vfp_regs) return 0; pred = get_irn_n(n, 0); @@ -1725,8 +1855,7 @@ static int sim_Copy(x87_state *state, ir_node *n) { keep_float_node_alive(state, pred); } - DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name, - arch_get_irn_register(sim->arch_env, node)->name)); + DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name)); } else { out_idx = x87_on_stack(state, arch_register_get_index(out)); @@ -1796,18 +1925,16 @@ static ir_node *get_call_result_proj(ir_node *call) { * * @param state the x87 state * @param n the node that should be simulated - * @param arch_env the architecture environment * * @return NO_NODE_ADDED */ -static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) +static int sim_Call(x87_state *state, ir_node *n) { ir_type *call_tp = be_Call_get_type(n); ir_type *res_type; ir_mode *mode; ir_node *resproj; const arch_register_t *reg; - (void) arch_env; DB((dbg, LEVEL_1, ">>> %+F\n", n)); @@ -2021,6 +2148,22 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * DEBUG_ONLY(vfp_dump_live(live)); DEBUG_ONLY(x87_dump_stack(state)); + if (kill_mask != 0 && live == 0) { + /* special case: kill all registers */ + if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) { + if (ia32_cg_config.use_femms) { + /* use FEMMS on AMD processors to clear all */ + keep = new_rd_ia32_femms(NULL, get_irn_irg(block), block); + } else { + /* use EMMS to clear all */ + keep = new_rd_ia32_emms(NULL, get_irn_irg(block), block); + } + sched_add_before(first_insn, keep); + keep_alive(keep); + x87_emms(state); + return state; + } + } /* now kill registers */ while (kill_mask) { /* we can only kill from TOS, so bring them up */ @@ -2182,6 +2325,12 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { bl_state->end = state; } /* x87_simulate_block */ +static void register_sim(ir_op *op, sim_func func) +{ + assert(op->ops.generic == NULL); + op->ops.generic = (op_func) func; +} + /** * Create a new x87 simulator. * @@ -2204,34 +2353,31 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg, /* set the generic function pointer of instruction we must simulate */ clear_irp_opcodes_generic_func(); -#define ASSOC(op) (op_ ## op)->ops.generic = (op_func)(sim_##op) -#define ASSOC_IA32(op) (op_ia32_v ## op)->ops.generic = (op_func)(sim_##op) -#define ASSOC_BE(op) (op_be_ ## op)->ops.generic = (op_func)(sim_##op) - ASSOC_IA32(fld); - ASSOC_IA32(fild); - ASSOC_IA32(fld1); - ASSOC_IA32(fldz); - ASSOC_IA32(fadd); - ASSOC_IA32(fsub); - ASSOC_IA32(fmul); - ASSOC_IA32(fdiv); - ASSOC_IA32(fprem); - ASSOC_IA32(fabs); - ASSOC_IA32(fchs); - ASSOC_IA32(fist); - ASSOC_IA32(fst); - ASSOC_IA32(fCmpJmp); - ASSOC_BE(Copy); - ASSOC_BE(Call); - ASSOC_BE(Spill); - ASSOC_BE(Reload); - ASSOC_BE(Return); - ASSOC_BE(Perm); - ASSOC_BE(Keep); - ASSOC_BE(Barrier); -#undef ASSOC_BE -#undef ASSOC_IA32 -#undef ASSOC + register_sim(op_ia32_vfld, sim_fld); + register_sim(op_ia32_vfild, sim_fild); + register_sim(op_ia32_vfld1, sim_fld1); + register_sim(op_ia32_vfldz, sim_fldz); + register_sim(op_ia32_vfadd, sim_fadd); + register_sim(op_ia32_vfsub, sim_fsub); + register_sim(op_ia32_vfmul, sim_fmul); + register_sim(op_ia32_vfdiv, sim_fdiv); + register_sim(op_ia32_vfprem, sim_fprem); + register_sim(op_ia32_vfabs, sim_fabs); + register_sim(op_ia32_vfchs, sim_fchs); + register_sim(op_ia32_vfist, sim_fist); + register_sim(op_ia32_vfisttp, sim_fisttp); + register_sim(op_ia32_vfst, sim_fst); + register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw); + register_sim(op_ia32_vFucomFnstsw, sim_Fucom); + register_sim(op_ia32_vFucomi, sim_Fucom); + register_sim(op_be_Copy, sim_Copy); + register_sim(op_be_Call, sim_Call); + register_sim(op_be_Spill, sim_Spill); + register_sim(op_be_Reload, sim_Reload); + register_sim(op_be_Return, sim_Return); + register_sim(op_be_Perm, sim_Perm); + register_sim(op_be_Keep, sim_Keep); + register_sim(op_be_Barrier, sim_Barrier); } /* x87_init_simulator */ /**