X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_x87.c;h=6e806fba3de47a50ec8cd3cc7f7ef777a694a395;hb=4137609950786f314fa679f833379ec63444c160;hp=45c2853d0959b15e6a6deacd49fd62f0738bd7a1;hpb=5057c4b3b6c48dc75dee684cd172ce4cfed00da7;p=libfirm

diff --git a/ir/be/ia32/ia32_x87.c b/ir/be/ia32/ia32_x87.c
index 45c2853d0..6e806fba3 100644
--- a/ir/be/ia32/ia32_x87.c
+++ b/ir/be/ia32/ia32_x87.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 1995-2007 University of Karlsruhe.  All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
  *
  * This file is part of libFirm.
  *
@@ -24,9 +24,7 @@
  * @author      Michael Beck
  * @version     $Id$
  */
-#ifdef HAVE_CONFIG_H
 #include "config.h"
-#endif
 
 #include <assert.h>
 
@@ -39,31 +37,27 @@
 #include "irgwalk.h"
 #include "obst.h"
 #include "pmap.h"
+#include "array_t.h"
 #include "pdeq.h"
 #include "irprintf.h"
 #include "debug.h"
 #include "error.h"
 
 #include "../belive_t.h"
-#include "../besched_t.h"
-#include "../benode_t.h"
+#include "../besched.h"
+#include "../benode.h"
+#include "bearch_ia32_t.h"
 #include "ia32_new_nodes.h"
 #include "gen_ia32_new_nodes.h"
 #include "gen_ia32_regalloc_if.h"
 #include "ia32_x87.h"
+#include "ia32_architecture.h"
 
 #define N_x87_REGS 8
 
-/* first and second binop index */
-#define BINOP_IDX_1 2
-#define BINOP_IDX_2 3
-
 /* the unop index */
 #define UNOP_IDX 0
 
-/* the store val index */
-#define STORE_VAL_IDX 2
-
 #define MASK_TOS(x)		((x) & (N_x87_REGS - 1))
 
 /** the debug handle */
@@ -108,9 +102,13 @@ typedef struct _x87_state {
 static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
 static x87_state *empty = (x87_state *)&_empty;
 
+/**
+ * Return values of the instruction simulator functions.
+ */
 enum {
-	NO_NODE_ADDED = 0,  /**< No node was added. */
-	NODE_ADDED = 1      /**< A node was added by the simulator in the schedule. */
+	NO_NODE_ADDED = 0,  /**< No node that needs simulation was added. */
+	NODE_ADDED    = 1   /**< A node that must be simulated was added by the simulator
+	                         in the schedule AFTER the current node. */
 };
 
 /**
@@ -119,8 +117,9 @@ enum {
  * @param state  the x87 state
  * @param n      the node to be simulated
  *
- * @return NODE_ADDED if a node was added AFTER n in schedule,
- *         NO_NODE_ADDED else
+ * @return NODE_ADDED    if a node was added AFTER n in schedule that MUST be
+ *                       simulated further
+ *         NO_NODE_ADDED otherwise
  */
 typedef int (*sim_func)(x87_state *state, ir_node *n);
 
@@ -143,11 +142,11 @@ typedef unsigned char vfp_liveness;
 struct _x87_simulator {
 	struct obstack obst;        /**< An obstack for fast allocating. */
 	pmap *blk_states;           /**< Map blocks to states. */
-	const arch_env_t *arch_env; /**< The architecture environment. */
 	be_lv_t *lv;                /**< intrablock liveness. */
 	vfp_liveness *live;         /**< Liveness information. */
 	unsigned n_idx;             /**< The cached get_irg_last_idx() result. */
 	waitq *worklist;            /**< Worklist of blocks that must be processed. */
+	ia32_isa_t *isa;            /**< the ISA object */
 };
 
 /**
@@ -157,7 +156,8 @@ struct _x87_simulator {
  *
  * @return the x87 stack depth
  */
-static int x87_get_depth(const x87_state *state) {
+static int x87_get_depth(const x87_state *state)
+{
 	return state->depth;
 }  /* x87_get_depth */
 
@@ -169,11 +169,13 @@ static int x87_get_depth(const x87_state *state) {
  *
  * @return the vfp register index that produced the value at st(pos)
  */
-static int x87_get_st_reg(const x87_state *state, int pos) {
+static int x87_get_st_reg(const x87_state *state, int pos)
+{
 	assert(pos < state->depth);
 	return state->st[MASK_TOS(state->tos + pos)].reg_idx;
 }  /* x87_get_st_reg */
 
+#ifdef DEBUG_libfirm
 /**
  * Return the node at st(pos).
  *
@@ -182,18 +184,19 @@ static int x87_get_st_reg(const x87_state *state, int pos) {
  *
  * @return the IR node that produced the value at st(pos)
  */
-static ir_node *x87_get_st_node(const x87_state *state, int pos) {
+static ir_node *x87_get_st_node(const x87_state *state, int pos)
+{
 	assert(pos < state->depth);
 	return state->st[MASK_TOS(state->tos + pos)].node;
 }  /* x87_get_st_node */
 
-#ifdef DEBUG_libfirm
 /**
  * Dump the stack for debugging.
  *
  * @param state  the x87 state
  */
-static void x87_dump_stack(const x87_state *state) {
+static void x87_dump_stack(const x87_state *state)
+{
 	int i;
 
 	for (i = state->depth - 1; i >= 0; --i) {
@@ -212,7 +215,8 @@ static void x87_dump_stack(const x87_state *state) {
  * @param node     the IR node that produces the value of the vfp register
  * @param pos      the stack position where the new value should be entered
  */
-static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) {
+static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
+{
 	assert(0 < state->depth);
 	state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
 	state->st[MASK_TOS(state->tos + pos)].node    = node;
@@ -228,7 +232,8 @@ static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) {
  * @param reg_idx  the vfp register index that should be set
  * @param node     the IR node that produces the value of the vfp register
  */
-static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node) {
+static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node)
+{
 	x87_set_st(state, reg_idx, node, 0);
 }  /* x87_set_tos */
 
@@ -238,7 +243,8 @@ static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node) {
  * @param state    the x87 state
  * @param pos      the stack position to change the tos with
  */
-static void x87_fxch(x87_state *state, int pos) {
+static void x87_fxch(x87_state *state, int pos)
+{
 	st_entry entry;
 	assert(pos < state->depth);
 
@@ -258,7 +264,8 @@ static void x87_fxch(x87_state *state, int pos) {
  * @return the stack position where the register is stacked
  *         or -1 if the virtual register was not found
  */
-static int x87_on_stack(const x87_state *state, int reg_idx) {
+static int x87_on_stack(const x87_state *state, int reg_idx)
+{
 	int i, tos = state->tos;
 
 	for (i = 0; i < state->depth; ++i)
@@ -274,7 +281,8 @@ static int x87_on_stack(const x87_state *state, int reg_idx) {
  * @param reg_idx   the register vfp index
  * @param node      the node that produces the value of the vfp register
  */
-static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) {
+static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node)
+{
 	assert(state->depth < N_x87_REGS && "stack overrun");
 
 	++state->depth;
@@ -293,7 +301,8 @@ static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) {
  * @param node      the node that produces the value of the vfp register
  * @param dbl_push  if != 0 double pushes are allowed
  */
-static void x87_push(x87_state *state, int reg_idx, ir_node *node) {
+static void x87_push(x87_state *state, int reg_idx, ir_node *node)
+{
 	assert(x87_on_stack(state, reg_idx) == -1 && "double push");
 
 	x87_push_dbl(state, reg_idx, node);
@@ -304,7 +313,8 @@ static void x87_push(x87_state *state, int reg_idx, ir_node *node) {
  *
  * @param state     the x87 state
  */
-static void x87_pop(x87_state *state) {
+static void x87_pop(x87_state *state)
+{
 	assert(state->depth > 0 && "stack underrun");
 
 	--state->depth;
@@ -313,6 +323,17 @@ static void x87_pop(x87_state *state) {
 	DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state));
 }  /* x87_pop */
 
+/**
+ * Empty the fpu stack
+ *
+ * @param state     the x87 state
+ */
+static void x87_emms(x87_state *state)
+{
+	state->depth = 0;
+	state->tos   = 0;
+}
+
 /**
  * Returns the block state of a block.
  *
@@ -321,7 +342,8 @@ static void x87_pop(x87_state *state) {
  *
  * @return the block state
  */
-static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block) {
+static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
+{
 	pmap_entry *entry = pmap_find(sim->blk_states, block);
 
 	if (! entry) {
@@ -343,7 +365,8 @@ static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block) {
  *
  * @return a new x87 state
  */
-static x87_state *x87_alloc_state(x87_simulator *sim) {
+static x87_state *x87_alloc_state(x87_simulator *sim)
+{
 	x87_state *res = obstack_alloc(&sim->obst, sizeof(*res));
 
 	res->sim = sim;
@@ -358,10 +381,11 @@ static x87_state *x87_alloc_state(x87_simulator *sim) {
  *
  * @return a cloned copy of the src state
  */
-static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) {
+static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
+{
 	x87_state *res = x87_alloc_state(sim);
 
-	memcpy(res, src, sizeof(*res));
+	*res = *src;
 	return res;
 }  /* x87_clone_state */
 
@@ -372,7 +396,8 @@ static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) {
  * @param n   the IR node to patch
  * @param op  the x87 opcode to patch in
  */
-static ir_node *x87_patch_insn(ir_node *n, ir_op *op) {
+static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
+{
 	ir_mode *mode = get_irn_mode(n);
 	ir_node *res = n;
 
@@ -388,12 +413,12 @@ static ir_node *x87_patch_insn(ir_node *n, ir_op *op) {
 				mode = get_irn_mode(proj);
 				if (mode_is_float(mode)) {
 					res = proj;
-					set_irn_mode(proj, mode_E);
+					set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
 				}
 			}
 		}
 	} else if (mode_is_float(mode))
-		set_irn_mode(n, mode_E);
+		set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
 	return res;
 }  /* x87_patch_insn */
 
@@ -404,7 +429,8 @@ static ir_node *x87_patch_insn(ir_node *n, ir_op *op) {
  * @param m  the desired mode of the Proj
  * @return The first Proj of mode @p m found or NULL.
  */
-static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) {
+static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
+{
 	const ir_edge_t *edge;
 
 	assert(get_irn_mode(n) == mode_T && "Need mode_T node");
@@ -421,14 +447,23 @@ static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) {
 /**
  * Wrap the arch_* function here so we can check for errors.
  */
-static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, const ir_node *irn) {
-	const arch_register_t *res;
+static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
+{
+	const arch_register_t *res = arch_get_irn_register(irn);
 
-	res = arch_get_irn_register(sim->arch_env, irn);
 	assert(res->reg_class->regs == ia32_vfp_regs);
 	return res;
 }  /* x87_get_irn_register */
 
+static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
+                                                          int pos)
+{
+	const arch_register_t *res = arch_irn_get_register(irn, pos);
+
+	assert(res->reg_class->regs == ia32_vfp_regs);
+	return res;
+}  /* x87_irn_get_register */
+
 /* -------------- x87 perm --------------- */
 
 /**
@@ -443,11 +478,12 @@ static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, co
  *
  * @return the fxch node
  */
-static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) {
+static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block)
+{
 	ir_node         *fxch;
 	ia32_x87_attr_t *attr;
 
-	fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block, mode_E);
+	fxch = new_bd_ia32_fxch(NULL, block);
 	attr = get_ia32_x87_attr(fxch);
 	attr->x87[0] = &ia32_st_regs[pos];
 	attr->x87[2] = &ia32_st_regs[0];
@@ -612,12 +648,11 @@ static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
 {
 	ir_node         *fxch;
 	ia32_x87_attr_t *attr;
-	ir_graph        *irg = get_irn_irg(n);
 	ir_node         *block = get_nodes_block(n);
 
 	x87_fxch(state, pos);
 
-	fxch = new_rd_ia32_fxch(NULL, irg, block, mode_E);
+	fxch = new_bd_ia32_fxch(NULL, block);
 	attr = get_ia32_x87_attr(fxch);
 	attr->x87[0] = &ia32_st_regs[pos];
 	attr->x87[2] = &ia32_st_regs[0];
@@ -637,14 +672,15 @@ static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
  * @param pos       push st(pos) on stack
  * @param op_idx    replace input op_idx of n with the fpush result
  */
-static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) {
+static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx)
+{
 	ir_node               *fpush, *pred = get_irn_n(n, op_idx);
 	ia32_x87_attr_t       *attr;
-	const arch_register_t *out = x87_get_irn_register(state->sim, pred);
+	const arch_register_t *out = x87_get_irn_register(pred);
 
 	x87_push_dbl(state, arch_register_get_index(out), pred);
 
-	fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n), mode_E);
+	fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
 	attr  = get_ia32_x87_attr(fpush);
 	attr->x87[0] = &ia32_st_regs[pos];
 	attr->x87[2] = &ia32_st_regs[0];
@@ -666,12 +702,16 @@ static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx)
  */
 static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
 {
-	ir_node *fpop;
+	ir_node         *fpop = NULL;
 	ia32_x87_attr_t *attr;
 
+	assert(num > 0);
 	while (num > 0) {
 		x87_pop(state);
-		fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n), mode_E);
+		if (ia32_cg_config.use_ffreep)
+			fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
+		else
+			fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
 		attr = get_ia32_x87_attr(fpop);
 		attr->x87[0] = &ia32_st_regs[0];
 		attr->x87[1] = &ia32_st_regs[0];
@@ -694,12 +734,12 @@ static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
  *
  * @return the fldz node
  */
-static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx) {
-	ir_graph *irg = get_irn_irg(n);
+static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx)
+{
 	ir_node *block = get_nodes_block(n);
 	ir_node *fldz;
 
-	fldz = new_rd_ia32_fldz(NULL, irg, block, mode_E);
+	fldz = new_bd_ia32_fldz(NULL, block, ia32_reg_classes[CLASS_ia32_st].mode);
 
 	sched_add_before(n, fldz);
 	DB((dbg, LEVEL_1, "<<< %s\n", get_irn_opname(fldz)));
@@ -717,18 +757,16 @@ static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx) {
  * Updates a live set over a single step from a given node to its predecessor.
  * Everything defined at the node is removed from the set, the uses of the node get inserted.
  *
- * @param sim      The simulator handle.
  * @param irn      The node at which liveness should be computed.
  * @param live     The bitset of registers live before @p irn. This set gets modified by updating it to
  *                 the registers live after irn.
  *
  * @return The live bitset.
  */
-static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_liveness live)
+static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
 {
 	int i, n;
 	const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
-	const arch_env_t *arch_env = sim->arch_env;
 
 	if (get_irn_mode(irn) == mode_T) {
 		const ir_edge_t *edge;
@@ -736,23 +774,24 @@ static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_
 		foreach_out_edge(irn, edge) {
 			ir_node *proj = get_edge_src_irn(edge);
 
-			if (arch_irn_consider_in_reg_alloc(arch_env, cls, proj)) {
-				const arch_register_t *reg = x87_get_irn_register(sim, proj);
+			if (arch_irn_consider_in_reg_alloc(cls, proj)) {
+				const arch_register_t *reg = x87_get_irn_register(proj);
 				live &= ~(1 << arch_register_get_index(reg));
 			}
 		}
 	}
 
-	if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) {
-		const arch_register_t *reg = x87_get_irn_register(sim, irn);
+	if (arch_irn_consider_in_reg_alloc(cls, irn)) {
+		const arch_register_t *reg = x87_get_irn_register(irn);
 		live &= ~(1 << arch_register_get_index(reg));
 	}
 
 	for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
 		ir_node *op = get_irn_n(irn, i);
 
-		if (mode_is_float(get_irn_mode(op)) && arch_irn_consider_in_reg_alloc(arch_env, cls, op)) {
-			const arch_register_t *reg = x87_get_irn_register(sim, op);
+		if (mode_is_float(get_irn_mode(op)) &&
+				arch_irn_consider_in_reg_alloc(cls, op)) {
+			const arch_register_t *reg = x87_get_irn_register(op);
 			live |= 1 << arch_register_get_index(reg);
 		}
 	}
@@ -773,16 +812,15 @@ static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node
 	int i;
 	vfp_liveness live = 0;
 	const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
-	const arch_env_t *arch_env = sim->arch_env;
 	const be_lv_t *lv = sim->lv;
 
 	be_lv_foreach(lv, block, be_lv_state_end, i) {
 		const arch_register_t *reg;
 		const ir_node *node = be_lv_get_irn(lv, block, i);
-		if (!arch_irn_consider_in_reg_alloc(arch_env, cls, node))
+		if (!arch_irn_consider_in_reg_alloc(cls, node))
 			continue;
 
-		reg = x87_get_irn_register(sim, node);
+		reg = x87_get_irn_register(node);
 		live |= 1 << arch_register_get_index(reg);
 	}
 
@@ -816,7 +854,8 @@ static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsi
  * @param lv    the liveness handle
  * @param block the block
  */
-static void update_liveness(x87_simulator *sim, ir_node *block) {
+static void update_liveness(x87_simulator *sim, ir_node *block)
+{
 	vfp_liveness live = vfp_liveness_end_of_block(sim, block);
 	unsigned idx;
 	ir_node *irn;
@@ -830,7 +869,7 @@ static void update_liveness(x87_simulator *sim, ir_node *block) {
 		idx = get_irn_idx(irn);
 		sim->live[idx] = live;
 
-		live = vfp_liveness_transfer(sim, irn, live);
+		live = vfp_liveness_transfer(irn, live);
 	}
 	idx = get_irn_idx(block);
 	sim->live[idx] = live;
@@ -850,7 +889,8 @@ static void update_liveness(x87_simulator *sim, ir_node *block) {
  *
  * @param live  the live bitset
  */
-static void vfp_dump_live(vfp_liveness live) {
+static void vfp_dump_live(vfp_liveness live)
+{
 	int i;
 
 	DB((dbg, LEVEL_2, "Live after: "));
@@ -865,8 +905,6 @@ static void vfp_dump_live(vfp_liveness live) {
 
 /* --------------------------------- simulators ---------------------------------------- */
 
-#define XCHG(a, b) do { int t = (a); (a) = (b); (b) = t; } while (0)
-
 /**
  * Simulate a virtual binop.
  *
@@ -876,42 +914,66 @@ static void vfp_dump_live(vfp_liveness live) {
  *
  * @return NO_NODE_ADDED
  */
-static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) {
+static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl)
+{
 	int op2_idx = 0, op1_idx;
 	int out_idx, do_pop = 0;
 	ia32_x87_attr_t *attr;
+	int permuted;
 	ir_node *patched_insn;
 	ir_op *dst;
-	x87_simulator         *sim = state->sim;
-	const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1));
-	const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2));
-	const arch_register_t *out = x87_get_irn_register(sim, n);
-	int reg_index_1 = arch_register_get_index(op1);
-	int reg_index_2 = arch_register_get_index(op2);
-	vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
+	x87_simulator         *sim     = state->sim;
+	ir_node               *op1     = get_irn_n(n, n_ia32_binary_left);
+	ir_node               *op2     = get_irn_n(n, n_ia32_binary_right);
+	const arch_register_t *op1_reg = x87_get_irn_register(op1);
+	const arch_register_t *op2_reg = x87_get_irn_register(op2);
+	const arch_register_t *out     = x87_irn_get_register(n, pn_ia32_res);
+	int reg_index_1                = arch_register_get_index(op1_reg);
+	int reg_index_2                = arch_register_get_index(op2_reg);
+	vfp_liveness           live    = vfp_live_args_after(sim, n, REGMASK(out));
+	int                    op1_live_after;
+	int                    op2_live_after;
 
 	DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
-		arch_register_get_name(op1), arch_register_get_name(op2),
+		arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
 		arch_register_get_name(out)));
 	DEBUG_ONLY(vfp_dump_live(live));
 	DB((dbg, LEVEL_1, "Stack before: "));
 	DEBUG_ONLY(x87_dump_stack(state));
 
-	op1_idx = x87_on_stack(state, reg_index_1);
-	assert(op1_idx >= 0);
+	if (reg_index_1 == REG_VFP_UKNWN) {
+		op1_idx        = 0;
+		op1_live_after = 1;
+	} else {
+		op1_idx = x87_on_stack(state, reg_index_1);
+		assert(op1_idx >= 0);
+		op1_live_after = is_vfp_live(arch_register_get_index(op1_reg), live);
+	}
+
+	attr     = get_ia32_x87_attr(n);
+	permuted = attr->attr.data.ins_permuted;
 
 	if (reg_index_2 != REG_VFP_NOREG) {
-		/* second operand is a vfp register */
-		op2_idx = x87_on_stack(state, reg_index_2);
-		assert(op2_idx >= 0);
+		assert(!permuted);
 
-		if (is_vfp_live(arch_register_get_index(op2), live)) {
+		if (reg_index_2 == REG_VFP_UKNWN) {
+			op2_idx        = 0;
+			op2_live_after = 1;
+		} else {
+			/* second operand is a vfp register */
+			op2_idx = x87_on_stack(state, reg_index_2);
+			assert(op2_idx >= 0);
+			op2_live_after
+				= is_vfp_live(arch_register_get_index(op2_reg), live);
+		}
+
+		if (op2_live_after) {
 			/* Second operand is live. */
 
-			if (is_vfp_live(arch_register_get_index(op1), live)) {
+			if (op1_live_after) {
 				/* Both operands are live: push the first one.
 				   This works even for op1 == op2. */
-				x87_create_fpush(state, n, op1_idx, BINOP_IDX_2);
+				x87_create_fpush(state, n, op1_idx, n_ia32_binary_right);
 				/* now do fxxx (tos=tos X op) */
 				op1_idx = 0;
 				op2_idx += 1;
@@ -931,7 +993,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) {
 			}
 		} else {
 			/* Second operand is dead. */
-			if (is_vfp_live(arch_register_get_index(op1), live)) {
+			if (op1_live_after) {
 				/* First operand is live: bring second to tos. */
 				if (op2_idx != 0) {
 					x87_create_fxch(state, n, op2_idx);
@@ -985,24 +1047,21 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) {
 		}
 	} else {
 		/* second operand is an address mode */
-		if (is_vfp_live(arch_register_get_index(op1), live)) {
+		if (op1_live_after) {
 			/* first operand is live: push it here */
-			x87_create_fpush(state, n, op1_idx, BINOP_IDX_1);
+			x87_create_fpush(state, n, op1_idx, n_ia32_binary_left);
 			op1_idx = 0;
-			/* use fxxx (tos = tos X mem) */
-			dst = tmpl->normal_op;
-			out_idx = 0;
 		} else {
 			/* first operand is dead: bring it to tos */
 			if (op1_idx != 0) {
 				x87_create_fxch(state, n, op1_idx);
 				op1_idx = 0;
 			}
-
-			/* use fxxxp (tos = tos X mem) */
-			dst = tmpl->normal_op;
-			out_idx = 0;
 		}
+
+		/* use fxxx (tos = tos X mem) */
+		dst = permuted ? tmpl->reverse_op : tmpl->normal_op;
+		out_idx = 0;
 	}
 
 	patched_insn = x87_patch_insn(n, dst);
@@ -1012,20 +1071,19 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) {
 	}
 
 	/* patch the operation */
-	attr = get_ia32_x87_attr(n);
-	attr->x87[0] = op1 = &ia32_st_regs[op1_idx];
+	attr->x87[0] = op1_reg = &ia32_st_regs[op1_idx];
 	if (reg_index_2 != REG_VFP_NOREG) {
-		attr->x87[1] = op2 = &ia32_st_regs[op2_idx];
+		attr->x87[1] = op2_reg = &ia32_st_regs[op2_idx];
 	}
 	attr->x87[2] = out = &ia32_st_regs[out_idx];
 
 	if (reg_index_2 != REG_VFP_NOREG) {
 		DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
-			arch_register_get_name(op1), arch_register_get_name(op2),
+			arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
 			arch_register_get_name(out)));
 	} else {
 		DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n),
-			arch_register_get_name(op1),
+			arch_register_get_name(op1_reg),
 			arch_register_get_name(out)));
 	}
 
@@ -1041,11 +1099,12 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) {
  *
  * @return NO_NODE_ADDED
  */
-static int sim_unop(x87_state *state, ir_node *n, ir_op *op) {
+static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
+{
 	int op1_idx, out_idx;
 	x87_simulator         *sim = state->sim;
-	const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, UNOP_IDX));
-	const arch_register_t *out = x87_get_irn_register(sim, n);
+	const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, UNOP_IDX));
+	const arch_register_t *out = x87_get_irn_register(n);
 	ia32_x87_attr_t *attr;
 	unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
 
@@ -1086,13 +1145,14 @@ static int sim_unop(x87_state *state, ir_node *n, ir_op *op) {
  *
  * @return NO_NODE_ADDED
  */
-static int sim_load(x87_state *state, ir_node *n, ir_op *op) {
-	const arch_register_t *out = x87_get_irn_register(state->sim, n);
+static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
+{
+	const arch_register_t *out = x87_irn_get_register(n, res_pos);
 	ia32_x87_attr_t *attr;
 
 	DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
 	x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
-	assert(out == x87_get_irn_register(state->sim, n));
+	assert(out == x87_irn_get_register(n, res_pos));
 	attr = get_ia32_x87_attr(n);
 	attr->x87[2] = out = &ia32_st_regs[0];
 	DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
@@ -1107,7 +1167,8 @@ static int sim_load(x87_state *state, ir_node *n, ir_op *op) {
  * @param old_val The former value
  * @param new_val The new value
  */
-static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val) {
+static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
+{
 	const ir_edge_t *edge, *ne;
 
 	foreach_out_edge_safe(old_val, edge, ne) {
@@ -1136,11 +1197,11 @@ static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *
  * @param op     the x87 store opcode
  * @param op_p   the x87 store and pop opcode
  */
-static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
-	x87_simulator         *sim = state->sim;
-	ir_node               *val = get_irn_n(n, STORE_VAL_IDX);
-	const arch_register_t *op2 = x87_get_irn_register(sim, val);
-	unsigned              live = vfp_live_args_after(sim, n, 0);
+static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p)
+{
+	ir_node               *val = get_irn_n(n, n_ia32_vfst_val);
+	const arch_register_t *op2 = x87_get_irn_register(val);
+	unsigned              live = vfp_live_args_after(state->sim, n, 0);
 	int                   insn = NO_NODE_ADDED;
 	ia32_x87_attr_t *attr;
 	int op2_reg_idx, op2_idx, depth;
@@ -1150,7 +1211,7 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
 	op2_reg_idx = arch_register_get_index(op2);
 	if (op2_reg_idx == REG_VFP_UKNWN) {
 		/* just take any value from stack */
-		if(state->depth > 0) {
+		if (state->depth > 0) {
 			op2_idx = 0;
 			DEBUG_ONLY(op2 = NULL);
 			live_after_node = 1;
@@ -1173,15 +1234,17 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
 
 	if (live_after_node) {
 		/*
-			Problem: fst doesn't support mode_E (spills), only fstp does
+			Problem: fst doesn't support 96bit modes (spills), only fstp does
+			         fist doesn't support 64bit mode, only fistp
 			Solution:
 				- stack not full: push value and fstp
 				- stack full: fstp value and load again
+			Note that we cannot test on mode_E, because floats might be 96bit ...
 		*/
-		if (mode == mode_E) {
+		if (get_mode_size_bits(mode) > 64 || (mode_is_int(mode) && get_mode_size_bits(mode) > 32)) {
 			if (depth < N_x87_REGS) {
 				/* ok, we have a free register: push + fstp */
-				x87_create_fpush(state, n, op2_idx, STORE_VAL_IDX);
+				x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val);
 				x87_pop(state);
 				x87_patch_insn(n, op_p);
 			} else {
@@ -1193,31 +1256,30 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
 				x87_patch_insn(n, op_p);
 
 				block = get_nodes_block(n);
-				irg   = get_irn_irg(n);
-				vfld  = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg), get_ia32_ls_mode(n));
+				vfld  = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), new_NoMem(), get_ia32_ls_mode(n));
 
 				/* copy all attributes */
 				set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
 				if (is_ia32_use_frame(n))
 					set_ia32_use_frame(vfld);
-				set_ia32_am_flavour(vfld, get_ia32_am_flavour(n));
-				set_ia32_op_type(vfld, ia32_am_Source);
+				set_ia32_op_type(vfld, ia32_AddrModeS);
 				add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
 				set_ia32_am_sc(vfld, get_ia32_am_sc(n));
 				set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
 
-				rproj = new_r_Proj(irg, block, vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
-				mproj = new_r_Proj(irg, block, vfld, mode_M, pn_ia32_vfld_M);
+				rproj = new_r_Proj(block, vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
+				mproj = new_r_Proj(block, vfld, mode_M, pn_ia32_vfld_M);
 				mem   = get_irn_Proj_for_mode(n, mode_M);
 
 				assert(mem && "Store memory not found");
 
-				arch_set_irn_register(sim->arch_env, rproj, op2);
+				arch_set_irn_register(rproj, op2);
 
 				/* reroute all former users of the store memory to the load memory */
+				irg = get_irn_irg(n);
 				edges_reroute(mem, mproj, irg);
 				/* set the memory input of the load to the store memory */
-				set_irn_n(vfld, 2, mem);
+				set_irn_n(vfld, n_ia32_vfld_mem, mem);
 
 				sched_add_after(n, vfld);
 				sched_add_after(vfld, rproj);
@@ -1232,7 +1294,7 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
 			if (op2_idx != 0)
 				x87_create_fxch(state, n, op2_idx);
 
-			/* mode != mode_E -> use normal fst */
+			/* mode size 64 or smaller -> use normal fst */
 			x87_patch_insn(n, op);
 		}
 	} else {
@@ -1260,13 +1322,11 @@ static int sim_##op(x87_state *state, ir_node *n) { \
 #define GEN_BINOP(op)   _GEN_BINOP(op, op)
 #define GEN_BINOPR(op)	_GEN_BINOP(op, op##r)
 
-#define GEN_LOAD2(op, nop) \
-static int sim_##op(x87_state *state, ir_node *n) { \
-	return sim_load(state, n, op_ia32_##nop); \
+#define GEN_LOAD(op)                                              \
+static int sim_##op(x87_state *state, ir_node *n) {               \
+	return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
 }
 
-#define GEN_LOAD(op)	GEN_LOAD2(op, op)
-
 #define GEN_UNOP(op) \
 static int sim_##op(x87_state *state, ir_node *n) { \
 	return sim_unop(state, n, op_ia32_##op); \
@@ -1296,27 +1356,126 @@ GEN_STORE(fst)
 GEN_STORE(fist)
 
 /**
- * Simulate a fCondJmp.
+ * Simulate a virtual fisttp.
+ *
+ * @param state  the x87 state
+ * @param n      the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
+static int sim_fisttp(x87_state *state, ir_node *n)
+{
+	ir_node               *val = get_irn_n(n, n_ia32_vfst_val);
+	const arch_register_t *op2 = x87_get_irn_register(val);
+	ia32_x87_attr_t *attr;
+	int op2_reg_idx, op2_idx, depth;
+
+	op2_reg_idx = arch_register_get_index(op2);
+	if (op2_reg_idx == REG_VFP_UKNWN) {
+		/* just take any value from stack */
+		if (state->depth > 0) {
+			op2_idx = 0;
+			DEBUG_ONLY(op2 = NULL);
+		} else {
+			/* produce a new value which we will consume immediately */
+			x87_create_fldz(state, n, op2_reg_idx);
+			op2_idx = x87_on_stack(state, op2_reg_idx);
+			assert(op2_idx >= 0);
+		}
+	} else {
+		op2_idx = x87_on_stack(state, op2_reg_idx);
+		DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
+		assert(op2_idx >= 0);
+	}
+
+	depth = x87_get_depth(state);
+
+	/* Note: although the value is still live here, it is destroyed because
+	   of the pop. The register allocator is aware of that and introduced a copy
+	   if the value must be alive. */
+
+	/* we can only store the tos to memory */
+	if (op2_idx != 0)
+		x87_create_fxch(state, n, op2_idx);
+
+	x87_pop(state);
+	x87_patch_insn(n, op_ia32_fisttp);
+
+	attr = get_ia32_x87_attr(n);
+	attr->x87[1] = op2 = &ia32_st_regs[0];
+	DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
+
+	return NO_NODE_ADDED;
+}  /* sim_fisttp */
+
+/**
+ * Simulate a virtual FtstFnstsw.
+ *
+ * @param state  the x87 state
+ * @param n      the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
+static int sim_FtstFnstsw(x87_state *state, ir_node *n)
+{
+	x87_simulator         *sim         = state->sim;
+	ia32_x87_attr_t       *attr        = get_ia32_x87_attr(n);
+	ir_node               *op1_node    = get_irn_n(n, n_ia32_vFtstFnstsw_left);
+	const arch_register_t *reg1        = x87_get_irn_register(op1_node);
+	int                    reg_index_1 = arch_register_get_index(reg1);
+	int                    op1_idx     = x87_on_stack(state, reg_index_1);
+	unsigned               live        = vfp_live_args_after(sim, n, 0);
+
+	DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
+	DEBUG_ONLY(vfp_dump_live(live));
+	DB((dbg, LEVEL_1, "Stack before: "));
+	DEBUG_ONLY(x87_dump_stack(state));
+	assert(op1_idx >= 0);
+
+	if (op1_idx != 0) {
+		/* bring the value to tos */
+		x87_create_fxch(state, n, op1_idx);
+		op1_idx = 0;
+	}
+
+	/* patch the operation */
+	x87_patch_insn(n, op_ia32_FtstFnstsw);
+	reg1 = &ia32_st_regs[op1_idx];
+	attr->x87[0] = reg1;
+	attr->x87[1] = NULL;
+	attr->x87[2] = NULL;
+
+	if (!is_vfp_live(reg_index_1, live))
+		x87_create_fpop(state, sched_next(n), 1);
+
+	return NO_NODE_ADDED;
+}  /* sim_FtstFnstsw */
+
+/**
+ * Simulate a Fucom
  *
  * @param state  the x87 state
  * @param n      the node that should be simulated (and patched)
  *
  * @return NO_NODE_ADDED
  */
-static int sim_fCondJmp(x87_state *state, ir_node *n) {
+static int sim_Fucom(x87_state *state, ir_node *n)
+{
 	int op1_idx;
 	int op2_idx = -1;
-	int pop_cnt = 0;
-	ia32_x87_attr_t *attr;
+	ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
 	ir_op *dst;
 	x87_simulator         *sim = state->sim;
-	ir_node               *op1_node = get_irn_n(n, n_ia32_vfCondJmp_left);
-	ir_node               *op2_node = get_irn_n(n, n_ia32_vfCondJmp_right);
-	const arch_register_t *op1      = x87_get_irn_register(sim, op1_node);
-	const arch_register_t *op2      = x87_get_irn_register(sim, op2_node);
+	ir_node               *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
+	ir_node               *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
+	const arch_register_t *op1      = x87_get_irn_register(op1_node);
+	const arch_register_t *op2      = x87_get_irn_register(op2_node);
 	int reg_index_1 = arch_register_get_index(op1);
 	int reg_index_2 = arch_register_get_index(op2);
 	unsigned live = vfp_live_args_after(sim, n, 0);
+	bool                   permuted = attr->attr.data.ins_permuted;
+	bool                   xchg     = false;
+	int                    pops     = 0;
 
 	DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
 		arch_register_get_name(op1), arch_register_get_name(op2)));
@@ -1333,18 +1492,18 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) {
 		op2_idx = x87_on_stack(state, reg_index_2);
 		assert(op2_idx >= 0);
 
-		if (is_vfp_live(arch_register_get_index(op2), live)) {
+		if (is_vfp_live(reg_index_2, live)) {
 			/* second operand is live */
 
-			if (is_vfp_live(arch_register_get_index(op1), live)) {
+			if (is_vfp_live(reg_index_1, live)) {
 				/* both operands are live */
 
 				if (op1_idx == 0) {
 					/* res = tos X op */
-					dst = op_ia32_fcomJmp;
 				} else if (op2_idx == 0) {
 					/* res = op X tos */
-					dst = op_ia32_fcomrJmp;
+					permuted = !permuted;
+					xchg     = true;
 				} else {
 					/* bring the first one to tos */
 					x87_create_fxch(state, n, op1_idx);
@@ -1352,7 +1511,6 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) {
 						op2_idx = op1_idx;
 					op1_idx = 0;
 					/* res = tos X op */
-					dst     = op_ia32_fcomJmp;
 				}
 			} else {
 				/* second live, first operand is dead here, bring it to tos.
@@ -1365,12 +1523,11 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) {
 					op1_idx = 0;
 				}
 				/* res = tos X op, pop */
-				dst     = op_ia32_fcompJmp;
-				pop_cnt = 1;
+				pops = 1;
 			}
 		} else {
 			/* second operand is dead */
-			if (is_vfp_live(arch_register_get_index(op1), live)) {
+			if (is_vfp_live(reg_index_1, live)) {
 				/* first operand is live: bring second to tos.
 				   This means further, op1_idx != op2_idx. */
 				assert(op1_idx != op2_idx);
@@ -1381,8 +1538,9 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) {
 					op2_idx = 0;
 				}
 				/* res = op X tos, pop */
-				dst     = op_ia32_fcomrpJmp;
-				pop_cnt = 1;
+				pops     = 1;
+				permuted = !permuted;
+				xchg     = true;
 			} else {
 				/* both operands are dead here, check first for identity. */
 				if (op1_idx == op2_idx) {
@@ -1393,8 +1551,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) {
 						op2_idx = 0;
 					}
 					/* res = tos X op, pop */
-					dst     = op_ia32_fcompJmp;
-					pop_cnt = 1;
+					pops    = 1;
 				}
 				/* different, move them to st and st(1) and pop both.
 				   The tricky part is to get one into st(1).*/
@@ -1407,8 +1564,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) {
 						op1_idx = 0;
 					}
 					/* res = tos X op, pop, pop */
-					dst     = op_ia32_fcomppJmp;
-					pop_cnt = 2;
+					pops = 2;
 				} else if (op1_idx == 1) {
 					/* good, first operand is already in the right place, move the second */
 					if (op2_idx != 0) {
@@ -1417,8 +1573,10 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) {
 						assert(op1_idx != 0);
 						op2_idx = 0;
 					}
-					dst     = op_ia32_fcomrppJmp;
-					pop_cnt = 2;
+					/* res = op X tos, pop, pop */
+					permuted = !permuted;
+					xchg     = true;
+					pops     = 2;
 				} else {
 					/* if one is already the TOS, we need two fxch */
 					if (op1_idx == 0) {
@@ -1429,8 +1587,9 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) {
 						x87_create_fxch(state, n, op2_idx);
 						op2_idx = 0;
 						/* res = op X tos, pop, pop */
-						dst     = op_ia32_fcomrppJmp;
-						pop_cnt = 2;
+						pops     = 2;
+						permuted = !permuted;
+						xchg     = true;
 					} else if (op2_idx == 0) {
 						/* second one is TOS, move to st(1) */
 						x87_create_fxch(state, n, 1);
@@ -1439,8 +1598,7 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) {
 						x87_create_fxch(state, n, op1_idx);
 						op1_idx = 0;
 						/* res = tos X op, pop, pop */
-						dst     = op_ia32_fcomppJmp;
-						pop_cnt = 2;
+						pops    = 2;
 					} else {
 						/* none of them is either TOS or st(1), 3 fxch needed */
 						x87_create_fxch(state, n, op2_idx);
@@ -1450,41 +1608,65 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) {
 						x87_create_fxch(state, n, op1_idx);
 						op1_idx = 0;
 						/* res = tos X op, pop, pop */
-						dst     = op_ia32_fcomppJmp;
-						pop_cnt = 2;
+						pops    = 2;
 					}
 				}
 			}
 		}
 	} else {
 		/* second operand is an address mode */
-		if (is_vfp_live(arch_register_get_index(op1), live)) {
+		if (is_vfp_live(reg_index_1, live)) {
 			/* first operand is live: bring it to TOS */
 			if (op1_idx != 0) {
 				x87_create_fxch(state, n, op1_idx);
 				op1_idx = 0;
 			}
-			dst = op_ia32_fcomJmp;
 		} else {
 			/* first operand is dead: bring it to tos */
 			if (op1_idx != 0) {
 				x87_create_fxch(state, n, op1_idx);
 				op1_idx = 0;
 			}
-			dst = op_ia32_fcompJmp;
-			pop_cnt = 1;
+			pops = 1;
+		}
+	}
+
+	/* patch the operation */
+	if (is_ia32_vFucomFnstsw(n)) {
+		int i;
+
+		switch (pops) {
+		case 0: dst = op_ia32_FucomFnstsw;   break;
+		case 1: dst = op_ia32_FucompFnstsw;  break;
+		case 2: dst = op_ia32_FucomppFnstsw; break;
+		default: panic("invalid popcount in sim_Fucom");
+		}
+
+		for (i = 0; i < pops; ++i) {
+			x87_pop(state);
+		}
+	} else if (is_ia32_vFucomi(n)) {
+		switch (pops) {
+		case 0: dst = op_ia32_Fucomi;                  break;
+		case 1: dst = op_ia32_Fucompi; x87_pop(state); break;
+		case 2:
+			dst = op_ia32_Fucompi;
+			x87_pop(state);
+			x87_create_fpop(state, sched_next(n), 1);
+			break;
+		default: panic("invalid popcount in sim_Fucom");
 		}
+	} else {
+		panic("invalid operation %+F in sim_FucomFnstsw", n);
 	}
 
 	x87_patch_insn(n, dst);
-	assert(pop_cnt < 3);
-	if (pop_cnt >= 2)
-		x87_pop(state);
-	if (pop_cnt >= 1)
-		x87_pop(state);
+	if (xchg) {
+		int tmp = op1_idx;
+		op1_idx = op2_idx;
+		op2_idx = tmp;
+	}
 
-	/* patch the operation */
-	attr = get_ia32_x87_attr(n);
 	op1 = &ia32_st_regs[op1_idx];
 	attr->x87[0] = op1;
 	if (op2_idx >= 0) {
@@ -1492,57 +1674,68 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) {
 		attr->x87[1] = op2;
 	}
 	attr->x87[2] = NULL;
+	attr->attr.data.ins_permuted = permuted;
 
-	if (op2_idx >= 0)
+	if (op2_idx >= 0) {
 		DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
 			arch_register_get_name(op1), arch_register_get_name(op2)));
-	else
+	} else {
 		DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
 			arch_register_get_name(op1)));
+	}
 
 	return NO_NODE_ADDED;
-}  /* sim_fCondJmp */
+}  /* sim_Fucom */
 
-static
-int sim_Keep(x87_state *state, ir_node *node)
+/**
+ * Simulate a Keep.
+ *
+ * @param state  the x87 state
+ * @param n      the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
+static int sim_Keep(x87_state *state, ir_node *node)
 {
 	const ir_node         *op;
 	const arch_register_t *op_reg;
 	int                    reg_id;
 	int                    op_stack_idx;
 	unsigned               live;
+	int                    i, arity;
 
-	op      = get_irn_n(node, 0);
-	op_reg  = arch_get_irn_register(state->sim->arch_env, op);
-	if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
-		return NO_NODE_ADDED;
+	DB((dbg, LEVEL_1, ">>> %+F\n", node));
+
+	arity = get_irn_arity(node);
+	for (i = 0; i < arity; ++i) {
+		op      = get_irn_n(node, i);
+		op_reg  = arch_get_irn_register(op);
+		if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
+			continue;
 
-	reg_id = arch_register_get_index(op_reg);
-	live   = vfp_live_args_after(state->sim, node, 0);
+		reg_id = arch_register_get_index(op_reg);
+		live   = vfp_live_args_after(state->sim, node, 0);
 
-	op_stack_idx = x87_on_stack(state, reg_id);
-	if(op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) {
-		x87_create_fpop(state, sched_next(node), 1);
-		return NODE_ADDED;
+		op_stack_idx = x87_on_stack(state, reg_id);
+		if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
+			x87_create_fpop(state, sched_next(node), 1);
 	}
 
+	DB((dbg, LEVEL_1, "Stack after: "));
+	DEBUG_ONLY(x87_dump_stack(state));
+
 	return NO_NODE_ADDED;
-}
+}  /* sim_Keep */
 
-static
-void keep_float_node_alive(x87_state *state, ir_node *node)
+/**
+ * Keep the given node alive by adding a be_Keep.
+ *
+ * @param node  the node to kept alive
+ */
+static void keep_float_node_alive(ir_node *node)
 {
-	ir_graph                    *irg;
-	ir_node                     *block;
-	ir_node                     *in[1];
-	ir_node                     *keep;
-	const arch_register_class_t *cls;
-
-	irg    = get_irn_irg(node);
-	block  = get_nodes_block(node);
-	cls    = arch_get_irn_reg_class(state->sim->arch_env, node, -1);
-	in[0]  = node;
-	keep   = be_new_Keep(cls, irg, block, 1, in);
+	ir_node *block = get_nodes_block(node);
+	ir_node *keep  = be_new_Keep(block, 1, &node);
 
 	assert(sched_is_scheduled(node));
 	sched_add_after(node, keep);
@@ -1556,14 +1749,13 @@ void keep_float_node_alive(x87_state *state, ir_node *node)
  *
  * @return the copy of n
  */
-static ir_node *create_Copy(x87_state *state, ir_node *n) {
-	x87_simulator *sim = state->sim;
-	ir_graph *irg = get_irn_irg(n);
+static ir_node *create_Copy(x87_state *state, ir_node *n)
+{
 	dbg_info *n_dbg = get_irn_dbg_info(n);
 	ir_mode *mode = get_irn_mode(n);
 	ir_node *block = get_nodes_block(n);
 	ir_node *pred = get_irn_n(n, 0);
-	ir_node *(*cnstr)(dbg_info *, ir_graph *, ir_node *, ir_mode *) = NULL;
+	ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
 	ir_node *res;
 	const arch_register_t *out;
 	const arch_register_t *op1;
@@ -1573,36 +1765,36 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) {
 	switch (get_ia32_irn_opcode(pred)) {
 	case iro_ia32_Unknown_VFP:
 	case iro_ia32_fldz:
-		cnstr = new_rd_ia32_fldz;
+		cnstr = new_bd_ia32_fldz;
 		break;
 	case iro_ia32_fld1:
-		cnstr = new_rd_ia32_fld1;
+		cnstr = new_bd_ia32_fld1;
 		break;
 	case iro_ia32_fldpi:
-		cnstr = new_rd_ia32_fldpi;
+		cnstr = new_bd_ia32_fldpi;
 		break;
 	case iro_ia32_fldl2e:
-		cnstr = new_rd_ia32_fldl2e;
+		cnstr = new_bd_ia32_fldl2e;
 		break;
 	case iro_ia32_fldl2t:
-		cnstr = new_rd_ia32_fldl2t;
+		cnstr = new_bd_ia32_fldl2t;
 		break;
 	case iro_ia32_fldlg2:
-		cnstr = new_rd_ia32_fldlg2;
+		cnstr = new_bd_ia32_fldlg2;
 		break;
 	case iro_ia32_fldln2:
-		cnstr = new_rd_ia32_fldln2;
+		cnstr = new_bd_ia32_fldln2;
 		break;
 	default:
 		break;
 	}
 
-	out = x87_get_irn_register(sim, n);
-	op1 = x87_get_irn_register(sim, pred);
+	out = x87_get_irn_register(n);
+	op1 = x87_get_irn_register(pred);
 
 	if (cnstr != NULL) {
 		/* copy a constant */
-		res = (*cnstr)(n_dbg, irg, block, mode);
+		res = (*cnstr)(n_dbg, block, mode);
 
 		x87_push(state, arch_register_get_index(out), res);
 
@@ -1611,7 +1803,7 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) {
 	} else {
 		int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
 
-		res = new_rd_ia32_fpushCopy(n_dbg, irg, block, pred, mode);
+		res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
 
 		x87_push(state, arch_register_get_index(out), res);
 
@@ -1619,7 +1811,7 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) {
 		attr->x87[0] = &ia32_st_regs[op1_idx];
 		attr->x87[2] = &ia32_st_regs[0];
 	}
-	arch_set_irn_register(sim->arch_env, res, out);
+	arch_set_irn_register(res, out);
 
 	return res;
 }  /* create_Copy */
@@ -1632,26 +1824,25 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) {
  *
  * @return NO_NODE_ADDED
  */
-static int sim_Copy(x87_state *state, ir_node *n) {
-	x87_simulator         *sim;
-	ir_node               *pred;
-	const arch_register_t *out;
-	const arch_register_t *op1;
-	ir_node               *node, *next;
-	ia32_x87_attr_t       *attr;
-	int                   op1_idx, out_idx;
-	unsigned              live;
-
-	ir_mode *mode = get_irn_mode(n);
+static int sim_Copy(x87_state *state, ir_node *n)
+{
+	ir_node                     *pred;
+	const arch_register_t       *out;
+	const arch_register_t       *op1;
+	const arch_register_class_t *cls;
+	ir_node                     *node, *next;
+	ia32_x87_attr_t             *attr;
+	int                         op1_idx, out_idx;
+	unsigned                    live;
 
-	if (!mode_is_float(mode))
+	cls = arch_get_irn_reg_class_out(n);
+	if (cls->regs != ia32_vfp_regs)
 		return 0;
 
-	sim = state->sim;
 	pred = get_irn_n(n, 0);
-	out = x87_get_irn_register(sim, n);
-	op1 = x87_get_irn_register(sim, pred);
-	live = vfp_live_args_after(sim, n, REGMASK(out));
+	out  = x87_get_irn_register(n);
+	op1  = x87_get_irn_register(pred);
+	live = vfp_live_args_after(state->sim, n, REGMASK(out));
 
 	DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
 		arch_register_get_name(op1), arch_register_get_name(out)));
@@ -1670,7 +1861,7 @@ static int sim_Copy(x87_state *state, ir_node *n) {
 		sched_add_before(next, node);
 
 		DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
-		    arch_get_irn_register(sim->arch_env, node)->name));
+		    arch_get_irn_register(node)->name));
 		return NO_NODE_ADDED;
 	}
 
@@ -1694,12 +1885,11 @@ static int sim_Copy(x87_state *state, ir_node *n) {
 		exchange(n, node);
 		sched_add_before(next, node);
 
-		if(get_irn_n_edges(pred) == 0) {
-			keep_float_node_alive(state, pred);
+		if (get_irn_n_edges(pred) == 0) {
+			keep_float_node_alive(pred);
 		}
 
-		DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
-		    arch_get_irn_register(sim->arch_env, node)->name));
+		DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
 	} else {
 		out_idx = x87_on_stack(state, arch_register_get_index(out));
 
@@ -1746,61 +1936,49 @@ static int sim_Copy(x87_state *state, ir_node *n) {
 }  /* sim_Copy */
 
 /**
- * Returns the result proj of the call, or NULL if the result is not used
+ * Returns the vf0 result Proj of a Call.
+ *
+ * @para call  the Call node
  */
-static ir_node *get_call_result_proj(ir_node *call) {
+static ir_node *get_call_result_proj(ir_node *call)
+{
 	const ir_edge_t *edge;
-	ir_node *resproj = NULL;
 
 	/* search the result proj */
 	foreach_out_edge(call, edge) {
 		ir_node *proj = get_edge_src_irn(edge);
 		long pn = get_Proj_proj(proj);
 
-		if (pn == pn_be_Call_first_res) {
-			resproj = proj;
-			break;
-		}
-	}
-	if (resproj == NULL) {
-		return NULL;
-	}
-
-	/* the result proj is connected to a Keep and maybe other nodes */
-	foreach_out_edge(resproj, edge) {
-		ir_node *pred = get_edge_src_irn(edge);
-		if (!be_is_Keep(pred)) {
-			return resproj;
-		}
+		if (pn == pn_ia32_Call_vf0)
+			return proj;
 	}
 
-	/* only be_Keep found, so result is not used */
 	return NULL;
 }  /* get_call_result_proj */
 
 /**
- * Simulate a be_Call.
+ * Simulate a ia32_Call.
  *
  * @param state      the x87 state
- * @param n          the node that should be simulated
- * @param arch_env   the architecture environment
+ * @param n          the node that should be simulated (and patched)
  *
  * @return NO_NODE_ADDED
  */
-static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env)
+static int sim_Call(x87_state *state, ir_node *n)
 {
-	ir_type *call_tp = be_Call_get_type(n);
+	ir_type *call_tp = get_ia32_call_attr_const(n)->call_tp;
 	ir_type *res_type;
 	ir_mode *mode;
 	ir_node *resproj;
 	const arch_register_t *reg;
-	(void) arch_env;
+
+	DB((dbg, LEVEL_1, ">>> %+F\n", n));
 
 	/* at the begin of a call the x87 state should be empty */
 	assert(state->depth == 0 && "stack not empty before call");
 
 	if (get_method_n_ress(call_tp) <= 0)
-		return NO_NODE_ADDED;
+		goto end_call;
 
 	/*
 	 * If the called function returns a float, it is returned in st(0).
@@ -1811,15 +1989,18 @@ static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env)
 	mode     = get_type_mode(res_type);
 
 	if (mode == NULL || !mode_is_float(mode))
-		return NO_NODE_ADDED;
+		goto end_call;
 
 	resproj = get_call_result_proj(n);
-	if (resproj == NULL)
-		return NO_NODE_ADDED;
+	assert(resproj != NULL);
 
-	reg = x87_get_irn_register(state->sim, resproj);
+	reg = x87_get_irn_register(resproj);
 	x87_push(state, arch_register_get_index(reg), resproj);
 
+end_call:
+	DB((dbg, LEVEL_1, "Stack after: "));
+	DEBUG_ONLY(x87_dump_stack(state));
+
 	return NO_NODE_ADDED;
 }  /* sim_Call */
 
@@ -1831,8 +2012,9 @@ static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env)
  *
  * Should not happen, spills are lowered before x87 simulator see them.
  */
-static int sim_Spill(x87_state *state, ir_node *n) {
-	assert(0 && "Spill not lowered");
+static int sim_Spill(x87_state *state, ir_node *n)
+{
+	panic("Spill not lowered before x87 simulator run");
 	return sim_fst(state, n);
 }  /* sim_Spill */
 
@@ -1844,8 +2026,9 @@ static int sim_Spill(x87_state *state, ir_node *n) {
  *
  * Should not happen, reloads are lowered before x87 simulator see them.
  */
-static int sim_Reload(x87_state *state, ir_node *n) {
-	assert(0 && "Reload not lowered");
+static int sim_Reload(x87_state *state, ir_node *n)
+{
+	panic("Reload not lowered before x87 simulator run");
 	return sim_fld(state, n);
 }  /* sim_Reload */
 
@@ -1857,11 +2040,12 @@ static int sim_Reload(x87_state *state, ir_node *n) {
  *
  * @return NO_NODE_ADDED
  */
-static int sim_Return(x87_state *state, ir_node *n) {
+static int sim_Return(x87_state *state, ir_node *n)
+{
 	int n_res = be_Return_get_n_rets(n);
 	int i, n_float_res = 0;
 
-	/* only floating point return values must resist on stack */
+	/* only floating point return values must reside on stack */
 	for (i = 0; i < n_res; ++i) {
 		ir_node *res = get_irn_n(n, be_pos_Return_val + i);
 
@@ -1890,9 +2074,9 @@ typedef struct _perm_data_t {
  *
  * @return NO_NODE_ADDED
  */
-static int sim_Perm(x87_state *state, ir_node *irn) {
+static int sim_Perm(x87_state *state, ir_node *irn)
+{
 	int             i, n;
-	x87_simulator   *sim = state->sim;
 	ir_node         *pred = get_irn_n(irn, 0);
 	int             *stack_pos;
 	const ir_edge_t *edge;
@@ -1912,7 +2096,7 @@ static int sim_Perm(x87_state *state, ir_node *irn) {
 
 	/* collect old stack positions */
 	for (i = 0; i < n; ++i) {
-		const arch_register_t *inreg = x87_get_irn_register(sim, get_irn_n(irn, i));
+		const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
 		int idx = x87_on_stack(state, arch_register_get_index(inreg));
 
 		assert(idx >= 0 && "Perm argument not on x87 stack");
@@ -1922,7 +2106,7 @@ static int sim_Perm(x87_state *state, ir_node *irn) {
 	/* now do the permutation */
 	foreach_out_edge(irn, edge) {
 		ir_node               *proj = get_edge_src_irn(edge);
-		const arch_register_t *out  = x87_get_irn_register(sim, proj);
+		const arch_register_t *out  = x87_get_irn_register(proj);
 		long                  num   = get_Proj_proj(proj);
 
 		assert(0 <= num && num < n && "More Proj's than Perm inputs");
@@ -1933,6 +2117,50 @@ static int sim_Perm(x87_state *state, ir_node *irn) {
 	return NO_NODE_ADDED;
 }  /* sim_Perm */
 
+/**
+ * Simulate the Barrier to generate Unknowns.
+ * We must push something on the stack for its value.
+ *
+ * @param state  the x87 state
+ * @param irn    the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
+static int sim_Barrier(x87_state *state, ir_node *node)
+{
+	int i, arity;
+
+	/* materialize unknown if needed */
+	arity = get_irn_arity(node);
+	for (i = 0; i < arity; ++i) {
+		const arch_register_t       *reg;
+		ir_node                     *zero;
+		ir_node                     *block;
+		ia32_x87_attr_t             *attr;
+		ir_node                     *in    = get_irn_n(node, i);
+
+		if (!is_ia32_Unknown_VFP(in))
+			continue;
+
+		/* TODO: not completely correct... */
+		reg = &ia32_vfp_regs[REG_VFP_UKNWN];
+
+		/* create a zero */
+		block = get_nodes_block(node);
+		zero  = new_bd_ia32_fldz(NULL, block, ia32_reg_classes[CLASS_ia32_st].mode);
+		x87_push(state, arch_register_get_index(reg), zero);
+
+		attr = get_ia32_x87_attr(zero);
+		attr->x87[2] = &ia32_st_regs[0];
+
+		sched_add_before(node, zero);
+
+		set_irn_n(node, i, zero);
+	}
+
+	return NO_NODE_ADDED;
+}  /* sim_Barrier */
+
 /**
  * Kill any dead registers at block start by popping them from the stack.
  *
@@ -1942,7 +2170,8 @@ static int sim_Perm(x87_state *state, ir_node *irn) {
  *
  * @return the x87 state after dead register killed
  */
-static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state) {
+static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state)
+{
 	x87_state *state = start_state;
 	ir_node *first_insn = sched_first(block);
 	ir_node *keep = NULL;
@@ -1967,6 +2196,22 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *
 		DEBUG_ONLY(vfp_dump_live(live));
 		DEBUG_ONLY(x87_dump_stack(state));
 
+		if (kill_mask != 0 && live == 0) {
+			/* special case: kill all registers */
+			if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
+				if (ia32_cg_config.use_femms) {
+					/* use FEMMS on AMD processors to clear all */
+					keep = new_bd_ia32_femms(NULL, block);
+				} else {
+					/* use EMMS to clear all */
+					keep = new_bd_ia32_emms(NULL, block);
+				}
+				sched_add_before(first_insn, keep);
+				keep_alive(keep);
+				x87_emms(state);
+				return state;
+			}
+		}
 		/* now kill registers */
 		while (kill_mask) {
 			/* we can only kill from TOS, so bring them up */
@@ -2004,30 +2249,32 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *
 }  /* x87_kill_deads */
 
 /**
- * If we have PhiEs with unknown operands then we have to make sure that some
- * value is actually put onto the stack.
+ * If we have PhiEs with unknown operands in a block
+ * we have to make sure that some value is actually put onto the stack.
+ *
+ * @param state       the x87 state
+ * @param block       the block that should be checked
+ * @param pred_block  check inputs from this predecessor block
+ * @param pos         index of pred_block
  */
 static void fix_unknown_phis(x87_state *state, ir_node *block,
                              ir_node *pred_block, int pos)
 {
-	ir_node *node, *op;
+	ir_node *phi, *op;
 
-	sched_foreach(block, node) {
+	sched_foreach_Phi(block, phi) {
 		ir_node               *zero;
 		const arch_register_t *reg;
 		ia32_x87_attr_t       *attr;
 
-		if(!is_Phi(node))
-			break;
-
-		op = get_Phi_pred(node, pos);
-		if(!is_ia32_Unknown_VFP(op))
+		op = get_Phi_pred(phi, pos);
+		if (!is_ia32_Unknown_VFP(op))
 			continue;
 
-		reg = arch_get_irn_register(state->sim->arch_env, node);
+		reg = arch_get_irn_register(phi);
 
 		/* create a zero at end of pred block */
-		zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E);
+		zero = new_bd_ia32_fldz(NULL, pred_block, ia32_reg_classes[CLASS_ia32_st].mode);
 		x87_push(state, arch_register_get_index(reg), zero);
 
 		attr = get_ia32_x87_attr(zero);
@@ -2036,9 +2283,9 @@ static void fix_unknown_phis(x87_state *state, ir_node *block,
 		assert(is_ia32_fldz(zero));
 		sched_add_before(sched_last(pred_block), zero);
 
-		set_Phi_pred(node, pos, zero);
+		set_Phi_pred(phi, pos, zero);
 	}
-}
+}  /* fix_unknown_phis */
 
 /**
  * Run a simulation and fix all virtual instructions for a block.
@@ -2046,7 +2293,8 @@ static void fix_unknown_phis(x87_state *state, ir_node *block,
  * @param sim          the simulator handle
  * @param block        the current block
  */
-static void x87_simulate_block(x87_simulator *sim, ir_node *block) {
+static void x87_simulate_block(x87_simulator *sim, ir_node *block)
+{
 	ir_node *n, *next;
 	blk_state *bl_state = x87_get_bl_state(sim, block);
 	x87_state *state = bl_state->begin;
@@ -2073,23 +2321,26 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) {
 		sim_func func;
 		ir_op *op = get_irn_op(n);
 
+		/*
+		 * get the next node to be simulated here.
+		 * n might be completely removed from the schedule-
+		 */
 		next = sched_next(n);
-		if (op->ops.generic == NULL)
-			continue;
-
-		func = (sim_func)op->ops.generic;
+		if (op->ops.generic != NULL) {
+			func = (sim_func)op->ops.generic;
 
-		/* simulate it */
-		node_inserted = (*func)(state, n);
+			/* simulate it */
+			node_inserted = (*func)(state, n);
 
-		/*
-			sim_func might have added an additional node after n,
-			so update next node
-			beware: n must not be changed by sim_func
-			(i.e. removed from schedule) in this case
-		*/
-		if (node_inserted != NO_NODE_ADDED)
-			next = sched_next(n);
+			/*
+			 * sim_func might have added an additional node after n,
+			 * so update next node
+			 * beware: n must not be changed by sim_func
+			 * (i.e. removed from schedule) in this case
+			 */
+			if (node_inserted != NO_NODE_ADDED)
+				next = sched_next(n);
+		}
 	}
 
 	start_block = get_irg_start_block(get_irn_irg(block));
@@ -2128,19 +2379,28 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) {
 	bl_state->end = state;
 }  /* x87_simulate_block */
 
+/**
+ * Register a simulator function.
+ *
+ * @param op    the opcode to simulate
+ * @param func  the simulator function for the opcode
+ */
+static void register_sim(ir_op *op, sim_func func)
+{
+	assert(op->ops.generic == NULL);
+	op->ops.generic = (op_func) func;
+}  /* register_sim */
+
 /**
  * Create a new x87 simulator.
  *
  * @param sim       a simulator handle, will be initialized
  * @param irg       the current graph
- * @param arch_env  the architecture environment
  */
-static void x87_init_simulator(x87_simulator *sim, ir_graph *irg,
-                               const arch_env_t *arch_env)
+static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
 {
 	obstack_init(&sim->obst);
 	sim->blk_states = pmap_create();
-	sim->arch_env   = arch_env;
 	sim->n_idx      = get_irg_last_idx(irg);
 	sim->live       = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
 
@@ -2150,33 +2410,31 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg,
 	/* set the generic function pointer of instruction we must simulate */
 	clear_irp_opcodes_generic_func();
 
-#define ASSOC(op)       (op_ ## op)->ops.generic = (op_func)(sim_##op)
-#define ASSOC_IA32(op)  (op_ia32_v ## op)->ops.generic = (op_func)(sim_##op)
-#define ASSOC_BE(op)    (op_be_ ## op)->ops.generic = (op_func)(sim_##op)
-	ASSOC_IA32(fld);
-	ASSOC_IA32(fild);
-	ASSOC_IA32(fld1);
-	ASSOC_IA32(fldz);
-	ASSOC_IA32(fadd);
-	ASSOC_IA32(fsub);
-	ASSOC_IA32(fmul);
-	ASSOC_IA32(fdiv);
-	ASSOC_IA32(fprem);
-	ASSOC_IA32(fabs);
-	ASSOC_IA32(fchs);
-	ASSOC_IA32(fist);
-	ASSOC_IA32(fst);
-	ASSOC_IA32(fCondJmp);
-	ASSOC_BE(Copy);
-	ASSOC_BE(Call);
-	ASSOC_BE(Spill);
-	ASSOC_BE(Reload);
-	ASSOC_BE(Return);
-	ASSOC_BE(Perm);
-	ASSOC_BE(Keep);
-#undef ASSOC_BE
-#undef ASSOC_IA32
-#undef ASSOC
+	register_sim(op_ia32_Call,         sim_Call);
+	register_sim(op_ia32_vfld,         sim_fld);
+	register_sim(op_ia32_vfild,        sim_fild);
+	register_sim(op_ia32_vfld1,        sim_fld1);
+	register_sim(op_ia32_vfldz,        sim_fldz);
+	register_sim(op_ia32_vfadd,        sim_fadd);
+	register_sim(op_ia32_vfsub,        sim_fsub);
+	register_sim(op_ia32_vfmul,        sim_fmul);
+	register_sim(op_ia32_vfdiv,        sim_fdiv);
+	register_sim(op_ia32_vfprem,       sim_fprem);
+	register_sim(op_ia32_vfabs,        sim_fabs);
+	register_sim(op_ia32_vfchs,        sim_fchs);
+	register_sim(op_ia32_vfist,        sim_fist);
+	register_sim(op_ia32_vfisttp,      sim_fisttp);
+	register_sim(op_ia32_vfst,         sim_fst);
+	register_sim(op_ia32_vFtstFnstsw,  sim_FtstFnstsw);
+	register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
+	register_sim(op_ia32_vFucomi,      sim_Fucom);
+	register_sim(op_be_Copy,           sim_Copy);
+	register_sim(op_be_Spill,          sim_Spill);
+	register_sim(op_be_Reload,         sim_Reload);
+	register_sim(op_be_Return,         sim_Return);
+	register_sim(op_be_Perm,           sim_Perm);
+	register_sim(op_be_Keep,           sim_Keep);
+	register_sim(op_be_Barrier,        sim_Barrier);
 }  /* x87_init_simulator */
 
 /**
@@ -2184,7 +2442,8 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg,
  *
  * @param sim  the simulator handle
  */
-static void x87_destroy_simulator(x87_simulator *sim) {
+static void x87_destroy_simulator(x87_simulator *sim)
+{
 	pmap_destroy(sim->blk_states);
 	obstack_free(&sim->obst, NULL);
 	DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
@@ -2194,30 +2453,31 @@ static void x87_destroy_simulator(x87_simulator *sim) {
  * Pre-block walker: calculate the liveness information for the block
  * and store it into the sim->live cache.
  */
-static void update_liveness_walker(ir_node *block, void *data) {
+static void update_liveness_walker(ir_node *block, void *data)
+{
 	x87_simulator *sim = data;
 	update_liveness(sim, block);
 }  /* update_liveness_walker */
 
-/**
+/*
  * Run a simulation and fix all virtual instructions for a graph.
- *
- * @param env       the architecture environment
- * @param irg       the current graph
- *
- * Needs a block-schedule.
+ * Replaces all virtual floating point instructions and registers
+ * by real ones.
  */
-void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) {
+void x87_simulate_graph(be_irg_t *birg)
+{
+	/* TODO improve code quality (less executed fxch) by using execfreqs */
+
 	ir_node       *block, *start_block;
 	blk_state     *bl_state;
 	x87_simulator sim;
 	ir_graph      *irg = be_get_birg_irg(birg);
 
 	/* create the simulator */
-	x87_init_simulator(&sim, irg, arch_env);
+	x87_init_simulator(&sim, irg);
 
 	start_block = get_irg_start_block(irg);
-	bl_state = x87_get_bl_state(&sim, start_block);
+	bl_state    = x87_get_bl_state(&sim, start_block);
 
 	/* start with the empty state */
 	bl_state->begin = empty;
@@ -2228,7 +2488,6 @@ void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) {
 
 	be_assure_liveness(birg);
 	sim.lv = be_get_birg_liveness(birg);
-//	sim.lv = be_liveness(be_get_birg_irg(birg));
 	be_liveness_assure_sets(sim.lv);
 
 	/* Calculate the liveness for all nodes. We must precalculate this info,
@@ -2250,6 +2509,8 @@ void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) {
 	x87_destroy_simulator(&sim);
 }  /* x87_simulate_graph */
 
-void ia32_init_x87(void) {
+/* Initializes the x87 simulator. */
+void ia32_init_x87(void)
+{
 	FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
 }  /* ia32_init_x87 */