X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_x87.c;h=4f856467ccc3b91e8c8b47e94e986a664be90339;hb=ac9e2a1306f3d90df39fb81ab4ea13559145fa19;hp=a0fd212d467711b1e1e2f55d1545046e2b6192df;hpb=2e291eab8268af551488b1f4fb4d9ca61b625e33;p=libfirm diff --git a/ir/be/ia32/ia32_x87.c b/ir/be/ia32/ia32_x87.c index a0fd212d4..4f856467c 100644 --- a/ir/be/ia32/ia32_x87.c +++ b/ir/be/ia32/ia32_x87.c @@ -24,9 +24,7 @@ * @author Michael Beck * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif #include @@ -104,9 +102,13 @@ typedef struct _x87_state { static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL }; static x87_state *empty = (x87_state *)&_empty; +/** + * Return values of the instruction simulator functions. + */ enum { - NO_NODE_ADDED = 0, /**< No node was added. */ - NODE_ADDED = 1 /**< A node was added by the simulator in the schedule. */ + NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */ + NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator + in the schedule AFTER the current node. */ }; /** @@ -115,8 +117,9 @@ enum { * @param state the x87 state * @param n the node to be simulated * - * @return NODE_ADDED if a node was added AFTER n in schedule, - * NO_NODE_ADDED else + * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be + * simulated further + * NO_NODE_ADDED otherwise */ typedef int (*sim_func)(x87_state *state, ir_node *n); @@ -139,7 +142,6 @@ typedef unsigned char vfp_liveness; struct _x87_simulator { struct obstack obst; /**< An obstack for fast allocating. */ pmap *blk_states; /**< Map blocks to states. */ - const arch_env_t *arch_env; /**< The architecture environment. */ be_lv_t *lv; /**< intrablock liveness. */ vfp_liveness *live; /**< Liveness information. */ unsigned n_idx; /**< The cached get_irg_last_idx() result. */ @@ -383,7 +385,7 @@ static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) { x87_state *res = x87_alloc_state(sim); - memcpy(res, src, sizeof(*res)); + *res = *src; return res; } /* x87_clone_state */ @@ -411,12 +413,12 @@ static ir_node *x87_patch_insn(ir_node *n, ir_op *op) mode = get_irn_mode(proj); if (mode_is_float(mode)) { res = proj; - set_irn_mode(proj, mode_E); + set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode); } } } } else if (mode_is_float(mode)) - set_irn_mode(n, mode_E); + set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode); return res; } /* x87_patch_insn */ @@ -445,7 +447,7 @@ static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) /** * Wrap the arch_* function here so we can check for errors. */ -static INLINE const arch_register_t *x87_get_irn_register(const ir_node *irn) +static inline const arch_register_t *x87_get_irn_register(const ir_node *irn) { const arch_register_t *res = arch_get_irn_register(irn); @@ -453,6 +455,15 @@ static INLINE const arch_register_t *x87_get_irn_register(const ir_node *irn) return res; } /* x87_get_irn_register */ +static inline const arch_register_t *x87_irn_get_register(const ir_node *irn, + int pos) +{ + const arch_register_t *res = arch_irn_get_register(irn, pos); + + assert(res->reg_class->regs == ia32_vfp_regs); + return res; +} /* x87_irn_get_register */ + /* -------------- x87 perm --------------- */ /** @@ -472,7 +483,7 @@ static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) ir_node *fxch; ia32_x87_attr_t *attr; - fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block); + fxch = new_bd_ia32_fxch(NULL, block); attr = get_ia32_x87_attr(fxch); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -637,12 +648,11 @@ static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos) { ir_node *fxch; ia32_x87_attr_t *attr; - ir_graph *irg = get_irn_irg(n); ir_node *block = get_nodes_block(n); x87_fxch(state, pos); - fxch = new_rd_ia32_fxch(NULL, irg, block); + fxch = new_bd_ia32_fxch(NULL, block); attr = get_ia32_x87_attr(fxch); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -670,7 +680,7 @@ static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) x87_push_dbl(state, arch_register_get_index(out), pred); - fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n)); + fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n)); attr = get_ia32_x87_attr(fpush); attr->x87[0] = &ia32_st_regs[pos]; attr->x87[2] = &ia32_st_regs[0]; @@ -699,9 +709,9 @@ static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num) while (num > 0) { x87_pop(state); if (ia32_cg_config.use_ffreep) - fpop = new_rd_ia32_ffreep(NULL, get_irn_irg(n), get_nodes_block(n)); + fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n)); else - fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n)); + fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n)); attr = get_ia32_x87_attr(fpop); attr->x87[0] = &ia32_st_regs[0]; attr->x87[1] = &ia32_st_regs[0]; @@ -726,11 +736,10 @@ static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num) */ static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx) { - ir_graph *irg = get_irn_irg(n); ir_node *block = get_nodes_block(n); ir_node *fldz; - fldz = new_rd_ia32_fldz(NULL, irg, block, mode_E); + fldz = new_bd_ia32_fldz(NULL, block, ia32_reg_classes[CLASS_ia32_st].mode); sched_add_before(n, fldz); DB((dbg, LEVEL_1, "<<< %s\n", get_irn_opname(fldz))); @@ -748,18 +757,16 @@ static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx) * Updates a live set over a single step from a given node to its predecessor. * Everything defined at the node is removed from the set, the uses of the node get inserted. * - * @param sim The simulator handle. * @param irn The node at which liveness should be computed. * @param live The bitset of registers live before @p irn. This set gets modified by updating it to * the registers live after irn. * * @return The live bitset. */ -static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_liveness live) +static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live) { int i, n; const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp]; - const arch_env_t *arch_env = sim->arch_env; if (get_irn_mode(irn) == mode_T) { const ir_edge_t *edge; @@ -767,14 +774,14 @@ static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_ foreach_out_edge(irn, edge) { ir_node *proj = get_edge_src_irn(edge); - if (arch_irn_consider_in_reg_alloc(arch_env, cls, proj)) { + if (arch_irn_consider_in_reg_alloc(cls, proj)) { const arch_register_t *reg = x87_get_irn_register(proj); live &= ~(1 << arch_register_get_index(reg)); } } } - if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) { + if (arch_irn_consider_in_reg_alloc(cls, irn)) { const arch_register_t *reg = x87_get_irn_register(irn); live &= ~(1 << arch_register_get_index(reg)); } @@ -782,7 +789,8 @@ static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_ for (i = 0, n = get_irn_arity(irn); i < n; ++i) { ir_node *op = get_irn_n(irn, i); - if (mode_is_float(get_irn_mode(op)) && arch_irn_consider_in_reg_alloc(arch_env, cls, op)) { + if (mode_is_float(get_irn_mode(op)) && + arch_irn_consider_in_reg_alloc(cls, op)) { const arch_register_t *reg = x87_get_irn_register(op); live |= 1 << arch_register_get_index(reg); } @@ -804,13 +812,12 @@ static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node int i; vfp_liveness live = 0; const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp]; - const arch_env_t *arch_env = sim->arch_env; const be_lv_t *lv = sim->lv; be_lv_foreach(lv, block, be_lv_state_end, i) { const arch_register_t *reg; const ir_node *node = be_lv_get_irn(lv, block, i); - if (!arch_irn_consider_in_reg_alloc(arch_env, cls, node)) + if (!arch_irn_consider_in_reg_alloc(cls, node)) continue; reg = x87_get_irn_register(node); @@ -862,7 +869,7 @@ static void update_liveness(x87_simulator *sim, ir_node *block) idx = get_irn_idx(irn); sim->live[idx] = live; - live = vfp_liveness_transfer(sim, irn, live); + live = vfp_liveness_transfer(irn, live); } idx = get_irn_idx(block); sim->live[idx] = live; @@ -898,17 +905,6 @@ static void vfp_dump_live(vfp_liveness live) /* --------------------------------- simulators ---------------------------------------- */ -#define XCHG(a, b) do { int t = (a); (a) = (b); (b) = t; } while (0) - -/* Pseudocode: - - - - - - -*/ - /** * Simulate a virtual binop. * @@ -931,7 +927,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) ir_node *op2 = get_irn_n(n, n_ia32_binary_right); const arch_register_t *op1_reg = x87_get_irn_register(op1); const arch_register_t *op2_reg = x87_get_irn_register(op2); - const arch_register_t *out = x87_get_irn_register(n); + const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res); int reg_index_1 = arch_register_get_index(op1_reg); int reg_index_2 = arch_register_get_index(op2_reg); vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out)); @@ -1149,14 +1145,14 @@ static int sim_unop(x87_state *state, ir_node *n, ir_op *op) * * @return NO_NODE_ADDED */ -static int sim_load(x87_state *state, ir_node *n, ir_op *op) +static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos) { - const arch_register_t *out = x87_get_irn_register(n); + const arch_register_t *out = x87_irn_get_register(n, res_pos); ia32_x87_attr_t *attr; DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out))); x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op)); - assert(out == x87_get_irn_register(n)); + assert(out == x87_irn_get_register(n, res_pos)); attr = get_ia32_x87_attr(n); attr->x87[2] = out = &ia32_st_regs[0]; DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out))); @@ -1238,13 +1234,14 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) if (live_after_node) { /* - Problem: fst doesn't support mode_E (spills), only fstp does + Problem: fst doesn't support 96bit modes (spills), only fstp does + fist doesn't support 64bit mode, only fistp Solution: - stack not full: push value and fstp - stack full: fstp value and load again Note that we cannot test on mode_E, because floats might be 96bit ... */ - if (get_mode_size_bits(mode) > 64 || mode == mode_Ls) { + if (get_mode_size_bits(mode) > 64 || (mode_is_int(mode) && get_mode_size_bits(mode) > 32)) { if (depth < N_x87_REGS) { /* ok, we have a free register: push + fstp */ x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val); @@ -1259,8 +1256,7 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) x87_patch_insn(n, op_p); block = get_nodes_block(n); - irg = get_irn_irg(n); - vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg), get_ia32_ls_mode(n)); + vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), new_NoMem(), get_ia32_ls_mode(n)); /* copy all attributes */ set_ia32_frame_ent(vfld, get_ia32_frame_ent(n)); @@ -1271,6 +1267,7 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) set_ia32_am_sc(vfld, get_ia32_am_sc(n)); set_ia32_ls_mode(vfld, get_ia32_ls_mode(n)); + irg = get_irn_irg(n); rproj = new_r_Proj(irg, block, vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res); mproj = new_r_Proj(irg, block, vfld, mode_M, pn_ia32_vfld_M); mem = get_irn_Proj_for_mode(n, mode_M); @@ -1297,7 +1294,7 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) if (op2_idx != 0) x87_create_fxch(state, n, op2_idx); - /* mode != mode_E -> use normal fst */ + /* mode size 64 or smaller -> use normal fst */ x87_patch_insn(n, op); } } else { @@ -1325,13 +1322,11 @@ static int sim_##op(x87_state *state, ir_node *n) { \ #define GEN_BINOP(op) _GEN_BINOP(op, op) #define GEN_BINOPR(op) _GEN_BINOP(op, op##r) -#define GEN_LOAD2(op, nop) \ -static int sim_##op(x87_state *state, ir_node *n) { \ - return sim_load(state, n, op_ia32_##nop); \ +#define GEN_LOAD(op) \ +static int sim_##op(x87_state *state, ir_node *n) { \ + return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \ } -#define GEN_LOAD(op) GEN_LOAD2(op, op) - #define GEN_UNOP(op) \ static int sim_##op(x87_state *state, ir_node *n) { \ return sim_unop(state, n, op_ia32_##op); \ @@ -1361,16 +1356,17 @@ GEN_STORE(fst) GEN_STORE(fist) /** -* Simulate a virtual fisttp. -* -* @param state the x87 state -* @param n the node that should be simulated (and patched) -*/ + * Simulate a virtual fisttp. + * + * @param state the x87 state + * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED + */ static int sim_fisttp(x87_state *state, ir_node *n) { ir_node *val = get_irn_n(n, n_ia32_vfst_val); const arch_register_t *op2 = x87_get_irn_register(val); - int insn = NO_NODE_ADDED; ia32_x87_attr_t *attr; int op2_reg_idx, op2_idx, depth; @@ -1409,9 +1405,17 @@ static int sim_fisttp(x87_state *state, ir_node *n) attr->x87[1] = op2 = &ia32_st_regs[0]; DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2))); - return insn; + return NO_NODE_ADDED; } /* sim_fisttp */ +/** + * Simulate a virtual FtstFnstsw. + * + * @param state the x87 state + * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED + */ static int sim_FtstFnstsw(x87_state *state, ir_node *n) { x87_simulator *sim = state->sim; @@ -1441,17 +1445,19 @@ static int sim_FtstFnstsw(x87_state *state, ir_node *n) attr->x87[1] = NULL; attr->x87[2] = NULL; - if (!is_vfp_live(reg_index_1, live)) { + if (!is_vfp_live(reg_index_1, live)) x87_create_fpop(state, sched_next(n), 1); - return NODE_ADDED; - } return NO_NODE_ADDED; -} +} /* sim_FtstFnstsw */ /** + * Simulate a Fucom + * * @param state the x87 state * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED */ static int sim_Fucom(x87_state *state, ir_node *n) { @@ -1470,7 +1476,6 @@ static int sim_Fucom(x87_state *state, ir_node *n) int permuted = attr->attr.data.ins_permuted; int xchg = 0; int pops = 0; - int node_added = NO_NODE_ADDED; DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n, arch_register_get_name(op1), arch_register_get_name(op2))); @@ -1648,7 +1653,6 @@ static int sim_Fucom(x87_state *state, ir_node *n) dst = op_ia32_Fucompi; x87_pop(state); x87_create_fpop(state, sched_next(n), 1); - node_added = NODE_ADDED; break; default: panic("invalid popcount in sim_Fucom"); } @@ -1680,9 +1684,17 @@ static int sim_Fucom(x87_state *state, ir_node *n) arch_register_get_name(op1))); } - return node_added; -} + return NO_NODE_ADDED; +} /* sim_Fucom */ +/** + * Simulate a Keep. + * + * @param state the x87 state + * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED + */ static int sim_Keep(x87_state *state, ir_node *node) { const ir_node *op; @@ -1691,7 +1703,6 @@ static int sim_Keep(x87_state *state, ir_node *node) int op_stack_idx; unsigned live; int i, arity; - int node_added = NO_NODE_ADDED; DB((dbg, LEVEL_1, ">>> %+F\n", node)); @@ -1706,35 +1717,33 @@ static int sim_Keep(x87_state *state, ir_node *node) live = vfp_live_args_after(state->sim, node, 0); op_stack_idx = x87_on_stack(state, reg_id); - if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) { + if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) x87_create_fpop(state, sched_next(node), 1); - node_added = NODE_ADDED; - } } DB((dbg, LEVEL_1, "Stack after: ")); DEBUG_ONLY(x87_dump_stack(state)); - return node_added; -} + return NO_NODE_ADDED; +} /* sim_Keep */ +/** + * Keep the given node alive by adding a be_Keep. + * + * @param node the node to kept alive + */ static void keep_float_node_alive(ir_node *node) { - ir_graph *irg; - ir_node *block; - ir_node *in[1]; + ir_graph *irg = get_irn_irg(node); + ir_node *block = get_nodes_block(node); + const arch_register_class_t *cls = arch_get_irn_reg_class_out(node); ir_node *keep; - const arch_register_class_t *cls; - irg = get_irn_irg(node); - block = get_nodes_block(node); - cls = arch_get_irn_reg_class(node, -1); - in[0] = node; - keep = be_new_Keep(cls, irg, block, 1, in); + keep = be_new_Keep(cls, irg, block, 1, &node); assert(sched_is_scheduled(node)); sched_add_after(node, keep); -} +} /* keep_float_node_alive */ /** * Create a copy of a node. Recreate the node if it's a constant. @@ -1746,12 +1755,11 @@ static void keep_float_node_alive(ir_node *node) */ static ir_node *create_Copy(x87_state *state, ir_node *n) { - ir_graph *irg = get_irn_irg(n); dbg_info *n_dbg = get_irn_dbg_info(n); ir_mode *mode = get_irn_mode(n); ir_node *block = get_nodes_block(n); ir_node *pred = get_irn_n(n, 0); - ir_node *(*cnstr)(dbg_info *, ir_graph *, ir_node *, ir_mode *) = NULL; + ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL; ir_node *res; const arch_register_t *out; const arch_register_t *op1; @@ -1761,25 +1769,25 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) switch (get_ia32_irn_opcode(pred)) { case iro_ia32_Unknown_VFP: case iro_ia32_fldz: - cnstr = new_rd_ia32_fldz; + cnstr = new_bd_ia32_fldz; break; case iro_ia32_fld1: - cnstr = new_rd_ia32_fld1; + cnstr = new_bd_ia32_fld1; break; case iro_ia32_fldpi: - cnstr = new_rd_ia32_fldpi; + cnstr = new_bd_ia32_fldpi; break; case iro_ia32_fldl2e: - cnstr = new_rd_ia32_fldl2e; + cnstr = new_bd_ia32_fldl2e; break; case iro_ia32_fldl2t: - cnstr = new_rd_ia32_fldl2t; + cnstr = new_bd_ia32_fldl2t; break; case iro_ia32_fldlg2: - cnstr = new_rd_ia32_fldlg2; + cnstr = new_bd_ia32_fldlg2; break; case iro_ia32_fldln2: - cnstr = new_rd_ia32_fldln2; + cnstr = new_bd_ia32_fldln2; break; default: break; @@ -1790,7 +1798,7 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) if (cnstr != NULL) { /* copy a constant */ - res = (*cnstr)(n_dbg, irg, block, mode); + res = (*cnstr)(n_dbg, block, mode); x87_push(state, arch_register_get_index(out), res); @@ -1799,7 +1807,7 @@ static ir_node *create_Copy(x87_state *state, ir_node *n) } else { int op1_idx = x87_on_stack(state, arch_register_get_index(op1)); - res = new_rd_ia32_fpushCopy(n_dbg, irg, block, pred, mode); + res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode); x87_push(state, arch_register_get_index(out), res); @@ -1831,7 +1839,7 @@ static int sim_Copy(x87_state *state, ir_node *n) int op1_idx, out_idx; unsigned live; - cls = arch_get_irn_reg_class(n, -1); + cls = arch_get_irn_reg_class_out(n); if (cls->regs != ia32_vfp_regs) return 0; @@ -1932,7 +1940,9 @@ static int sim_Copy(x87_state *state, ir_node *n) } /* sim_Copy */ /** - * Returns the result proj of the call + * Returns the vf0 result Proj of a Call. + * + * @para call the Call node */ static ir_node *get_call_result_proj(ir_node *call) { @@ -1943,9 +1953,8 @@ static ir_node *get_call_result_proj(ir_node *call) ir_node *proj = get_edge_src_irn(edge); long pn = get_Proj_proj(proj); - if (pn == pn_ia32_Call_vf0) { + if (pn == pn_ia32_Call_vf0) return proj; - } } return NULL; @@ -1955,7 +1964,7 @@ static ir_node *get_call_result_proj(ir_node *call) * Simulate a ia32_Call. * * @param state the x87 state - * @param n the node that should be simulated + * @param n the node that should be simulated (and patched) * * @return NO_NODE_ADDED */ @@ -2009,7 +2018,7 @@ end_call: */ static int sim_Spill(x87_state *state, ir_node *n) { - assert(0 && "Spill not lowered"); + panic("Spill not lowered before x87 simulator run"); return sim_fst(state, n); } /* sim_Spill */ @@ -2023,7 +2032,7 @@ static int sim_Spill(x87_state *state, ir_node *n) */ static int sim_Reload(x87_state *state, ir_node *n) { - assert(0 && "Reload not lowered"); + panic("Reload not lowered before x87 simulator run"); return sim_fld(state, n); } /* sim_Reload */ @@ -2112,9 +2121,17 @@ static int sim_Perm(x87_state *state, ir_node *irn) return NO_NODE_ADDED; } /* sim_Perm */ +/** + * Simulate the Barrier to generate Unknowns. + * We must push something on the stack for its value. + * + * @param state the x87 state + * @param irn the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED + */ static int sim_Barrier(x87_state *state, ir_node *node) { - //const arch_env_t *arch_env = state->sim->arch_env; int i, arity; /* materialize unknown if needed */ @@ -2134,7 +2151,7 @@ static int sim_Barrier(x87_state *state, ir_node *node) /* create a zero */ block = get_nodes_block(node); - zero = new_rd_ia32_fldz(NULL, current_ir_graph, block, mode_E); + zero = new_bd_ia32_fldz(NULL, block, ia32_reg_classes[CLASS_ia32_st].mode); x87_push(state, arch_register_get_index(reg), zero); attr = get_ia32_x87_attr(zero); @@ -2146,8 +2163,7 @@ static int sim_Barrier(x87_state *state, ir_node *node) } return NO_NODE_ADDED; -} - +} /* sim_Barrier */ /** * Kill any dead registers at block start by popping them from the stack. @@ -2189,10 +2205,10 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) { if (ia32_cg_config.use_femms) { /* use FEMMS on AMD processors to clear all */ - keep = new_rd_ia32_femms(NULL, get_irn_irg(block), block); + keep = new_bd_ia32_femms(NULL, block); } else { /* use EMMS to clear all */ - keep = new_rd_ia32_emms(NULL, get_irn_irg(block), block); + keep = new_bd_ia32_emms(NULL, block); } sched_add_before(first_insn, keep); keep_alive(keep); @@ -2237,30 +2253,32 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * } /* x87_kill_deads */ /** - * If we have PhiEs with unknown operands then we have to make sure that some - * value is actually put onto the stack. + * If we have PhiEs with unknown operands in a block + * we have to make sure that some value is actually put onto the stack. + * + * @param state the x87 state + * @param block the block that should be checked + * @param pred_block check inputs from this predecessor block + * @param pos index of pred_block */ static void fix_unknown_phis(x87_state *state, ir_node *block, ir_node *pred_block, int pos) { - ir_node *node, *op; + ir_node *phi, *op; - sched_foreach(block, node) { + sched_foreach_Phi(block, phi) { ir_node *zero; const arch_register_t *reg; ia32_x87_attr_t *attr; - if (!is_Phi(node)) - break; - - op = get_Phi_pred(node, pos); + op = get_Phi_pred(phi, pos); if (!is_ia32_Unknown_VFP(op)) continue; - reg = arch_get_irn_register(node); + reg = arch_get_irn_register(phi); /* create a zero at end of pred block */ - zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E); + zero = new_bd_ia32_fldz(NULL, pred_block, ia32_reg_classes[CLASS_ia32_st].mode); x87_push(state, arch_register_get_index(reg), zero); attr = get_ia32_x87_attr(zero); @@ -2269,9 +2287,9 @@ static void fix_unknown_phis(x87_state *state, ir_node *block, assert(is_ia32_fldz(zero)); sched_add_before(sched_last(pred_block), zero); - set_Phi_pred(node, pos, zero); + set_Phi_pred(phi, pos, zero); } -} +} /* fix_unknown_phis */ /** * Run a simulation and fix all virtual instructions for a block. @@ -2307,23 +2325,26 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) sim_func func; ir_op *op = get_irn_op(n); + /* + * get the next node to be simulated here. + * n might be completely removed from the schedule- + */ next = sched_next(n); - if (op->ops.generic == NULL) - continue; - - func = (sim_func)op->ops.generic; + if (op->ops.generic != NULL) { + func = (sim_func)op->ops.generic; - /* simulate it */ - node_inserted = (*func)(state, n); + /* simulate it */ + node_inserted = (*func)(state, n); - /* - sim_func might have added an additional node after n, - so update next node - beware: n must not be changed by sim_func - (i.e. removed from schedule) in this case - */ - if (node_inserted != NO_NODE_ADDED) - next = sched_next(n); + /* + * sim_func might have added an additional node after n, + * so update next node + * beware: n must not be changed by sim_func + * (i.e. removed from schedule) in this case + */ + if (node_inserted != NO_NODE_ADDED) + next = sched_next(n); + } } start_block = get_irg_start_block(get_irn_irg(block)); @@ -2362,25 +2383,28 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) bl_state->end = state; } /* x87_simulate_block */ +/** + * Register a simulator function. + * + * @param op the opcode to simulate + * @param func the simulator function for the opcode + */ static void register_sim(ir_op *op, sim_func func) { assert(op->ops.generic == NULL); op->ops.generic = (op_func) func; -} +} /* register_sim */ /** * Create a new x87 simulator. * * @param sim a simulator handle, will be initialized * @param irg the current graph - * @param arch_env the architecture environment */ -static void x87_init_simulator(x87_simulator *sim, ir_graph *irg, - const arch_env_t *arch_env) +static void x87_init_simulator(x87_simulator *sim, ir_graph *irg) { obstack_init(&sim->obst); sim->blk_states = pmap_create(); - sim->arch_env = arch_env; sim->n_idx = get_irg_last_idx(irg); sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx); @@ -2439,23 +2463,22 @@ static void update_liveness_walker(ir_node *block, void *data) update_liveness(sim, block); } /* update_liveness_walker */ -/** +/* * Run a simulation and fix all virtual instructions for a graph. - * - * @param env the architecture environment - * @param irg the current graph - * - * Needs a block-schedule. + * Replaces all virtual floating point instructions and registers + * by real ones. */ -void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) +void x87_simulate_graph(be_irg_t *birg) { + /* TODO improve code quality (less executed fxch) by using execfreqs */ + ir_node *block, *start_block; blk_state *bl_state; x87_simulator sim; ir_graph *irg = be_get_birg_irg(birg); /* create the simulator */ - x87_init_simulator(&sim, irg, arch_env); + x87_init_simulator(&sim, irg); start_block = get_irg_start_block(irg); bl_state = x87_get_bl_state(&sim, start_block); @@ -2469,7 +2492,6 @@ void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) be_assure_liveness(birg); sim.lv = be_get_birg_liveness(birg); -// sim.lv = be_liveness(be_get_birg_irg(birg)); be_liveness_assure_sets(sim.lv); /* Calculate the liveness for all nodes. We must precalculate this info, @@ -2491,6 +2513,7 @@ void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) x87_destroy_simulator(&sim); } /* x87_simulate_graph */ +/* Initializes the x87 simulator. */ void ia32_init_x87(void) { FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");