X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_x87.c;h=3977b94ffd621f0aff3dd49c067ceacd90299021;hb=41dc42afc8d00e0f364711ed0c919e4e29cb20e4;hp=456a62111202d4f6e456d3a799295bdab26a0c19;hpb=eb3692350976be4efea32417a503d91f1a761ba9;p=libfirm diff --git a/ir/be/ia32/ia32_x87.c b/ir/be/ia32/ia32_x87.c index 456a62111..3977b94ff 100644 --- a/ir/be/ia32/ia32_x87.c +++ b/ir/be/ia32/ia32_x87.c @@ -1,15 +1,30 @@ -/** - * This file implements the x87 support and virtual to stack - * register translation for the ia32 backend. +/* + * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. * - * @author: Michael Beck + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. * - * $Id$ + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. */ -#ifdef HAVE_CONFIG_H +/** + * @file + * @brief This file implements the x87 support and virtual to stack + * register translation for the ia32 backend. + * @author Michael Beck + * @version $Id$ + */ #include "config.h" -#endif /* HAVE_CONFIG_H */ #include @@ -19,39 +34,32 @@ #include "iredges_t.h" #include "irgmod.h" #include "ircons.h" +#include "irgwalk.h" #include "obst.h" #include "pmap.h" +#include "array_t.h" #include "pdeq.h" #include "irprintf.h" #include "debug.h" +#include "error.h" #include "../belive_t.h" -#include "../besched_t.h" -#include "../benode_t.h" +#include "../besched.h" +#include "../benode.h" +#include "bearch_ia32_t.h" #include "ia32_new_nodes.h" #include "gen_ia32_new_nodes.h" #include "gen_ia32_regalloc_if.h" #include "ia32_x87.h" +#include "ia32_architecture.h" -#define N_x87_REGS 8 - -/* first and second binop index */ -#define BINOP_IDX_1 2 -#define BINOP_IDX_2 3 - -/* the unop index */ -#define UNOP_IDX 0 - -/* the store val index */ -#define STORE_VAL_IDX 2 - -#define MASK_TOS(x) ((x) & (N_x87_REGS - 1)) +#define MASK_TOS(x) ((x) & (N_ia32_st_REGS - 1)) /** the debug handle */ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) /* Forward declaration. */ -typedef struct _x87_simulator x87_simulator; +typedef struct x87_simulator x87_simulator; /** * An exchange template. @@ -60,7 +68,7 @@ typedef struct _x87_simulator x87_simulator; * their opcodes! * Further, x87 supports inverse instructions, so we can handle them. */ -typedef struct _exchange_tmpl { +typedef struct exchange_tmpl { ir_op *normal_op; /**< the normal one */ ir_op *reverse_op; /**< the reverse one if exists */ ir_op *normal_pop_op; /**< the normal one with tos pop */ @@ -70,7 +78,7 @@ typedef struct _exchange_tmpl { /** * An entry on the simulated x87 stack. */ -typedef struct _st_entry { +typedef struct st_entry { int reg_idx; /**< the virtual register index of this stack value */ ir_node *node; /**< the node that produced this value */ } st_entry; @@ -78,29 +86,47 @@ typedef struct _st_entry { /** * The x87 state. */ -typedef struct _x87_state { - st_entry st[N_x87_REGS]; /**< the register stack */ - int depth; /**< the current stack depth */ - int tos; /**< position of the tos */ - x87_simulator *sim; /**< The simulator. */ +typedef struct x87_state { + st_entry st[N_ia32_st_REGS]; /**< the register stack */ + int depth; /**< the current stack depth */ + int tos; /**< position of the tos */ + x87_simulator *sim; /**< The simulator. */ } x87_state; /** An empty state, used for blocks without fp instructions. */ -static x87_state _empty = { { {0, NULL}, }, 0, 0 }; +static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL }; static x87_state *empty = (x87_state *)&_empty; -/** The type of an instruction simulator function. */ +/** + * Return values of the instruction simulator functions. + */ +enum { + NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */ + NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator + in the schedule AFTER the current node. */ +}; + +/** + * The type of an instruction simulator function. + * + * @param state the x87 state + * @param n the node to be simulated + * + * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be + * simulated further + * NO_NODE_ADDED otherwise + */ typedef int (*sim_func)(x87_state *state, ir_node *n); /** * A block state: Every block has a x87 state at the beginning and at the end. */ -typedef struct _blk_state { +typedef struct blk_state { x87_state *begin; /**< state at the begin or NULL if not assigned */ x87_state *end; /**< state at the end or NULL if not assigned */ } blk_state; -#define PTR_TO_BLKSTATE(p) ((blk_state *)(p)) +#define PTR_TO_BLKSTATE(p) ((blk_state *)(p)) /** liveness bitset for vfp registers. */ typedef unsigned char vfp_liveness; @@ -108,14 +134,14 @@ typedef unsigned char vfp_liveness; /** * The x87 simulator. */ -struct _x87_simulator { - struct obstack obst; /**< An obstack for fast allocating. */ - pmap *blk_states; /**< Map blocks to states. */ - const arch_env_t *env; /**< The architecture environment. */ - be_lv_t *lv; /**< intrablock liveness. */ - vfp_liveness *live; /**< Liveness information. */ - unsigned n_idx; /**< The cached get_irg_last_idx() result. */ - waitq *worklist; /**< list of blocks to process. */ +struct x87_simulator { + struct obstack obst; /**< An obstack for fast allocating. */ + pmap *blk_states; /**< Map blocks to states. */ + be_lv_t *lv; /**< intrablock liveness. */ + vfp_liveness *live; /**< Liveness information. */ + unsigned n_idx; /**< The cached get_irg_last_idx() result. */ + waitq *worklist; /**< Worklist of blocks that must be processed. */ + ia32_isa_t *isa; /**< the ISA object */ }; /** @@ -125,20 +151,10 @@ struct _x87_simulator { * * @return the x87 stack depth */ -static int x87_get_depth(const x87_state *state) { +static int x87_get_depth(const x87_state *state) +{ return state->depth; -} - -/** - * Check if the state is empty. - * - * @param state the x87 state - * - * returns non-zero if the x87 stack is empty - */ -static int x87_state_is_empty(const x87_state *state) { - return state->depth == 0; -} +} /* x87_get_depth */ /** * Return the virtual register index at st(pos). @@ -148,11 +164,13 @@ static int x87_state_is_empty(const x87_state *state) { * * @return the vfp register index that produced the value at st(pos) */ -static int x87_get_st_reg(const x87_state *state, int pos) { +static int x87_get_st_reg(const x87_state *state, int pos) +{ assert(pos < state->depth); return state->st[MASK_TOS(state->tos + pos)].reg_idx; -} +} /* x87_get_st_reg */ +#ifdef DEBUG_libfirm /** * Return the node at st(pos). * @@ -161,22 +179,24 @@ static int x87_get_st_reg(const x87_state *state, int pos) { * * @return the IR node that produced the value at st(pos) */ -static ir_node *x87_get_st_node(const x87_state *state, int pos) { +static ir_node *x87_get_st_node(const x87_state *state, int pos) +{ assert(pos < state->depth); return state->st[MASK_TOS(state->tos + pos)].node; } /* x87_get_st_node */ -#ifdef DEBUG_libfirm /** * Dump the stack for debugging. * * @param state the x87 state */ -static void x87_dump_stack(const x87_state *state) { +static void x87_dump_stack(const x87_state *state) +{ int i; for (i = state->depth - 1; i >= 0; --i) { - DB((dbg, LEVEL_2, "vf%d ", x87_get_st_reg(state, i))); + DB((dbg, LEVEL_2, "vf%d(%+F) ", x87_get_st_reg(state, i), + x87_get_st_node(state, i))); } DB((dbg, LEVEL_2, "<-- TOS\n")); } /* x87_dump_stack */ @@ -190,7 +210,8 @@ static void x87_dump_stack(const x87_state *state) { * @param node the IR node that produces the value of the vfp register * @param pos the stack position where the new value should be entered */ -static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) { +static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) +{ assert(0 < state->depth); state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx; state->st[MASK_TOS(state->tos + pos)].node = node; @@ -206,29 +227,19 @@ static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) { * @param reg_idx the vfp register index that should be set * @param node the IR node that produces the value of the vfp register */ -static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node) { +static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node) +{ x87_set_st(state, reg_idx, node, 0); } /* x87_set_tos */ -#if 0 -/** - * Flush the x87 stack. - * - * @param state the x87 state - */ -static void x87_flush(x87_state *state) { - state->depth = 0; - state->tos = 0; -} /* x87_flush */ -#endif - /** * Swap st(0) with st(pos). * * @param state the x87 state * @param pos the stack position to change the tos with */ -static void x87_fxch(x87_state *state, int pos) { +static void x87_fxch(x87_state *state, int pos) +{ st_entry entry; assert(pos < state->depth); @@ -236,7 +247,8 @@ static void x87_fxch(x87_state *state, int pos) { state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)]; state->st[MASK_TOS(state->tos)] = entry; - DB((dbg, LEVEL_2, "After FXCH: ")); DEBUG_ONLY(x87_dump_stack(state)); + DB((dbg, LEVEL_2, "After FXCH: ")); + DEBUG_ONLY(x87_dump_stack(state)); } /* x87_fxch */ /** @@ -248,7 +260,8 @@ static void x87_fxch(x87_state *state, int pos) { * @return the stack position where the register is stacked * or -1 if the virtual register was not found */ -static int x87_on_stack(const x87_state *state, int reg_idx) { +static int x87_on_stack(const x87_state *state, int reg_idx) +{ int i, tos = state->tos; for (i = 0; i < state->depth; ++i) @@ -264,8 +277,9 @@ static int x87_on_stack(const x87_state *state, int reg_idx) { * @param reg_idx the register vfp index * @param node the node that produces the value of the vfp register */ -static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) { - assert(state->depth < N_x87_REGS && "stack overrun"); +static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) +{ + assert(state->depth < N_ia32_st_REGS && "stack overrun"); ++state->depth; state->tos = MASK_TOS(state->tos - 1); @@ -276,14 +290,15 @@ static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) { } /* x87_push_dbl */ /** - * Push a virtual Register onto the stack, double pushes are NOT allowed.. + * Push a virtual Register onto the stack, double pushes are NOT allowed. * * @param state the x87 state * @param reg_idx the register vfp index * @param node the node that produces the value of the vfp register * @param dbl_push if != 0 double pushes are allowed */ -static void x87_push(x87_state *state, int reg_idx, ir_node *node) { +static void x87_push(x87_state *state, int reg_idx, ir_node *node) +{ assert(x87_on_stack(state, reg_idx) == -1 && "double push"); x87_push_dbl(state, reg_idx, node); @@ -291,8 +306,11 @@ static void x87_push(x87_state *state, int reg_idx, ir_node *node) { /** * Pop a virtual Register from the stack. + * + * @param state the x87 state */ -static void x87_pop(x87_state *state) { +static void x87_pop(x87_state *state) +{ assert(state->depth > 0 && "stack underrun"); --state->depth; @@ -301,6 +319,17 @@ static void x87_pop(x87_state *state) { DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state)); } /* x87_pop */ +/** + * Empty the fpu stack + * + * @param state the x87 state + */ +static void x87_emms(x87_state *state) +{ + state->depth = 0; + state->tos = 0; +} + /** * Returns the block state of a block. * @@ -309,11 +338,12 @@ static void x87_pop(x87_state *state) { * * @return the block state */ -static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block) { +static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block) +{ pmap_entry *entry = pmap_find(sim->blk_states, block); if (! entry) { - blk_state *bl_state = obstack_alloc(&sim->obst, sizeof(*bl_state)); + blk_state *bl_state = OALLOC(&sim->obst, blk_state); bl_state->begin = NULL; bl_state->end = NULL; @@ -331,29 +361,14 @@ static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block) { * * @return a new x87 state */ -static x87_state *x87_alloc_state(x87_simulator *sim) { - x87_state *res = obstack_alloc(&sim->obst, sizeof(*res)); +static x87_state *x87_alloc_state(x87_simulator *sim) +{ + x87_state *res = OALLOC(&sim->obst, x87_state); res->sim = sim; return res; } /* x87_alloc_state */ -#if 0 -/** - * Create a new empty x87 state. - * - * @param sim the x87 simulator handle - * - * @return a new empty x87 state - */ -static x87_state *x87_alloc_empty_state(x87_simulator *sim) { - x87_state *res = x87_alloc_state(sim); - - x87_flush(res); - return res; -} /* x87_alloc_empty_state */ -#endif - /** * Clone a x87 state. * @@ -362,21 +377,23 @@ static x87_state *x87_alloc_empty_state(x87_simulator *sim) { * * @return a cloned copy of the src state */ -static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) { +static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) +{ x87_state *res = x87_alloc_state(sim); - memcpy(res, src, sizeof(*res)); + *res = *src; return res; } /* x87_clone_state */ /** * Patch a virtual instruction into a x87 one and return - * the value node. + * the node representing the result value. * * @param n the IR node to patch * @param op the x87 opcode to patch in */ -static ir_node *x87_patch_insn(ir_node *n, ir_op *op) { +static ir_node *x87_patch_insn(ir_node *n, ir_op *op) +{ ir_mode *mode = get_irn_mode(n); ir_node *res = n; @@ -392,13 +409,12 @@ static ir_node *x87_patch_insn(ir_node *n, ir_op *op) { mode = get_irn_mode(proj); if (mode_is_float(mode)) { res = proj; - set_irn_mode(proj, mode_E); + set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode); } } } - } - else if (mode_is_float(mode)) - set_irn_mode(n, mode_E); + } else if (mode_is_float(mode)) + set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode); return res; } /* x87_patch_insn */ @@ -409,7 +425,8 @@ static ir_node *x87_patch_insn(ir_node *n, ir_op *op) { * @param m the desired mode of the Proj * @return The first Proj of mode @p m found or NULL. */ -static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) { +static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) +{ const ir_edge_t *edge; assert(get_irn_mode(n) == mode_T && "Need mode_T node"); @@ -426,12 +443,26 @@ static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) { /** * Wrap the arch_* function here so we can check for errors. */ -static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, const ir_node *irn) { - const arch_register_t *res; +static inline const arch_register_t *x87_get_irn_register(const ir_node *irn) +{ + const arch_register_t *res = arch_get_irn_register(irn); + + assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]); + return res; +} /* x87_get_irn_register */ - res = arch_get_irn_register(sim->env, irn); - assert(res->reg_class->regs == ia32_vfp_regs); +static inline const arch_register_t *x87_irn_get_register(const ir_node *irn, + int pos) +{ + const arch_register_t *res = arch_get_irn_register_out(irn, pos); + + assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]); return res; +} /* x87_irn_get_register */ + +static inline const arch_register_t *get_st_reg(int index) +{ + return &ia32_registers[REG_ST0 + index]; } /* -------------- x87 perm --------------- */ @@ -451,12 +482,12 @@ static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, co static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) { ir_node *fxch; - ia32_attr_t *attr; + ia32_x87_attr_t *attr; - fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block, mode_E); - attr = get_ia32_attr(fxch); - attr->x87[0] = &ia32_st_regs[pos]; - attr->x87[2] = &ia32_st_regs[0]; + fxch = new_bd_ia32_fxch(NULL, block); + attr = get_ia32_x87_attr(fxch); + attr->x87[0] = get_st_reg(pos); + attr->x87[2] = get_st_reg(0); keep_alive(fxch); @@ -481,11 +512,16 @@ static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) * * @return state */ -static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, x87_state *state, ir_node *dst_block, const x87_state *dst_state) { +static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, + x87_state *state, ir_node *dst_block, + const x87_state *dst_state) +{ int i, n_cycles, k, ri; unsigned cycles[4], all_mask; char cycle_idx[4][8]; ir_node *fxch, *before, *after; + (void) sim; + (void) dst_block; assert(state->depth == dst_state->depth); @@ -606,22 +642,21 @@ static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, x87_state *sta * @param state the x87 state * @param n the node after the fxch * @param pos exchange st(pos) with st(0) - * @param op_idx if >= 0, replace input op_idx of n with the fxch result * * @return the fxch */ -static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos, int op_idx) { - ir_node *fxch; - ia32_attr_t *attr; - ir_graph *irg = get_irn_irg(n); - ir_node *block = get_nodes_block(n); +static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos) +{ + ir_node *fxch; + ia32_x87_attr_t *attr; + ir_node *block = get_nodes_block(n); x87_fxch(state, pos); - fxch = new_rd_ia32_fxch(NULL, irg, block, mode_E); - attr = get_ia32_attr(fxch); - attr->x87[0] = &ia32_st_regs[pos]; - attr->x87[2] = &ia32_st_regs[0]; + fxch = new_bd_ia32_fxch(NULL, block); + attr = get_ia32_x87_attr(fxch); + attr->x87[0] = get_st_reg(pos); + attr->x87[2] = get_st_reg(0); keep_alive(fxch); @@ -638,17 +673,18 @@ static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos, int op_id * @param pos push st(pos) on stack * @param op_idx replace input op_idx of n with the fpush result */ -static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) { +static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) +{ ir_node *fpush, *pred = get_irn_n(n, op_idx); - ia32_attr_t *attr; - const arch_register_t *out = x87_get_irn_register(state->sim, pred); + ia32_x87_attr_t *attr; + const arch_register_t *out = x87_get_irn_register(pred); x87_push_dbl(state, arch_register_get_index(out), pred); - fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n), mode_E); - attr = get_ia32_attr(fpush); - attr->x87[0] = &ia32_st_regs[pos]; - attr->x87[2] = &ia32_st_regs[0]; + fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n)); + attr = get_ia32_x87_attr(fpush); + attr->x87[0] = get_st_reg(pos); + attr->x87[2] = get_st_reg(0); keep_alive(fpush); sched_add_before(n, fpush); @@ -662,57 +698,33 @@ static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) * @param state the x87 state * @param n the node after the fpop * @param num pop 1 or 2 values - * @param pred node to use as predecessor of the fpop * * @return the fpop node */ -static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num, ir_node *pred) { - ir_node *fpop = pred; - ia32_attr_t *attr; - - while (num > 0) { - keep_alive(pred); +static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num) +{ + ir_node *fpop = NULL; + ia32_x87_attr_t *attr; + assert(num > 0); + do { x87_pop(state); - fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n), mode_E); - attr = get_ia32_attr(fpop); - attr->x87[0] = &ia32_st_regs[0]; - attr->x87[1] = &ia32_st_regs[0]; - attr->x87[2] = &ia32_st_regs[0]; - + if (ia32_cg_config.use_ffreep) + fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n)); + else + fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n)); + attr = get_ia32_x87_attr(fpop); + attr->x87[0] = get_st_reg(0); + attr->x87[1] = get_st_reg(0); + attr->x87[2] = get_st_reg(0); + + keep_alive(fpop); sched_add_before(n, fpop); DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name)); - - pred = fpop; - --num; - } + } while (--num > 0); return fpop; } /* x87_create_fpop */ -/** - * Creates an fldz before node n - * - * @param state the x87 state - * @param n the node after the fldz - * - * @return the fldz node - */ -static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx) { - ir_graph *irg = get_irn_irg(n); - ir_node *block = get_nodes_block(n); - ir_node *fldz; - - fldz = new_rd_ia32_fldz(NULL, irg, block, mode_E); - - sched_add_before(n, fldz); - DB((dbg, LEVEL_1, "<<< %s\n", get_irn_opname(fldz))); - keep_alive(fldz); - - x87_push(state, regidx, fldz); - - return fldz; -} - /* --------------------------------- liveness ------------------------------------------ */ /** @@ -720,29 +732,39 @@ static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx) { * Updates a live set over a single step from a given node to its predecessor. * Everything defined at the node is removed from the set, the uses of the node get inserted. * - * @param sim The simulator handle. * @param irn The node at which liveness should be computed. * @param live The bitset of registers live before @p irn. This set gets modified by updating it to * the registers live after irn. * * @return The live bitset. */ -static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_liveness live) +static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live) { int i, n; const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp]; - const arch_env_t *arch_env = sim->env; - if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) { - const arch_register_t *reg = x87_get_irn_register(sim, irn); - live &= ~(1 << arch_register_get_index(reg)); + if (get_irn_mode(irn) == mode_T) { + const ir_edge_t *edge; + + foreach_out_edge(irn, edge) { + ir_node *proj = get_edge_src_irn(edge); + + if (arch_irn_consider_in_reg_alloc(cls, proj)) { + const arch_register_t *reg = x87_get_irn_register(proj); + live &= ~(1 << arch_register_get_index(reg)); + } + } + } else if (arch_irn_consider_in_reg_alloc(cls, irn)) { + const arch_register_t *reg = x87_get_irn_register(irn); + live &= ~(1 << arch_register_get_index(reg)); } for (i = 0, n = get_irn_arity(irn); i < n; ++i) { ir_node *op = get_irn_n(irn, i); - if (mode_is_float(get_irn_mode(op)) && arch_irn_consider_in_reg_alloc(arch_env, cls, op)) { - const arch_register_t *reg = x87_get_irn_register(sim, op); + if (mode_is_float(get_irn_mode(op)) && + arch_irn_consider_in_reg_alloc(cls, op)) { + const arch_register_t *reg = x87_get_irn_register(op); live |= 1 << arch_register_get_index(reg); } } @@ -763,16 +785,15 @@ static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node int i; vfp_liveness live = 0; const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp]; - const arch_env_t *arch_env = sim->env; const be_lv_t *lv = sim->lv; be_lv_foreach(lv, block, be_lv_state_end, i) { const arch_register_t *reg; const ir_node *node = be_lv_get_irn(lv, block, i); - if (!arch_irn_consider_in_reg_alloc(arch_env, cls, node)) + if (!arch_irn_consider_in_reg_alloc(cls, node)) continue; - reg = x87_get_irn_register(sim, node); + reg = x87_get_irn_register(node); live |= 1 << arch_register_get_index(reg); } @@ -780,7 +801,7 @@ static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node } /* vfp_liveness_end_of_block */ /** get the register mask from an arch_register */ -#define REGMASK(reg) (1 << (arch_register_get_index(reg))) +#define REGMASK(reg) (1 << (arch_register_get_index(reg))) /** * Return a bitset of argument registers which are live at the end of a node. @@ -806,7 +827,8 @@ static unsigned vfp_live_args_after(x87_simulator *sim, const ir_node *pos, unsi * @param lv the liveness handle * @param block the block */ -static void update_liveness(x87_simulator *sim, ir_node *block) { +static void update_liveness(x87_simulator *sim, ir_node *block) +{ vfp_liveness live = vfp_liveness_end_of_block(sim, block); unsigned idx; ir_node *irn; @@ -820,7 +842,7 @@ static void update_liveness(x87_simulator *sim, ir_node *block) { idx = get_irn_idx(irn); sim->live[idx] = live; - live = vfp_liveness_transfer(sim, irn, live); + live = vfp_liveness_transfer(irn, live); } idx = get_irn_idx(block); sim->live[idx] = live; @@ -840,7 +862,8 @@ static void update_liveness(x87_simulator *sim, ir_node *block) { * * @param live the live bitset */ -static void vfp_dump_live(vfp_liveness live) { +static void vfp_dump_live(vfp_liveness live) +{ int i; DB((dbg, LEVEL_2, "Live after: ")); @@ -855,30 +878,37 @@ static void vfp_dump_live(vfp_liveness live) { /* --------------------------------- simulators ---------------------------------------- */ -#define XCHG(a, b) do { int t = (a); (a) = (b); (b) = t; } while (0) - /** * Simulate a virtual binop. * * @param state the x87 state * @param n the node that should be simulated (and patched) * @param tmpl the template containing the 4 possible x87 opcodes + * + * @return NO_NODE_ADDED */ -static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { - int op2_idx, op1_idx; +static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) +{ + int op2_idx = 0, op1_idx; int out_idx, do_pop = 0; - ia32_attr_t *attr; + ia32_x87_attr_t *attr; + int permuted; + ir_node *patched_insn; ir_op *dst; - x87_simulator *sim = state->sim; - const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1)); - const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2)); - const arch_register_t *out = x87_get_irn_register(sim, n); - int reg_index_1 = arch_register_get_index(op1); - int reg_index_2 = arch_register_get_index(op2); - vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out)); + x87_simulator *sim = state->sim; + ir_node *op1 = get_irn_n(n, n_ia32_binary_left); + ir_node *op2 = get_irn_n(n, n_ia32_binary_right); + const arch_register_t *op1_reg = x87_get_irn_register(op1); + const arch_register_t *op2_reg = x87_get_irn_register(op2); + const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res); + int reg_index_1 = arch_register_get_index(op1_reg); + int reg_index_2 = arch_register_get_index(op2_reg); + vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out)); + int op1_live_after; + int op2_live_after; DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n, - arch_register_get_name(op1), arch_register_get_name(op2), + arch_register_get_name(op1_reg), arch_register_get_name(op2_reg), arch_register_get_name(out))); DEBUG_ONLY(vfp_dump_live(live)); DB((dbg, LEVEL_1, "Stack before: ")); @@ -886,19 +916,26 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { op1_idx = x87_on_stack(state, reg_index_1); assert(op1_idx >= 0); + op1_live_after = is_vfp_live(reg_index_1, live); + + attr = get_ia32_x87_attr(n); + permuted = attr->attr.data.ins_permuted; + + if (reg_index_2 != REG_VFP_VFP_NOREG) { + assert(!permuted); - if (reg_index_2 != REG_VFP_NOREG) { /* second operand is a vfp register */ op2_idx = x87_on_stack(state, reg_index_2); assert(op2_idx >= 0); + op2_live_after = is_vfp_live(reg_index_2, live); - if (is_vfp_live(arch_register_get_index(op2), live)) { + if (op2_live_after) { /* Second operand is live. */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* Both operands are live: push the first one. This works even for op1 == op2. */ - x87_create_fpush(state, n, op1_idx, BINOP_IDX_2); + x87_create_fpush(state, n, op1_idx, n_ia32_binary_right); /* now do fxxx (tos=tos X op) */ op1_idx = 0; op2_idx += 1; @@ -907,7 +944,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } else { /* Second live, first operand is dead here, bring it to tos. */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); if (op2_idx == 0) op2_idx = op1_idx; op1_idx = 0; @@ -916,13 +953,12 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { out_idx = 0; dst = tmpl->normal_op; } - } - else { + } else { /* Second operand is dead. */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* First operand is live: bring second to tos. */ if (op2_idx != 0) { - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); if (op1_idx == 0) op1_idx = op2_idx; op2_idx = 0; @@ -930,8 +966,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { /* now do fxxxr (tos = op X tos) */ out_idx = 0; dst = tmpl->reverse_op; - } - else { + } else { /* Both operands are dead here, pop them from the stack. */ if (op2_idx == 0) { if (op1_idx == 0) { @@ -939,24 +974,21 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { /* here fxxx (tos = tos X tos) */ dst = tmpl->normal_op; out_idx = 0; - } - else { + } else { /* now do fxxxp (op = op X tos, pop) */ dst = tmpl->normal_pop_op; do_pop = 1; out_idx = op1_idx; } - } - else if (op1_idx == 0) { + } else if (op1_idx == 0) { assert(op1_idx != op2_idx); /* now do fxxxrp (op = tos X op, pop) */ dst = tmpl->reverse_pop_op; do_pop = 1; out_idx = op2_idx; - } - else { + } else { /* Bring the second on top. */ - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); if (op1_idx == op2_idx) { /* Both are identically and on tos now, no pop needed. */ op1_idx = 0; @@ -964,8 +996,7 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { /* use fxxx (tos = tos X tos) */ dst = tmpl->normal_op; out_idx = 0; - } - else { + } else { /* op2 is on tos now */ op2_idx = 0; /* use fxxxp (op = op X tos, pop) */ @@ -976,54 +1007,49 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { } } } - } - else { + } else { /* second operand is an address mode */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (op1_live_after) { /* first operand is live: push it here */ - x87_create_fpush(state, n, op1_idx, BINOP_IDX_1); + x87_create_fpush(state, n, op1_idx, n_ia32_binary_left); op1_idx = 0; - /* use fxxx (tos = tos X mem) */ - dst = tmpl->normal_op; - out_idx = 0; - } - else { + } else { /* first operand is dead: bring it to tos */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } - - /* use fxxxp (tos = tos X mem) */ - dst = tmpl->normal_op; - out_idx = 0; } + + /* use fxxx (tos = tos X mem) */ + dst = permuted ? tmpl->reverse_op : tmpl->normal_op; + out_idx = 0; } - x87_set_st(state, arch_register_get_index(out), x87_patch_insn(n, dst), out_idx); + patched_insn = x87_patch_insn(n, dst); + x87_set_st(state, arch_register_get_index(out), patched_insn, out_idx); if (do_pop) { x87_pop(state); } /* patch the operation */ - attr = get_ia32_attr(n); - attr->x87[0] = op1 = &ia32_st_regs[op1_idx]; - if (reg_index_2 != REG_VFP_NOREG) { - attr->x87[1] = op2 = &ia32_st_regs[op2_idx]; + attr->x87[0] = op1_reg = get_st_reg(op1_idx); + if (reg_index_2 != REG_VFP_VFP_NOREG) { + attr->x87[1] = op2_reg = get_st_reg(op2_idx); } - attr->x87[2] = out = &ia32_st_regs[out_idx]; + attr->x87[2] = out = get_st_reg(out_idx); - if (reg_index_2 != REG_VFP_NOREG) { + if (reg_index_2 != REG_VFP_VFP_NOREG) { DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n), - arch_register_get_name(op1), arch_register_get_name(op2), + arch_register_get_name(op1_reg), arch_register_get_name(op2_reg), arch_register_get_name(out))); } else { DB((dbg, LEVEL_1, "<<< %s %s, [AM] -> %s\n", get_irn_opname(n), - arch_register_get_name(op1), + arch_register_get_name(op1_reg), arch_register_get_name(out))); } - return 0; + return NO_NODE_ADDED; } /* sim_binop */ /** @@ -1032,13 +1058,16 @@ static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) { * @param state the x87 state * @param n the node that should be simulated (and patched) * @param op the x87 opcode that will replace n's opcode + * + * @return NO_NODE_ADDED */ -static int sim_unop(x87_state *state, ir_node *n, ir_op *op) { - int op1_idx, out_idx; +static int sim_unop(x87_state *state, ir_node *n, ir_op *op) +{ + int op1_idx; x87_simulator *sim = state->sim; - const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, UNOP_IDX)); - const arch_register_t *out = x87_get_irn_register(sim, n); - ia32_attr_t *attr; + const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, 0)); + const arch_register_t *out = x87_get_irn_register(n); + ia32_x87_attr_t *attr; unsigned live = vfp_live_args_after(sim, n, REGMASK(out)); DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name)); @@ -1048,25 +1077,24 @@ static int sim_unop(x87_state *state, ir_node *n, ir_op *op) { if (is_vfp_live(arch_register_get_index(op1), live)) { /* push the operand here */ - x87_create_fpush(state, n, op1_idx, UNOP_IDX); + x87_create_fpush(state, n, op1_idx, 0); op1_idx = 0; } else { /* operand is dead, bring it to tos */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, UNOP_IDX); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } } x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op)); - out_idx = 0; - attr = get_ia32_attr(n); - attr->x87[0] = op1 = &ia32_st_regs[0]; - attr->x87[2] = out = &ia32_st_regs[0]; + attr = get_ia32_x87_attr(n); + attr->x87[0] = op1 = get_st_reg(0); + attr->x87[2] = out = get_st_reg(0); DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name)); - return 0; + return NO_NODE_ADDED; } /* sim_unop */ /** @@ -1075,19 +1103,22 @@ static int sim_unop(x87_state *state, ir_node *n, ir_op *op) { * @param state the x87 state * @param n the node that should be simulated (and patched) * @param op the x87 opcode that will replace n's opcode + * + * @return NO_NODE_ADDED */ -static int sim_load(x87_state *state, ir_node *n, ir_op *op) { - const arch_register_t *out = x87_get_irn_register(state->sim, n); - ia32_attr_t *attr; +static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos) +{ + const arch_register_t *out = x87_irn_get_register(n, res_pos); + ia32_x87_attr_t *attr; DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out))); x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op)); - assert(out == x87_get_irn_register(state->sim, n)); - attr = get_ia32_attr(n); - attr->x87[2] = out = &ia32_st_regs[0]; + assert(out == x87_irn_get_register(n, res_pos)); + attr = get_ia32_x87_attr(n); + attr->x87[2] = out = get_st_reg(0); DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out))); - return 0; + return NO_NODE_ADDED; } /* sim_load */ /** @@ -1097,7 +1128,8 @@ static int sim_load(x87_state *state, ir_node *n, ir_op *op) { * @param old_val The former value * @param new_val The new value */ -static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val) { +static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val) +{ const ir_edge_t *edge, *ne; foreach_out_edge_safe(old_val, edge, ne) { @@ -1126,89 +1158,74 @@ static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node * * @param op the x87 store opcode * @param op_p the x87 store and pop opcode */ -static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { - x87_simulator *sim = state->sim; - ir_node *val = get_irn_n(n, STORE_VAL_IDX); - const arch_register_t *op2 = x87_get_irn_register(sim, val); - unsigned live = vfp_live_args_after(sim, n, 0); - int insn = 0; - ia32_attr_t *attr; +static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) +{ + ir_node *val = get_irn_n(n, n_ia32_vfst_val); + const arch_register_t *op2 = x87_get_irn_register(val); + unsigned live = vfp_live_args_after(state->sim, n, 0); + int insn = NO_NODE_ADDED; + ia32_x87_attr_t *attr; int op2_reg_idx, op2_idx, depth; int live_after_node; ir_mode *mode; op2_reg_idx = arch_register_get_index(op2); - if (op2_reg_idx == REG_VFP_UKNWN) { - // just take any value from stack - if(state->depth > 0) { - op2_idx = 0; - DEBUG_ONLY(op2 = NULL); - live_after_node = 1; - } else { - // produce a new value which we will consume imediately - x87_create_fldz(state, n, op2_reg_idx); - live_after_node = 0; - op2_idx = x87_on_stack(state, op2_reg_idx); - assert(op2_idx >= 0); - } - } else { - op2_idx = x87_on_stack(state, op2_reg_idx); - live_after_node = is_vfp_live(arch_register_get_index(op2), live); - assert(op2_idx >= 0); - DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2))); - } + op2_idx = x87_on_stack(state, op2_reg_idx); + live_after_node = is_vfp_live(arch_register_get_index(op2), live); + DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2))); + assert(op2_idx >= 0); mode = get_ia32_ls_mode(n); depth = x87_get_depth(state); if (live_after_node) { /* - Problem: fst doesn't support mode_E (spills), only fstp does + Problem: fst doesn't support 96bit modes (spills), only fstp does + fist doesn't support 64bit mode, only fistp Solution: - stack not full: push value and fstp - stack full: fstp value and load again + Note that we cannot test on mode_E, because floats might be 96bit ... */ - if (mode == mode_E) { - if (depth < N_x87_REGS) { + if (get_mode_size_bits(mode) > 64 || (mode_is_int(mode) && get_mode_size_bits(mode) > 32)) { + if (depth < N_ia32_st_REGS) { /* ok, we have a free register: push + fstp */ - x87_create_fpush(state, n, op2_idx, STORE_VAL_IDX); + x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val); x87_pop(state); x87_patch_insn(n, op_p); - } - else { + } else { ir_node *vfld, *mem, *block, *rproj, *mproj; - ir_graph *irg; + ir_graph *irg = get_irn_irg(n); + ir_node *nomem = get_irg_no_mem(irg); /* stack full here: need fstp + load */ x87_pop(state); x87_patch_insn(n, op_p); block = get_nodes_block(n); - irg = get_irn_irg(n); - vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg)); + vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), nomem, get_ia32_ls_mode(n)); /* copy all attributes */ set_ia32_frame_ent(vfld, get_ia32_frame_ent(n)); if (is_ia32_use_frame(n)) set_ia32_use_frame(vfld); - set_ia32_am_flavour(vfld, get_ia32_am_flavour(n)); - set_ia32_op_type(vfld, ia32_am_Source); + set_ia32_op_type(vfld, ia32_AddrModeS); add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n)); set_ia32_am_sc(vfld, get_ia32_am_sc(n)); set_ia32_ls_mode(vfld, get_ia32_ls_mode(n)); - rproj = new_r_Proj(irg, block, vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res); - mproj = new_r_Proj(irg, block, vfld, mode_M, pn_ia32_vfld_M); + rproj = new_r_Proj(vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res); + mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M); mem = get_irn_Proj_for_mode(n, mode_M); assert(mem && "Store memory not found"); - arch_set_irn_register(sim->env, rproj, op2); + arch_set_irn_register(rproj, op2); /* reroute all former users of the store memory to the load memory */ - edges_reroute(mem, mproj, irg); + edges_reroute(mem, mproj); /* set the memory input of the load to the store memory */ - set_irn_n(vfld, 2, mem); + set_irn_n(vfld, n_ia32_vfld_mem, mem); sched_add_after(n, vfld); sched_add_after(vfld, rproj); @@ -1216,52 +1233,32 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) { /* rewire all users, scheduled after the store, to the loaded value */ collect_and_rewire_users(n, val, rproj); - insn = 1; + insn = NODE_ADDED; } - } - else { + } else { /* we can only store the tos to memory */ - if(op2_idx != 0) - x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX); + if (op2_idx != 0) + x87_create_fxch(state, n, op2_idx); - /* mode != mode_E -> use normal fst */ + /* mode size 64 or smaller -> use normal fst */ x87_patch_insn(n, op); } - } - else { + } else { /* we can only store the tos to memory */ - if(op2_idx != 0) - x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX); + if (op2_idx != 0) + x87_create_fxch(state, n, op2_idx); x87_pop(state); x87_patch_insn(n, op_p); } - attr = get_ia32_attr(n); - attr->x87[1] = op2 = &ia32_st_regs[0]; + attr = get_ia32_x87_attr(n); + attr->x87[1] = op2 = get_st_reg(0); DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2))); return insn; } /* sim_store */ -/** - * Simulate a virtual Phi. - * Just for cosmetic reasons change the mode of Phi nodes to mode_E. - * - * @param state the x87 state - * @param n the node that should be simulated (and patched) - * @param env the architecture environment - */ -static int sim_Phi(x87_state *state, ir_node *n, const arch_env_t *env) { - ir_mode *mode = get_irn_mode(n); - - if (mode_is_float(mode)) - set_irn_mode(n, mode_E); - - return 0; -} /* sim_Phi */ - - #define _GEN_BINOP(op, rev) \ static int sim_##op(x87_state *state, ir_node *n) { \ exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \ @@ -1269,15 +1266,13 @@ static int sim_##op(x87_state *state, ir_node *n) { \ } #define GEN_BINOP(op) _GEN_BINOP(op, op) -#define GEN_BINOPR(op) _GEN_BINOP(op, op##r) +#define GEN_BINOPR(op) _GEN_BINOP(op, op##r) -#define GEN_LOAD2(op, nop) \ -static int sim_##op(x87_state *state, ir_node *n) { \ - return sim_load(state, n, op_ia32_##nop); \ +#define GEN_LOAD(op) \ +static int sim_##op(x87_state *state, ir_node *n) { \ + return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \ } -#define GEN_LOAD(op) GEN_LOAD2(op, op) - #define GEN_UNOP(op) \ static int sim_##op(x87_state *state, ir_node *n) { \ return sim_unop(state, n, op_ia32_##op); \ @@ -1297,37 +1292,121 @@ GEN_BINOP(fprem) GEN_UNOP(fabs) GEN_UNOP(fchs) -GEN_UNOP(fsin) -GEN_UNOP(fcos) -GEN_UNOP(fsqrt) GEN_LOAD(fld) GEN_LOAD(fild) GEN_LOAD(fldz) GEN_LOAD(fld1) -GEN_LOAD2(fConst, fldConst) GEN_STORE(fst) GEN_STORE(fist) /** - * Simulate a fCondJmp. + * Simulate a virtual fisttp. * * @param state the x87 state * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED + */ +static int sim_fisttp(x87_state *state, ir_node *n) +{ + ir_node *val = get_irn_n(n, n_ia32_vfst_val); + const arch_register_t *op2 = x87_get_irn_register(val); + ia32_x87_attr_t *attr; + int op2_reg_idx, op2_idx; + + op2_reg_idx = arch_register_get_index(op2); + op2_idx = x87_on_stack(state, op2_reg_idx); + DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2))); + assert(op2_idx >= 0); + + /* Note: although the value is still live here, it is destroyed because + of the pop. The register allocator is aware of that and introduced a copy + if the value must be alive. */ + + /* we can only store the tos to memory */ + if (op2_idx != 0) + x87_create_fxch(state, n, op2_idx); + + x87_pop(state); + x87_patch_insn(n, op_ia32_fisttp); + + attr = get_ia32_x87_attr(n); + attr->x87[1] = op2 = get_st_reg(0); + DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2))); + + return NO_NODE_ADDED; +} /* sim_fisttp */ + +/** + * Simulate a virtual FtstFnstsw. + * + * @param state the x87 state + * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED */ -static int sim_fCondJmp(x87_state *state, ir_node *n) { +static int sim_FtstFnstsw(x87_state *state, ir_node *n) +{ + x87_simulator *sim = state->sim; + ia32_x87_attr_t *attr = get_ia32_x87_attr(n); + ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left); + const arch_register_t *reg1 = x87_get_irn_register(op1_node); + int reg_index_1 = arch_register_get_index(reg1); + int op1_idx = x87_on_stack(state, reg_index_1); + unsigned live = vfp_live_args_after(sim, n, 0); + + DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1))); + DEBUG_ONLY(vfp_dump_live(live)); + DB((dbg, LEVEL_1, "Stack before: ")); + DEBUG_ONLY(x87_dump_stack(state)); + assert(op1_idx >= 0); + + if (op1_idx != 0) { + /* bring the value to tos */ + x87_create_fxch(state, n, op1_idx); + op1_idx = 0; + } + + /* patch the operation */ + x87_patch_insn(n, op_ia32_FtstFnstsw); + reg1 = get_st_reg(op1_idx); + attr->x87[0] = reg1; + attr->x87[1] = NULL; + attr->x87[2] = NULL; + + if (!is_vfp_live(reg_index_1, live)) + x87_create_fpop(state, sched_next(n), 1); + + return NO_NODE_ADDED; +} /* sim_FtstFnstsw */ + +/** + * Simulate a Fucom + * + * @param state the x87 state + * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED + */ +static int sim_Fucom(x87_state *state, ir_node *n) +{ int op1_idx; int op2_idx = -1; - int pop_cnt = 0; - ia32_attr_t *attr; + ia32_x87_attr_t *attr = get_ia32_x87_attr(n); ir_op *dst; - x87_simulator *sim = state->sim; - const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1)); - const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2)); + x87_simulator *sim = state->sim; + ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left); + ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right); + const arch_register_t *op1 = x87_get_irn_register(op1_node); + const arch_register_t *op2 = x87_get_irn_register(op2_node); int reg_index_1 = arch_register_get_index(op1); - int reg_index_2 = arch_register_get_index(op2); - unsigned live = vfp_live_args_after(sim, n, 0); + int reg_index_2 = arch_register_get_index(op2); + unsigned live = vfp_live_args_after(sim, n, 0); + bool permuted = attr->attr.data.ins_permuted; + bool xchg = false; + int pops = 0; DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n, arch_register_get_name(op1), arch_register_get_name(op2))); @@ -1339,70 +1418,74 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { assert(op1_idx >= 0); /* BEWARE: check for comp a,a cases, they might happen */ - if (reg_index_2 != REG_VFP_NOREG) { + if (reg_index_2 != REG_VFP_VFP_NOREG) { /* second operand is a vfp register */ op2_idx = x87_on_stack(state, reg_index_2); assert(op2_idx >= 0); - if (is_vfp_live(arch_register_get_index(op2), live)) { + if (is_vfp_live(reg_index_2, live)) { /* second operand is live */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (is_vfp_live(reg_index_1, live)) { /* both operands are live */ if (op1_idx == 0) { - dst = op_ia32_fcomJmp; + /* res = tos X op */ } else if (op2_idx == 0) { - dst = op_ia32_fcomrJmp; + /* res = op X tos */ + permuted = !permuted; + xchg = true; } else { /* bring the first one to tos */ - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); - if (op2_idx == 0) + x87_create_fxch(state, n, op1_idx); + if (op1_idx == op2_idx) { + op2_idx = 0; + } else if (op2_idx == 0) { op2_idx = op1_idx; + } op1_idx = 0; - dst = op_ia32_fcomJmp; + /* res = tos X op */ } - } - else { + } else { /* second live, first operand is dead here, bring it to tos. This means further, op1_idx != op2_idx. */ assert(op1_idx != op2_idx); if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); if (op2_idx == 0) op2_idx = op1_idx; op1_idx = 0; } - dst = op_ia32_fcompJmp; - pop_cnt = 1; + /* res = tos X op, pop */ + pops = 1; } - } - else { + } else { /* second operand is dead */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (is_vfp_live(reg_index_1, live)) { /* first operand is live: bring second to tos. This means further, op1_idx != op2_idx. */ assert(op1_idx != op2_idx); if (op2_idx != 0) { - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); if (op1_idx == 0) op1_idx = op2_idx; op2_idx = 0; } - dst = op_ia32_fcomrpJmp; - pop_cnt = 1; - } - else { + /* res = op X tos, pop */ + pops = 1; + permuted = !permuted; + xchg = true; + } else { /* both operands are dead here, check first for identity. */ if (op1_idx == op2_idx) { /* identically, one pop needed */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; op2_idx = 0; } - dst = op_ia32_fcompJmp; - pop_cnt = 1; + /* res = tos X op, pop */ + pops = 1; } /* different, move them to st and st(1) and pop both. The tricky part is to get one into st(1).*/ @@ -1410,342 +1493,450 @@ static int sim_fCondJmp(x87_state *state, ir_node *n) { /* good, second operand is already in the right place, move the first */ if (op1_idx != 0) { /* bring the first on top */ - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); + assert(op2_idx != 0); op1_idx = 0; } - dst = op_ia32_fcomppJmp; - pop_cnt = 2; - } - else if (op1_idx == 1) { + /* res = tos X op, pop, pop */ + pops = 2; + } else if (op1_idx == 1) { /* good, first operand is already in the right place, move the second */ if (op2_idx != 0) { /* bring the first on top */ - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); + assert(op1_idx != 0); op2_idx = 0; } - dst = op_ia32_fcomrppJmp; - pop_cnt = 2; - } - else { + /* res = op X tos, pop, pop */ + permuted = !permuted; + xchg = true; + pops = 2; + } else { /* if one is already the TOS, we need two fxch */ if (op1_idx == 0) { /* first one is TOS, move to st(1) */ - x87_create_fxch(state, n, 1, BINOP_IDX_1); + x87_create_fxch(state, n, 1); + assert(op2_idx != 1); op1_idx = 1; - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); op2_idx = 0; - dst = op_ia32_fcomrppJmp; - pop_cnt = 2; - } - else if (op2_idx == 0) { + /* res = op X tos, pop, pop */ + pops = 2; + permuted = !permuted; + xchg = true; + } else if (op2_idx == 0) { /* second one is TOS, move to st(1) */ - x87_create_fxch(state, n, 1, BINOP_IDX_2); + x87_create_fxch(state, n, 1); + assert(op1_idx != 1); op2_idx = 1; - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; - dst = op_ia32_fcomrppJmp; - pop_cnt = 2; - } - else { + /* res = tos X op, pop, pop */ + pops = 2; + } else { /* none of them is either TOS or st(1), 3 fxch needed */ - x87_create_fxch(state, n, op2_idx, BINOP_IDX_2); - x87_create_fxch(state, n, 1, BINOP_IDX_2); + x87_create_fxch(state, n, op2_idx); + assert(op1_idx != 0); + x87_create_fxch(state, n, 1); op2_idx = 1; - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; - dst = op_ia32_fcomppJmp; - pop_cnt = 2; + /* res = tos X op, pop, pop */ + pops = 2; } } } } - } - else { + } else { /* second operand is an address mode */ - if (is_vfp_live(arch_register_get_index(op1), live)) { + if (is_vfp_live(reg_index_1, live)) { /* first operand is live: bring it to TOS */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } - dst = op_ia32_fcomJmp; - } - else { + } else { /* first operand is dead: bring it to tos */ if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, BINOP_IDX_1); + x87_create_fxch(state, n, op1_idx); op1_idx = 0; } - dst = op_ia32_fcompJmp; - pop_cnt = 1; + pops = 1; } } + /* patch the operation */ + if (is_ia32_vFucomFnstsw(n)) { + int i; + + switch (pops) { + case 0: dst = op_ia32_FucomFnstsw; break; + case 1: dst = op_ia32_FucompFnstsw; break; + case 2: dst = op_ia32_FucomppFnstsw; break; + default: panic("invalid popcount in sim_Fucom"); + } + + for (i = 0; i < pops; ++i) { + x87_pop(state); + } + } else if (is_ia32_vFucomi(n)) { + switch (pops) { + case 0: dst = op_ia32_Fucomi; break; + case 1: dst = op_ia32_Fucompi; x87_pop(state); break; + case 2: + dst = op_ia32_Fucompi; + x87_pop(state); + x87_create_fpop(state, sched_next(n), 1); + break; + default: panic("invalid popcount in sim_Fucom"); + } + } else { + panic("invalid operation %+F in sim_FucomFnstsw", n); + } + x87_patch_insn(n, dst); - assert(pop_cnt < 3); - if (pop_cnt >= 2) - x87_pop(state); - if (pop_cnt >= 1) - x87_pop(state); + if (xchg) { + int tmp = op1_idx; + op1_idx = op2_idx; + op2_idx = tmp; + } - /* patch the operation */ - attr = get_ia32_attr(n); - op1 = &ia32_st_regs[op1_idx]; + op1 = get_st_reg(op1_idx); attr->x87[0] = op1; if (op2_idx >= 0) { - op2 = &ia32_st_regs[op2_idx]; + op2 = get_st_reg(op2_idx); attr->x87[1] = op2; } attr->x87[2] = NULL; + attr->attr.data.ins_permuted = permuted; - if (op2_idx >= 0) + if (op2_idx >= 0) { DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n), arch_register_get_name(op1), arch_register_get_name(op2))); - else + } else { DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n), arch_register_get_name(op1))); + } - return 0; -} /* sim_fCondJmp */ + return NO_NODE_ADDED; +} /* sim_Fucom */ /** - * Simulate a be_Copy. + * Simulate a Keep. * * @param state the x87 state * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED */ -static int sim_Copy(x87_state *state, ir_node *n) { - ir_mode *mode = get_irn_mode(n); +static int sim_Keep(x87_state *state, ir_node *node) +{ + const ir_node *op; + const arch_register_t *op_reg; + int reg_id; + int op_stack_idx; + unsigned live; + int i, arity; + + DB((dbg, LEVEL_1, ">>> %+F\n", node)); + + arity = get_irn_arity(node); + for (i = 0; i < arity; ++i) { + op = get_irn_n(node, i); + op_reg = arch_get_irn_register(op); + if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp]) + continue; - if (mode_is_float(mode)) { - x87_simulator *sim = state->sim; - ir_node *pred = get_irn_n(n, 0); - const arch_register_t *out = x87_get_irn_register(sim, n); - const arch_register_t *op1 = x87_get_irn_register(sim, pred); - ir_node *node, *next; - ia32_attr_t *attr; - int op1_idx, out_idx; - unsigned live = vfp_live_args_after(sim, n, REGMASK(out)); - ir_node *(*cnstr)(dbg_info *, ir_graph *, ir_node *, ir_mode *); - - DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, - arch_register_get_name(op1), arch_register_get_name(out))); - DEBUG_ONLY(vfp_dump_live(live)); + reg_id = arch_register_get_index(op_reg); + live = vfp_live_args_after(state->sim, node, 0); - /* Do not copy constants, recreate them. */ - switch (get_ia32_irn_opcode(pred)) { - case iro_ia32_fldz: - cnstr = new_rd_ia32_fldz; - break; - case iro_ia32_fld1: - cnstr = new_rd_ia32_fld1; - break; - case iro_ia32_fldpi: - cnstr = new_rd_ia32_fldpi; - break; - case iro_ia32_fldl2e: - cnstr = new_rd_ia32_fldl2e; - break; - case iro_ia32_fldl2t: - cnstr = new_rd_ia32_fldl2t; - break; - case iro_ia32_fldlg2: - cnstr = new_rd_ia32_fldlg2; - break; - case iro_ia32_fldln2: - cnstr = new_rd_ia32_fldln2; - break; - default: - goto no_constant; - } + op_stack_idx = x87_on_stack(state, reg_id); + if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) + x87_create_fpop(state, sched_next(node), 1); + } + + DB((dbg, LEVEL_1, "Stack after: ")); + DEBUG_ONLY(x87_dump_stack(state)); + + return NO_NODE_ADDED; +} /* sim_Keep */ + +/** + * Keep the given node alive by adding a be_Keep. + * + * @param node the node to kept alive + */ +static void keep_float_node_alive(ir_node *node) +{ + ir_node *block = get_nodes_block(node); + ir_node *keep = be_new_Keep(block, 1, &node); + assert(sched_is_scheduled(node)); + sched_add_after(node, keep); +} + +/** + * Create a copy of a node. Recreate the node if it's a constant. + * + * @param state the x87 state + * @param n the node to be copied + * + * @return the copy of n + */ +static ir_node *create_Copy(x87_state *state, ir_node *n) +{ + dbg_info *n_dbg = get_irn_dbg_info(n); + ir_mode *mode = get_irn_mode(n); + ir_node *block = get_nodes_block(n); + ir_node *pred = get_irn_n(n, 0); + ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL; + ir_node *res; + const arch_register_t *out; + const arch_register_t *op1; + ia32_x87_attr_t *attr; + + /* Do not copy constants, recreate them. */ + switch (get_ia32_irn_opcode(pred)) { + case iro_ia32_fldz: + cnstr = new_bd_ia32_fldz; + break; + case iro_ia32_fld1: + cnstr = new_bd_ia32_fld1; + break; + case iro_ia32_fldpi: + cnstr = new_bd_ia32_fldpi; + break; + case iro_ia32_fldl2e: + cnstr = new_bd_ia32_fldl2e; + break; + case iro_ia32_fldl2t: + cnstr = new_bd_ia32_fldl2t; + break; + case iro_ia32_fldlg2: + cnstr = new_bd_ia32_fldlg2; + break; + case iro_ia32_fldln2: + cnstr = new_bd_ia32_fldln2; + break; + default: + break; + } + + out = x87_get_irn_register(n); + op1 = x87_get_irn_register(pred); + + if (cnstr != NULL) { /* copy a constant */ - node = (*cnstr)(get_irn_dbg_info(n), get_irn_irg(n), get_nodes_block(n), mode); - arch_set_irn_register(sim->env, node, out); + res = (*cnstr)(n_dbg, block, mode); - x87_push(state, arch_register_get_index(out), node); + x87_push(state, arch_register_get_index(out), res); - attr = get_ia32_attr(node); - attr->x87[2] = out = &ia32_st_regs[0]; + attr = get_ia32_x87_attr(res); + attr->x87[2] = get_st_reg(0); + } else { + int op1_idx = x87_on_stack(state, arch_register_get_index(op1)); - next = sched_next(n); - sched_remove(n); - exchange(n, node); - sched_add_before(next, node); - DB((dbg, LEVEL_1, ">>> %+F -> %s\n", node, arch_register_get_name(out))); - return 0; + res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode); -no_constant: - /* handle the infamous unknown value */ - if (arch_register_get_index(op1) == REG_VFP_UKNWN) { - /* This happens before Phi nodes */ - if (x87_state_is_empty(state)) { - /* create some value */ - x87_patch_insn(n, op_ia32_fldz); - attr = get_ia32_attr(n); - attr->x87[2] = out = &ia32_st_regs[0]; - DB((dbg, LEVEL_1, "<<< %+F -> %s\n", n, - arch_register_get_name(out))); - } else { - /* Just copy one. We need here an fpush that can hold a - a register, so use the fpushCopy. */ - node = new_rd_ia32_fpushCopy(get_irn_dbg_info(n), get_irn_irg(n), get_nodes_block(n), get_irn_n(n, 0), mode); - arch_set_irn_register(sim->env, node, out); + x87_push(state, arch_register_get_index(out), res); - x87_push(state, arch_register_get_index(out), node); + attr = get_ia32_x87_attr(res); + attr->x87[0] = get_st_reg(op1_idx); + attr->x87[2] = get_st_reg(0); + } + arch_set_irn_register(res, out); - attr = get_ia32_attr(node); - attr->x87[0] = op1 = - attr->x87[2] = out = &ia32_st_regs[0]; + return res; +} /* create_Copy */ - next = sched_next(n); - sched_remove(n); - exchange(n, node); - sched_add_before(next, node); - DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, - arch_register_get_name(op1), - arch_register_get_name(out))); - } - return 0; - } +/** + * Simulate a be_Copy. + * + * @param state the x87 state + * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED + */ +static int sim_Copy(x87_state *state, ir_node *n) +{ + ir_node *pred; + const arch_register_t *out; + const arch_register_t *op1; + const arch_register_class_t *cls; + ir_node *node, *next; + int op1_idx, out_idx; + unsigned live; + + cls = arch_get_irn_reg_class(n); + if (cls != &ia32_reg_classes[CLASS_ia32_vfp]) + return 0; - op1_idx = x87_on_stack(state, arch_register_get_index(op1)); + pred = get_irn_n(n, 0); + out = x87_get_irn_register(n); + op1 = x87_get_irn_register(pred); + live = vfp_live_args_after(state->sim, n, REGMASK(out)); - if (is_vfp_live(arch_register_get_index(op1), live)) { - /* Operand is still live,a real copy. We need here an fpush that can hold a - a register, so use the fpushCopy. */ - node = new_rd_ia32_fpushCopy(get_irn_dbg_info(n), get_irn_irg(n), get_nodes_block(n), get_irn_n(n, 0), mode); - arch_set_irn_register(sim->env, node, out); + DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, + arch_register_get_name(op1), arch_register_get_name(out))); + DEBUG_ONLY(vfp_dump_live(live)); - x87_push(state, arch_register_get_index(out), node); + op1_idx = x87_on_stack(state, arch_register_get_index(op1)); - attr = get_ia32_attr(node); - attr->x87[0] = op1 = &ia32_st_regs[op1_idx]; - attr->x87[2] = out = &ia32_st_regs[0]; + if (is_vfp_live(arch_register_get_index(op1), live)) { + /* Operand is still live, a real copy. We need here an fpush that can + hold a a register, so use the fpushCopy or recreate constants */ + node = create_Copy(state, n); + + /* We have to make sure the old value doesn't go dead (which can happen + * when we recreate constants). As the simulator expected that value in + * the pred blocks. This is unfortunate as removing it would save us 1 + * instruction, but we would have to rerun all the simulation to get + * this correct... + */ + next = sched_next(n); + sched_remove(n); + exchange(n, node); + sched_add_before(next, node); - next = sched_next(n); - sched_remove(n); - exchange(n, node); - sched_add_before(next, node); - DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", node, op1->name, out->name)); + if (get_irn_n_edges(pred) == 0) { + keep_float_node_alive(pred); } - else { - out_idx = x87_on_stack(state, arch_register_get_index(out)); - - if (out_idx >= 0 && out_idx != op1_idx) { - /* op1 must be killed and placed where out is */ - if (out_idx == 0) { - /* best case, simple remove and rename */ - x87_patch_insn(n, op_ia32_Pop); - attr = get_ia32_attr(n); - attr->x87[0] = op1 = &ia32_st_regs[0]; - - x87_pop(state); - x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1); - } - else { - /* move op1 to tos, store and pop it */ - if (op1_idx != 0) { - x87_create_fxch(state, n, op1_idx, 0); - op1_idx = 0; - } - x87_patch_insn(n, op_ia32_Pop); - attr = get_ia32_attr(n); - attr->x87[0] = op1 = &ia32_st_regs[out_idx]; - x87_pop(state); - x87_set_st(state, arch_register_get_index(out), n, out_idx - 1); + DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name)); + } else { + out_idx = x87_on_stack(state, arch_register_get_index(out)); + + if (out_idx >= 0 && out_idx != op1_idx) { + /* Matze: out already on stack? how can this happen? */ + panic("invalid stack state in x87 simulator"); + +#if 0 + /* op1 must be killed and placed where out is */ + if (out_idx == 0) { + ia32_x87_attr_t *attr; + /* best case, simple remove and rename */ + x87_patch_insn(n, op_ia32_Pop); + attr = get_ia32_x87_attr(n); + attr->x87[0] = op1 = get_st_reg(0); + + x87_pop(state); + x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1); + } else { + ia32_x87_attr_t *attr; + /* move op1 to tos, store and pop it */ + if (op1_idx != 0) { + x87_create_fxch(state, n, op1_idx); + op1_idx = 0; } - DB((dbg, LEVEL_1, ">>> %+F %s\n", n, op1->name)); - } - else { - /* just a virtual copy */ - x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx); - sched_remove(n); - DB((dbg, LEVEL_1, ">>> KILLED %s\n", get_irn_opname(n))); - exchange(n, get_unop_op(n)); + x87_patch_insn(n, op_ia32_Pop); + attr = get_ia32_x87_attr(n); + attr->x87[0] = op1 = get_st_reg(out_idx); + + x87_pop(state); + x87_set_st(state, arch_register_get_index(out), n, out_idx - 1); } + DB((dbg, LEVEL_1, "<<< %+F %s\n", n, op1->name)); +#endif + } else { + /* just a virtual copy */ + x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx); + /* don't remove the node to keep the verifier quiet :), + the emitter won't emit any code for the node */ +#if 0 + sched_remove(n); + DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n))); + exchange(n, get_unop_op(n)); +#endif } } - return 0; + return NO_NODE_ADDED; } /* sim_Copy */ /** - * Simulate a be_Call. + * Returns the vf0 result Proj of a Call. * - * @param state the x87 state - * @param n the node that should be simulated - * @param env the architecture environment + * @para call the Call node + */ +static ir_node *get_call_result_proj(ir_node *call) +{ + const ir_edge_t *edge; + + /* search the result proj */ + foreach_out_edge(call, edge) { + ir_node *proj = get_edge_src_irn(edge); + long pn = get_Proj_proj(proj); + + if (pn == pn_ia32_Call_vf0) + return proj; + } + + return NULL; +} /* get_call_result_proj */ + +/** + * Simulate a ia32_Call. + * + * @param state the x87 state + * @param n the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED */ -static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *env) { - ir_type *call_tp = be_Call_get_type(n); +static int sim_Call(x87_state *state, ir_node *n) +{ + ir_type *call_tp = get_ia32_call_attr_const(n)->call_tp; + ir_type *res_type; + ir_mode *mode; + ir_node *resproj; + const arch_register_t *reg; + + DB((dbg, LEVEL_1, ">>> %+F\n", n)); /* at the begin of a call the x87 state should be empty */ assert(state->depth == 0 && "stack not empty before call"); + if (get_method_n_ress(call_tp) <= 0) + goto end_call; + /* * If the called function returns a float, it is returned in st(0). * This even happens if the return value is NOT used. * Moreover, only one return result is supported. */ - if (get_method_n_ress(call_tp) > 0) { - ir_type *res_type = get_method_res_type(call_tp, 0); - ir_mode *mode = get_type_mode(res_type); + res_type = get_method_res_type(call_tp, 0); + mode = get_type_mode(res_type); - if (mode && mode_is_float(mode)) { - /* - * TODO: what to push here? The result might be unused and currently - * we have no possibility to detect this :-( - */ - x87_push(state, 0, n); - } - } + if (mode == NULL || !mode_is_float(mode)) + goto end_call; - return 0; -} /* sim_Call */ + resproj = get_call_result_proj(n); + assert(resproj != NULL); -/** - * Simulate a be_Spill. - * - * @param state the x87 state - * @param n the node that should be simulated (and patched) - * @param env the architecture environment - * - * Should not happen, spills are lowered before x87 simulator see them. - */ -static int sim_Spill(x87_state *state, ir_node *n) { - assert(0 && "Spill not lowered"); - return sim_fst(state, n); -} /* sim_Spill */ + reg = x87_get_irn_register(resproj); + x87_push(state, arch_register_get_index(reg), resproj); -/** - * Simulate a be_Reload. - * - * @param state the x87 state - * @param n the node that should be simulated (and patched) - * @param env the architecture environment - * - * Should not happen, reloads are lowered before x87 simulator see them. - */ -static int sim_Reload(x87_state *state, ir_node *n) { - assert(0 && "Reload not lowered"); - return sim_fld(state, n); -} /* sim_Reload */ +end_call: + DB((dbg, LEVEL_1, "Stack after: ")); + DEBUG_ONLY(x87_dump_stack(state)); + + return NO_NODE_ADDED; +} /* sim_Call */ /** * Simulate a be_Return. * * @param state the x87 state * @param n the node that should be simulated (and patched) - * @param env the architecture environment + * + * @return NO_NODE_ADDED */ -static int sim_Return(x87_state *state, ir_node *n) { +static int sim_Return(x87_state *state, ir_node *n) +{ int n_res = be_Return_get_n_rets(n); int i, n_float_res = 0; - /* only floating point return values must resist on stack */ + /* only floating point return values must reside on stack */ for (i = 0; i < n_res; ++i) { - ir_node *res = get_irn_n(n, be_pos_Return_val + i); + ir_node *res = get_irn_n(n, n_be_Return_val + i); if (mode_is_float(get_irn_mode(res))) ++n_float_res; @@ -1756,10 +1947,10 @@ static int sim_Return(x87_state *state, ir_node *n) { for (i = n_float_res - 1; i >= 0; --i) x87_pop(state); - return 0; + return NO_NODE_ADDED; } /* sim_Return */ -typedef struct _perm_data_t { +typedef struct perm_data_t { const arch_register_t *in; const arch_register_t *out; } perm_data_t; @@ -1769,17 +1960,19 @@ typedef struct _perm_data_t { * * @param state the x87 state * @param irn the node that should be simulated (and patched) + * + * @return NO_NODE_ADDED */ -static int sim_Perm(x87_state *state, ir_node *irn) { +static int sim_Perm(x87_state *state, ir_node *irn) +{ int i, n; - x87_simulator *sim = state->sim; ir_node *pred = get_irn_n(irn, 0); int *stack_pos; const ir_edge_t *edge; /* handle only floating point Perms */ if (! mode_is_float(get_irn_mode(pred))) - return 0; + return NO_NODE_ADDED; DB((dbg, LEVEL_1, ">>> %+F\n", irn)); @@ -1792,7 +1985,7 @@ static int sim_Perm(x87_state *state, ir_node *irn) { /* collect old stack positions */ for (i = 0; i < n; ++i) { - const arch_register_t *inreg = x87_get_irn_register(sim, get_irn_n(irn, i)); + const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i)); int idx = x87_on_stack(state, arch_register_get_index(inreg)); assert(idx >= 0 && "Perm argument not on x87 stack"); @@ -1802,7 +1995,7 @@ static int sim_Perm(x87_state *state, ir_node *irn) { /* now do the permutation */ foreach_out_edge(irn, edge) { ir_node *proj = get_edge_src_irn(edge); - const arch_register_t *out = x87_get_irn_register(sim, proj); + const arch_register_t *out = x87_get_irn_register(proj); long num = get_Proj_proj(proj); assert(0 <= num && num < n && "More Proj's than Perm inputs"); @@ -1810,8 +2003,8 @@ static int sim_Perm(x87_state *state, ir_node *irn) { } DB((dbg, LEVEL_1, "<<< %+F\n", irn)); - return 0; -} /* be_Perm */ + return NO_NODE_ADDED; +} /* sim_Perm */ /** * Kill any dead registers at block start by popping them from the stack. @@ -1819,8 +2012,11 @@ static int sim_Perm(x87_state *state, ir_node *irn) { * @param sim the simulator handle * @param block the current block * @param start_state the x87 state at the begin of the block + * + * @return the x87 state after dead register killed */ -static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state) { +static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state) +{ x87_state *state = start_state; ir_node *first_insn = sched_first(block); ir_node *keep = NULL; @@ -1845,6 +2041,22 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * DEBUG_ONLY(vfp_dump_live(live)); DEBUG_ONLY(x87_dump_stack(state)); + if (kill_mask != 0 && live == 0) { + /* special case: kill all registers */ + if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) { + if (ia32_cg_config.use_femms) { + /* use FEMMS on AMD processors to clear all */ + keep = new_bd_ia32_femms(NULL, block); + } else { + /* use EMMS to clear all */ + keep = new_bd_ia32_emms(NULL, block); + } + sched_add_before(first_insn, keep); + keep_alive(keep); + x87_emms(state); + return state; + } + } /* now kill registers */ while (kill_mask) { /* we can only kill from TOS, so bring them up */ @@ -1860,10 +2072,8 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * if (keep) x87_set_st(state, -1, keep, i); - keep = x87_create_fxch(state, first_insn, i, -1); + x87_create_fxch(state, first_insn, i); } - else if (! keep) - keep = x87_get_st_node(state, 0); if ((kill_mask & 3) == 3) { /* we can do a double-pop */ @@ -1876,7 +2086,7 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * depth -= num_pop; kill_mask >>= num_pop; - keep = x87_create_fpop(state, first_insn, num_pop, keep); + keep = x87_create_fpop(state, first_insn, num_pop); } keep_alive(keep); } @@ -1888,11 +2098,9 @@ static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state * * * @param sim the simulator handle * @param block the current block - * - * @return non-zero if simulation is complete, - * zero if the simulation must be rerun */ -static void x87_simulate_block(x87_simulator *sim, ir_node *block) { +static void x87_simulate_block(x87_simulator *sim, ir_node *block) +{ ir_node *n, *next; blk_state *bl_state = x87_get_bl_state(sim, block); x87_state *state = bl_state->begin; @@ -1900,93 +2108,105 @@ static void x87_simulate_block(x87_simulator *sim, ir_node *block) { ir_node *start_block; assert(state != NULL); - // already processed? - if(bl_state->end != NULL) + /* already processed? */ + if (bl_state->end != NULL) return; - update_liveness(sim, block); - DB((dbg, LEVEL_1, "Simulate %+F\n", block)); DB((dbg, LEVEL_2, "State at Block begin:\n ")); DEBUG_ONLY(x87_dump_stack(state)); /* at block begin, kill all dead registers */ state = x87_kill_deads(sim, block, state); + /* create a new state, will be changed */ + state = x87_clone_state(sim, state); - /* beware, n might changed */ + /* beware, n might change */ for (n = sched_first(block); !sched_is_end(n); n = next) { int node_inserted; sim_func func; ir_op *op = get_irn_op(n); + /* + * get the next node to be simulated here. + * n might be completely removed from the schedule- + */ next = sched_next(n); - if (op->ops.generic == NULL) - continue; + if (op->ops.generic != NULL) { + func = (sim_func)op->ops.generic; - func = (sim_func)op->ops.generic; + /* simulate it */ + node_inserted = (*func)(state, n); - /* have work to do */ - if (state == bl_state->begin) { - /* create a new state, will be changed */ - state = x87_clone_state(sim, state); + /* + * sim_func might have added an additional node after n, + * so update next node + * beware: n must not be changed by sim_func + * (i.e. removed from schedule) in this case + */ + if (node_inserted != NO_NODE_ADDED) + next = sched_next(n); } - - /* simulate it */ - node_inserted = (*func)(state, n); - - /* - sim_func might have added additional nodes after n, - so update next node - beware: n must not be changed by sim_func - (i.e. removed from schedule) in this case - */ - if (node_inserted) - next = sched_next(n); } start_block = get_irg_start_block(get_irn_irg(block)); + DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state)); + /* check if the state must be shuffled */ foreach_block_succ(block, edge) { ir_node *succ = get_edge_src_irn(edge); blk_state *succ_state; - if(succ == start_block) + if (succ == start_block) continue; succ_state = x87_get_bl_state(sim, succ); if (succ_state->begin == NULL) { + DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ)); + DEBUG_ONLY(x87_dump_stack(state)); succ_state->begin = state; + waitq_put(sim->worklist, succ); } else { + DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ)); /* There is already a begin state for the successor, bad. Do the necessary permutations. - Note that critical edges are removed, so this is always possible. */ + Note that critical edges are removed, so this is always possible: + If the successor has more than one possible input, then it must + be the only one. + */ x87_shuffle(sim, block, state, succ, succ_state->begin); } } bl_state->end = state; - - DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state)); } /* x87_simulate_block */ +/** + * Register a simulator function. + * + * @param op the opcode to simulate + * @param func the simulator function for the opcode + */ +static void register_sim(ir_op *op, sim_func func) +{ + assert(op->ops.generic == NULL); + op->ops.generic = (op_func) func; +} /* register_sim */ + /** * Create a new x87 simulator. * - * @param sim a simulator handle, will be initialized - * @param irg the current graph - * @param env the architecture environment + * @param sim a simulator handle, will be initialized + * @param irg the current graph */ -static void x87_init_simulator(x87_simulator *sim, ir_graph *irg, const arch_env_t *env) +static void x87_init_simulator(x87_simulator *sim, ir_graph *irg) { obstack_init(&sim->obst); sim->blk_states = pmap_create(); - sim->env = env; sim->n_idx = get_irg_last_idx(irg); - sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx); - - FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87"); + sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx); DB((dbg, LEVEL_1, "--------------------------------\n" "x87 Simulator started for %+F\n", irg)); @@ -1994,37 +2214,28 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg, const arch_env /* set the generic function pointer of instruction we must simulate */ clear_irp_opcodes_generic_func(); -#define ASSOC(op) (op_ ## op)->ops.generic = (op_func)(sim_##op) -#define ASSOC_IA32(op) (op_ia32_v ## op)->ops.generic = (op_func)(sim_##op) -#define ASSOC_BE(op) (op_be_ ## op)->ops.generic = (op_func)(sim_##op) - ASSOC_IA32(fConst); - ASSOC_IA32(fld); - ASSOC_IA32(fild); - ASSOC_IA32(fld1); - ASSOC_IA32(fldz); - ASSOC_IA32(fadd); - ASSOC_IA32(fsub); - ASSOC_IA32(fmul); - ASSOC_IA32(fdiv); - ASSOC_IA32(fprem); - ASSOC_IA32(fabs); - ASSOC_IA32(fchs); - ASSOC_IA32(fsin); - ASSOC_IA32(fcos); - ASSOC_IA32(fsqrt); - ASSOC_IA32(fist); - ASSOC_IA32(fst); - ASSOC_IA32(fCondJmp); - ASSOC_BE(Copy); - ASSOC_BE(Call); - ASSOC_BE(Spill); - ASSOC_BE(Reload); - ASSOC_BE(Return); - ASSOC_BE(Perm); - ASSOC(Phi); -#undef ASSOC_BE -#undef ASSOC_IA32 -#undef ASSOC + register_sim(op_ia32_Call, sim_Call); + register_sim(op_ia32_vfld, sim_fld); + register_sim(op_ia32_vfild, sim_fild); + register_sim(op_ia32_vfld1, sim_fld1); + register_sim(op_ia32_vfldz, sim_fldz); + register_sim(op_ia32_vfadd, sim_fadd); + register_sim(op_ia32_vfsub, sim_fsub); + register_sim(op_ia32_vfmul, sim_fmul); + register_sim(op_ia32_vfdiv, sim_fdiv); + register_sim(op_ia32_vfprem, sim_fprem); + register_sim(op_ia32_vfabs, sim_fabs); + register_sim(op_ia32_vfchs, sim_fchs); + register_sim(op_ia32_vfist, sim_fist); + register_sim(op_ia32_vfisttp, sim_fisttp); + register_sim(op_ia32_vfst, sim_fst); + register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw); + register_sim(op_ia32_vFucomFnstsw, sim_Fucom); + register_sim(op_ia32_vFucomi, sim_Fucom); + register_sim(op_be_Copy, sim_Copy); + register_sim(op_be_Return, sim_Return); + register_sim(op_be_Perm, sim_Perm); + register_sim(op_be_Keep, sim_Keep); } /* x87_init_simulator */ /** @@ -2032,31 +2243,41 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg, const arch_env * * @param sim the simulator handle */ -static void x87_destroy_simulator(x87_simulator *sim) { +static void x87_destroy_simulator(x87_simulator *sim) +{ pmap_destroy(sim->blk_states); obstack_free(&sim->obst, NULL); DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n")); } /* x87_destroy_simulator */ /** + * Pre-block walker: calculate the liveness information for the block + * and store it into the sim->live cache. + */ +static void update_liveness_walker(ir_node *block, void *data) +{ + x87_simulator *sim = (x87_simulator*)data; + update_liveness(sim, block); +} /* update_liveness_walker */ + +/* * Run a simulation and fix all virtual instructions for a graph. - * - * @param env the architecture environment - * @param irg the current graph - * - * Needs a block-schedule. + * Replaces all virtual floating point instructions and registers + * by real ones. */ -void x87_simulate_graph(const arch_env_t *env, be_irg_t *birg) { +void ia32_x87_simulate_graph(ir_graph *irg) +{ + /* TODO improve code quality (less executed fxch) by using execfreqs */ + ir_node *block, *start_block; blk_state *bl_state; x87_simulator sim; - ir_graph *irg = birg->irg; /* create the simulator */ - x87_init_simulator(&sim, irg, env); + x87_init_simulator(&sim, irg); start_block = get_irg_start_block(irg); - bl_state = x87_get_bl_state(&sim, start_block); + bl_state = x87_get_bl_state(&sim, start_block); /* start with the empty state */ bl_state->begin = empty; @@ -2065,31 +2286,31 @@ void x87_simulate_graph(const arch_env_t *env, be_irg_t *birg) { sim.worklist = new_waitq(); waitq_put(sim.worklist, start_block); - be_invalidate_liveness(birg); - be_assure_liveness(birg); - sim.lv = birg->lv; + be_assure_liveness(irg); + sim.lv = be_get_irg_liveness(irg); + be_liveness_assure_sets(sim.lv); -#if 0 - /* Create the worklist for the schedule and calculate the liveness - for all nodes. We must precalculate this info, because the - simulator adds new nodes (and possible before Phi nodes) which - let fail the old lazy calculation. - On the other hand we reduce the computation amount due to - precaching from O(n^2) to O(n) at the expense of O(n) cache memory. + /* Calculate the liveness for all nodes. We must precalculate this info, + * because the simulator adds new nodes (possible before Phi nodes) which + * would let a lazy calculation fail. + * On the other hand we reduce the computation amount due to + * precaching from O(n^2) to O(n) at the expense of O(n) cache memory. */ - for (i = 0, n = ARR_LEN(blk_list); i < n; ++i) { - update_liveness(&sim, lv, blk_list[i]); - waitq_put(worklist, blk_list[i]); - } -#endif + irg_block_walk_graph(irg, update_liveness_walker, NULL, &sim); /* iterate */ do { - block = waitq_get(sim.worklist); + block = (ir_node*)waitq_get(sim.worklist); x87_simulate_block(&sim, block); - } while (! pdeq_empty(sim.worklist)); + } while (! waitq_empty(sim.worklist)); /* kill it */ del_waitq(sim.worklist); x87_destroy_simulator(&sim); -} /* x87_simulate_graph */ +} /* ia32_x87_simulate_graph */ + +/* Initializes the x87 simulator. */ +void ia32_init_x87(void) +{ + FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87"); +} /* ia32_init_x87 */