X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=e34902a09c0a45ad36f5f6b2a1ab86dfbb6b1c8f;hb=8d2eb4b443fde55c4296656605c07ddd36019636;hp=145af7a90230e5261243011b056aa71fd091e52a;hpb=1650d6cbcdc4e3b70109e59751168103916a04e0;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 145af7a90..e34902a09 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -48,11 +48,11 @@ #include "array_t.h" #include "height.h" -#include "../benode_t.h" +#include "../benode.h" #include "../besched.h" #include "../beabi.h" #include "../beutil.h" -#include "../beirg_t.h" +#include "../beirg.h" #include "../betranshlp.h" #include "../be_t.h" @@ -70,6 +70,10 @@ #include "gen_ia32_regalloc_if.h" +/* define this to construct SSE constants instead of load them */ +#undef CONSTRUCT_SSE_CONST + + #define SFP_SIGN "0x80000000" #define DFP_SIGN "0x8000000000000000" #define SFP_ABS "0x7FFFFFFF" @@ -89,8 +93,7 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) static ir_node *initial_fpcw = NULL; - -extern ir_op *get_op_Mulh(void); +int no_pic_adjust; typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, @@ -122,6 +125,13 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, dbg_info *dbgi, ir_node *block, ir_node *op, ir_node *orig_node); +/* its enough to have those once */ +static ir_node *nomem, *noreg_GP; + +/** a list to postprocess all calls */ +static ir_node **call_list; +static ir_type **call_types; + /** Return non-zero is a node represents the 0 constant. */ static bool is_Const_0(ir_node *node) { @@ -164,9 +174,13 @@ static bool is_simple_sse_Const(ir_node *node) if (mode == mode_F) return true; - if (tarval_is_null(tv) || tarval_is_one(tv)) + if (tarval_is_null(tv) +#ifdef CONSTRUCT_SSE_CONST + || tarval_is_one(tv) +#endif + ) return true; - +#ifdef CONSTRUCT_SSE_CONST if (mode == mode_D) { unsigned val = get_tarval_sub_bits(tv, 0) | (get_tarval_sub_bits(tv, 1) << 8) | @@ -176,7 +190,7 @@ static bool is_simple_sse_Const(ir_node *node) /* lower 32bit are zero, really a 32bit constant */ return true; } - +#endif /* CONSTRUCT_SSE_CONST */ /* TODO: match all the other float constants */ return false; } @@ -195,8 +209,6 @@ static ir_node *gen_Const(ir_node *node) if (mode_is_float(mode)) { ir_node *res = NULL; - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *load; ir_entity *floatent; @@ -206,10 +218,11 @@ static ir_node *gen_Const(ir_node *node) load = new_bd_ia32_xZero(dbgi, block); set_ia32_ls_mode(load, mode); res = load; +#ifdef CONSTRUCT_SSE_CONST } else if (tarval_is_one(tv)) { int cnst = mode == mode_F ? 26 : 55; - ir_node *imm1 = create_Immediate(NULL, 0, cnst); - ir_node *imm2 = create_Immediate(NULL, 0, 2); + ir_node *imm1 = ia32_create_Immediate(NULL, 0, cnst); + ir_node *imm2 = ia32_create_Immediate(NULL, 0, 2); ir_node *pslld, *psrld; load = new_bd_ia32_xAllOnes(dbgi, block); @@ -219,24 +232,26 @@ static ir_node *gen_Const(ir_node *node) psrld = new_bd_ia32_xPsrld(dbgi, block, pslld, imm2); set_ia32_ls_mode(psrld, mode); res = psrld; +#endif /* CONSTRUCT_SSE_CONST */ } else if (mode == mode_F) { /* we can place any 32bit constant by using a movd gp, sse */ unsigned val = get_tarval_sub_bits(tv, 0) | (get_tarval_sub_bits(tv, 1) << 8) | (get_tarval_sub_bits(tv, 2) << 16) | (get_tarval_sub_bits(tv, 3) << 24); - ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val); + ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val); load = new_bd_ia32_xMovd(dbgi, block, cnst); set_ia32_ls_mode(load, mode); res = load; } else { +#ifdef CONSTRUCT_SSE_CONST if (mode == mode_D) { unsigned val = get_tarval_sub_bits(tv, 0) | (get_tarval_sub_bits(tv, 1) << 8) | (get_tarval_sub_bits(tv, 2) << 16) | (get_tarval_sub_bits(tv, 3) << 24); if (val == 0) { - ir_node *imm32 = create_Immediate(NULL, 0, 32); + ir_node *imm32 = ia32_create_Immediate(NULL, 0, 32); ir_node *cnst, *psllq; /* fine, lower 32bit are zero, produce 32bit value */ @@ -244,7 +259,7 @@ static ir_node *gen_Const(ir_node *node) (get_tarval_sub_bits(tv, 5) << 8) | (get_tarval_sub_bits(tv, 6) << 16) | (get_tarval_sub_bits(tv, 7) << 24); - cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val); + cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val); load = new_bd_ia32_xMovd(dbgi, block, cnst); set_ia32_ls_mode(load, mode); psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32); @@ -253,14 +268,14 @@ static ir_node *gen_Const(ir_node *node) goto end; } } +#endif /* CONSTRUCT_SSE_CONST */ floatent = create_float_const_entity(node); - load = new_bd_ia32_xLoad(dbgi, block, noreg, noreg, nomem, - mode); + load = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); arch_irn_add_flags(load, arch_irn_flags_rematerializable); - res = new_r_Proj(current_ir_graph, block, load, mode_xmm, pn_ia32_xLoad_res); + res = new_r_Proj(block, load, mode_xmm, pn_ia32_xLoad_res); } } else { if (is_Const_null(node)) { @@ -272,18 +287,24 @@ static ir_node *gen_Const(ir_node *node) res = load; set_ia32_ls_mode(load, mode); } else { + ir_mode *ls_mode; + floatent = create_float_const_entity(node); + /* create_float_const_ent is smart and sometimes creates + smaller entities */ + ls_mode = get_type_mode(get_entity_type(floatent)); - load = new_bd_ia32_vfld(dbgi, block, noreg, noreg, nomem, mode); + load = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, + ls_mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); arch_irn_add_flags(load, arch_irn_flags_rematerializable); - res = new_r_Proj(current_ir_graph, block, load, mode_vfp, pn_ia32_vfld_res); - /* take the mode from the entity */ - set_ia32_ls_mode(load, get_type_mode(get_entity_type(floatent))); + res = new_r_Proj(block, load, mode_vfp, pn_ia32_vfld_res); } } +#ifdef CONSTRUCT_SSE_CONST end: +#endif /* CONSTRUCT_SSE_CONST */ SET_IA32_ORIG_NODE(load, node); be_dep_on_frame(load); @@ -301,7 +322,7 @@ end: } val = get_tarval_long(tv); - cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val); + cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val); SET_IA32_ORIG_NODE(cnst, node); be_dep_on_frame(cnst); @@ -321,13 +342,10 @@ static ir_node *gen_SymConst(ir_node *node) ir_node *cnst; if (mode_is_float(mode)) { - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); - if (ia32_cg_config.use_sse2) - cnst = new_bd_ia32_xLoad(dbgi, block, noreg, noreg, nomem, mode_E); + cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E); else - cnst = new_bd_ia32_vfld(dbgi, block, noreg, noreg, nomem, mode_E); + cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E); set_ia32_am_sc(cnst, get_SymConst_entity(node)); set_ia32_use_frame(cnst); } else { @@ -337,7 +355,7 @@ static ir_node *gen_SymConst(ir_node *node) panic("backend only support symconst_addr_ent (at %+F)", node); } entity = get_SymConst_entity(node); - cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0); + cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0); } SET_IA32_ORIG_NODE(cnst, node); @@ -352,8 +370,8 @@ static ir_node *gen_SymConst(ir_node *node) * @param mode the mode for the float type (might be integer mode for SSE2 types) * @param align alignment */ -static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { - char buf[32]; +static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) +{ ir_type *tp; assert(align <= 16); @@ -362,8 +380,7 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { static ir_type *int_Iu[16] = {NULL, }; if (int_Iu[align] == NULL) { - snprintf(buf, sizeof(buf), "int_Iu_%u", align); - int_Iu[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + int_Iu[align] = tp = new_type_primitive(mode); /* set the specified alignment */ set_type_alignment_bytes(tp, align); } @@ -372,8 +389,7 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { static ir_type *int_Lu[16] = {NULL, }; if (int_Lu[align] == NULL) { - snprintf(buf, sizeof(buf), "int_Lu_%u", align); - int_Lu[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + int_Lu[align] = tp = new_type_primitive(mode); /* set the specified alignment */ set_type_alignment_bytes(tp, align); } @@ -382,8 +398,7 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { static ir_type *float_F[16] = {NULL, }; if (float_F[align] == NULL) { - snprintf(buf, sizeof(buf), "float_F_%u", align); - float_F[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + float_F[align] = tp = new_type_primitive(mode); /* set the specified alignment */ set_type_alignment_bytes(tp, align); } @@ -392,8 +407,7 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { static ir_type *float_D[16] = {NULL, }; if (float_D[align] == NULL) { - snprintf(buf, sizeof(buf), "float_D_%u", align); - float_D[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + float_D[align] = tp = new_type_primitive(mode); /* set the specified alignment */ set_type_alignment_bytes(tp, align); } @@ -402,8 +416,7 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { static ir_type *float_E[16] = {NULL, }; if (float_E[align] == NULL) { - snprintf(buf, sizeof(buf), "float_E_%u", align); - float_E[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + float_E[align] = tp = new_type_primitive(mode); /* set the specified alignment */ set_type_alignment_bytes(tp, align); } @@ -416,8 +429,8 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { * * @param tp the atomic type */ -static ir_type *ia32_create_float_array(ir_type *tp) { - char buf[32]; +static ir_type *ia32_create_float_array(ir_type *tp) +{ ir_mode *mode = get_type_mode(tp); unsigned align = get_type_alignment_bytes(tp); ir_type *arr; @@ -429,22 +442,19 @@ static ir_type *ia32_create_float_array(ir_type *tp) { if (float_F[align] != NULL) return float_F[align]; - snprintf(buf, sizeof(buf), "arr_float_F_%u", align); - arr = float_F[align] = new_type_array(new_id_from_str(buf), 1, tp); + arr = float_F[align] = new_type_array(1, tp); } else if (mode == mode_D) { static ir_type *float_D[16] = {NULL, }; if (float_D[align] != NULL) return float_D[align]; - snprintf(buf, sizeof(buf), "arr_float_D_%u", align); - arr = float_D[align] = new_type_array(new_id_from_str(buf), 1, tp); + arr = float_D[align] = new_type_array(1, tp); } else { static ir_type *float_E[16] = {NULL, }; if (float_E[align] != NULL) return float_E[align]; - snprintf(buf, sizeof(buf), "arr_float_E_%u", align); - arr = float_E[align] = new_type_array(new_id_from_str(buf), 1, tp); + arr = float_E[align] = new_type_array(1, tp); } set_type_alignment_bytes(arr, align); set_type_size_bytes(arr, 2 * get_type_size_bytes(tp)); @@ -588,23 +598,19 @@ struct ia32_address_mode_t { static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem) { - ir_node *noreg_gp; - /* construct load address */ memset(addr, 0, sizeof(addr[0])); ia32_create_address_mode(addr, ptr, 0); - noreg_gp = ia32_new_NoReg_gp(env_cg); - addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp; - addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp; + addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP; + addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP; addr->mem = be_transform_node(mem); } static void build_address(ia32_address_mode_t *am, ir_node *node, ia32_create_am_flags_t flags) { - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ia32_address_t *addr = &am->addr; + ia32_address_t *addr = &am->addr; ir_node *load; ir_node *ptr; ir_node *mem; @@ -612,9 +618,9 @@ static void build_address(ia32_address_mode_t *am, ir_node *node, if (is_Const(node)) { ir_entity *entity = create_float_const_entity(node); - addr->base = noreg_gp; - addr->index = noreg_gp; - addr->mem = new_NoMem(); + addr->base = noreg_GP; + addr->index = noreg_GP; + addr->mem = nomem; addr->symconst_ent = entity; addr->use_frame = 1; am->ls_mode = get_type_mode(get_entity_type(entity)); @@ -634,8 +640,8 @@ static void build_address(ia32_address_mode_t *am, ir_node *node, /* construct load address */ ia32_create_address_mode(addr, ptr, flags); - addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp; - addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp; + addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP; + addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP; addr->mem = new_mem; } @@ -744,7 +750,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, ia32_address_t *addr = &am->addr; ir_mode *mode = get_irn_mode(op2); int mode_bits = get_mode_size_bits(mode); - ir_node *noreg_gp, *new_op1, *new_op2; + ir_node *new_op1, *new_op2; int use_am; unsigned commutative; int use_am_and_immediates; @@ -764,7 +770,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, assert(use_am || !(flags & match_16bit_am)); if ((mode_bits == 8 && !(flags & match_8bit_am)) || - (mode_bits == 16 && !(flags & match_16bit_am))) { + (mode_bits == 16 && !(flags & match_16bit_am))) { use_am = 0; } @@ -784,7 +790,6 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, new_op2 = try_create_Immediate(op2, 0); } - noreg_gp = ia32_new_NoReg_gp(env_cg); if (new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) { build_address(am, op2, 0); @@ -792,7 +797,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, if (mode_is_float(mode)) { new_op2 = ia32_new_NoReg_vfp(env_cg); } else { - new_op2 = noreg_gp; + new_op2 = noreg_GP; } am->op_type = ia32_AddrModeS; } else if (commutative && (new_op2 == NULL || use_am_and_immediates) && @@ -804,7 +809,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, if (mode_is_float(mode)) { noreg = ia32_new_NoReg_vfp(env_cg); } else { - noreg = noreg_gp; + noreg = noreg_GP; } if (new_op2 != NULL) { @@ -816,6 +821,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } am->op_type = ia32_AddrModeS; } else { + ir_mode *mode; am->op_type = ia32_Normal; if (flags & match_try_am) { @@ -824,24 +830,41 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, return; } - new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); - if (new_op2 == NULL) - new_op2 = be_transform_node(op2); - am->ls_mode = - (flags & match_mode_neutral ? mode_Iu : get_irn_mode(op2)); + mode = get_irn_mode(op2); + if (flags & match_upconv_32 && get_mode_size_bits(mode) != 32) { + new_op1 = (op1 == NULL ? NULL : create_upconv(op1, NULL)); + if (new_op2 == NULL) + new_op2 = create_upconv(op2, NULL); + am->ls_mode = mode_Iu; + } else { + new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); + if (new_op2 == NULL) + new_op2 = be_transform_node(op2); + am->ls_mode = (flags & match_mode_neutral) ? mode_Iu : mode; + } } if (addr->base == NULL) - addr->base = noreg_gp; + addr->base = noreg_GP; if (addr->index == NULL) - addr->index = noreg_gp; + addr->index = noreg_GP; if (addr->mem == NULL) - addr->mem = new_NoMem(); + addr->mem = nomem; am->new_op1 = new_op1; am->new_op2 = new_op2; am->commutative = commutative; } +/** + * "Fixes" a node that uses address mode by turning it into mode_T + * and returning a pn_ia32_res Proj. + * + * @param node the node + * @param am its address mode + * + * @return a Proj(pn_ia32_res) if a memory address mode is used, + * node else + */ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) { ir_mode *mode; @@ -858,7 +881,7 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) if (mode != mode_T) { set_irn_mode(node, mode_T); - return new_rd_Proj(NULL, current_ir_graph, get_nodes_block(node), node, mode, pn_ia32_res); + return new_rd_Proj(NULL, get_nodes_block(node), node, mode, pn_ia32_res); } else { return node; } @@ -900,10 +923,13 @@ static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2, return new_node; } +/** + * Generic names for the inputs of an ia32 binary op. + */ enum { - n_ia32_l_binop_left, - n_ia32_l_binop_right, - n_ia32_l_binop_eflags + n_ia32_l_binop_left, /**< ia32 left input */ + n_ia32_l_binop_right, /**< ia32 right input */ + n_ia32_l_binop_eflags /**< ia32 eflags input */ }; COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left) COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right) @@ -938,7 +964,7 @@ static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, block = be_transform_node(src_block); new_eflags = be_transform_node(eflags); new_node = func(dbgi, block, addr->base, addr->index, addr->mem, - am.new_op1, am.new_op2, new_eflags); + am.new_op1, am.new_op2, new_eflags); set_am_attributes(new_node, &am); /* we can't use source address mode anymore when using immediates */ if (!(flags & match_am_and_immediates) && @@ -975,7 +1001,7 @@ static ir_node *get_fpcw(void) static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, construct_binop_float_func *func) { - ir_mode *mode = get_irn_mode(node); + ir_mode *mode = get_irn_mode(node); dbg_info *dbgi; ir_node *block, *new_block, *new_node; ia32_address_mode_t am; @@ -985,6 +1011,10 @@ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, * variants */ match_flags_t flags = match_commutative; + /* happens for div nodes... */ + if (mode == mode_T) + mode = get_divop_resmod(node); + /* cannot use address mode with long double on x87 */ if (get_mode_size_bits(mode) <= 64) flags |= match_am; @@ -995,7 +1025,7 @@ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, dbgi = get_irn_dbg_info(node); new_block = be_transform_node(block); new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem, - am.new_op1, am.new_op2, get_fpcw()); + am.new_op1, am.new_op2, get_fpcw()); set_am_attributes(new_node, &am); attr = get_ia32_x87_attr(new_node); @@ -1100,14 +1130,14 @@ static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, base = addr->base; if (base == NULL) { - base = ia32_new_NoReg_gp(env_cg); + base = noreg_GP; } else { base = be_transform_node(base); } index = addr->index; if (index == NULL) { - index = ia32_new_NoReg_gp(env_cg); + index = noreg_GP; } else { index = be_transform_node(index); } @@ -1174,7 +1204,7 @@ static ir_node *gen_Add(ir_node *node) /* a constant? */ if (addr.base == NULL && addr.index == NULL) { new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent, - addr.symconst_sign, addr.offset); + addr.symconst_sign, 0, addr.offset); be_dep_on_frame(new_node); SET_IA32_ORIG_NODE(new_node, node); return new_node; @@ -1265,14 +1295,16 @@ static ir_node *gen_Mulh(ir_node *node) ir_node *new_node; ir_node *proj_res_high; + if (get_mode_size_bits(mode) != 32) { + panic("Mulh without 32bit size not supported in ia32 backend (%+F)", node); + } + if (mode_is_signed(mode)) { new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am); - proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node, - mode_Iu, pn_ia32_IMul1OP_res_high); + proj_res_high = new_rd_Proj(dbgi, new_block, new_node, mode_Iu, pn_ia32_IMul1OP_res_high); } else { new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am); - proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node, - mode_Iu, pn_ia32_Mul_res_high); + proj_res_high = new_rd_Proj(dbgi, new_block, new_node, mode_Iu, pn_ia32_Mul_res_high); } return proj_res_high; } @@ -1376,7 +1408,7 @@ static ir_node *gen_Sub(ir_node *node) | match_am | match_immediate); } -static ir_node *transform_AM_mem(ir_graph *const irg, ir_node *const block, +static ir_node *transform_AM_mem(ir_node *const block, ir_node *const src_val, ir_node *const src_mem, ir_node *const am_mem) @@ -1412,16 +1444,24 @@ static ir_node *transform_AM_mem(ir_graph *const irg, ir_node *const block, ins[n++] = am_mem; - return new_r_Sync(irg, block, n, ins); + return new_r_Sync(block, n, ins); } else { ir_node *ins[2]; ins[0] = be_transform_node(src_mem); ins[1] = am_mem; - return new_r_Sync(irg, block, 2, ins); + return new_r_Sync(block, 2, ins); } } +/** + * Create a 32bit to 64bit signed extension. + * + * @param dbgi debug info + * @param block the block where node nodes should be placed + * @param val the value to extend + * @param orig the original node + */ static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block, ir_node *val, const ir_node *orig) { @@ -1433,7 +1473,7 @@ static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block, be_dep_on_frame(pval); res = new_bd_ia32_Cltd(dbgi, block, val, pval); } else { - ir_node *imm31 = create_Immediate(NULL, 0, 31); + ir_node *imm31 = ia32_create_Immediate(NULL, 0, 31); res = new_bd_ia32_Sar(dbgi, block, val, imm31); } SET_IA32_ORIG_NODE(res, orig); @@ -1483,19 +1523,19 @@ static ir_node *create_Div(ir_node *node) panic("invalid divmod node %+F", node); } - match_arguments(&am, block, op1, op2, NULL, match_am); + match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv_32); /* Beware: We don't need a Sync, if the memory predecessor of the Div node is the memory of the consumed address. We can have only the second op as address in Div nodes, so check only op2. */ - new_mem = transform_AM_mem(current_ir_graph, block, op2, mem, addr->mem); + new_mem = transform_AM_mem(block, op2, mem, addr->mem); if (mode_is_signed(mode)) { sign_extension = create_sex_32_64(dbgi, new_block, am.new_op1, node); new_node = new_bd_ia32_IDiv(dbgi, new_block, addr->base, addr->index, new_mem, am.new_op2, am.new_op1, sign_extension); } else { - sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0); + sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0, 0); be_dep_on_frame(sign_extension); new_node = new_bd_ia32_Div(dbgi, new_block, addr->base, @@ -1513,17 +1553,25 @@ static ir_node *create_Div(ir_node *node) return new_node; } - +/** + * Generates an ia32 Mod. + */ static ir_node *gen_Mod(ir_node *node) { return create_Div(node); } +/** + * Generates an ia32 Div. + */ static ir_node *gen_Div(ir_node *node) { return create_Div(node); } +/** + * Generates an ia32 DivMod. + */ static ir_node *gen_DivMod(ir_node *node) { return create_Div(node); @@ -1731,11 +1779,9 @@ static ir_node *gen_Minus(ir_node *node) /* TODO: non-optimal... if we have many xXors, then we should * rather create a load for the const and use that instead of * several AM nodes... */ - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg); - ir_node *nomem = new_NoMem(); - new_node = new_bd_ia32_xXor(dbgi, block, noreg_gp, noreg_gp, + new_node = new_bd_ia32_xXor(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, noreg_xmm); size = get_mode_size_bits(mode); @@ -1785,8 +1831,6 @@ static ir_node *gen_Abs(ir_node *node) ir_node *op = get_Abs_op(node); dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *new_op; ir_node *new_node; int size; @@ -1797,7 +1841,7 @@ static ir_node *gen_Abs(ir_node *node) if (ia32_cg_config.use_sse2) { ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg); - new_node = new_bd_ia32_xAnd(dbgi, new_block, noreg_gp, noreg_gp, + new_node = new_bd_ia32_xAnd(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, noreg_fp); size = get_mode_size_bits(mode); @@ -1824,11 +1868,11 @@ static ir_node *gen_Abs(ir_node *node) sign_extension = create_sex_32_64(dbgi, new_block, new_op, node); - xor = new_bd_ia32_Xor(dbgi, new_block, noreg_gp, noreg_gp, + xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, sign_extension); SET_IA32_ORIG_NODE(xor, node); - new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_gp, noreg_gp, + new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, xor, sign_extension); SET_IA32_ORIG_NODE(new_node, node); } @@ -1860,8 +1904,6 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) { ir_node *flags; ir_node *new_op; - ir_node *noreg; - ir_node *nomem; ir_node *new_block; dbg_info *dbgi; @@ -1916,10 +1958,8 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) dbgi = get_irn_dbg_info(node); new_block = be_transform_node(get_nodes_block(node)); new_op = be_transform_node(node); - noreg = ia32_new_NoReg_gp(env_cg); - nomem = new_NoMem(); - flags = new_bd_ia32_Test(dbgi, new_block, noreg, noreg, nomem, new_op, - new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0); + flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, + new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0); *pnc_out = pn_Cmp_Lg; return flags; } @@ -1939,7 +1979,6 @@ static ir_node *gen_Load(ir_node *node) ir_node *base; ir_node *index; dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_mode *mode = get_Load_mode(node); ir_mode *res_mode; ir_node *new_node; @@ -1952,13 +1991,13 @@ static ir_node *gen_Load(ir_node *node) index = addr.index; if (base == NULL) { - base = noreg; + base = noreg_GP; } else { base = be_transform_node(base); } if (index == NULL) { - index = noreg; + index = noreg_GP; } else { index = be_transform_node(index); } @@ -1979,7 +2018,7 @@ static ir_node *gen_Load(ir_node *node) /* create a conv node with address mode for smaller modes */ if (get_mode_size_bits(mode) < 32) { new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index, - new_mem, noreg, mode); + new_mem, noreg_GP, mode); } else { new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem); } @@ -2049,7 +2088,6 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, { ir_node *src_block = get_nodes_block(node); ir_node *block; - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); dbg_info *dbgi; ir_node *new_mem; ir_node *new_node; @@ -2074,15 +2112,15 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, } if (addr->base == NULL) - addr->base = noreg_gp; + addr->base = noreg_GP; if (addr->index == NULL) - addr->index = noreg_gp; + addr->index = noreg_GP; if (addr->mem == NULL) - addr->mem = new_NoMem(); + addr->mem = nomem; dbgi = get_irn_dbg_info(node); block = be_transform_node(src_block); - new_mem = transform_AM_mem(current_ir_graph, block, am.am_node, mem, addr->mem); + new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem); if (get_mode_size_bits(mode) == 8) { new_node = func8bit(dbgi, block, addr->base, addr->index, new_mem, new_op); @@ -2122,7 +2160,7 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, dbgi = get_irn_dbg_info(node); block = be_transform_node(src_block); - new_mem = transform_AM_mem(current_ir_graph, block, am.am_node, mem, addr->mem); + new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem); new_node = func(dbgi, block, addr->base, addr->index, new_mem); set_address(new_node, addr); set_ia32_op_type(new_node, ia32_AddrModeD); @@ -2386,7 +2424,7 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) (get_tarval_sub_bits(tv, ofs + 1) << 8) | (get_tarval_sub_bits(tv, ofs + 2) << 16) | (get_tarval_sub_bits(tv, ofs + 3) << 24); - ir_node *imm = create_Immediate(NULL, 0, val); + ir_node *imm = ia32_create_Immediate(NULL, 0, val); ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base, addr.index, addr.mem, imm); @@ -2406,7 +2444,7 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) } while (size != 0); if (i > 1) { - return new_rd_Sync(dbgi, current_ir_graph, new_block, i, ins); + return new_rd_Sync(dbgi, new_block, i, ins); } else { return ins[0]; } @@ -2415,7 +2453,7 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) /** * Generate a vfist or vfisttp instruction. */ -static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, +static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node **fist) { ir_node *new_node; @@ -2423,12 +2461,11 @@ static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node if (ia32_cg_config.use_fisttp) { /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied if other users exists */ - const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp]; ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val); - ir_node *value = new_r_Proj(irg, block, vfisttp, mode_E, pn_ia32_vfisttp_res); - be_new_Keep(reg_class, irg, block, 1, &value); + ir_node *value = new_r_Proj(block, vfisttp, mode_E, pn_ia32_vfisttp_res); + be_new_Keep(block, 1, &value); - new_node = new_r_Proj(irg, block, vfisttp, mode_M, pn_ia32_vfisttp_M); + new_node = new_r_Proj(block, vfisttp, mode_M, pn_ia32_vfisttp_M); *fist = vfisttp; } else { ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); @@ -2453,7 +2490,6 @@ static ir_node *gen_general_Store(ir_node *node) ir_node *ptr = get_Store_ptr(node); ir_node *mem = get_Store_mem(node); dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_node *new_val, *new_node, *store; ia32_address_t addr; @@ -2467,13 +2503,13 @@ static ir_node *gen_general_Store(ir_node *node) ia32_create_address_mode(&addr, ptr, 0); if (addr.base == NULL) { - addr.base = noreg; + addr.base = noreg_GP; } else { addr.base = be_transform_node(addr.base); } if (addr.index == NULL) { - addr.index = noreg; + addr.index = noreg_GP; } else { addr.index = be_transform_node(addr.index); } @@ -2511,7 +2547,7 @@ static ir_node *gen_general_Store(ir_node *node) val = op; } new_val = be_transform_node(val); - new_node = gen_vfist(dbgi, current_ir_graph, new_block, addr.base, addr.index, addr.mem, new_val, &store); + new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, &store); } else { new_val = create_immediate_or_transform(val, 0); assert(mode != mode_b); @@ -2568,9 +2604,9 @@ static ir_node *create_Switch(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *sel = get_Cond_selector(node); ir_node *new_sel = be_transform_node(sel); - int switch_min = INT_MAX; - int switch_max = INT_MIN; - long default_pn = get_Cond_defaultProj(node); + long switch_min = LONG_MAX; + long switch_max = LONG_MIN; + long default_pn = get_Cond_default_proj(node); ir_node *new_node; const ir_edge_t *edge; @@ -2589,15 +2625,13 @@ static ir_node *create_Switch(ir_node *node) switch_max = pn; } - if ((unsigned) (switch_max - switch_min) > 256000) { - panic("Size of switch %+F bigger than 256000", node); + if ((unsigned long) (switch_max - switch_min) > 128000) { + panic("Size of switch %+F bigger than 128000", node); } if (switch_min != 0) { - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - /* if smallest switch case is not 0 we need an additional sub */ - new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg); + new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg_GP); add_ia32_am_offs_int(new_sel, -switch_min); set_ia32_op_type(new_sel, ia32_AddrModeS); @@ -2637,6 +2671,9 @@ static ir_node *gen_Cond(ir_node *node) return new_node; } +/** + * Transform a be_Copy. + */ static ir_node *gen_be_Copy(ir_node *node) { ir_node *new_node = be_duplicate_node(node); @@ -2942,8 +2979,6 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, ir_node *flags, pn_Cmp pnc, ir_node *orig_node, int ins_permuted) { - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_mode *mode = get_irn_mode(orig_node); ir_node *new_node; @@ -2952,7 +2987,7 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, /* we might need to conv the result up */ if (get_mode_size_bits(mode) > 8) { - new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg, noreg, + new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, mode_Bu); SET_IA32_ORIG_NODE(new_node, orig_node); } @@ -2965,10 +3000,8 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, */ static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) { - ir_graph *irg = current_ir_graph; ir_mode *mode = get_irn_mode(psi); - ir_node *nomem = new_NoMem(); - ir_node *new_node, *sub, *sbb, *eflags, *block, *noreg; + ir_node *new_node, *sub, *sbb, *eflags, *block; dbg_info *dbgi; @@ -2983,15 +3016,14 @@ static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) } else { sub = new_node; set_irn_mode(sub, mode_T); - new_node = new_rd_Proj(NULL, irg, block, sub, mode, pn_ia32_res); + new_node = new_rd_Proj(NULL, block, sub, mode, pn_ia32_res); } - eflags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags); + eflags = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_Sub_flags); dbgi = get_irn_dbg_info(psi); sbb = new_bd_ia32_Sbb0(dbgi, block, eflags); - noreg = ia32_new_NoReg_gp(env_cg); - new_node = new_bd_ia32_And(dbgi, block, noreg, noreg, nomem, new_node, sbb); + new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, sbb); set_ia32_commutative(new_node); return new_node; } @@ -3056,7 +3088,7 @@ static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **ne } /** - * Transforms a Mux node into CMov. + * Transforms a Mux node into some code sequence. * * @return The transformed node. */ @@ -3107,14 +3139,12 @@ static ir_node *gen_Mux(ir_node *node) } if (is_Const(mux_true) && is_Const(mux_false)) { ia32_address_mode_t am; - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *load; ir_mode *new_mode; unsigned scale; flags = get_flags_node(cond, &pnc); - new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0); + new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_permuted=*/0); if (ia32_cg_config.use_sse2) { /* cannot load from different mode on SSE */ @@ -3148,14 +3178,14 @@ static ir_node *gen_Mux(ir_node *node) case 16: /* arg, shift 16 NOT supported */ scale = 3; - new_node = new_bd_ia32_Add(dbgi, new_block, noreg, noreg, nomem, new_node, new_node); + new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, new_node); break; default: panic("Unsupported constant size"); } am.ls_mode = new_mode; - am.addr.base = noreg; + am.addr.base = noreg_GP; am.addr.index = new_node; am.addr.mem = nomem; am.addr.offset = 0; @@ -3177,7 +3207,7 @@ static ir_node *gen_Mux(ir_node *node) load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode); set_am_attributes(load, &am); - return new_rd_Proj(NULL, current_ir_graph, block, load, mode_vfp, pn_ia32_res); + return new_rd_Proj(NULL, block, load, mode_vfp, pn_ia32_res); } panic("cannot transform floating point Mux"); @@ -3235,14 +3265,12 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op = get_Conv_op(node); ir_node *new_op = be_transform_node(op); - ia32_code_gen_t *cg = env_cg; ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(cg); ir_mode *mode = get_irn_mode(node); ir_node *fist, *load, *mem; - mem = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, new_NoMem(), new_op, &fist); + mem = gen_vfist(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist); set_irn_pinned(fist, op_pin_state_floats); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); @@ -3258,7 +3286,7 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) SET_IA32_ORIG_NODE(fist, node); /* do a Load */ - load = new_bd_ia32_Load(dbgi, block, get_irg_frame(irg), noreg, mem); + load = new_bd_ia32_Load(dbgi, block, get_irg_frame(irg), noreg_GP, mem); set_irn_pinned(load, op_pin_state_floats); set_ia32_use_frame(load); @@ -3273,7 +3301,7 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) } SET_IA32_ORIG_NODE(load, node); - return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res); + return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res); } /** @@ -3282,25 +3310,23 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) { ir_node *block = get_nodes_block(node); - ir_graph *irg = current_ir_graph; + ir_graph *irg = get_Block_irg(block); dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *frame = get_irg_frame(irg); ir_node *store, *load; ir_node *new_node; - store = new_bd_ia32_vfst(dbgi, block, frame, noreg, nomem, node, tgt_mode); + store = new_bd_ia32_vfst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode); set_ia32_use_frame(store); set_ia32_op_type(store, ia32_AddrModeD); SET_IA32_ORIG_NODE(store, node); - load = new_bd_ia32_vfld(dbgi, block, frame, noreg, store, tgt_mode); + load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store, tgt_mode); set_ia32_use_frame(load); set_ia32_op_type(load, ia32_AddrModeS); SET_IA32_ORIG_NODE(load, node); - new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res); + new_node = new_r_Proj(block, load, mode_E, pn_ia32_vfld_res); return new_node; } @@ -3321,12 +3347,10 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { ir_node *src_block = get_nodes_block(node); ir_node *block = be_transform_node(src_block); - ir_graph *irg = current_ir_graph; + ir_graph *irg = get_Block_irg(block); dbg_info *dbgi = get_irn_dbg_info(node); ir_node *op = get_Conv_op(node); ir_node *new_op = NULL; - ir_node *noreg; - ir_node *nomem; ir_mode *mode; ir_mode *store_mode; ir_node *fild; @@ -3341,10 +3365,8 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) if (am.op_type == ia32_AddrModeS) { ia32_address_t *addr = &am.addr; - fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, - addr->mem); - new_node = new_r_Proj(irg, block, fild, mode_vfp, - pn_ia32_vfild_res); + fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem); + new_node = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res); set_am_attributes(fild, &am); SET_IA32_ORIG_NODE(fild, node); @@ -3358,14 +3380,12 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) new_op = be_transform_node(op); } - noreg = ia32_new_NoReg_gp(env_cg); - nomem = new_NoMem(); - mode = get_irn_mode(op); + mode = get_irn_mode(op); /* first convert to 32 bit signed if necessary */ if (get_mode_size_bits(src_mode) < 32) { if (!upper_bits_clean(new_op, src_mode)) { - new_op = create_Conv_I2I(dbgi, block, noreg, noreg, nomem, new_op, src_mode); + new_op = create_Conv_I2I(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, src_mode); SET_IA32_ORIG_NODE(new_op, node); } mode = mode_Is; @@ -3374,8 +3394,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) assert(get_mode_size_bits(mode) == 32); /* do a store */ - store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg, nomem, - new_op); + store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op); set_ia32_use_frame(store); set_ia32_op_type(store, ia32_AddrModeD); @@ -3385,10 +3404,10 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) if (!mode_is_signed(mode)) { ir_node *in[2]; /* store a zero */ - ir_node *zero_const = create_Immediate(NULL, 0, 0); + ir_node *zero_const = ia32_create_Immediate(NULL, 0, 0); ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), - noreg, nomem, zero_const); + noreg_GP, nomem, zero_const); set_ia32_use_frame(zero_store); set_ia32_op_type(zero_store, ia32_AddrModeD); @@ -3398,20 +3417,20 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) in[0] = zero_store; in[1] = store; - store = new_rd_Sync(dbgi, irg, block, 2, in); + store = new_rd_Sync(dbgi, block, 2, in); store_mode = mode_Ls; } else { store_mode = mode_Is; } /* do a fild */ - fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg, store); + fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store); set_ia32_use_frame(fild); set_ia32_op_type(fild, ia32_AddrModeS); set_ia32_ls_mode(fild, store_mode); - new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); + new_node = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res); return new_node; } @@ -3483,17 +3502,14 @@ static ir_node *gen_Conv(ir_node *node) ir_mode *tgt_mode = get_irn_mode(node); int src_bits = get_mode_size_bits(src_mode); int tgt_bits = get_mode_size_bits(tgt_mode); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *res = NULL; assert(!mode_is_int(src_mode) || src_bits <= 32); assert(!mode_is_int(tgt_mode) || tgt_bits <= 32); + /* modeB -> X should already be lowered by the lower_mode_b pass */ if (src_mode == mode_b) { - assert(mode_is_int(tgt_mode) || mode_is_reference(tgt_mode)); - /* nothing to do, we already model bools as 0/1 ints */ - return be_transform_node(op); + panic("ConvB not lowered %+F", node); } if (src_mode == tgt_mode) { @@ -3514,23 +3530,36 @@ static ir_node *gen_Conv(ir_node *node) new_op = be_transform_node(op); /* we convert from float ... */ if (mode_is_float(tgt_mode)) { +#if 0 + /* Matze: I'm a bit unsure what the following is for? seems wrong + * to me... */ if (src_mode == mode_E && tgt_mode == mode_D && !get_Conv_strict(node)) { DB((dbg, LEVEL_1, "killed Conv(mode, mode) ...")); return new_op; } +#endif /* ... to float */ if (ia32_cg_config.use_sse2) { DB((dbg, LEVEL_1, "create Conv(float, float) ...")); - res = new_bd_ia32_Conv_FP2FP(dbgi, new_block, noreg, noreg, + res = new_bd_ia32_Conv_FP2FP(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op); set_ia32_ls_mode(res, tgt_mode); } else { if (get_Conv_strict(node)) { - res = gen_x87_strict_conv(tgt_mode, new_op); - SET_IA32_ORIG_NODE(get_Proj_pred(res), node); - return res; + /* if fp_no_float_fold is not set then we assume that we + * don't have any float operations in a non + * mode_float_arithmetic mode and can skip strict upconvs */ + if (src_bits < tgt_bits + && !(get_irg_fp_model(current_ir_graph) & fp_no_float_fold)) { + DB((dbg, LEVEL_1, "killed Conv(float, float) ...")); + return new_op; + } else { + res = gen_x87_strict_conv(tgt_mode, new_op); + SET_IA32_ORIG_NODE(get_Proj_pred(res), node); + return res; + } } DB((dbg, LEVEL_1, "killed Conv(float, float) ...")); return new_op; @@ -3539,7 +3568,7 @@ static ir_node *gen_Conv(ir_node *node) /* ... to int */ DB((dbg, LEVEL_1, "create Conv(float, int) ...")); if (ia32_cg_config.use_sse2) { - res = new_bd_ia32_Conv_FP2I(dbgi, new_block, noreg, noreg, + res = new_bd_ia32_Conv_FP2I(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op); set_ia32_ls_mode(res, src_mode); } else { @@ -3553,28 +3582,19 @@ static ir_node *gen_Conv(ir_node *node) DB((dbg, LEVEL_1, "create Conv(int, float) ...")); if (ia32_cg_config.use_sse2) { new_op = be_transform_node(op); - res = new_bd_ia32_Conv_I2FP(dbgi, new_block, noreg, noreg, + res = new_bd_ia32_Conv_I2FP(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op); set_ia32_ls_mode(res, tgt_mode); } else { + unsigned int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0); + unsigned float_mantissa = tarval_ieee754_get_mantissa_size(tgt_mode); res = gen_x87_gp_to_fp(node, src_mode); - if (get_Conv_strict(node)) { - /* The strict-Conv is only necessary, if the int mode has more bits - * than the float mantissa */ - size_t int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0); - size_t float_mantissa; - /* FIXME There is no way to get the mantissa size of a mode */ - switch (get_mode_size_bits(tgt_mode)) { - case 32: float_mantissa = 23 + 1; break; // + 1 for implicit 1 - case 64: float_mantissa = 52 + 1; break; - case 80: - case 96: float_mantissa = 64; break; - default: float_mantissa = 0; break; - } - if (float_mantissa < int_mantissa) { - res = gen_x87_strict_conv(tgt_mode, res); - SET_IA32_ORIG_NODE(get_Proj_pred(res), node); - } + + /* we need a strict-Conv, if the int mode has more bits than the + * float mantissa */ + if (float_mantissa < int_mantissa) { + res = gen_x87_strict_conv(tgt_mode, res); + SET_IA32_ORIG_NODE(get_Proj_pred(res), node); } return res; } @@ -3618,10 +3638,9 @@ static ir_node *gen_be_FrameAddr(ir_node *node) ir_node *op = be_get_FrameAddr_frame(node); ir_node *new_op = be_transform_node(op); dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_node *new_node; - new_node = new_bd_ia32_Lea(dbgi, block, new_op, noreg); + new_node = new_bd_ia32_Lea(dbgi, block, new_op, noreg_GP); set_ia32_frame_ent(new_node, arch_get_frame_entity(node)); set_ia32_use_frame(new_node); @@ -3646,7 +3665,6 @@ static ir_node *gen_be_Return(ir_node *node) ir_mode *mode; ir_node *frame, *sse_store, *fld, *mproj, *barrier; ir_node *new_barrier, *new_ret_val, *new_ret_mem; - ir_node *noreg; ir_node **in; int pn_ret_val, pn_ret_mem, arity, i; @@ -3687,22 +3705,20 @@ static ir_node *gen_be_Return(ir_node *node) dbgi = get_irn_dbg_info(barrier); block = be_transform_node(get_nodes_block(barrier)); - noreg = ia32_new_NoReg_gp(env_cg); - /* store xmm0 onto stack */ - sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg, + sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg_GP, new_ret_mem, new_ret_val); set_ia32_ls_mode(sse_store, mode); set_ia32_op_type(sse_store, ia32_AddrModeD); set_ia32_use_frame(sse_store); /* load into x87 register */ - fld = new_bd_ia32_vfld(dbgi, block, frame, noreg, sse_store, mode); + fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, sse_store, mode); set_ia32_op_type(fld, ia32_AddrModeS); set_ia32_use_frame(fld); - mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M); - fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res); + mproj = new_r_Proj(block, fld, mode_M, pn_ia32_vfld_M); + fld = new_r_Proj(block, fld, mode_vfp, pn_ia32_vfld_res); /* create a new barrier */ arity = get_irn_arity(barrier); @@ -3761,6 +3777,7 @@ static ir_node *gen_be_SubSP(ir_node *node) */ static ir_node *gen_Phi(ir_node *node) { + const arch_register_req_t *req; ir_node *block = be_transform_node(get_nodes_block(node)); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); @@ -3772,12 +3789,17 @@ static ir_node *gen_Phi(ir_node *node) assert(get_mode_size_bits(mode) <= 32); /* all integer operations are on 32bit registers now */ mode = mode_Iu; + req = ia32_reg_classes[CLASS_ia32_gp].class_req; } else if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) { mode = mode_xmm; + req = ia32_reg_classes[CLASS_ia32_xmm].class_req; } else { mode = mode_vfp; + req = ia32_reg_classes[CLASS_ia32_vfp].class_req; } + } else { + req = arch_no_register_req; } /* phi nodes allow loops, so we use the old arguments for now @@ -3787,11 +3809,26 @@ static ir_node *gen_Phi(ir_node *node) copy_node_attr(node, phi); be_duplicate_deps(node, phi); + arch_set_out_register_req(phi, 0, req); + be_enqueue_preds(node); return phi; } +static ir_node *gen_Jmp(ir_node *node) +{ + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_node; + + new_node = new_bd_ia32_Jmp(dbgi, new_block); + SET_IA32_ORIG_NODE(new_node, node); + + return new_node; +} + /** * Transform IJmp */ @@ -3831,7 +3868,6 @@ static ir_node *gen_Bound(ir_node *node) if (is_Const_0(lower)) { /* typical case for Java */ ir_node *sub, *res, *flags, *block; - ir_graph *irg = current_ir_graph; res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node), new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate); @@ -3840,11 +3876,11 @@ static ir_node *gen_Bound(ir_node *node) if (! is_Proj(res)) { sub = res; set_irn_mode(sub, mode_T); - res = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_res); + res = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_res); } else { sub = get_Proj_pred(res); } - flags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags); + flags = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_Sub_flags); new_node = new_bd_ia32_Jcc(dbgi, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned); SET_IA32_ORIG_NODE(new_node, node); } else { @@ -4018,8 +4054,6 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *frame = get_irg_frame(irg); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low); ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high); ir_node *new_val_low = be_transform_node(val_low); @@ -4033,9 +4067,9 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) } /* do a store */ - store_low = new_bd_ia32_Store(dbgi, block, frame, noreg, nomem, + store_low = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem, new_val_low); - store_high = new_bd_ia32_Store(dbgi, block, frame, noreg, nomem, + store_high = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem, new_val_high); SET_IA32_ORIG_NODE(store_low, node); SET_IA32_ORIG_NODE(store_high, node); @@ -4050,10 +4084,10 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) in[0] = store_low; in[1] = store_high; - sync = new_rd_Sync(dbgi, irg, block, 2, in); + sync = new_rd_Sync(dbgi, block, 2, in); /* do a fild */ - fild = new_bd_ia32_vfild(dbgi, block, frame, noreg, sync); + fild = new_bd_ia32_vfild(dbgi, block, frame, noreg_GP, sync); set_ia32_use_frame(fild); set_ia32_op_type(fild, ia32_AddrModeS); @@ -4061,15 +4095,15 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) SET_IA32_ORIG_NODE(fild, node); - res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); + res = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res); if (! mode_is_signed(get_irn_mode(val_high))) { ia32_address_mode_t am; - ir_node *count = create_Immediate(NULL, 0, 31); + ir_node *count = ia32_create_Immediate(NULL, 0, 31); ir_node *fadd; - am.addr.base = ia32_new_NoReg_gp(env_cg); + am.addr.base = noreg_GP; am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count); am.addr.mem = nomem; am.addr.offset = 0; @@ -4092,7 +4126,7 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) set_am_attributes(fadd, &am); set_irn_mode(fadd, mode_T); - res = new_rd_Proj(NULL, irg, block, fadd, mode_vfp, pn_ia32_res); + res = new_rd_Proj(NULL, block, fadd, mode_vfp, pn_ia32_res); } return res; } @@ -4101,16 +4135,14 @@ static ir_node *gen_ia32_l_FloattoLL(ir_node *node) { ir_node *src_block = get_nodes_block(node); ir_node *block = be_transform_node(src_block); - ir_graph *irg = current_ir_graph; + ir_graph *irg = get_Block_irg(block); dbg_info *dbgi = get_irn_dbg_info(node); ir_node *frame = get_irg_frame(irg); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val); ir_node *new_val = be_transform_node(val); ir_node *fist, *mem; - mem = gen_vfist(dbgi, irg, block, frame, noreg, nomem, new_val, &fist); + mem = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val, &fist); SET_IA32_ORIG_NODE(fist, node); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); @@ -4130,19 +4162,18 @@ static ir_node *bad_transform(ir_node *node) static ir_node *gen_Proj_l_FloattoLL(ir_node *node) { - ir_graph *irg = current_ir_graph; ir_node *block = be_transform_node(get_nodes_block(node)); + ir_graph *irg = get_Block_irg(block); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); ir_node *frame = get_irg_frame(irg); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); dbg_info *dbgi = get_irn_dbg_info(node); long pn = get_Proj_proj(node); ir_node *load; ir_node *proj; ia32_attr_t *attr; - load = new_bd_ia32_Load(dbgi, block, frame, noreg, new_pred); + load = new_bd_ia32_Load(dbgi, block, frame, noreg_GP, new_pred); SET_IA32_ORIG_NODE(load, node); set_ia32_use_frame(load); set_ia32_op_type(load, ia32_AddrModeS); @@ -4158,7 +4189,7 @@ static ir_node *gen_Proj_l_FloattoLL(ir_node *node) assert(pn == pn_ia32_l_FloattoLL_res_low); } - proj = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res); + proj = new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res); return proj; } @@ -4171,20 +4202,19 @@ static ir_node *gen_Proj_be_AddSP(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); if (proj == pn_be_AddSP_sp) { - ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, + ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_SubSP_stack); arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); return res; } else if (proj == pn_be_AddSP_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_SubSP_addr); } else if (proj == pn_be_AddSP_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_SubSP_M); } panic("No idea how to transform proj->AddSP"); @@ -4198,17 +4228,16 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); if (proj == pn_be_SubSP_sp) { - ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, + ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_AddSP_stack); arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); return res; } else if (proj == pn_be_SubSP_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_AddSP_M); } panic("No idea how to transform proj->SubSP"); @@ -4222,7 +4251,6 @@ static ir_node *gen_Proj_Load(ir_node *node) ir_node *new_pred; ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); @@ -4232,12 +4260,13 @@ static ir_node *gen_Proj_Load(ir_node *node) */ if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) { ir_node *res; + ir_node *old_block = get_nodes_block(node); /* this is needed, because sometimes we have loops that are only reachable through the ProjM */ be_enqueue_preds(node); /* do it in 2 steps, to silence firm verifier */ - res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M); + res = new_rd_Proj(dbgi, old_block, pred, mode_M, pn_Load_M); set_Proj_proj(res, pn_ia32_mem); return res; } @@ -4247,15 +4276,15 @@ static ir_node *gen_Proj_Load(ir_node *node) if (is_ia32_Load(new_pred)) { switch (proj) { case pn_Load_res: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Load_res); case pn_Load_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Load_M); case pn_Load_X_regular: - return new_rd_Jmp(dbgi, irg, block); + return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Load_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Load_X_exc); default: break; } @@ -4263,37 +4292,37 @@ static ir_node *gen_Proj_Load(ir_node *node) is_ia32_Conv_I2I8Bit(new_pred)) { set_irn_mode(new_pred, mode_T); if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_res); } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_mem); } } else if (is_ia32_xLoad(new_pred)) { switch (proj) { case pn_Load_res: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res); + return new_rd_Proj(dbgi, block, new_pred, mode_xmm, pn_ia32_xLoad_res); case pn_Load_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_xLoad_M); case pn_Load_X_regular: - return new_rd_Jmp(dbgi, irg, block); + return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); default: break; } } else if (is_ia32_vfld(new_pred)) { switch (proj) { case pn_Load_res: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res); + return new_rd_Proj(dbgi, block, new_pred, mode_vfp, pn_ia32_vfld_res); case pn_Load_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_vfld_M); case pn_Load_X_regular: - return new_rd_Jmp(dbgi, irg, block); + return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_vfld_X_exc); default: break; } @@ -4307,7 +4336,7 @@ static ir_node *gen_Proj_Load(ir_node *node) if (proj != pn_Load_M) { panic("internal error: transformed node not a Load"); } - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1); + return new_rd_Proj(dbgi, block, new_pred, mode_M, 1); } panic("No idea how to transform proj"); @@ -4321,7 +4350,6 @@ static ir_node *gen_Proj_DivMod(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); @@ -4331,14 +4359,14 @@ static ir_node *gen_Proj_DivMod(ir_node *node) case iro_Div: switch (proj) { case pn_Div_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Div_res: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_div_res); case pn_Div_X_regular: - return new_rd_Jmp(dbgi, irg, block); + return new_rd_Jmp(dbgi, block); case pn_Div_X_except: set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4346,12 +4374,12 @@ static ir_node *gen_Proj_DivMod(ir_node *node) case iro_Mod: switch (proj) { case pn_Mod_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Mod_res: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); case pn_Mod_X_except: set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4359,16 +4387,16 @@ static ir_node *gen_Proj_DivMod(ir_node *node) case iro_DivMod: switch (proj) { case pn_DivMod_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M); case pn_DivMod_res_div: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_div_res); case pn_DivMod_res_mod: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); case pn_DivMod_X_regular: - return new_rd_Jmp(dbgi, irg, block); + return new_rd_Jmp(dbgi, block); case pn_DivMod_X_except: set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4388,16 +4416,15 @@ static ir_node *gen_Proj_CopyB(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); switch (proj) { case pn_CopyB_M_regular: if (is_ia32_CopyB_i(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_CopyB_i_M); } else if (is_ia32_CopyB(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_CopyB_M); } break; default: @@ -4415,23 +4442,22 @@ static ir_node *gen_Proj_Quot(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); switch (proj) { case pn_Quot_M: if (is_ia32_xDiv(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_xDiv_M); } else if (is_ia32_vfdiv(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_vfdiv_M); } break; case pn_Quot_res: if (is_ia32_xDiv(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res); + return new_rd_Proj(dbgi, block, new_pred, mode_xmm, pn_ia32_xDiv_res); } else if (is_ia32_vfdiv(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res); + return new_rd_Proj(dbgi, block, new_pred, mode_vfp, pn_ia32_vfdiv_res); } break; case pn_Quot_X_regular: @@ -4446,25 +4472,24 @@ static ir_node *gen_Proj_Quot(ir_node *node) static ir_node *gen_be_Call(ir_node *node) { dbg_info *const dbgi = get_irn_dbg_info(node); - ir_graph *const irg = current_ir_graph; ir_node *const src_block = get_nodes_block(node); ir_node *const block = be_transform_node(src_block); ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem); ir_node *const src_sp = get_irn_n(node, be_pos_Call_sp); ir_node *const sp = be_transform_node(src_sp); ir_node *const src_ptr = get_irn_n(node, be_pos_Call_ptr); - ir_node *const noreg = ia32_new_NoReg_gp(env_cg); ia32_address_mode_t am; ia32_address_t *const addr = &am.addr; ir_node * mem; ir_node * call; int i; ir_node * fpcw; - ir_node * eax = noreg; - ir_node * ecx = noreg; - ir_node * edx = noreg; + ir_node * eax = noreg_GP; + ir_node * ecx = noreg_GP; + ir_node * edx = noreg_GP; unsigned const pop = be_Call_get_pop(node); ir_type *const call_tp = be_Call_get_type(node); + int old_no_pic_adjust; /* Run the x87 simulator if the call returns a float value */ if (get_method_n_ress(call_tp) > 0) { @@ -4479,9 +4504,15 @@ static ir_node *gen_be_Call(ir_node *node) /* We do not want be_Call direct calls */ assert(be_Call_get_entity(node) == NULL); + /* special case for PIC trampoline calls */ + old_no_pic_adjust = no_pic_adjust; + no_pic_adjust = env_cg->birg->main_env->options->pic; + match_arguments(&am, src_block, NULL, src_ptr, src_mem, match_am | match_immediate); + no_pic_adjust = old_no_pic_adjust; + i = get_irn_arity(node) - 1; fpcw = be_transform_node(get_irn_n(node, i--)); for (; i >= be_pos_Call_first_arg; --i) { @@ -4492,14 +4523,14 @@ static ir_node *gen_be_Call(ir_node *node) assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]); switch (*req->limited) { - case 1 << REG_EAX: assert(eax == noreg); eax = reg_parm; break; - case 1 << REG_ECX: assert(ecx == noreg); ecx = reg_parm; break; - case 1 << REG_EDX: assert(edx == noreg); edx = reg_parm; break; + case 1 << REG_EAX: assert(eax == noreg_GP); eax = reg_parm; break; + case 1 << REG_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break; + case 1 << REG_EDX: assert(edx == noreg_GP); edx = reg_parm; break; default: panic("Invalid GP register for register parameter"); } } - mem = transform_AM_mem(irg, block, src_ptr, src_mem, addr->mem); + mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem); call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem, am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp); set_am_attributes(call, &am); @@ -4509,9 +4540,690 @@ static ir_node *gen_be_Call(ir_node *node) set_irn_pinned(call, op_pin_state_pinned); SET_IA32_ORIG_NODE(call, node); + + if (ia32_cg_config.use_sse2) { + /* remember this call for post-processing */ + ARR_APP1(ir_node *, call_list, call); + ARR_APP1(ir_type *, call_types, be_Call_get_type(node)); + } + return call; } +/** + * Transform Builtin trap + */ +static ir_node *gen_trap(ir_node *node) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *mem = be_transform_node(get_Builtin_mem(node)); + + return new_bd_ia32_UD2(dbgi, block, mem); +} + +/** + * Transform Builtin debugbreak + */ +static ir_node *gen_debugbreak(ir_node *node) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *mem = be_transform_node(get_Builtin_mem(node)); + + return new_bd_ia32_Breakpoint(dbgi, block, mem); +} + +/** + * Transform Builtin return_address + */ +static ir_node *gen_return_address(ir_node *node) { + ir_node *param = get_Builtin_param(node, 0); + ir_node *frame = get_Builtin_param(node, 1); + dbg_info *dbgi = get_irn_dbg_info(node); + tarval *tv = get_Const_tarval(param); + unsigned long value = get_tarval_long(tv); + + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *ptr = be_transform_node(frame); + ir_node *load; + + if (value > 0) { + ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block); + ir_node *res = new_bd_ia32_ProduceVal(dbgi, block); + ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value); + } + + /* load the return address from this frame */ + load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem); + + set_irn_pinned(load, get_irn_pinned(node)); + set_ia32_op_type(load, ia32_AddrModeS); + set_ia32_ls_mode(load, mode_Iu); + + set_ia32_am_offs_int(load, 0); + set_ia32_use_frame(load); + set_ia32_frame_ent(load, ia32_get_return_address_entity()); + + if (get_irn_pinned(node) == op_pin_state_floats) { + assert(pn_ia32_xLoad_res == pn_ia32_vfld_res + && pn_ia32_vfld_res == pn_ia32_Load_res + && pn_ia32_Load_res == pn_ia32_res); + arch_irn_add_flags(load, arch_irn_flags_rematerializable); + } + + SET_IA32_ORIG_NODE(load, node); + return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res); +} + +/** + * Transform Builtin frame_address + */ +static ir_node *gen_frame_address(ir_node *node) { + ir_node *param = get_Builtin_param(node, 0); + ir_node *frame = get_Builtin_param(node, 1); + dbg_info *dbgi = get_irn_dbg_info(node); + tarval *tv = get_Const_tarval(param); + unsigned long value = get_tarval_long(tv); + + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *ptr = be_transform_node(frame); + ir_node *load; + ir_entity *ent; + + if (value > 0) { + ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block); + ir_node *res = new_bd_ia32_ProduceVal(dbgi, block); + ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value); + } + + /* load the frame address from this frame */ + load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem); + + set_irn_pinned(load, get_irn_pinned(node)); + set_ia32_op_type(load, ia32_AddrModeS); + set_ia32_ls_mode(load, mode_Iu); + + ent = ia32_get_frame_address_entity(); + if (ent != NULL) { + set_ia32_am_offs_int(load, 0); + set_ia32_use_frame(load); + set_ia32_frame_ent(load, ent); + } else { + /* will fail anyway, but gcc does this: */ + set_ia32_am_offs_int(load, 0); + } + + if (get_irn_pinned(node) == op_pin_state_floats) { + assert(pn_ia32_xLoad_res == pn_ia32_vfld_res + && pn_ia32_vfld_res == pn_ia32_Load_res + && pn_ia32_Load_res == pn_ia32_res); + arch_irn_add_flags(load, arch_irn_flags_rematerializable); + } + + SET_IA32_ORIG_NODE(load, node); + return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res); +} + +/** + * Transform Builtin frame_address + */ +static ir_node *gen_prefetch(ir_node *node) { + dbg_info *dbgi; + ir_node *ptr, *block, *mem, *base, *index; + ir_node *param, *new_node; + long rw, locality; + tarval *tv; + ia32_address_t addr; + + if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) { + /* no prefetch at all, route memory */ + return be_transform_node(get_Builtin_mem(node)); + } + + param = get_Builtin_param(node, 1); + tv = get_Const_tarval(param); + rw = get_tarval_long(tv); + + /* construct load address */ + memset(&addr, 0, sizeof(addr)); + ptr = get_Builtin_param(node, 0); + ia32_create_address_mode(&addr, ptr, 0); + base = addr.base; + index = addr.index; + + if (base == NULL) { + base = noreg_GP; + } else { + base = be_transform_node(base); + } + + if (index == NULL) { + index = noreg_GP; + } else { + index = be_transform_node(index); + } + + dbgi = get_irn_dbg_info(node); + block = be_transform_node(get_nodes_block(node)); + mem = be_transform_node(get_Builtin_mem(node)); + + if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) { + /* we have 3DNow!, this was already checked above */ + new_node = new_bd_ia32_PrefetchW(dbgi, block, base, index, mem); + } else if (ia32_cg_config.use_sse_prefetch) { + /* note: rw == 1 is IGNORED in that case */ + param = get_Builtin_param(node, 2); + tv = get_Const_tarval(param); + locality = get_tarval_long(tv); + + /* SSE style prefetch */ + switch (locality) { + case 0: + new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, index, mem); + break; + case 1: + new_node = new_bd_ia32_Prefetch2(dbgi, block, base, index, mem); + break; + case 2: + new_node = new_bd_ia32_Prefetch1(dbgi, block, base, index, mem); + break; + default: + new_node = new_bd_ia32_Prefetch0(dbgi, block, base, index, mem); + break; + } + } else { + assert(ia32_cg_config.use_3dnow_prefetch); + /* 3DNow! style prefetch */ + new_node = new_bd_ia32_Prefetch(dbgi, block, base, index, mem); + } + + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode_Bu); + set_address(new_node, &addr); + + SET_IA32_ORIG_NODE(new_node, node); + + be_dep_on_frame(new_node); + return new_r_Proj(block, new_node, mode_M, pn_ia32_Prefetch_M); +} + +/** + * Transform bsf like node + */ +static ir_node *gen_unop_AM(ir_node *node, construct_binop_dest_func *func) +{ + ir_node *param = get_Builtin_param(node, 0); + dbg_info *dbgi = get_irn_dbg_info(node); + + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; + ir_node *cnt; + + match_arguments(&am, block, NULL, param, NULL, match_am); + + cnt = func(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2); + set_am_attributes(cnt, &am); + set_ia32_ls_mode(cnt, get_irn_mode(param)); + + SET_IA32_ORIG_NODE(cnt, node); + return fix_mem_proj(cnt, &am); +} + +/** + * Transform builtin ffs. + */ +static ir_node *gen_ffs(ir_node *node) +{ + ir_node *bsf = gen_unop_AM(node, new_bd_ia32_Bsf); + ir_node *real = skip_Proj(bsf); + dbg_info *dbgi = get_irn_dbg_info(real); + ir_node *block = get_nodes_block(real); + ir_node *flag, *set, *conv, *neg, *or; + + /* bsf x */ + if (get_irn_mode(real) != mode_T) { + set_irn_mode(real, mode_T); + bsf = new_r_Proj(block, real, mode_Iu, pn_ia32_res); + } + + flag = new_r_Proj(block, real, mode_b, pn_ia32_flags); + + /* sete */ + set = new_bd_ia32_Set(dbgi, block, flag, pn_Cmp_Eq, 0); + SET_IA32_ORIG_NODE(set, node); + + /* conv to 32bit */ + conv = new_bd_ia32_Conv_I2I8Bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu); + SET_IA32_ORIG_NODE(conv, node); + + /* neg */ + neg = new_bd_ia32_Neg(dbgi, block, conv); + + /* or */ + or = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg); + set_ia32_commutative(or); + + /* add 1 */ + return new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP, nomem, or, ia32_create_Immediate(NULL, 0, 1)); +} + +/** + * Transform builtin clz. + */ +static ir_node *gen_clz(ir_node *node) +{ + ir_node *bsr = gen_unop_AM(node, new_bd_ia32_Bsr); + ir_node *real = skip_Proj(bsr); + dbg_info *dbgi = get_irn_dbg_info(real); + ir_node *block = get_nodes_block(real); + ir_node *imm = ia32_create_Immediate(NULL, 0, 31); + + return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm); +} + +/** + * Transform builtin ctz. + */ +static ir_node *gen_ctz(ir_node *node) +{ + return gen_unop_AM(node, new_bd_ia32_Bsf); +} + +/** + * Transform builtin parity. + */ +static ir_node *gen_parity(ir_node *node) +{ + ir_node *param = get_Builtin_param(node, 0); + dbg_info *dbgi = get_irn_dbg_info(node); + + ir_node *block = get_nodes_block(node); + + ir_node *new_block = be_transform_node(block); + ir_node *imm, *cmp, *new_node; + + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; + + + /* cmp param, 0 */ + match_arguments(&am, block, NULL, param, NULL, match_am); + imm = ia32_create_Immediate(NULL, 0, 0); + cmp = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index, + addr->mem, imm, am.new_op2, am.ins_permuted, 0); + set_am_attributes(cmp, &am); + set_ia32_ls_mode(cmp, mode_Iu); + + SET_IA32_ORIG_NODE(cmp, node); + + cmp = fix_mem_proj(cmp, &am); + + /* setp */ + new_node = new_bd_ia32_Set(dbgi, new_block, cmp, ia32_pn_Cmp_parity, 0); + SET_IA32_ORIG_NODE(new_node, node); + + /* conv to 32bit */ + new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP, + nomem, new_node, mode_Bu); + SET_IA32_ORIG_NODE(new_node, node); + return new_node; +} + +/** + * Transform builtin popcount + */ +static ir_node *gen_popcount(ir_node *node) { + ir_node *param = get_Builtin_param(node, 0); + dbg_info *dbgi = get_irn_dbg_info(node); + + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + + ir_node *new_param; + ir_node *imm, *simm, *m1, *s1, *s2, *s3, *s4, *s5, *m2, *m3, *m4, *m5, *m6, *m7, *m8, *m9, *m10, *m11, *m12, *m13; + + /* check for SSE4.2 or SSE4a and use the popcnt instruction */ + if (ia32_cg_config.use_popcnt) { + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; + ir_node *cnt; + + match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am); + + cnt = new_bd_ia32_Popcnt(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2); + set_am_attributes(cnt, &am); + set_ia32_ls_mode(cnt, get_irn_mode(param)); + + SET_IA32_ORIG_NODE(cnt, node); + return fix_mem_proj(cnt, &am); + } + + new_param = be_transform_node(param); + + /* do the standard popcount algo */ + + /* m1 = x & 0x55555555 */ + imm = ia32_create_Immediate(NULL, 0, 0x55555555); + m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_param, imm); + + /* s1 = x >> 1 */ + simm = ia32_create_Immediate(NULL, 0, 1); + s1 = new_bd_ia32_Shl(dbgi, new_block, new_param, simm); + + /* m2 = s1 & 0x55555555 */ + m2 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s1, imm); + + /* m3 = m1 + m2 */ + m3 = new_bd_ia32_Lea(dbgi, new_block, m2, m1); + + /* m4 = m3 & 0x33333333 */ + imm = ia32_create_Immediate(NULL, 0, 0x33333333); + m4 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m3, imm); + + /* s2 = m3 >> 2 */ + simm = ia32_create_Immediate(NULL, 0, 2); + s2 = new_bd_ia32_Shl(dbgi, new_block, m3, simm); + + /* m5 = s2 & 0x33333333 */ + m5 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, imm); + + /* m6 = m4 + m5 */ + m6 = new_bd_ia32_Lea(dbgi, new_block, m4, m5); + + /* m7 = m6 & 0x0F0F0F0F */ + imm = ia32_create_Immediate(NULL, 0, 0x0F0F0F0F); + m7 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m6, imm); + + /* s3 = m6 >> 4 */ + simm = ia32_create_Immediate(NULL, 0, 4); + s3 = new_bd_ia32_Shl(dbgi, new_block, m6, simm); + + /* m8 = s3 & 0x0F0F0F0F */ + m8 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, imm); + + /* m9 = m7 + m8 */ + m9 = new_bd_ia32_Lea(dbgi, new_block, m7, m8); + + /* m10 = m9 & 0x00FF00FF */ + imm = ia32_create_Immediate(NULL, 0, 0x00FF00FF); + m10 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m9, imm); + + /* s4 = m9 >> 8 */ + simm = ia32_create_Immediate(NULL, 0, 8); + s4 = new_bd_ia32_Shl(dbgi, new_block, m9, simm); + + /* m11 = s4 & 0x00FF00FF */ + m11 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s4, imm); + + /* m12 = m10 + m11 */ + m12 = new_bd_ia32_Lea(dbgi, new_block, m10, m11); + + /* m13 = m12 & 0x0000FFFF */ + imm = ia32_create_Immediate(NULL, 0, 0x0000FFFF); + m13 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m12, imm); + + /* s5 = m12 >> 16 */ + simm = ia32_create_Immediate(NULL, 0, 16); + s5 = new_bd_ia32_Shl(dbgi, new_block, m12, simm); + + /* res = m13 + s5 */ + return new_bd_ia32_Lea(dbgi, new_block, m13, s5); +} + +/** + * Transform builtin byte swap. + */ +static ir_node *gen_bswap(ir_node *node) { + ir_node *param = be_transform_node(get_Builtin_param(node, 0)); + dbg_info *dbgi = get_irn_dbg_info(node); + + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_mode *mode = get_irn_mode(param); + unsigned size = get_mode_size_bits(mode); + ir_node *m1, *m2, *m3, *m4, *s1, *s2, *s3, *s4; + + switch (size) { + case 32: + if (ia32_cg_config.use_i486) { + /* swap available */ + return new_bd_ia32_Bswap(dbgi, new_block, param); + } + s1 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24)); + s2 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8)); + + m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, ia32_create_Immediate(NULL, 0, 0xFF00)); + m2 = new_bd_ia32_Lea(dbgi, new_block, s1, m1); + + s3 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8)); + + m3 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, ia32_create_Immediate(NULL, 0, 0xFF0000)); + m4 = new_bd_ia32_Lea(dbgi, new_block, m2, m3); + + s4 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24)); + return new_bd_ia32_Lea(dbgi, new_block, m4, s4); + + case 16: + /* swap16 always available */ + return new_bd_ia32_Bswap16(dbgi, new_block, param); + + default: + panic("Invalid bswap size (%d)", size); + } +} + +/** + * Transform builtin outport. + */ +static ir_node *gen_outport(ir_node *node) { + ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0); + ir_node *oldv = get_Builtin_param(node, 1); + ir_mode *mode = get_irn_mode(oldv); + ir_node *value = be_transform_node(oldv); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *mem = be_transform_node(get_Builtin_mem(node)); + dbg_info *dbgi = get_irn_dbg_info(node); + + ir_node *res = new_bd_ia32_Outport(dbgi, block, port, value, mem); + set_ia32_ls_mode(res, mode); + return res; +} + +/** + * Transform builtin inport. + */ +static ir_node *gen_inport(ir_node *node) { + ir_type *tp = get_Builtin_type(node); + ir_type *rstp = get_method_res_type(tp, 0); + ir_mode *mode = get_type_mode(rstp); + ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *mem = be_transform_node(get_Builtin_mem(node)); + dbg_info *dbgi = get_irn_dbg_info(node); + + ir_node *res = new_bd_ia32_Inport(dbgi, block, port, mem); + set_ia32_ls_mode(res, mode); + + /* check for missing Result Proj */ + return res; +} + +/** + * Transform a builtin inner trampoline + */ +static ir_node *gen_inner_trampoline(ir_node *node) { + ir_node *ptr = get_Builtin_param(node, 0); + ir_node *callee = get_Builtin_param(node, 1); + ir_node *env = be_transform_node(get_Builtin_param(node, 2)); + ir_node *mem = get_Builtin_mem(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *val; + ir_node *store; + ir_node *rel; + ir_node *trampoline; + ir_node *in[2]; + dbg_info *dbgi = get_irn_dbg_info(node); + ia32_address_t addr; + + /* construct store address */ + memset(&addr, 0, sizeof(addr)); + ia32_create_address_mode(&addr, ptr, 0); + + if (addr.base == NULL) { + addr.base = noreg_GP; + } else { + addr.base = be_transform_node(addr.base); + } + + if (addr.index == NULL) { + addr.index = noreg_GP; + } else { + addr.index = be_transform_node(addr.index); + } + addr.mem = be_transform_node(mem); + + /* mov ecx, */ + val = ia32_create_Immediate(NULL, 0, 0xB9); + store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base, + addr.index, addr.mem, val); + set_irn_pinned(store, get_irn_pinned(node)); + set_ia32_op_type(store, ia32_AddrModeD); + set_ia32_ls_mode(store, mode_Bu); + set_address(store, &addr); + addr.mem = store; + addr.offset += 1; + + store = new_bd_ia32_Store(dbgi, new_block, addr.base, + addr.index, addr.mem, env); + set_irn_pinned(store, get_irn_pinned(node)); + set_ia32_op_type(store, ia32_AddrModeD); + set_ia32_ls_mode(store, mode_Iu); + set_address(store, &addr); + addr.mem = store; + addr.offset += 4; + + /* jmp rel */ + val = ia32_create_Immediate(NULL, 0, 0xE9); + store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base, + addr.index, addr.mem, val); + set_irn_pinned(store, get_irn_pinned(node)); + set_ia32_op_type(store, ia32_AddrModeD); + set_ia32_ls_mode(store, mode_Bu); + set_address(store, &addr); + addr.mem = store; + addr.offset += 1; + + trampoline = be_transform_node(ptr); + + /* the callee is typically an immediate */ + if (is_SymConst(callee)) { + rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, 0, -10); + } else { + rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), ia32_create_Immediate(NULL, 0, -10)); + } + rel = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, rel, trampoline); + + store = new_bd_ia32_Store(dbgi, new_block, addr.base, + addr.index, addr.mem, rel); + set_irn_pinned(store, get_irn_pinned(node)); + set_ia32_op_type(store, ia32_AddrModeD); + set_ia32_ls_mode(store, mode_Iu); + set_address(store, &addr); + + in[0] = store; + in[1] = trampoline; + + return new_r_Tuple(new_block, 2, in); +} + +/** + * Transform Builtin node. + */ +static ir_node *gen_Builtin(ir_node *node) { + ir_builtin_kind kind = get_Builtin_kind(node); + + switch (kind) { + case ir_bk_trap: + return gen_trap(node); + case ir_bk_debugbreak: + return gen_debugbreak(node); + case ir_bk_return_address: + return gen_return_address(node); + case ir_bk_frame_address: + return gen_frame_address(node); + case ir_bk_prefetch: + return gen_prefetch(node); + case ir_bk_ffs: + return gen_ffs(node); + case ir_bk_clz: + return gen_clz(node); + case ir_bk_ctz: + return gen_ctz(node); + case ir_bk_parity: + return gen_parity(node); + case ir_bk_popcount: + return gen_popcount(node); + case ir_bk_bswap: + return gen_bswap(node); + case ir_bk_outport: + return gen_outport(node); + case ir_bk_inport: + return gen_inport(node); + case ir_bk_inner_trampoline: + return gen_inner_trampoline(node); + } + panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind)); +} + +/** + * Transform Proj(Builtin) node. + */ +static ir_node *gen_Proj_Builtin(ir_node *proj) { + ir_node *node = get_Proj_pred(proj); + ir_node *new_node = be_transform_node(node); + ir_builtin_kind kind = get_Builtin_kind(node); + + switch (kind) { + case ir_bk_return_address: + case ir_bk_frame_address: + case ir_bk_ffs: + case ir_bk_clz: + case ir_bk_ctz: + case ir_bk_parity: + case ir_bk_popcount: + case ir_bk_bswap: + assert(get_Proj_proj(proj) == pn_Builtin_1_result); + return new_node; + case ir_bk_trap: + case ir_bk_debugbreak: + case ir_bk_prefetch: + case ir_bk_outport: + assert(get_Proj_proj(proj) == pn_Builtin_M); + return new_node; + case ir_bk_inport: + if (get_Proj_proj(proj) == pn_Builtin_1_result) { + return new_r_Proj(get_nodes_block(new_node), + new_node, get_irn_mode(proj), pn_ia32_Inport_res); + } else { + assert(get_Proj_proj(proj) == pn_Builtin_M); + return new_r_Proj(get_nodes_block(new_node), + new_node, mode_M, pn_ia32_Inport_M); + } + case ir_bk_inner_trampoline: + if (get_Proj_proj(proj) == pn_Builtin_1_result) { + return get_Tuple_pred(new_node, 1); + } else { + assert(get_Proj_proj(proj) == pn_Builtin_M); + return get_Tuple_pred(new_node, 0); + } + } + panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind)); +} + static ir_node *gen_be_IncSP(ir_node *node) { ir_node *res = be_duplicate_node(node); @@ -4528,74 +5240,14 @@ static ir_node *gen_Proj_be_Call(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *call = get_Proj_pred(node); ir_node *new_call = be_transform_node(call); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_type *method_type = be_Call_get_type(call); - int n_res = get_method_n_ress(method_type); long proj = get_Proj_proj(node); ir_mode *mode = get_irn_mode(node); - ir_node *sse_load; ir_node *res; - /* The following is kinda tricky: If we're using SSE, then we have to - * move the result value of the call in floating point registers to an - * xmm register, we therefore construct a GetST0 -> xLoad sequence - * after the call, we have to make sure to correctly make the - * MemProj and the result Proj use these 2 nodes - */ if (proj == pn_be_Call_M_regular) { - // get new node for result, are we doing the sse load/store hack? - ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res); - ir_node *call_res_new; - ir_node *call_res_pred = NULL; - - if (call_res != NULL) { - call_res_new = be_transform_node(call_res); - call_res_pred = get_Proj_pred(call_res_new); - } - - if (call_res_pred == NULL || is_ia32_Call(call_res_pred)) { - return new_rd_Proj(dbgi, irg, block, new_call, mode_M, - n_ia32_Call_mem); - } else { - assert(is_ia32_xLoad(call_res_pred)); - return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, - pn_ia32_xLoad_M); - } + return new_rd_Proj(dbgi, block, new_call, mode_M, n_ia32_Call_mem); } - if (ia32_cg_config.use_sse2 && proj >= pn_be_Call_first_res - && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)) { - ir_node *fstp; - ir_node *frame = get_irg_frame(irg); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - //ir_node *p; - ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular); - ir_node *call_res; - - /* in case there is no memory output: create one to serialize the copy - FPU -> SSE */ - call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, - pn_be_Call_M_regular); - call_res = new_rd_Proj(dbgi, irg, block, new_call, mode, - pn_be_Call_first_res); - - /* store st(0) onto stack */ - fstp = new_bd_ia32_vfst(dbgi, block, frame, noreg, call_mem, - call_res, mode); - set_ia32_op_type(fstp, ia32_AddrModeD); - set_ia32_use_frame(fstp); - - /* load into SSE register */ - sse_load = new_bd_ia32_xLoad(dbgi, block, frame, noreg, fstp, mode); - set_ia32_op_type(sse_load, ia32_AddrModeS); - set_ia32_use_frame(sse_load); - - sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, - pn_ia32_xLoad_res); - - return sse_load; - } - /* transform call modes */ if (mode_is_data(mode)) { const arch_register_class_t *cls = arch_get_irn_reg_class_out(node); @@ -4616,7 +5268,8 @@ static ir_node *gen_Proj_be_Call(ir_node *node) assert(req->type & arch_register_req_type_limited); for (i = 0; i < n_outs; ++i) { - arch_register_req_t const *const new_req = get_ia32_out_req(new_call, i); + arch_register_req_t const *const new_req + = arch_get_out_register_req(new_call, i); if (!(new_req->type & arch_register_req_type_limited) || new_req->cls != req->cls || @@ -4629,7 +5282,7 @@ static ir_node *gen_Proj_be_Call(ir_node *node) assert(i < n_outs); } - res = new_rd_Proj(dbgi, irg, block, new_call, mode, proj); + res = new_rd_Proj(dbgi, block, new_call, mode, proj); /* TODO arch_set_irn_register() only operates on Projs, need variant with index */ switch (proj) { @@ -4669,11 +5322,11 @@ static ir_node *gen_Proj_Bound(ir_node *node) case pn_Bound_X_regular: new_node = be_transform_node(pred); block = get_nodes_block(new_node); - return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_true); + return new_r_Proj(block, new_node, mode_X, pn_ia32_Jcc_true); case pn_Bound_X_except: new_node = be_transform_node(pred); block = get_nodes_block(new_node); - return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_false); + return new_r_Proj(block, new_node, mode_X, pn_ia32_Jcc_false); case pn_Bound_res: return be_transform_node(get_Bound_index(pred)); default: @@ -4683,18 +5336,23 @@ static ir_node *gen_Proj_Bound(ir_node *node) static ir_node *gen_Proj_ASM(ir_node *node) { - ir_node *pred; - ir_node *new_pred; - ir_node *block; - - if (get_irn_mode(node) != mode_M) - return be_duplicate_node(node); + ir_mode *mode = get_irn_mode(node); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + ir_node *block = get_nodes_block(new_pred); + long pos = get_Proj_proj(node); + + if (mode == mode_M) { + pos = arch_irn_get_n_outs(new_pred)-1; + } else if (mode_is_int(mode) || mode_is_reference(mode)) { + mode = mode_Iu; + } else if (mode_is_float(mode)) { + mode = mode_E; + } else { + panic("unexpected proj mode at ASM"); + } - pred = get_Proj_pred(node); - new_pred = be_transform_node(pred); - block = get_nodes_block(new_pred); - return new_r_Proj(current_ir_graph, block, new_pred, mode_M, - arch_irn_get_n_outs(new_pred) + 1); + return new_r_Proj(block, new_pred, mode, pos); } /** @@ -4717,6 +5375,8 @@ static ir_node *gen_Proj(ir_node *node) return gen_Proj_Load(node); case iro_ASM: return gen_Proj_ASM(node); + case iro_Builtin: + return gen_Proj_Builtin(node); case iro_Div: case iro_Mod: case iro_DivMod: @@ -4743,7 +5403,7 @@ static ir_node *gen_Proj(ir_node *node) ir_node *new_block = be_transform_node(block); dbg_info *dbgi = get_irn_dbg_info(node); /* we exchange the ProjX with a jump */ - ir_node *jump = new_rd_Jmp(dbgi, current_ir_graph, new_block); + ir_node *jump = new_rd_Jmp(dbgi, new_block); return jump; } @@ -4765,11 +5425,9 @@ static ir_node *gen_Proj(ir_node *node) if (ia32_mode_needs_gp_reg(mode)) { ir_node *new_pred = be_transform_node(pred); ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_proj = new_r_Proj(current_ir_graph, block, new_pred, + ir_node *new_proj = new_r_Proj(block, new_pred, mode_Iu, get_Proj_proj(node)); -#ifdef DEBUG_libfirm new_proj->node_nr = node->node_nr; -#endif return new_proj; } } @@ -4782,8 +5440,6 @@ static ir_node *gen_Proj(ir_node *node) */ static void register_transformers(void) { - ir_op *op_Mulh; - /* first clear the generic function pointer for all ops */ clear_irp_opcodes_generic_func(); @@ -4793,6 +5449,7 @@ static void register_transformers(void) GEN(Add); GEN(Sub); GEN(Mul); + GEN(Mulh); GEN(And); GEN(Or); GEN(Eor); @@ -4823,6 +5480,7 @@ static void register_transformers(void) GEN(Mux); GEN(Proj); GEN(Phi); + GEN(Jmp); GEN(IJmp); GEN(Bound); @@ -4860,6 +5518,9 @@ static void register_transformers(void) BAD(EndReg); BAD(EndExcept); + /* handle builtins */ + GEN(Builtin); + /* handle generic backend nodes */ GEN(be_FrameAddr); GEN(be_Call); @@ -4869,10 +5530,6 @@ static void register_transformers(void) GEN(be_SubSP); GEN(be_Copy); - op_Mulh = get_op_Mulh(); - if (op_Mulh) - GEN(Mulh); - #undef GEN #undef BAD } @@ -4890,6 +5547,10 @@ static void ia32_pretransform_node(void) cg->noreg_gp = be_pre_transform_node(cg->noreg_gp); cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp); cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm); + + nomem = get_irg_no_mem(current_ir_graph); + noreg_GP = ia32_new_NoReg_gp(cg); + get_fpcw(); } @@ -4946,7 +5607,7 @@ static void add_missing_keep_walker(ir_node *node, void *data) continue; } - req = get_ia32_out_req(node, i); + req = arch_get_out_register_req(node, i); cls = req->cls; if (cls == NULL) { continue; @@ -4956,12 +5617,11 @@ static void add_missing_keep_walker(ir_node *node, void *data) } block = get_nodes_block(node); - in[0] = new_r_Proj(current_ir_graph, block, node, - arch_register_class_mode(cls), i); + in[0] = new_r_Proj(block, node, arch_register_class_mode(cls), i); if (last_keep != NULL) { be_Keep_add_node(last_keep, cls, in[0]); } else { - last_keep = be_new_Keep(cls, current_ir_graph, block, 1, in); + last_keep = be_new_Keep(block, 1, in); if (sched_is_scheduled(node)) { sched_add_after(node, last_keep); } @@ -4979,18 +5639,112 @@ void ia32_add_missing_keeps(ia32_code_gen_t *cg) irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL); } +/** + * Post-process all calls if we are in SSE mode. + * The ABI requires that the results are in st0, copy them + * to a xmm register. + */ +static void postprocess_fp_call_results(void) { + int i; + + for (i = ARR_LEN(call_list) - 1; i >= 0; --i) { + ir_node *call = call_list[i]; + ir_type *mtp = call_types[i]; + int j; + + for (j = get_method_n_ress(mtp) - 1; j >= 0; --j) { + ir_type *res_tp = get_method_res_type(mtp, j); + ir_node *res, *new_res; + const ir_edge_t *edge, *next; + ir_mode *mode; + + if (! is_atomic_type(res_tp)) { + /* no floating point return */ + continue; + } + mode = get_type_mode(res_tp); + if (! mode_is_float(mode)) { + /* no floating point return */ + continue; + } + + res = be_get_Proj_for_pn(call, pn_ia32_Call_vf0 + j); + new_res = NULL; + + /* now patch the users */ + foreach_out_edge_safe(res, edge, next) { + ir_node *succ = get_edge_src_irn(edge); + + /* ignore Keeps */ + if (be_is_Keep(succ)) + continue; + + if (is_ia32_xStore(succ)) { + /* an xStore can be patched into an vfst */ + dbg_info *db = get_irn_dbg_info(succ); + ir_node *block = get_nodes_block(succ); + ir_node *base = get_irn_n(succ, n_ia32_xStore_base); + ir_node *index = get_irn_n(succ, n_ia32_xStore_index); + ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem); + ir_node *value = get_irn_n(succ, n_ia32_xStore_val); + ir_mode *mode = get_ia32_ls_mode(succ); + + ir_node *st = new_bd_ia32_vfst(db, block, base, index, mem, value, mode); + set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ)); + if (is_ia32_use_frame(succ)) + set_ia32_use_frame(st); + set_ia32_frame_ent(st, get_ia32_frame_ent(succ)); + set_irn_pinned(st, get_irn_pinned(succ)); + set_ia32_op_type(st, ia32_AddrModeD); + + exchange(succ, st); + } else { + if (new_res == NULL) { + dbg_info *db = get_irn_dbg_info(call); + ir_node *block = get_nodes_block(call); + ir_node *frame = get_irg_frame(current_ir_graph); + ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M); + ir_node *call_mem = new_r_Proj(block, call, mode_M, pn_ia32_Call_M); + ir_node *vfst, *xld, *new_mem; + + /* store st(0) on stack */ + vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, res, mode); + set_ia32_op_type(vfst, ia32_AddrModeD); + set_ia32_use_frame(vfst); + + /* load into SSE register */ + xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst, mode); + set_ia32_op_type(xld, ia32_AddrModeS); + set_ia32_use_frame(xld); + + new_res = new_r_Proj(block, xld, mode, pn_ia32_xLoad_res); + new_mem = new_r_Proj(block, xld, mode_M, pn_ia32_xLoad_M); + + if (old_mem != NULL) { + edges_reroute(old_mem, new_mem, current_ir_graph); + kill_node(old_mem); + } + } + set_irn_n(succ, get_edge_src_pos(edge), new_res); + } + } + } + } +} + /* do the transformation */ void ia32_transform_graph(ia32_code_gen_t *cg) { int cse_last; register_transformers(); - env_cg = cg; - initial_fpcw = NULL; + env_cg = cg; + initial_fpcw = NULL; + no_pic_adjust = 0; - BE_TIMER_PUSH(t_heights); + be_timer_push(T_HEIGHTS); heights = heights_new(cg->irg); - BE_TIMER_POP(t_heights); + be_timer_pop(T_HEIGHTS); ia32_calculate_non_address_mode_nodes(cg->birg); /* the transform phase is not safe for CSE (yet) because several nodes get @@ -4998,8 +5752,15 @@ void ia32_transform_graph(ia32_code_gen_t *cg) cse_last = get_opt_cse(); set_opt_cse(0); + call_list = NEW_ARR_F(ir_node *, 0); + call_types = NEW_ARR_F(ir_type *, 0); be_transform_graph(cg->birg, ia32_pretransform_node); + if (ia32_cg_config.use_sse2) + postprocess_fp_call_results(); + DEL_ARR_F(call_types); + DEL_ARR_F(call_list); + set_opt_cse(cse_last); ia32_free_non_address_mode_nodes();