X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=c32c060f03ccfe89de6bb0eaa83460bea400418a;hb=4bdf858cdb11749577b89e449b9665e6fc6ab5e8;hp=df93fc156543c88c1ccf699c3aa7846eda844363;hpb=7438ae082c9ec7658ccd006b40aa62084aedca2d;p=libfirm

diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c
index df93fc156..c32c060f0 100644
--- a/ir/be/ia32/ia32_transform.c
+++ b/ir/be/ia32/ia32_transform.c
@@ -36,6 +36,13 @@
 
 #include "gen_ia32_regalloc_if.h"
 
+#ifdef NDEBUG
+#define SET_IA32_ORIG_NODE(n, o)
+#else
+#define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
+#endif /* NDEBUG */
+
+
 #define SFP_SIGN "0x80000000"
 #define DFP_SIGN "0x8000000000000000"
 #define SFP_ABS  "0x7FFFFFFF"
@@ -60,7 +67,7 @@ typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block
 									 ir_node *op, ir_node *mem, ir_mode *mode);
 
 typedef enum {
-	ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS
+	ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
 } ia32_known_const_t;
 
 /****************************************************************************************************
@@ -73,66 +80,51 @@ typedef enum {
  *
  ****************************************************************************************************/
 
-struct tv_ent {
-	entity *ent;
-	tarval *tv;
-};
+/**
+ * Gets the Proj with number pn from irn.
+ */
+static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
+	const ir_edge_t *edge;
+	ir_node   *proj;
+	assert(get_irn_mode(irn) == mode_T && "need mode_T");
+
+	foreach_out_edge(irn, edge) {
+		proj = get_edge_src_irn(edge);
 
-/* Compares two (entity, tarval) combinations */
-static int cmp_tv_ent(const void *a, const void *b, size_t len) {
-	const struct tv_ent *e1 = a;
-	const struct tv_ent *e2 = b;
+		if (get_Proj_proj(proj) == pn)
+			return proj;
+	}
 
-	return !(e1->tv == e2->tv);
+	return NULL;
 }
 
 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
-static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
-	static set    *const_set = NULL;
-	struct tv_ent  key;
-	struct tv_ent *entry;
-	char          *tp_name;
-	char          *ent_name;
-	char          *cnst_str;
+static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
+	static const struct {
+		const char *tp_name;
+		const char *ent_name;
+		const char *cnst_str;
+	} names [ia32_known_const_max] = {
+		{ TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN },	/* ia32_SSIGN */
+		{ TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN },	/* ia32_DSIGN */
+		{ TP_SFP_ABS,  ENT_SFP_ABS,  SFP_ABS },		/* ia32_SABS */
+		{ TP_DFP_ABS,  ENT_DFP_ABS,  DFP_ABS }		/* ia32_DABS */
+	};
+	static struct entity *ent_cache[ia32_known_const_max];
+
+	const char    *tp_name, *ent_name, *cnst_str;
 	ir_type       *tp;
 	ir_node       *cnst;
 	ir_graph      *rem;
 	entity        *ent;
+	tarval        *tv;
 
-	if (! const_set) {
-		const_set = new_set(cmp_tv_ent, 10);
-	}
+	ent_name = names[kct].ent_name;
+	if (! ent_cache[kct]) {
+		tp_name  = names[kct].tp_name;
+		cnst_str = names[kct].cnst_str;
 
-	switch (kct) {
-		case ia32_SSIGN:
-			tp_name  = TP_SFP_SIGN;
-			ent_name = ENT_SFP_SIGN;
-			cnst_str = SFP_SIGN;
-			break;
-		case ia32_DSIGN:
-			tp_name  = TP_DFP_SIGN;
-			ent_name = ENT_DFP_SIGN;
-			cnst_str = DFP_SIGN;
-			break;
-		case ia32_SABS:
-			tp_name  = TP_SFP_ABS;
-			ent_name = ENT_SFP_ABS;
-			cnst_str = SFP_ABS;
-			break;
-		case ia32_DABS:
-			tp_name  = TP_DFP_ABS;
-			ent_name = ENT_DFP_ABS;
-			cnst_str = DFP_ABS;
-			break;
-	}
-
-
-	key.tv  = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
-	key.ent = NULL;
-
-	entry = set_insert(const_set, &key, sizeof(key), HASH_PTR(key.tv));
-
-	if (! entry->ent) {
+		tv  = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
 		tp  = new_type_primitive(new_id_from_str(tp_name), mode);
 		ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
 
@@ -145,16 +137,16 @@ static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
 		    const code irg */
 		rem = current_ir_graph;
 		current_ir_graph = get_const_code_irg();
-		cnst = new_Const(mode, key.tv);
+		cnst = new_Const(mode, tv);
 		current_ir_graph = rem;
 
 		set_atomic_ent_value(ent, cnst);
 
-		/* set the entry for hashmap */
-		entry->ent = ent;
+		/* cache the entry */
+		ent_cache[kct] = ent;
 	}
 
-	return ent_name;
+	return get_entity_ident(ent_cache[kct]);
 }
 
 #ifndef NDEBUG
@@ -162,16 +154,11 @@ static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
  * Prints the old node name on cg obst and returns a pointer to it.
  */
 const char *get_old_node_name(ia32_transform_env_t *env) {
-	static int name_cnt = 0;
 	ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
 
 	lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
 	obstack_1grow(isa->name_obst, 0);
 	isa->name_obst_size += obstack_object_size(isa->name_obst);
-	name_cnt++;
-	if (name_cnt % 1024 == 0) {
-		printf("name obst size reached %d bytes after %d nodes\n", isa->name_obst_size, name_cnt);
-	}
  	return obstack_finish(isa->name_obst);
 }
 #endif /* NDEBUG */
@@ -267,9 +254,7 @@ static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2,
 		}
 	}
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	set_ia32_res_mode(new_op, mode);
 
@@ -346,9 +331,7 @@ static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node
 	/* set AM support */
 	set_ia32_am_support(new_op, ia32_am_Dest);
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	set_ia32_res_mode(new_op, mode);
 
@@ -386,9 +369,7 @@ static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_
 		set_ia32_am_support(new_op, ia32_am_Dest);
 	}
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	set_ia32_res_mode(new_op, mode);
 
@@ -508,9 +489,7 @@ static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
 		}
 	}
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	set_ia32_res_mode(new_op, mode);
 
@@ -558,7 +537,7 @@ static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2)
 	ir_node *proj_EAX, *proj_EDX, *mulh;
 	ir_node *in[1];
 
-	assert(mode_is_float(env->mode) && "Mulh with float not supported");
+	assert(!mode_is_float(env->mode) && "Mulh with float not supported");
 	proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
 	mulh     = get_Proj_pred(proj_EAX);
 	proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
@@ -566,7 +545,7 @@ static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2)
 	/* to be on the save side */
 	set_Proj_proj(proj_EAX, pn_EAX);
 
-	if (get_ia32_cnst(mulh)) {
+	if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
 		/* Mulh with const cannot have AM */
 		set_ia32_am_support(mulh, ia32_am_None);
 	}
@@ -659,9 +638,7 @@ static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
 	else {
 		new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
 		set_ia32_am_support(new_op, ia32_am_None);
-#ifndef NDEBUG
-		set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+		SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 	}
 
 	return new_op;
@@ -686,9 +663,7 @@ static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
 	else {
 		new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
 		set_ia32_am_support(new_op, ia32_am_None);
-#ifndef NDEBUG
-		set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+		SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 	}
 
 	return new_op;
@@ -805,9 +780,7 @@ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
 		}
 	}
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	set_ia32_res_mode(new_op, mode);
 
@@ -839,13 +812,16 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir
 
 	switch (dm_flav) {
 		case flavour_Div:
-			mem = get_Div_mem(irn);
+			mem  = get_Div_mem(irn);
+			mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
 			break;
 		case flavour_Mod:
-			mem = get_Mod_mem(irn);
+			mem  = get_Mod_mem(irn);
+			mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
 			break;
 		case flavour_DivMod:
-			mem = get_DivMod_mem(irn);
+			mem  = get_DivMod_mem(irn);
+			mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
 			break;
 		default:
 			assert(0);
@@ -885,9 +861,7 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir
 		be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
 	}
 
-#ifndef NDEBUG
-	set_ia32_orig_node(res, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(res, get_old_node_name(env));
 
 	set_ia32_res_mode(res, mode_Is);
 
@@ -935,12 +909,18 @@ static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2)
 	ir_node *nomem = new_rd_NoMem(env->irg);
 	ir_node *new_op;
 
-	new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, env->mode);
-	set_ia32_am_support(new_op, ia32_am_Source);
+	if (is_ia32_fConst(op2)) {
+		new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem, mode_T);
+		set_ia32_am_support(new_op, ia32_am_None);
+		set_ia32_Immop_attr(new_op, op2);
+	}
+	else {
+		new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
+		set_ia32_am_support(new_op, ia32_am_Source);
+	}
+	set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	return new_op;
 }
@@ -1074,7 +1054,7 @@ static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
  * @return The created ia32 Minus node
  */
 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
-	char    *name;
+	ident   *name;
 	ir_node *new_op;
 	ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
 	ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
@@ -1089,11 +1069,10 @@ static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
 
 		set_ia32_sc(new_op, name);
 
-#ifndef NDEBUG
-		set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+		SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 		set_ia32_res_mode(new_op, env->mode);
+		set_ia32_immop_type(new_op, ia32_ImmSymConst);
 
 		new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
 	}
@@ -1145,7 +1124,7 @@ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
 	ir_node  *noreg_fp = ia32_new_NoReg_fp(env->cg);
 	ir_node  *nomem    = new_NoMem();
 	int       size;
-	char     *name;
+	ident    *name;
 
 	if (mode_is_float(mode)) {
 		res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
@@ -1155,36 +1134,29 @@ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
 
 		set_ia32_sc(res, name);
 
-#ifndef NDEBUG
-		set_ia32_orig_node(res, get_old_node_name(env));
-#endif /* NDEBUG */
+		SET_IA32_ORIG_NODE(res, get_old_node_name(env));
 
 		set_ia32_res_mode(res, mode);
+		set_ia32_immop_type(res, ia32_ImmSymConst);
 
 		res = new_rd_Proj(dbg, irg, block, res, mode, 0);
 	}
 	else {
 		res   = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
-#ifndef NDEBUG
-		set_ia32_orig_node(res, get_old_node_name(env));
-#endif /* NDEBUG */
+		SET_IA32_ORIG_NODE(res, get_old_node_name(env));
 		set_ia32_res_mode(res, mode);
 
 		p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
 		p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
 
 		res   = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
-#ifndef NDEBUG
-		set_ia32_orig_node(res, get_old_node_name(env));
-#endif /* NDEBUG */
+		SET_IA32_ORIG_NODE(res, get_old_node_name(env));
 		set_ia32_res_mode(res, mode);
 
 		res   = new_rd_Proj(dbg, irg, block, res, mode, 0);
 
 		res   = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
-#ifndef NDEBUG
-		set_ia32_orig_node(res, get_old_node_name(env));
-#endif /* NDEBUG */
+		SET_IA32_ORIG_NODE(res, get_old_node_name(env));
 		set_ia32_res_mode(res, mode);
 
 		res   = new_rd_Proj(dbg, irg, block, res, mode, 0);
@@ -1205,25 +1177,39 @@ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
  * @return the created ia32 Load node
  */
 static ir_node *gen_Load(ia32_transform_env_t *env) {
-	ir_node *node  = env->irn;
-	ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+	ir_node    *node  = env->irn;
+	ir_node    *noreg = ia32_new_NoReg_gp(env->cg);
+	ir_node    *ptr   = get_Load_ptr(node);
+	ir_mode    *mode  = get_Load_mode(node);
+	const char *offs  = NULL;
 	ir_node *new_op;
+	ia32_am_flavour_t am_flav = ia32_B;
 
-	if (mode_is_float(env->mode)) {
-		new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
+	/* address might be a constant (symconst or absolute address) */
+	if (is_ia32_Const(ptr)) {
+		offs = get_ia32_cnst(ptr);
+		ptr  = noreg;
+	}
+
+	if (mode_is_float(mode)) {
+		new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, get_Load_mem(node), env->mode);
 	}
 	else {
-		new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
+		new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, get_Load_mem(node), env->mode);
+	}
+
+	/* base is an constant address */
+	if (offs) {
+		add_ia32_am_offs(new_op, offs);
+		am_flav = ia32_O;
 	}
 
 	set_ia32_am_support(new_op, ia32_am_Source);
 	set_ia32_op_type(new_op, ia32_AddrModeS);
-	set_ia32_am_flavour(new_op, ia32_B);
-	set_ia32_ls_mode(new_op, get_Load_mode(node));
+	set_ia32_am_flavour(new_op, am_flav);
+	set_ia32_ls_mode(new_op, mode);
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	return new_op;
 }
@@ -1240,24 +1226,48 @@ static ir_node *gen_Load(ia32_transform_env_t *env) {
  * @return the created ia32 Store node
  */
 static ir_node *gen_Store(ia32_transform_env_t *env) {
-	ir_node *node  = env->irn;
-	ir_node *noreg = ia32_new_NoReg_gp(env->cg);
-	ir_node *val   = get_Store_value(node);
-	ir_node *ptr   = get_Store_ptr(node);
-	ir_node *mem   = get_Store_mem(node);
-	ir_node *sval  = val;
+	ir_node    *node  = env->irn;
+	ir_node    *noreg = ia32_new_NoReg_gp(env->cg);
+	ir_node    *val   = get_Store_value(node);
+	ir_node    *ptr   = get_Store_ptr(node);
+	ir_node    *mem   = get_Store_mem(node);
+	ir_mode    *mode  = get_irn_mode(val);
+	ir_node    *sval  = val;
+	const char *offs  = NULL;
 	ir_node *new_op;
+	ia32_am_flavour_t am_flav = ia32_B;
+	ia32_immop_type_t immop   = ia32_ImmNone;
 
-	/* in case of storing a const -> make it an attribute */
+	/* in case of storing a const (but not a symconst) -> make it an attribute */
 	if (is_ia32_Cnst(val)) {
+		switch (get_ia32_op_type(val)) {
+			case ia32_Const:
+				immop = ia32_ImmConst;
+				break;
+			case ia32_SymConst:
+				immop = ia32_ImmSymConst;
+				break;
+			default:
+				assert(0 && "unsupported Const type");
+		}
+
 		sval = noreg;
 	}
 
-	if (mode_is_float(env->mode)) {
-		new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
+	/* address might be a constant (symconst or absolute address) */
+	if (is_ia32_Const(ptr)) {
+		offs = get_ia32_cnst(ptr);
+		ptr  = noreg;
+	}
+
+	if (mode_is_float(mode)) {
+		new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
+	}
+	else if (get_mode_size_bits(mode) == 8) {
+		new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
 	}
 	else {
-		new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
+		new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
 	}
 
 	/* stored const is an attribute (saves a register) */
@@ -1265,14 +1275,19 @@ static ir_node *gen_Store(ia32_transform_env_t *env) {
 		set_ia32_Immop_attr(new_op, val);
 	}
 
+	/* base is an constant address */
+	if (offs) {
+		add_ia32_am_offs(new_op, offs);
+		am_flav = ia32_O;
+	}
+
 	set_ia32_am_support(new_op, ia32_am_Dest);
 	set_ia32_op_type(new_op, ia32_AddrModeD);
-	set_ia32_am_flavour(new_op, ia32_B);
+	set_ia32_am_flavour(new_op, am_flav);
 	set_ia32_ls_mode(new_op, get_irn_mode(val));
+	set_ia32_immop_type(new_op, immop);
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	return new_op;
 }
@@ -1280,7 +1295,7 @@ static ir_node *gen_Store(ia32_transform_env_t *env) {
 
 
 /**
- * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i
+ * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
  *
  * @param env   The transformation environment
  * @return The transformed node.
@@ -1295,10 +1310,11 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) {
 	ir_node  *res      = NULL;
 	ir_node  *pred     = NULL;
 	ir_node  *noreg    = ia32_new_NoReg_gp(env->cg);
-	ir_node  *nomem    = new_NoMem();
 	ir_node  *cmp_a, *cmp_b, *cnst, *expr;
 
 	if (is_Proj(sel) && sel_mode == mode_b) {
+		ir_node  *nomem = new_NoMem();
+
 		pred  = get_Proj_pred(sel);
 
 		/* get both compare operators */
@@ -1310,11 +1326,50 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) {
 		expr = get_expr_op(cmp_a, cmp_b);
 
 		if (cnst && expr) {
-			res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
+			pn_Cmp pnc = get_Proj_proj(sel);
+
+			if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
+				if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
+					/* a Cmp A =/!= 0 */
+					ir_node    *op1  = expr;
+					ir_node    *op2  = expr;
+					ir_node    *and  = skip_Proj(expr);
+					const char *cnst = NULL;
+
+					/* check, if expr is an only once used And operation */
+					if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
+						op1 = get_irn_n(and, 2);
+						op2 = get_irn_n(and, 3);
+
+						cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
+					}
+					res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
+					set_ia32_pncode(res, get_Proj_proj(sel));
+
+					if (cnst) {
+						copy_ia32_Immop_attr(res, and);
+					}
+
+					SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+					return res;
+				}
+			}
+
+			if (mode_is_float(get_irn_mode(expr))) {
+				res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
+			}
+			else {
+				res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
+			}
 			set_ia32_Immop_attr(res, cnst);
 		}
 		else {
-			res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
+			if (mode_is_float(get_irn_mode(cmp_a))) {
+				res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
+			}
+			else {
+				res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
+			}
 		}
 
 		set_ia32_pncode(res, get_Proj_proj(sel));
@@ -1325,10 +1380,7 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) {
 		set_ia32_pncode(res, get_Cond_defaultProj(node));
 	}
 
-#ifndef NDEBUG
-	set_ia32_orig_node(res, get_old_node_name(env));
-#endif /* NDEBUG */
-
+	SET_IA32_ORIG_NODE(res, get_old_node_name(env));
 	return res;
 }
 
@@ -1369,11 +1421,10 @@ static ir_node *gen_CopyB(ia32_transform_env_t *env) {
 	else {
 		res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
 		set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
+		set_ia32_immop_type(res, ia32_ImmConst);
 	}
 
-#ifndef NDEBUG
-	set_ia32_orig_node(res, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(res, get_old_node_name(env));
 
 	return res;
 }
@@ -1391,14 +1442,69 @@ static ir_node *gen_Mux(ia32_transform_env_t *env) {
 	ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
 		get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	return new_op;
 }
 
 
+/**
+ * Following conversion rules apply:
+ *
+ *  INT -> INT
+ * ============
+ *  1) n bit -> m bit   n > m (downscale)
+ *     a) target is signed:    movsx
+ *     b) target is unsigned:  and with lower bits sets
+ *  2) n bit -> m bit   n == m   (sign change)
+ *     always ignored
+ *  3) n bit -> m bit   n < m (upscale)
+ *     a) source is signed:    movsx
+ *     b) source is unsigned:  and with lower bits sets
+ *
+ *  INT -> FLOAT
+ * ==============
+ *  SSE(1/2) convert to float or double (cvtsi2ss/sd)
+ *
+ *  FLOAT -> INT
+ * ==============
+ *  SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
+ *  if target mode < 32bit: additional INT -> INT conversion (see above)
+ *
+ *  FLOAT -> FLOAT
+ * ================
+ *  SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
+ */
+
+//static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
+//									   ir_mode *src_mode, ir_mode *tgt_mode)
+//{
+//	int       n     = get_mode_size_bits(src_mode);
+//	int       m     = get_mode_size_bits(tgt_mode);
+//	dbg_info *dbg   = env->dbg;
+//	ir_graph *irg   = env->irg;
+//	ir_node  *block = env->block;
+//	ir_node  *noreg = ia32_new_NoReg_gp(env->cg);
+//	ir_node  *nomem = new_rd_NoMem(irg);
+//	ir_node  *new_op, *proj;
+//	assert(n > m && "downscale expected");
+//	if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
+//		/* ASHL Sn, n - m */
+//		new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
+//		proj   = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
+//		set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
+//		set_ia32_am_support(new_op, ia32_am_Source);
+//		SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+//		/* ASHR Sn, n - m */
+//		new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
+//		set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
+//	}
+//	else {
+//		new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
+//		set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
+//	}
+//	return new_op;
+//}
 
 /**
  * Transforms a Conv node.
@@ -1412,11 +1518,14 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
 	ir_graph          *irg      = env->irg;
 	ir_mode           *src_mode = get_irn_mode(op);
 	ir_mode           *tgt_mode = env->mode;
+	int                src_bits = get_mode_size_bits(src_mode);
+	int                tgt_bits = get_mode_size_bits(tgt_mode);
 	ir_node           *block    = env->block;
 	ir_node           *new_op   = NULL;
 	ir_node           *noreg    = ia32_new_NoReg_gp(env->cg);
 	ir_node           *nomem    = new_rd_NoMem(irg);
 	firm_dbg_module_t *mod      = env->mod;
+	ir_node           *proj;
 
 	if (src_mode == tgt_mode) {
 		/* this can happen when changing mode_P to mode_Is */
@@ -1434,6 +1543,21 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
 			/* ... to int */
 			DB((mod, LEVEL_1, "create Conv(float, int) ..."));
 			new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+			/* if target mode is not int: add an additional downscale convert */
+			if (tgt_bits < 32) {
+				SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+				set_ia32_res_mode(new_op, tgt_mode);
+				set_ia32_am_support(new_op, ia32_am_Source);
+
+				proj   = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
+
+				if (tgt_bits == 8 || src_bits == 8) {
+					new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
+				}
+				else {
+					new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
+				}
+			}
 		}
 	}
 	else {
@@ -1445,15 +1569,24 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
 		}
 		else {
 			/* ... to int */
-			DB((mod, LEVEL_1, "omitting Conv(Int, Int) ..."));
-			edges_reroute(env->irn, op, irg);
+			if (get_mode_size_bits(src_mode) == tgt_bits) {
+				DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
+				edges_reroute(env->irn, op, irg);
+			}
+			else {
+				DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
+				if (tgt_bits == 8 || src_bits == 8) {
+					new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+				}
+				else {
+					new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+				}
+			}
 		}
 	}
 
 	if (new_op) {
-#ifndef NDEBUG
-		set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+		SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 		set_ia32_res_mode(new_op, tgt_mode);
 
 		set_ia32_am_support(new_op, ia32_am_Source);
@@ -1485,6 +1618,12 @@ static ir_node *gen_StackParam(ia32_transform_env_t *env) {
 	entity  *ent    = be_get_frame_entity(node);
 	ir_mode *mode   = env->mode;
 
+	/* If the StackParam has only one user ->     */
+	/* put it in the Block where the user resides */
+	if (get_irn_n_edges(node) == 1) {
+		env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
+	}
+
 	if (mode_is_float(mode)) {
 		new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
 	}
@@ -1500,9 +1639,7 @@ static ir_node *gen_StackParam(ia32_transform_env_t *env) {
 	set_ia32_am_flavour(new_op, ia32_B);
 	set_ia32_ls_mode(new_op, mode);
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
 }
@@ -1521,10 +1658,9 @@ static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
 	set_ia32_frame_ent(new_op, be_get_frame_entity(node));
 	set_ia32_am_support(new_op, ia32_am_Full);
 	set_ia32_use_frame(new_op);
+	set_ia32_immop_type(new_op, ia32_ImmConst);
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
 }
@@ -1556,9 +1692,7 @@ static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
 	set_ia32_am_flavour(new_op, ia32_B);
 	set_ia32_ls_mode(new_op, mode);
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	return new_op;
 }
@@ -1580,6 +1714,9 @@ static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
 	if (mode_is_float(mode)) {
 		new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
 	}
+	else if (get_mode_size_bits(mode) == 8) {
+		new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+	}
 	else {
 		new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
 	}
@@ -1592,9 +1729,7 @@ static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
 	set_ia32_am_flavour(new_op, ia32_B);
 	set_ia32_ls_mode(new_op, mode);
 
-#ifndef NDEBUG
-	set_ia32_orig_node(new_op, get_old_node_name(env));
-#endif /* NDEBUG */
+	SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
 
 	return new_op;
 }
@@ -1652,14 +1787,14 @@ void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
 		/* generate the add */
 		if (mode_is_float(tenv.mode)) {
 			res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
+			set_ia32_am_support(res, ia32_am_Source);
 		}
 		else {
 			res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
+			set_ia32_am_support(res, ia32_am_Full);
 		}
 
-#ifndef NDEBUG
-		set_ia32_orig_node(res, get_old_node_name(&tenv));
-#endif /* NDEBUG */
+		SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
 		/* copy register */
 		slots    = get_ia32_slots(res);
 		slots[0] = in2_reg;
@@ -1675,6 +1810,122 @@ void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
 	}
 }
 
+/**
+ * Transforms a LEA into an Add if possible
+ * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
+ */
+void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
+	ia32_am_flavour_t am_flav;
+	int               imm = 0;
+	ir_node          *res = NULL;
+	ir_node          *nomem, *noreg, *base, *index, *op1, *op2;
+	char             *offs;
+	ia32_transform_env_t tenv;
+	const arch_register_t *out_reg, *base_reg, *index_reg;
+
+	/* must be a LEA */
+	if (! is_ia32_Lea(irn))
+		return;
+
+	am_flav = get_ia32_am_flavour(irn);
+
+	/* only some LEAs can be transformed to an Add */
+	if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
+		return;
+
+	noreg = ia32_new_NoReg_gp(cg);
+	nomem = new_rd_NoMem(cg->irg);
+	op1   = noreg;
+	op2   = noreg;
+	base  = get_irn_n(irn, 0);
+	index = get_irn_n(irn,1);
+
+	offs  = get_ia32_am_offs(irn);
+
+	/* offset has a explicit sign -> we need to skip + */
+	if (offs && offs[0] == '+')
+		offs++;
+
+	out_reg   = arch_get_irn_register(cg->arch_env, irn);
+	base_reg  = arch_get_irn_register(cg->arch_env, base);
+	index_reg = arch_get_irn_register(cg->arch_env, index);
+
+	tenv.block = get_nodes_block(irn);
+	tenv.dbg   = get_irn_dbg_info(irn);
+	tenv.irg   = cg->irg;
+	tenv.irn   = irn;
+	tenv.mod   = cg->mod;
+	tenv.mode  = get_irn_mode(irn);
+	tenv.cg    = cg;
+
+	switch(get_ia32_am_flavour(irn)) {
+		case ia32_am_B:
+			/* out register must be same as base register */
+			if (! REGS_ARE_EQUAL(out_reg, base_reg))
+				return;
+
+			op1 = base;
+			break;
+		case ia32_am_OB:
+			/* out register must be same as base register */
+			if (! REGS_ARE_EQUAL(out_reg, base_reg))
+				return;
+
+			op1 = base;
+			imm = 1;
+			break;
+		case ia32_am_OI:
+			/* out register must be same as index register */
+			if (! REGS_ARE_EQUAL(out_reg, index_reg))
+				return;
+
+			op1 = index;
+			imm = 1;
+			break;
+		case ia32_am_BI:
+			/* out register must be same as one in register */
+			if (REGS_ARE_EQUAL(out_reg, base_reg)) {
+				op1 = base;
+				op2 = index;
+			}
+			else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
+				op1 = index;
+				op2 = base;
+			}
+			else {
+				/* in registers a different from out -> no Add possible */
+				return;
+			}
+		default:
+			break;
+	}
+
+	res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T);
+	arch_set_irn_register(cg->arch_env, res, out_reg);
+	set_ia32_op_type(res, ia32_Normal);
+
+	if (imm) {
+		set_ia32_cnst(res, offs);
+		set_ia32_immop_type(res, ia32_ImmConst);
+	}
+
+	SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
+
+	/* add Add to schedule */
+	sched_add_before(irn, res);
+
+	res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
+
+	/* add result Proj to schedule */
+	sched_add_before(irn, res);
+
+	/* remove the old LEA */
+	sched_remove(irn);
+
+	/* exchange the Add and the LEA */
+	exchange(irn, res);
+}
+
 /**
  * Transforms the given firm node (and maybe some other related nodes)
  * into one or more assembler nodes.
@@ -1684,7 +1935,7 @@ void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
  */
 void ia32_transform_node(ir_node *node, void *env) {
 	ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
-	opcode  code           = get_irn_opcode(node);
+	opcode  code;
 	ir_node *asm_node      = NULL;
 	ia32_transform_env_t  tenv;
 
@@ -1717,6 +1968,7 @@ void ia32_transform_node(ir_node *node, void *env) {
 
 	DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
 
+	code = get_irn_opcode(node);
 	switch (code) {
 		BINOP(Add);
 		BINOP(Sub);