X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=b1d7d6ce03653867101d8b8fe7ab80cb92105999;hb=9246866a19201d235897e8ef842a28542911cd68;hp=9ded8187d3c75ddadd6c3e411e87d2f87ea70a57;hpb=b152c943b88744d5e212f86d315a36c7b43ae574;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 9ded8187d..b1d7d6ce0 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -225,7 +225,6 @@ static ir_node *gen_Const(ir_node *node) if (mode_is_float(mode)) { ir_node *res = NULL; ir_node *load; - ir_node *base; ir_entity *floatent; if (ia32_cg_config.use_sse2) { @@ -260,6 +259,7 @@ static ir_node *gen_Const(ir_node *node) set_ia32_ls_mode(load, mode); res = load; } else { + ir_node *base; #ifdef CONSTRUCT_SSE_CONST if (mode == mode_D) { unsigned val = get_tarval_sub_bits(tv, 0) | @@ -292,7 +292,7 @@ static ir_node *gen_Const(ir_node *node) mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); res = new_r_Proj(load, mode_xmm, pn_ia32_xLoad_res); } } else { @@ -317,7 +317,7 @@ static ir_node *gen_Const(ir_node *node) ls_mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); res = new_r_Proj(load, mode_vfp, pn_ia32_vfld_res); } } @@ -881,7 +881,6 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } am->op_type = ia32_AddrModeS; } else { - ir_mode *mode; am->op_type = ia32_Normal; if (flags & match_try_am) { @@ -1112,15 +1111,19 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, { dbg_info *dbgi; ir_node *block, *new_block, *new_op1, *new_op2, *new_node; + ir_mode *mode = get_irn_mode(node); - assert(! mode_is_float(get_irn_mode(node))); + assert(! mode_is_float(mode)); assert(flags & match_immediate); assert((flags & ~(match_mode_neutral | match_immediate)) == 0); + if (get_mode_modulo_shift(mode) != 32) + panic("modulo shift!=32 not supported by ia32 backend"); + if (flags & match_mode_neutral) { op1 = ia32_skip_downconv(op1); new_op1 = be_transform_node(op1); - } else if (get_mode_size_bits(get_irn_mode(node)) != 32) { + } else if (get_mode_size_bits(mode) != 32) { new_op1 = create_upconv(op1, node); } else { new_op1 = be_transform_node(op1); @@ -1190,7 +1193,9 @@ static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, ia32_address_t *addr) { - ir_node *base, *index, *res; + ir_node *base; + ir_node *idx; + ir_node *res; base = addr->base; if (base == NULL) { @@ -1199,11 +1204,11 @@ static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, base = be_transform_node(base); } - index = addr->index; - if (index == NULL) { - index = noreg_GP; + idx = addr->index; + if (idx == NULL) { + idx = noreg_GP; } else { - index = be_transform_node(index); + idx = be_transform_node(idx); } /* segment overrides are ineffective for Leas :-( so we have to patch @@ -1218,7 +1223,7 @@ static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, addr->tls_segment = false; } - res = new_bd_ia32_Lea(dbgi, block, base, index); + res = new_bd_ia32_Lea(dbgi, block, base, idx); set_address(res, addr); return res; @@ -1431,7 +1436,7 @@ static bool is_complementary_shifts(ir_node *value1, ir_node *value2) if (tarval_is_long(tv1) && tarval_is_long(tv2)) { long v1 = get_tarval_long(tv1); long v2 = get_tarval_long(tv2); - return v1 < v2 && v2 == 32-v1; + return v1 <= v2 && v2 == 32-v1; } } return false; @@ -1677,9 +1682,10 @@ static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block, */ static ir_node *create_Div(ir_node *node) { - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + int throws_exception = ir_throws_exception(node); ir_node *mem; ir_node *new_mem; ir_node *op1; @@ -1726,6 +1732,7 @@ static ir_node *create_Div(ir_node *node) addr->index, new_mem, am.new_op2, am.new_op1, sign_extension); } + ir_set_throws_exception(new_node, throws_exception); set_irn_pinned(new_node, get_irn_pinned(node)); @@ -1960,68 +1967,42 @@ static ir_node *gen_Not(ir_node *node) return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral); } -static ir_node *create_abs(dbg_info *dbgi, ir_node *block, ir_node *op, - bool negate, ir_node *node) +static ir_node *create_float_abs(dbg_info *dbgi, ir_node *block, ir_node *op, + bool negate, ir_node *node) { ir_node *new_block = be_transform_node(block); ir_mode *mode = get_irn_mode(op); - ir_node *new_op; + ir_node *new_op = be_transform_node(op); ir_node *new_node; int size; ir_entity *ent; - if (mode_is_float(mode)) { - new_op = be_transform_node(op); + assert(mode_is_float(mode)); - if (ia32_cg_config.use_sse2) { - ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph); - new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(), - noreg_GP, nomem, new_op, noreg_fp); + if (ia32_cg_config.use_sse2) { + ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph); + new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(), + noreg_GP, nomem, new_op, noreg_fp); - size = get_mode_size_bits(mode); - ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS); + size = get_mode_size_bits(mode); + ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS); - set_ia32_am_sc(new_node, ent); + set_ia32_am_sc(new_node, ent); - SET_IA32_ORIG_NODE(new_node, node); + SET_IA32_ORIG_NODE(new_node, node); - set_ia32_op_type(new_node, ia32_AddrModeS); - set_ia32_ls_mode(new_node, mode); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode); - /* TODO, implement -Abs case */ - assert(!negate); - } else { - new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op); - SET_IA32_ORIG_NODE(new_node, node); - if (negate) { - new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node); - SET_IA32_ORIG_NODE(new_node, node); - } - } + /* TODO, implement -Abs case */ + assert(!negate); } else { - ir_node *xorn; - ir_node *sign_extension; - - if (get_mode_size_bits(mode) == 32) { - new_op = be_transform_node(op); - } else { - new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node); - } - - sign_extension = create_sex_32_64(dbgi, new_block, new_op, node); - - xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, - nomem, new_op, sign_extension); - SET_IA32_ORIG_NODE(xorn, node); - + new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op); + SET_IA32_ORIG_NODE(new_node, node); if (negate) { - new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, - nomem, sign_extension, xorn); - } else { - new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, - nomem, xorn, sign_extension); + new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node); + SET_IA32_ORIG_NODE(new_node, node); } - SET_IA32_ORIG_NODE(new_node, node); } return new_node; @@ -2124,6 +2105,7 @@ static ir_node *get_flags_mode_b(ir_node *node, ia32_condition_code_t *cc_out) ir_node *new_block = be_transform_node(get_nodes_block(node)); ir_node *new_op = be_transform_node(node); ir_node *flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, new_op, false); + set_ia32_ls_mode(flags, get_irn_mode(new_op)); *cc_out = ia32_cc_not_equal; return flags; } @@ -2209,16 +2191,17 @@ static ir_node *gen_Load(ir_node *node) ir_node *new_mem = be_transform_node(mem); dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_Load_mode(node); + int throws_exception = ir_throws_exception(node); ir_node *base; - ir_node *index; + ir_node *idx; ir_node *new_node; ia32_address_t addr; /* construct load address */ memset(&addr, 0, sizeof(addr)); ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); - base = addr.base; - index = addr.index; + base = addr.base; + idx = addr.index; if (base == NULL) { base = noreg_GP; @@ -2226,18 +2209,18 @@ static ir_node *gen_Load(ir_node *node) base = be_transform_node(base); } - if (index == NULL) { - index = noreg_GP; + if (idx == NULL) { + idx = noreg_GP; } else { - index = be_transform_node(index); + idx = be_transform_node(idx); } if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) { - new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem, + new_node = new_bd_ia32_xLoad(dbgi, block, base, idx, new_mem, mode); } else { - new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem, + new_node = new_bd_ia32_vfld(dbgi, block, base, idx, new_mem, mode); } } else { @@ -2245,12 +2228,13 @@ static ir_node *gen_Load(ir_node *node) /* create a conv node with address mode for smaller modes */ if (get_mode_size_bits(mode) < 32) { - new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index, + new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, idx, new_mem, noreg_GP, mode); } else { - new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem); + new_node = new_bd_ia32_Load(dbgi, block, base, idx, new_mem); } } + ir_set_throws_exception(new_node, throws_exception); set_irn_pinned(new_node, get_irn_pinned(node)); set_ia32_op_type(new_node, ia32_AddrModeS); @@ -2261,7 +2245,7 @@ static ir_node *gen_Load(ir_node *node) assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res && (int)pn_ia32_Load_res == (int)pn_ia32_res); - arch_irn_add_flags(new_node, arch_irn_flags_rematerializable); + arch_add_irn_flags(new_node, arch_irn_flags_rematerializable); } SET_IA32_ORIG_NODE(new_node, node); @@ -2643,6 +2627,7 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) dbg_info *dbgi = get_irn_dbg_info(node); int ofs = 0; int i = 0; + int throws_exception = ir_throws_exception(node); ir_node *ins[4]; ia32_address_t addr; @@ -2661,7 +2646,9 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base, addr.index, addr.mem, imm); + ir_node *new_mem = new_r_Proj(new_node, mode_M, pn_ia32_Store_M); + ir_set_throws_exception(new_node, throws_exception); set_irn_pinned(new_node, get_irn_pinned(node)); set_ia32_op_type(new_node, ia32_AddrModeD); set_ia32_ls_mode(new_node, mode_Iu); @@ -2669,7 +2656,7 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) SET_IA32_ORIG_NODE(new_node, node); assert(i < 4); - ins[i++] = new_node; + ins[i++] = new_mem; size -= 4; ofs += 4; @@ -2679,18 +2666,16 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) if (i > 1) { return new_rd_Sync(dbgi, new_block, i, ins); } else { - return ins[0]; + return get_Proj_pred(ins[0]); } } /** * Generate a vfist or vfisttp instruction. */ -static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, - ir_node *mem, ir_node *val, ir_node **fist) +static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, + ir_node *index, ir_node *mem, ir_node *val) { - ir_node *new_node; - if (ia32_cg_config.use_fisttp) { /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied if other users exists */ @@ -2698,17 +2683,16 @@ static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node ir_node *value = new_r_Proj(vfisttp, mode_E, pn_ia32_vfisttp_res); be_new_Keep(block, 1, &value); - new_node = new_r_Proj(vfisttp, mode_M, pn_ia32_vfisttp_M); - *fist = vfisttp; + return vfisttp; } else { ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph); /* do a fist */ - new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode); - *fist = new_node; + ir_node *vfist = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode); + return vfist; } - return new_node; } + /** * Transforms a general (no special case) Store. * @@ -2723,7 +2707,9 @@ static ir_node *gen_general_Store(ir_node *node) ir_node *ptr = get_Store_ptr(node); ir_node *mem = get_Store_mem(node); dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_val, *new_node, *store; + int throws_exception = ir_throws_exception(node); + ir_node *new_val; + ir_node *new_node; ia32_address_t addr; /* check for destination address mode */ @@ -2765,12 +2751,12 @@ static ir_node *gen_general_Store(ir_node *node) new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, mode); } - store = new_node; } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) { val = get_Conv_op(val); /* TODO: is this optimisation still necessary at all (middleend)? */ - /* We can skip ALL float->float up-Convs (and strict-up-Convs) before stores. */ + /* We can skip ALL float->float up-Convs (and strict-up-Convs) before + * stores. */ while (is_Conv(val)) { ir_node *op = get_Conv_op(val); if (!mode_is_float(get_irn_mode(op))) @@ -2780,7 +2766,7 @@ static ir_node *gen_general_Store(ir_node *node) val = op; } new_val = be_transform_node(val); - new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, &store); + new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val); } else { new_val = create_immediate_or_transform(val, 0); assert(mode != mode_b); @@ -2792,15 +2778,15 @@ static ir_node *gen_general_Store(ir_node *node) new_node = new_bd_ia32_Store(dbgi, new_block, addr.base, addr.index, addr.mem, new_val); } - store = new_node; } + ir_set_throws_exception(new_node, throws_exception); - set_irn_pinned(store, get_irn_pinned(node)); - set_ia32_op_type(store, ia32_AddrModeD); - set_ia32_ls_mode(store, mode); + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeD); + set_ia32_ls_mode(new_node, mode); - set_address(store, &addr); - SET_IA32_ORIG_NODE(store, node); + set_address(new_node, &addr); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -2833,46 +2819,31 @@ static ir_node *gen_Store(ir_node *node) */ static ir_node *create_Switch(ir_node *node) { - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *sel = get_Cond_selector(node); - ir_node *new_sel = be_transform_node(sel); - long switch_min = LONG_MAX; - long switch_max = LONG_MIN; - long default_pn = get_Cond_default_proj(node); - ir_node *new_node; - const ir_edge_t *edge; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *sel = get_Cond_selector(node); + ir_node *new_sel = be_transform_node(sel); + long default_pn = get_Cond_default_proj(node); + ir_node *new_node; + ir_entity *entity; assert(get_mode_size_bits(get_irn_mode(sel)) == 32); - /* determine the smallest switch case value */ - foreach_out_edge(node, edge) { - ir_node *proj = get_edge_src_irn(edge); - long pn = get_Proj_proj(proj); - if (pn == default_pn) - continue; - - if (pn < switch_min) - switch_min = pn; - if (pn > switch_max) - switch_max = pn; - } - - if ((unsigned long) (switch_max - switch_min) > 128000) { - panic("Size of switch %+F bigger than 128000", node); - } - - if (switch_min != 0) { - /* if smallest switch case is not 0 we need an additional sub */ - new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg_GP); - add_ia32_am_offs_int(new_sel, -switch_min); - set_ia32_op_type(new_sel, ia32_AddrModeS); - - SET_IA32_ORIG_NODE(new_sel, node); - } + entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type()); + set_entity_visibility(entity, ir_visibility_private); + add_entity_linkage(entity, IR_LINKAGE_CONSTANT); - new_node = new_bd_ia32_SwitchJmp(dbgi, block, new_sel, default_pn); + /* TODO: we could perform some more matching here to also use the base + * register of the address mode */ + new_node + = new_bd_ia32_SwitchJmp(dbgi, block, noreg_GP, new_sel, default_pn); + set_ia32_am_scale(new_node, 2); + set_ia32_am_sc(new_node, entity); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode_Iu); SET_IA32_ORIG_NODE(new_node, node); + // FIXME This seems wrong. GCC uses PIC for switch on OS X. + get_ia32_attr(new_node)->data.am_sc_no_pic_adjust = true; return new_node; } @@ -3439,11 +3410,11 @@ static void find_const_transform(ia32_condition_code_t cc, ++step; res->steps[step].transform = SETCC_TR_NEG; } else { - int v = get_tarval_lowest_bit(t); - assert(v >= 0); + int val = get_tarval_lowest_bit(t); + assert(val >= 0); res->steps[step].transform = SETCC_TR_SHL; - res->steps[step].scale = v; + res->steps[step].scale = val; } } ++step; @@ -3475,9 +3446,15 @@ static ir_node *gen_Mux(ir_node *node) assert(get_irn_mode(sel) == mode_b); - is_abs = be_mux_is_abs(sel, mux_true, mux_false); + is_abs = ir_mux_is_abs(sel, mux_true, mux_false); if (is_abs != 0) { - return create_abs(dbgi, block, be_get_abs_op(sel), is_abs < 0, node); + if (ia32_mode_needs_gp_reg(mode)) { + ir_fprintf(stderr, "Optimisation warning: Integer abs %+F not transformed\n", + node); + } else { + ir_node *op = ir_get_abs_op(sel, mux_true, mux_false); + return create_float_abs(dbgi, block, op, is_abs < 0, node); + } } /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */ @@ -3690,13 +3667,17 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); + ir_node *frame = get_irg_frame(irg); ir_node *fist, *load, *mem; - mem = gen_vfist(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist); + fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_op); set_irn_pinned(fist, op_pin_state_floats); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); + assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M); + mem = new_r_Proj(fist, mode_M, pn_ia32_vfist_M); + assert(get_mode_size_bits(mode) <= 32); /* exception we can only store signed 32 bit integers, so for unsigned we store a 64bit (signed) integer and load the lower bits */ @@ -3735,6 +3716,7 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) ir_graph *irg = get_Block_irg(block); dbg_info *dbgi = get_irn_dbg_info(node); ir_node *frame = get_irg_frame(irg); + ir_node *store_mem; ir_node *store, *load; ir_node *new_node; @@ -3743,7 +3725,9 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) set_ia32_op_type(store, ia32_AddrModeD); SET_IA32_ORIG_NODE(store, node); - load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store, tgt_mode); + store_mem = new_r_Proj(store, mode_M, pn_ia32_vfst_M); + + load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode); set_ia32_use_frame(load); set_ia32_op_type(load, ia32_AddrModeS); SET_IA32_ORIG_NODE(load, node); @@ -3777,6 +3761,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) ir_mode *store_mode; ir_node *fild; ir_node *store; + ir_node *store_mem; ir_node *new_node; /* fild can use source AM if the operand is a signed 16bit or 32bit integer */ @@ -3822,6 +3807,8 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) set_ia32_op_type(store, ia32_AddrModeD); set_ia32_ls_mode(store, mode_Iu); + store_mem = new_r_Proj(store, mode_M, pn_ia32_Store_M); + /* exception for 32bit unsigned, do a 64bit spill+load */ if (!mode_is_signed(mode)) { ir_node *in[2]; @@ -3830,23 +3817,24 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, zero_const); + ir_node *zero_store_mem = new_r_Proj(zero_store, mode_M, pn_ia32_Store_M); set_ia32_use_frame(zero_store); set_ia32_op_type(zero_store, ia32_AddrModeD); add_ia32_am_offs_int(zero_store, 4); set_ia32_ls_mode(zero_store, mode_Iu); - in[0] = zero_store; - in[1] = store; + in[0] = zero_store_mem; + in[1] = store_mem; - store = new_rd_Sync(dbgi, block, 2, in); + store_mem = new_rd_Sync(dbgi, block, 2, in); store_mode = mode_Ls; } else { store_mode = mode_Is; } /* do a fild */ - fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store); + fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem); set_ia32_use_frame(fild); set_ia32_op_type(fild, ia32_AddrModeS); @@ -4076,7 +4064,11 @@ static ir_node *gen_be_Return(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_type *res_type; ir_mode *mode; - ir_node *frame, *sse_store, *fld, *mproj; + ir_node *frame; + ir_node *sse_store; + ir_node *store_mem; + ir_node *fld; + ir_node *mproj; int i; int arity; unsigned pop; @@ -4109,9 +4101,10 @@ static ir_node *gen_be_Return(ir_node *node) set_ia32_ls_mode(sse_store, mode); set_ia32_op_type(sse_store, ia32_AddrModeD); set_ia32_use_frame(sse_store); + store_mem = new_r_Proj(sse_store, mode_M, pn_ia32_xStoreSimple_M); /* load into x87 register */ - fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, sse_store, mode); + fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, mode); set_ia32_op_type(fld, ia32_AddrModeS); set_ia32_use_frame(fld); @@ -4149,8 +4142,8 @@ static ir_node *gen_be_AddSP(ir_node *node) ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_SubSP, match_am | match_immediate); assert(is_ia32_SubSP(new_node)); - arch_irn_set_register(new_node, pn_ia32_SubSP_stack, - &ia32_registers[REG_ESP]); + arch_set_irn_register_out(new_node, pn_ia32_SubSP_stack, + &ia32_registers[REG_ESP]); return new_node; } @@ -4165,8 +4158,8 @@ static ir_node *gen_be_SubSP(ir_node *node) ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_AddSP, match_am | match_immediate); assert(is_ia32_AddSP(new_node)); - arch_irn_set_register(new_node, pn_ia32_AddSP_stack, - &ia32_registers[REG_ESP]); + arch_set_irn_register_out(new_node, pn_ia32_AddSP_stack, + &ia32_registers[REG_ESP]); return new_node; } @@ -4207,7 +4200,7 @@ static ir_node *gen_Phi(ir_node *node) copy_node_attr(irg, node, phi); be_duplicate_deps(node, phi); - arch_set_out_register_req(phi, 0, req); + arch_set_irn_register_req_out(phi, 0, req); be_enqueue_preds(node); @@ -4343,7 +4336,10 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) ir_node *new_val_high = be_transform_node(val_high); ir_node *in[2]; ir_node *sync, *fild, *res; - ir_node *store_low, *store_high; + ir_node *store_low; + ir_node *store_high; + ir_node *mem_low; + ir_node *mem_high; if (ia32_cg_config.use_sse2) { panic("ia32_l_LLtoFloat not implemented for SSE2"); @@ -4357,6 +4353,9 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) SET_IA32_ORIG_NODE(store_low, node); SET_IA32_ORIG_NODE(store_high, node); + mem_low = new_r_Proj(store_low, mode_M, pn_ia32_Store_M); + mem_high = new_r_Proj(store_high, mode_M, pn_ia32_Store_M); + set_ia32_use_frame(store_low); set_ia32_use_frame(store_high); set_ia32_op_type(store_low, ia32_AddrModeD); @@ -4365,8 +4364,8 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) set_ia32_ls_mode(store_high, mode_Is); add_ia32_am_offs_int(store_high, 4); - in[0] = store_low; - in[1] = store_high; + in[0] = mem_low; + in[1] = mem_high; sync = new_rd_Sync(dbgi, block, 2, in); /* do a fild */ @@ -4424,15 +4423,16 @@ static ir_node *gen_ia32_l_FloattoLL(ir_node *node) ir_node *frame = get_irg_frame(irg); ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val); ir_node *new_val = be_transform_node(val); - ir_node *fist, *mem; + ir_node *fist; - mem = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val, &fist); + fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val); SET_IA32_ORIG_NODE(fist, node); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); set_ia32_ls_mode(fist, mode_Ls); - return mem; + assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M); + return new_r_Proj(fist, mode_M, pn_ia32_vfist_M); } static ir_node *gen_Proj_l_FloattoLL(ir_node *node) @@ -4522,10 +4522,9 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node) static ir_node *gen_Proj_Load(ir_node *node) { ir_node *new_pred; - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *pred = get_Proj_pred(node); - dbg_info *dbgi = get_irn_dbg_info(node); - long proj = get_Proj_proj(node); + ir_node *pred = get_Proj_pred(node); + dbg_info *dbgi = get_irn_dbg_info(node); + long proj = get_Proj_proj(node); /* loads might be part of source address mode matches, so we don't * transform the ProjMs yet (with the exception of loads whose result is @@ -4546,57 +4545,58 @@ static ir_node *gen_Proj_Load(ir_node *node) /* renumber the proj */ new_pred = be_transform_node(pred); if (is_ia32_Load(new_pred)) { - switch (proj) { + switch ((pn_Load)proj) { case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Load_res); case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Load_M); - case pn_Load_X_regular: - return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_regular); } } else if (is_ia32_Conv_I2I(new_pred) || is_ia32_Conv_I2I8Bit(new_pred)) { set_irn_mode(new_pred, mode_T); - if (proj == pn_Load_res) { + switch ((pn_Load)proj) { + case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_res); - } else if (proj == pn_Load_M) { + case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_mem); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_regular); } } else if (is_ia32_xLoad(new_pred)) { - switch (proj) { + switch ((pn_Load)proj) { case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xLoad_res); case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xLoad_M); - case pn_Load_X_regular: - return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_regular); } } else if (is_ia32_vfld(new_pred)) { - switch (proj) { + switch ((pn_Load)proj) { case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res); case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M); - case pn_Load_X_regular: - return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_regular); } } else { /* can happen for ProJMs when source address mode happened for the @@ -4611,7 +4611,76 @@ static ir_node *gen_Proj_Load(ir_node *node) return new_rd_Proj(dbgi, new_pred, mode_M, 1); } - panic("No idea how to transform proj"); + panic("No idea how to transform Proj(Load) %+F", node); +} + +static ir_node *gen_Proj_Store(ir_node *node) +{ + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + dbg_info *dbgi = get_irn_dbg_info(node); + long pn = get_Proj_proj(node); + + if (is_ia32_Store(new_pred) || is_ia32_Store8Bit(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Store_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_regular); + } + } else if (is_ia32_vfist(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfist_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_regular); + } + } else if (is_ia32_vfisttp(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfisttp_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_regular); + } + } else if (is_ia32_vfst(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfst_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_regular); + } + } else if (is_ia32_xStore(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xStore_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_regular); + } + } else if (is_Sync(new_pred)) { + /* hack for the case that gen_float_const_Store produced a Sync */ + if (pn == pn_Store_M) { + return new_pred; + } + panic("exception control flow for gen_float_const_Store not implemented yet"); + } else if (get_ia32_op_type(new_pred) == ia32_AddrModeD) { + /* destination address mode */ + if (pn == pn_Store_M) { + return new_pred; + } + panic("exception control flow for destination AM not implemented yet"); + } + + panic("No idea how to transform Proj(Store) %+F", node); } /** @@ -4619,16 +4688,15 @@ static ir_node *gen_Proj_Load(ir_node *node) */ static ir_node *gen_Proj_Div(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); dbg_info *dbgi = get_irn_dbg_info(node); - long proj = get_Proj_proj(node); + long proj = get_Proj_proj(node); - assert(pn_ia32_Div_M == pn_ia32_IDiv_M); - assert(pn_ia32_Div_div_res == pn_ia32_IDiv_div_res); + assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M); + assert((long)pn_ia32_Div_div_res == (long)pn_ia32_IDiv_div_res); - switch (proj) { + switch ((pn_Div)proj) { case pn_Div_M: if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) { return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); @@ -4649,13 +4717,11 @@ static ir_node *gen_Proj_Div(ir_node *node) } else { panic("Div transformed to unexpected thing %+F", new_pred); } - case pn_Div_X_regular: - return new_rd_Jmp(dbgi, block); case pn_Div_X_except: set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except); + case pn_Div_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular); } panic("No idea how to transform proj->Div"); @@ -4672,19 +4738,19 @@ static ir_node *gen_Proj_Mod(ir_node *node) long proj = get_Proj_proj(node); assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)); - assert(pn_ia32_Div_M == pn_ia32_IDiv_M); - assert(pn_ia32_Div_mod_res == pn_ia32_IDiv_mod_res); + assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M); + assert((long)pn_ia32_Div_mod_res == (long)pn_ia32_IDiv_mod_res); - switch (proj) { + switch ((pn_Mod)proj) { case pn_Mod_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); case pn_Mod_res: return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res); case pn_Mod_X_except: set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except); + case pn_Mod_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular); } panic("No idea how to transform proj->Mod"); } @@ -4699,7 +4765,7 @@ static ir_node *gen_Proj_CopyB(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); - switch (proj) { + switch ((pn_CopyB)proj) { case pn_CopyB_M: if (is_ia32_CopyB_i(new_pred)) { return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M); @@ -4707,7 +4773,19 @@ static ir_node *gen_Proj_CopyB(ir_node *node) return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M); } break; - default: + case pn_CopyB_X_regular: + if (is_ia32_CopyB_i(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_regular); + } else if (is_ia32_CopyB(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_regular); + } + break; + case pn_CopyB_X_except: + if (is_ia32_CopyB_i(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_except); + } else if (is_ia32_CopyB(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_except); + } break; } @@ -4735,6 +4813,7 @@ static ir_node *gen_be_Call(ir_node *node) unsigned const pop = be_Call_get_pop(node); ir_type *const call_tp = be_Call_get_type(node); int old_no_pic_adjust; + int throws_exception = ir_throws_exception(node); /* Run the x87 simulator if the call returns a float value */ if (get_method_n_ress(call_tp) > 0) { @@ -4763,7 +4842,8 @@ static ir_node *gen_be_Call(ir_node *node) i = get_irn_arity(node) - 1; fpcw = be_transform_node(get_irn_n(node, i--)); for (; i >= n_be_Call_first_arg; --i) { - arch_register_req_t const *const req = arch_get_register_req(node, i); + arch_register_req_t const *const req + = arch_get_irn_register_req_in(node, i); ir_node *const reg_parm = be_transform_node(get_irn_n(node, i)); assert(req->type == arch_register_req_type_limited); @@ -4780,6 +4860,7 @@ static ir_node *gen_be_Call(ir_node *node) mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem); call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem, am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp); + ir_set_throws_exception(call, throws_exception); set_am_attributes(call, &am); call = fix_mem_proj(call, &am); @@ -4858,7 +4939,7 @@ static ir_node *gen_return_address(ir_node *node) assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res && (int)pn_ia32_Load_res == (int)pn_ia32_res); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); } SET_IA32_ORIG_NODE(load, node); @@ -4909,7 +4990,7 @@ static ir_node *gen_frame_address(ir_node *node) assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res && (int)pn_ia32_Load_res == (int)pn_ia32_res); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); } SET_IA32_ORIG_NODE(load, node); @@ -4922,7 +5003,7 @@ static ir_node *gen_frame_address(ir_node *node) static ir_node *gen_prefetch(ir_node *node) { dbg_info *dbgi; - ir_node *ptr, *block, *mem, *base, *index; + ir_node *ptr, *block, *mem, *base, *idx; ir_node *param, *new_node; long rw, locality; ir_tarval *tv; @@ -4941,8 +5022,8 @@ static ir_node *gen_prefetch(ir_node *node) memset(&addr, 0, sizeof(addr)); ptr = get_Builtin_param(node, 0); ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); - base = addr.base; - index = addr.index; + base = addr.base; + idx = addr.index; if (base == NULL) { base = noreg_GP; @@ -4950,10 +5031,10 @@ static ir_node *gen_prefetch(ir_node *node) base = be_transform_node(base); } - if (index == NULL) { - index = noreg_GP; + if (idx == NULL) { + idx = noreg_GP; } else { - index = be_transform_node(index); + idx = be_transform_node(idx); } dbgi = get_irn_dbg_info(node); @@ -4962,7 +5043,7 @@ static ir_node *gen_prefetch(ir_node *node) if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) { /* we have 3DNow!, this was already checked above */ - new_node = new_bd_ia32_PrefetchW(dbgi, block, base, index, mem); + new_node = new_bd_ia32_PrefetchW(dbgi, block, base, idx, mem); } else if (ia32_cg_config.use_sse_prefetch) { /* note: rw == 1 is IGNORED in that case */ param = get_Builtin_param(node, 2); @@ -4972,22 +5053,22 @@ static ir_node *gen_prefetch(ir_node *node) /* SSE style prefetch */ switch (locality) { case 0: - new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, index, mem); + new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, idx, mem); break; case 1: - new_node = new_bd_ia32_Prefetch2(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch2(dbgi, block, base, idx, mem); break; case 2: - new_node = new_bd_ia32_Prefetch1(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch1(dbgi, block, base, idx, mem); break; default: - new_node = new_bd_ia32_Prefetch0(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch0(dbgi, block, base, idx, mem); break; } } else { assert(ia32_cg_config.use_3dnow_prefetch); /* 3DNow! style prefetch */ - new_node = new_bd_ia32_Prefetch(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch(dbgi, block, base, idx, mem); } set_irn_pinned(new_node, get_irn_pinned(node)); @@ -5494,7 +5575,7 @@ static ir_node *gen_Proj_Builtin(ir_node *proj) static ir_node *gen_be_IncSP(ir_node *node) { ir_node *res = be_duplicate_node(node); - arch_irn_add_flags(res, arch_irn_flags_modify_flags); + arch_add_irn_flags(res, arch_irn_flags_modify_flags); return res; } @@ -5511,23 +5592,27 @@ static ir_node *gen_Proj_be_Call(ir_node *node) ir_mode *mode = get_irn_mode(node); ir_node *res; - if (proj == pn_be_Call_M_regular) { + if (proj == pn_be_Call_M) { return new_rd_Proj(dbgi, new_call, mode_M, n_ia32_Call_mem); } /* transform call modes */ if (mode_is_data(mode)) { - const arch_register_class_t *cls = arch_get_irn_reg_class_out(node); + const arch_register_class_t *cls = arch_get_irn_reg_class(node); mode = cls->mode; } /* Map from be_Call to ia32_Call proj number */ if (proj == pn_be_Call_sp) { proj = pn_ia32_Call_stack; - } else if (proj == pn_be_Call_M_regular) { + } else if (proj == pn_be_Call_M) { proj = pn_ia32_Call_M; + } else if (proj == pn_be_Call_X_except) { + proj = pn_ia32_Call_X_except; + } else if (proj == pn_be_Call_X_regular) { + proj = pn_ia32_Call_X_regular; } else { - arch_register_req_t const *const req = arch_get_register_req_out(node); - int const n_outs = arch_irn_get_n_outs(new_call); + arch_register_req_t const *const req = arch_get_irn_register_req(node); + int const n_outs = arch_get_irn_n_outs(new_call); int i; assert(proj >= pn_be_Call_first_res); @@ -5535,7 +5620,7 @@ static ir_node *gen_Proj_be_Call(ir_node *node) for (i = 0; i < n_outs; ++i) { arch_register_req_t const *const new_req - = arch_get_out_register_req(new_call, i); + = arch_get_irn_register_req_out(new_call, i); if (!(new_req->type & arch_register_req_type_limited) || new_req->cls != req->cls || @@ -5552,13 +5637,13 @@ static ir_node *gen_Proj_be_Call(ir_node *node) /* TODO arch_set_irn_register() only operates on Projs, need variant with index */ switch (proj) { - case pn_ia32_Call_stack: - arch_set_irn_register(res, &ia32_registers[REG_ESP]); - break; + case pn_ia32_Call_stack: + arch_set_irn_register(res, &ia32_registers[REG_ESP]); + break; - case pn_ia32_Call_fpcw: - arch_set_irn_register(res, &ia32_registers[REG_FPCW]); - break; + case pn_ia32_Call_fpcw: + arch_set_irn_register(res, &ia32_registers[REG_FPCW]); + break; } return res; @@ -5582,7 +5667,7 @@ static ir_node *gen_Proj_ASM(ir_node *node) long pos = get_Proj_proj(node); if (mode == mode_M) { - pos = arch_irn_get_n_outs(new_pred)-1; + pos = arch_get_irn_n_outs(new_pred)-1; } else if (mode_is_int(mode) || mode_is_reference(mode)) { mode = mode_Iu; } else if (mode_is_float(mode)) { @@ -5603,15 +5688,10 @@ static ir_node *gen_Proj(ir_node *node) long proj; switch (get_irn_opcode(pred)) { - case iro_Store: - proj = get_Proj_proj(node); - if (proj == pn_Store_M) { - return be_transform_node(pred); - } else { - panic("No idea how to transform proj->Store"); - } case iro_Load: return gen_Proj_Load(node); + case iro_Store: + return gen_Proj_Store(node); case iro_ASM: return gen_Proj_ASM(node); case iro_Builtin: @@ -5766,14 +5846,14 @@ static void postprocess_fp_call_results(void) ir_type *res_tp = get_method_res_type(mtp, j); ir_node *res, *new_res; const ir_edge_t *edge, *next; - ir_mode *mode; + ir_mode *res_mode; if (! is_atomic_type(res_tp)) { /* no floating point return */ continue; } - mode = get_type_mode(res_tp); - if (! mode_is_float(mode)) { + res_mode = get_type_mode(res_tp); + if (! mode_is_float(res_mode)) { /* no floating point return */ continue; } @@ -5794,12 +5874,13 @@ static void postprocess_fp_call_results(void) dbg_info *db = get_irn_dbg_info(succ); ir_node *block = get_nodes_block(succ); ir_node *base = get_irn_n(succ, n_ia32_xStore_base); - ir_node *index = get_irn_n(succ, n_ia32_xStore_index); + ir_node *idx = get_irn_n(succ, n_ia32_xStore_index); ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem); ir_node *value = get_irn_n(succ, n_ia32_xStore_val); ir_mode *mode = get_ia32_ls_mode(succ); - ir_node *st = new_bd_ia32_vfst(db, block, base, index, mem, value, mode); + ir_node *st = new_bd_ia32_vfst(db, block, base, idx, mem, value, mode); + //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_vfst_M); set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ)); if (is_ia32_use_frame(succ)) set_ia32_use_frame(st); @@ -5807,36 +5888,43 @@ static void postprocess_fp_call_results(void) set_irn_pinned(st, get_irn_pinned(succ)); set_ia32_op_type(st, ia32_AddrModeD); + assert((long)pn_ia32_xStore_M == (long)pn_ia32_vfst_M); + assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_vfst_X_regular); + assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_vfst_X_except); + exchange(succ, st); - } else { - if (new_res == NULL) { - dbg_info *db = get_irn_dbg_info(call); - ir_node *block = get_nodes_block(call); - ir_node *frame = get_irg_frame(current_ir_graph); - ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M); - ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M); - ir_node *vfst, *xld, *new_mem; - - /* store st(0) on stack */ - vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, res, mode); - set_ia32_op_type(vfst, ia32_AddrModeD); - set_ia32_use_frame(vfst); - - /* load into SSE register */ - xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst, mode); - set_ia32_op_type(xld, ia32_AddrModeS); - set_ia32_use_frame(xld); - - new_res = new_r_Proj(xld, mode, pn_ia32_xLoad_res); - new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M); - - if (old_mem != NULL) { - edges_reroute(old_mem, new_mem); - kill_node(old_mem); - } + } else if (new_res == NULL) { + dbg_info *db = get_irn_dbg_info(call); + ir_node *block = get_nodes_block(call); + ir_node *frame = get_irg_frame(current_ir_graph); + ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M); + ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M); + ir_node *vfst, *xld, *new_mem; + ir_node *vfst_mem; + + /* store st(0) on stack */ + vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, + res, res_mode); + set_ia32_op_type(vfst, ia32_AddrModeD); + set_ia32_use_frame(vfst); + + vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_vfst_M); + + /* load into SSE register */ + xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst_mem, + res_mode); + set_ia32_op_type(xld, ia32_AddrModeS); + set_ia32_use_frame(xld); + + new_res = new_r_Proj(xld, res_mode, pn_ia32_xLoad_res); + new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M); + + if (old_mem != NULL) { + edges_reroute(old_mem, new_mem); + kill_node(old_mem); } - set_irn_n(succ, get_edge_src_pos(edge), new_res); } + set_irn_n(succ, get_edge_src_pos(edge), new_res); } } }