X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=aaaf4d4fc5cb459c2672459df4e3174d855613c8;hb=77084aec066bb38f99b742f27e931827e5f52e04;hp=fd042eafa7236e1c3d9b9cfe62d6afdc457531b9;hpb=9b7f5d6dba8b8b5832185713253e1bad0c9f2871;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index fd042eafa..aaaf4d4fc 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -24,11 +24,10 @@ * @author Christian Wuerdig, Matthias Braun * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif #include +#include #include "irargs_t.h" #include "irnode_t.h" @@ -45,8 +44,8 @@ #include "irprintf.h" #include "debug.h" #include "irdom.h" -#include "archop.h" #include "error.h" +#include "array_t.h" #include "height.h" #include "../benode_t.h" @@ -76,18 +75,13 @@ #define SFP_ABS "0x7FFFFFFF" #define DFP_ABS "0x7FFFFFFFFFFFFFFF" #define DFP_INTMAX "9223372036854775807" +#define ULL_BIAS "18446744073709551616" -#define TP_SFP_SIGN "ia32_sfp_sign" -#define TP_DFP_SIGN "ia32_dfp_sign" -#define TP_SFP_ABS "ia32_sfp_abs" -#define TP_DFP_ABS "ia32_dfp_abs" -#define TP_INT_MAX "ia32_int_max" - -#define ENT_SFP_SIGN "IA32_SFP_SIGN" -#define ENT_DFP_SIGN "IA32_DFP_SIGN" -#define ENT_SFP_ABS "IA32_SFP_ABS" -#define ENT_DFP_ABS "IA32_DFP_ABS" -#define ENT_INT_MAX "IA32_INT_MAX" +#define ENT_SFP_SIGN ".LC_ia32_sfp_sign" +#define ENT_DFP_SIGN ".LC_ia32_dfp_sign" +#define ENT_SFP_ABS ".LC_ia32_sfp_abs" +#define ENT_DFP_ABS ".LC_ia32_dfp_abs" +#define ENT_ULL_BIAS ".LC_ia32_ull_bias" #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode) #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode) @@ -96,32 +90,28 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) static ir_node *initial_fpcw = NULL; -extern ir_op *get_op_Mulh(void); - -typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, - ir_node *block, ir_node *base, ir_node *index, ir_node *mem, - ir_node *op1, ir_node *op2); +typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block, + ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, + ir_node *op2); -typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg, - ir_node *block, ir_node *base, ir_node *index, ir_node *mem, - ir_node *op1, ir_node *op2, ir_node *flags); +typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_node *block, + ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2, + ir_node *flags); -typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg, - ir_node *block, ir_node *op1, ir_node *op2); +typedef ir_node *construct_shift_func(dbg_info *db, ir_node *block, + ir_node *op1, ir_node *op2); -typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg, - ir_node *block, ir_node *base, ir_node *index, ir_node *mem, - ir_node *op); +typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_node *block, + ir_node *base, ir_node *index, ir_node *mem, ir_node *op); -typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg, - ir_node *block, ir_node *base, ir_node *index, ir_node *mem); +typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_node *block, + ir_node *base, ir_node *index, ir_node *mem); -typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg, - ir_node *block, ir_node *base, ir_node *index, ir_node *mem, - ir_node *op1, ir_node *op2, ir_node *fpcw); +typedef ir_node *construct_binop_float_func(dbg_info *db, ir_node *block, + ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2, + ir_node *fpcw); -typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, - ir_node *block, ir_node *op); +typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op); static ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type); @@ -130,47 +120,53 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, dbg_info *dbgi, ir_node *block, ir_node *op, ir_node *orig_node); +/* its enough to have those once */ +static ir_node *nomem, *noreg_GP; + /** Return non-zero is a node represents the 0 constant. */ -static int is_Const_0(ir_node *node) { +static bool is_Const_0(ir_node *node) +{ return is_Const(node) && is_Const_null(node); } /** Return non-zero is a node represents the 1 constant. */ -static int is_Const_1(ir_node *node) { +static bool is_Const_1(ir_node *node) +{ return is_Const(node) && is_Const_one(node); } /** Return non-zero is a node represents the -1 constant. */ -static int is_Const_Minus_1(ir_node *node) { +static bool is_Const_Minus_1(ir_node *node) +{ return is_Const(node) && is_Const_all_one(node); } /** * returns true if constant can be created with a simple float command */ -static int is_simple_x87_Const(ir_node *node) +static bool is_simple_x87_Const(ir_node *node) { tarval *tv = get_Const_tarval(node); if (tarval_is_null(tv) || tarval_is_one(tv)) - return 1; + return true; /* TODO: match all the other float constants */ - return 0; + return false; } /** * returns true if constant can be created with a simple float command */ -static int is_simple_sse_Const(ir_node *node) +static bool is_simple_sse_Const(ir_node *node) { tarval *tv = get_Const_tarval(node); ir_mode *mode = get_tarval_mode(tv); if (mode == mode_F) - return 1; + return true; if (tarval_is_null(tv) || tarval_is_one(tv)) - return 1; + return true; if (mode == mode_D) { unsigned val = get_tarval_sub_bits(tv, 0) | @@ -179,36 +175,34 @@ static int is_simple_sse_Const(ir_node *node) (get_tarval_sub_bits(tv, 3) << 24); if (val == 0) /* lower 32bit are zero, really a 32bit constant */ - return 1; + return true; } /* TODO: match all the other float constants */ - return 0; + return false; } /** * Transforms a Const. */ -static ir_node *gen_Const(ir_node *node) { - ir_graph *irg = current_ir_graph; - ir_node *old_block = get_nodes_block(node); - ir_node *block = be_transform_node(old_block); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); +static ir_node *gen_Const(ir_node *node) +{ + ir_node *old_block = get_nodes_block(node); + ir_node *block = be_transform_node(old_block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); assert(is_Const(node)); if (mode_is_float(mode)) { ir_node *res = NULL; - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *load; ir_entity *floatent; if (ia32_cg_config.use_sse2) { tarval *tv = get_Const_tarval(node); if (tarval_is_null(tv)) { - load = new_rd_ia32_xZero(dbgi, irg, block); + load = new_bd_ia32_xZero(dbgi, block); set_ia32_ls_mode(load, mode); res = load; } else if (tarval_is_one(tv)) { @@ -217,11 +211,11 @@ static ir_node *gen_Const(ir_node *node) { ir_node *imm2 = create_Immediate(NULL, 0, 2); ir_node *pslld, *psrld; - load = new_rd_ia32_xAllOnes(dbgi, irg, block); + load = new_bd_ia32_xAllOnes(dbgi, block); set_ia32_ls_mode(load, mode); - pslld = new_rd_ia32_xPslld(dbgi, irg, block, load, imm1); + pslld = new_bd_ia32_xPslld(dbgi, block, load, imm1); set_ia32_ls_mode(pslld, mode); - psrld = new_rd_ia32_xPsrld(dbgi, irg, block, pslld, imm2); + psrld = new_bd_ia32_xPsrld(dbgi, block, pslld, imm2); set_ia32_ls_mode(psrld, mode); res = psrld; } else if (mode == mode_F) { @@ -230,8 +224,8 @@ static ir_node *gen_Const(ir_node *node) { (get_tarval_sub_bits(tv, 1) << 8) | (get_tarval_sub_bits(tv, 2) << 16) | (get_tarval_sub_bits(tv, 3) << 24); - ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val); - load = new_rd_ia32_xMovd(dbgi, irg, block, cnst); + ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val); + load = new_bd_ia32_xMovd(dbgi, block, cnst); set_ia32_ls_mode(load, mode); res = load; } else { @@ -249,10 +243,10 @@ static ir_node *gen_Const(ir_node *node) { (get_tarval_sub_bits(tv, 5) << 8) | (get_tarval_sub_bits(tv, 6) << 16) | (get_tarval_sub_bits(tv, 7) << 24); - cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val); - load = new_rd_ia32_xMovd(dbgi, irg, block, cnst); + cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val); + load = new_bd_ia32_xMovd(dbgi, block, cnst); set_ia32_ls_mode(load, mode); - psllq = new_rd_ia32_xPsllq(dbgi, irg, block, load, imm32); + psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32); set_ia32_ls_mode(psllq, mode); res = psllq; goto end; @@ -260,45 +254,41 @@ static ir_node *gen_Const(ir_node *node) { } floatent = create_float_const_entity(node); - load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, - mode); + load = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); - set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable); - res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res); + arch_irn_add_flags(load, arch_irn_flags_rematerializable); + res = new_r_Proj(current_ir_graph, block, load, mode_xmm, pn_ia32_xLoad_res); } } else { if (is_Const_null(node)) { - load = new_rd_ia32_vfldz(dbgi, irg, block); + load = new_bd_ia32_vfldz(dbgi, block); res = load; set_ia32_ls_mode(load, mode); } else if (is_Const_one(node)) { - load = new_rd_ia32_vfld1(dbgi, irg, block); + load = new_bd_ia32_vfld1(dbgi, block); res = load; set_ia32_ls_mode(load, mode); } else { + ir_mode *ls_mode; + floatent = create_float_const_entity(node); + /* create_float_const_ent is smart and sometimes creates + smaller entities */ + ls_mode = get_type_mode(get_entity_type(floatent)); - load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode); + load = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, + ls_mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); - set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable); - res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res); - /* take the mode from the entity */ - set_ia32_ls_mode(load, get_type_mode(get_entity_type(floatent))); + arch_irn_add_flags(load, arch_irn_flags_rematerializable); + res = new_r_Proj(current_ir_graph, block, load, mode_vfp, pn_ia32_vfld_res); } } end: - /* Const Nodes before the initial IncSP are a bad idea, because - * they could be spilled and we have no SP ready at that point yet. - * So add a dependency to the initial frame pointer calculation to - * avoid that situation. - */ - if (get_irg_start_block(irg) == block) { - add_irn_dep(load, get_irg_frame(irg)); - } + SET_IA32_ORIG_NODE(load, node); - SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); + be_dep_on_frame(load); return res; } else { /* non-float mode */ ir_node *cnst; @@ -313,14 +303,10 @@ end: } val = get_tarval_long(tv); - cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val); - SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node)); - - /* see above */ - if (get_irg_start_block(irg) == block) { - add_irn_dep(cnst, get_irg_frame(irg)); - } + cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val); + SET_IA32_ORIG_NODE(cnst, node); + be_dep_on_frame(cnst); return cnst; } } @@ -328,8 +314,8 @@ end: /** * Transforms a SymConst. */ -static ir_node *gen_SymConst(ir_node *node) { - ir_graph *irg = current_ir_graph; +static ir_node *gen_SymConst(ir_node *node) +{ ir_node *old_block = get_nodes_block(node); ir_node *block = be_transform_node(old_block); dbg_info *dbgi = get_irn_dbg_info(node); @@ -337,77 +323,171 @@ static ir_node *gen_SymConst(ir_node *node) { ir_node *cnst; if (mode_is_float(mode)) { - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); - if (ia32_cg_config.use_sse2) - cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E); + cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E); else - cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E); + cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E); set_ia32_am_sc(cnst, get_SymConst_entity(node)); set_ia32_use_frame(cnst); } else { ir_entity *entity; - if(get_SymConst_kind(node) != symconst_addr_ent) { + if (get_SymConst_kind(node) != symconst_addr_ent) { panic("backend only support symconst_addr_ent (at %+F)", node); } entity = get_SymConst_entity(node); - cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0); + cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0); } - /* Const Nodes before the initial IncSP are a bad idea, because - * they could be spilled and we have no SP ready at that point yet - */ - if (get_irg_start_block(irg) == block) { - add_irn_dep(cnst, get_irg_frame(irg)); + SET_IA32_ORIG_NODE(cnst, node); + + be_dep_on_frame(cnst); + return cnst; +} + +/** + * Create a float type for the given mode and cache it. + * + * @param mode the mode for the float type (might be integer mode for SSE2 types) + * @param align alignment + */ +static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { + char buf[32]; + ir_type *tp; + + assert(align <= 16); + + if (mode == mode_Iu) { + static ir_type *int_Iu[16] = {NULL, }; + + if (int_Iu[align] == NULL) { + snprintf(buf, sizeof(buf), "int_Iu_%u", align); + int_Iu[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + /* set the specified alignment */ + set_type_alignment_bytes(tp, align); + } + return int_Iu[align]; + } else if (mode == mode_Lu) { + static ir_type *int_Lu[16] = {NULL, }; + + if (int_Lu[align] == NULL) { + snprintf(buf, sizeof(buf), "int_Lu_%u", align); + int_Lu[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + /* set the specified alignment */ + set_type_alignment_bytes(tp, align); + } + return int_Lu[align]; + } else if (mode == mode_F) { + static ir_type *float_F[16] = {NULL, }; + + if (float_F[align] == NULL) { + snprintf(buf, sizeof(buf), "float_F_%u", align); + float_F[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + /* set the specified alignment */ + set_type_alignment_bytes(tp, align); + } + return float_F[align]; + } else if (mode == mode_D) { + static ir_type *float_D[16] = {NULL, }; + + if (float_D[align] == NULL) { + snprintf(buf, sizeof(buf), "float_D_%u", align); + float_D[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + /* set the specified alignment */ + set_type_alignment_bytes(tp, align); + } + return float_D[align]; + } else { + static ir_type *float_E[16] = {NULL, }; + + if (float_E[align] == NULL) { + snprintf(buf, sizeof(buf), "float_E_%u", align); + float_E[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + /* set the specified alignment */ + set_type_alignment_bytes(tp, align); + } + return float_E[align]; } +} - SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node)); +/** + * Create a float[2] array type for the given atomic type. + * + * @param tp the atomic type + */ +static ir_type *ia32_create_float_array(ir_type *tp) { + char buf[32]; + ir_mode *mode = get_type_mode(tp); + unsigned align = get_type_alignment_bytes(tp); + ir_type *arr; + + assert(align <= 16); + + if (mode == mode_F) { + static ir_type *float_F[16] = {NULL, }; + + if (float_F[align] != NULL) + return float_F[align]; + snprintf(buf, sizeof(buf), "arr_float_F_%u", align); + arr = float_F[align] = new_type_array(new_id_from_str(buf), 1, tp); + } else if (mode == mode_D) { + static ir_type *float_D[16] = {NULL, }; + + if (float_D[align] != NULL) + return float_D[align]; + snprintf(buf, sizeof(buf), "arr_float_D_%u", align); + arr = float_D[align] = new_type_array(new_id_from_str(buf), 1, tp); + } else { + static ir_type *float_E[16] = {NULL, }; - return cnst; + if (float_E[align] != NULL) + return float_E[align]; + snprintf(buf, sizeof(buf), "arr_float_E_%u", align); + arr = float_E[align] = new_type_array(new_id_from_str(buf), 1, tp); + } + set_type_alignment_bytes(arr, align); + set_type_size_bytes(arr, 2 * get_type_size_bytes(tp)); + set_type_state(arr, layout_fixed); + return arr; } /* Generates an entity for a known FP const (used for FP Neg + Abs) */ -ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) { +ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) +{ static const struct { - const char *tp_name; const char *ent_name; const char *cnst_str; char mode; - char align; + unsigned char align; } names [ia32_known_const_max] = { - { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */ - { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */ - { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */ - { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */ - { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */ + { ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */ + { ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */ + { ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */ + { ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */ + { ENT_ULL_BIAS, ULL_BIAS, 2, 4 } /* ia32_ULLBIAS */ }; static ir_entity *ent_cache[ia32_known_const_max]; - const char *tp_name, *ent_name, *cnst_str; + const char *ent_name, *cnst_str; ir_type *tp; - ir_node *cnst; - ir_graph *rem; ir_entity *ent; tarval *tv; ir_mode *mode; ent_name = names[kct].ent_name; if (! ent_cache[kct]) { - tp_name = names[kct].tp_name; cnst_str = names[kct].cnst_str; switch (names[kct].mode) { case 0: mode = mode_Iu; break; case 1: mode = mode_Lu; break; - default: mode = mode_F; break; + default: mode = mode_F; break; } tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode); - tp = new_type_primitive(new_id_from_str(tp_name), mode); - /* set the specified alignment */ - set_type_alignment_bytes(tp, names[kct].align); + tp = ia32_create_float_type(mode, names[kct].align); + if (kct == ia32_ULLBIAS) + tp = ia32_create_float_array(tp); ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp); set_entity_ld_ident(ent, get_entity_ident(ent)); @@ -415,14 +495,18 @@ ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) { set_entity_variability(ent, variability_constant); set_entity_allocation(ent, allocation_static); - /* we create a new entity here: It's initialization must resist on the - const code irg */ - rem = current_ir_graph; - current_ir_graph = get_const_code_irg(); - cnst = new_Const(mode, tv); - current_ir_graph = rem; + if (kct == ia32_ULLBIAS) { + ir_initializer_t *initializer = create_initializer_compound(2); - set_atomic_ent_value(ent, cnst); + set_initializer_compound_value(initializer, 0, + create_initializer_tarval(get_tarval_null(mode))); + set_initializer_compound_value(initializer, 1, + create_initializer_tarval(tv)); + + set_entity_initializer(ent, initializer); + } else { + set_entity_initializer(ent, create_initializer_tarval(tv)); + } /* cache the entry */ ent_cache[kct] = ent; @@ -431,44 +515,6 @@ ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) { return ent_cache[kct]; } -static int prevents_AM(ir_node *const block, ir_node *const am_candidate, - ir_node *const other) -{ - if (get_nodes_block(other) != block) - return 0; - - if (is_Sync(other)) { - int i; - - for (i = get_Sync_n_preds(other) - 1; i >= 0; --i) { - ir_node *const pred = get_Sync_pred(other, i); - - if (get_nodes_block(pred) != block) - continue; - - /* Do not block ourselves from getting eaten */ - if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate) - continue; - - if (!heights_reachable_in_block(heights, pred, am_candidate)) - continue; - - return 1; - } - - return 0; - } else { - /* Do not block ourselves from getting eaten */ - if (is_Proj(other) && get_Proj_pred(other) == am_candidate) - return 0; - - if (!heights_reachable_in_block(heights, other, am_candidate)) - return 0; - - return 1; - } -} - /** * return true if the node is a Proj(Load) and could be used in source address * mode for another node. Will return only true if the @p other node is not @@ -541,22 +587,19 @@ struct ia32_address_mode_t { static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem) { - ir_node *noreg_gp; - /* construct load address */ memset(addr, 0, sizeof(addr[0])); - ia32_create_address_mode(addr, ptr, /*force=*/0); + ia32_create_address_mode(addr, ptr, 0); - noreg_gp = ia32_new_NoReg_gp(env_cg); - addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp; - addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp; + addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP; + addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP; addr->mem = be_transform_node(mem); } -static void build_address(ia32_address_mode_t *am, ir_node *node) +static void build_address(ia32_address_mode_t *am, ir_node *node, + ia32_create_am_flags_t flags) { - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ia32_address_t *addr = &am->addr; + ia32_address_t *addr = &am->addr; ir_node *load; ir_node *ptr; ir_node *mem; @@ -564,9 +607,9 @@ static void build_address(ia32_address_mode_t *am, ir_node *node) if (is_Const(node)) { ir_entity *entity = create_float_const_entity(node); - addr->base = noreg_gp; - addr->index = noreg_gp; - addr->mem = new_NoMem(); + addr->base = noreg_GP; + addr->index = noreg_GP; + addr->mem = nomem; addr->symconst_ent = entity; addr->use_frame = 1; am->ls_mode = get_type_mode(get_entity_type(entity)); @@ -584,10 +627,10 @@ static void build_address(ia32_address_mode_t *am, ir_node *node) am->am_node = node; /* construct load address */ - ia32_create_address_mode(addr, ptr, /*force=*/0); + ia32_create_address_mode(addr, ptr, flags); - addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp; - addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp; + addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP; + addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP; addr->mem = new_mem; } @@ -596,9 +639,9 @@ static void set_address(ir_node *node, const ia32_address_t *addr) set_ia32_am_scale(node, addr->scale); set_ia32_am_sc(node, addr->symconst_ent); set_ia32_am_offs_int(node, addr->offset); - if(addr->symconst_sign) + if (addr->symconst_sign) set_ia32_am_sc_sign(node); - if(addr->use_frame) + if (addr->use_frame) set_ia32_use_frame(node); set_ia32_frame_ent(node, addr->frame_entity); } @@ -634,24 +677,26 @@ static int is_downconv(const ir_node *node) ir_mode *src_mode; ir_mode *dest_mode; - if(!is_Conv(node)) + if (!is_Conv(node)) return 0; /* we only want to skip the conv when we're the only user * (not optimal but for now...) */ - if(get_irn_n_edges(node) > 1) + if (get_irn_n_edges(node) > 1) return 0; src_mode = get_irn_mode(get_Conv_op(node)); dest_mode = get_irn_mode(node); - return ia32_mode_needs_gp_reg(src_mode) - && ia32_mode_needs_gp_reg(dest_mode) - && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode); + return + ia32_mode_needs_gp_reg(src_mode) && + ia32_mode_needs_gp_reg(dest_mode) && + get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode); } /* Skip all Down-Conv's on a given node and return the resulting node. */ -ir_node *ia32_skip_downconv(ir_node *node) { +ir_node *ia32_skip_downconv(ir_node *node) +{ while (is_downconv(node)) node = get_Conv_op(node); @@ -665,7 +710,7 @@ static ir_node *create_upconv(ir_node *node, ir_node *orig_node) ir_mode *tgt_mode; dbg_info *dbgi; - if(mode_is_signed(mode)) { + if (mode_is_signed(mode)) { tgt_mode = mode_Is; } else { tgt_mode = mode_Iu; @@ -694,7 +739,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, ia32_address_t *addr = &am->addr; ir_mode *mode = get_irn_mode(op2); int mode_bits = get_mode_size_bits(mode); - ir_node *noreg_gp, *new_op1, *new_op2; + ir_node *new_op1, *new_op2; int use_am; unsigned commutative; int use_am_and_immediates; @@ -713,16 +758,9 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, assert(use_am || !(flags & match_8bit_am)); assert(use_am || !(flags & match_16bit_am)); - if (mode_bits == 8) { - if (!(flags & match_8bit_am)) - use_am = 0; - /* we don't automatically add upconvs yet */ - assert((flags & match_mode_neutral) || (flags & match_8bit)); - } else if (mode_bits == 16) { - if (!(flags & match_16bit_am)) - use_am = 0; - /* we don't automatically add upconvs yet */ - assert((flags & match_mode_neutral) || (flags & match_16bit)); + if ((mode_bits == 8 && !(flags & match_8bit_am)) || + (mode_bits == 16 && !(flags & match_16bit_am))) { + use_am = 0; } /* we can simply skip downconvs for mode neutral nodes: the upper bits @@ -741,27 +779,26 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, new_op2 = try_create_Immediate(op2, 0); } - noreg_gp = ia32_new_NoReg_gp(env_cg); if (new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) { - build_address(am, op2); + build_address(am, op2, 0); new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); if (mode_is_float(mode)) { new_op2 = ia32_new_NoReg_vfp(env_cg); } else { - new_op2 = noreg_gp; + new_op2 = noreg_GP; } am->op_type = ia32_AddrModeS; } else if (commutative && (new_op2 == NULL || use_am_and_immediates) && use_am && ia32_use_source_address_mode(block, op1, op2, other_op, flags)) { ir_node *noreg; - build_address(am, op1); + build_address(am, op1, 0); if (mode_is_float(mode)) { noreg = ia32_new_NoReg_vfp(env_cg); } else { - noreg = noreg_gp; + noreg = noreg_GP; } if (new_op2 != NULL) { @@ -773,27 +810,26 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } am->op_type = ia32_AddrModeS; } else { + am->op_type = ia32_Normal; + if (flags & match_try_am) { am->new_op1 = NULL; am->new_op2 = NULL; - am->op_type = ia32_Normal; return; } new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); if (new_op2 == NULL) new_op2 = be_transform_node(op2); - am->op_type = ia32_Normal; - am->ls_mode = get_irn_mode(op2); - if (flags & match_mode_neutral) - am->ls_mode = mode_Iu; + am->ls_mode = + (flags & match_mode_neutral ? mode_Iu : get_irn_mode(op2)); } if (addr->base == NULL) - addr->base = noreg_gp; + addr->base = noreg_GP; if (addr->index == NULL) - addr->index = noreg_gp; + addr->index = noreg_GP; if (addr->mem == NULL) - addr->mem = new_NoMem(); + addr->mem = nomem; am->new_op1 = new_op1; am->new_op2 = new_op2; @@ -812,7 +848,6 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) mode = get_irn_mode(node); load = get_Proj_pred(am->mem_proj); - mark_irn_visited(load); be_set_transformed_node(load, node); if (mode != mode_T) { @@ -845,14 +880,14 @@ static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2, dbgi = get_irn_dbg_info(node); new_block = be_transform_node(block); - new_node = func(dbgi, current_ir_graph, new_block, - addr->base, addr->index, addr->mem, - am.new_op1, am.new_op2); + new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem, + am.new_op1, am.new_op2); set_am_attributes(new_node, &am); /* we can't use source address mode anymore when using immediates */ - if (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) - set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + if (!(flags & match_am_and_immediates) && + (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))) + set_ia32_am_support(new_node, ia32_am_none); + SET_IA32_ORIG_NODE(new_node, node); new_node = fix_mem_proj(new_node, &am); @@ -896,13 +931,14 @@ static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, dbgi = get_irn_dbg_info(node); block = be_transform_node(src_block); new_eflags = be_transform_node(eflags); - new_node = func(dbgi, current_ir_graph, block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, new_eflags); + new_node = func(dbgi, block, addr->base, addr->index, addr->mem, + am.new_op1, am.new_op2, new_eflags); set_am_attributes(new_node, &am); /* we can't use source address mode anymore when using immediates */ - if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) - set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + if (!(flags & match_am_and_immediates) && + (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))) + set_ia32_am_support(new_node, ia32_am_none); + SET_IA32_ORIG_NODE(new_node, node); new_node = fix_mem_proj(new_node, &am); @@ -931,30 +967,35 @@ static ir_node *get_fpcw(void) * @return The constructed ia32 node. */ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, - construct_binop_float_func *func, - match_flags_t flags) + construct_binop_float_func *func) { ir_mode *mode = get_irn_mode(node); dbg_info *dbgi; ir_node *block, *new_block, *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; + ia32_x87_attr_t *attr; + /* All operations are considered commutative, because there are reverse + * variants */ + match_flags_t flags = match_commutative; /* cannot use address mode with long double on x87 */ - if (get_mode_size_bits(mode) > 64) - flags &= ~match_am; + if (get_mode_size_bits(mode) <= 64) + flags |= match_am; block = get_nodes_block(node); match_arguments(&am, block, op1, op2, NULL, flags); dbgi = get_irn_dbg_info(node); new_block = be_transform_node(block); - new_node = func(dbgi, current_ir_graph, new_block, - addr->base, addr->index, addr->mem, - am.new_op1, am.new_op2, get_fpcw()); + new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem, + am.new_op1, am.new_op2, get_fpcw()); set_am_attributes(new_node, &am); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + attr = get_ia32_x87_attr(new_node); + attr->attr.data.ins_permuted = am.ins_permuted; + + SET_IA32_ORIG_NODE(new_node, node); new_node = fix_mem_proj(new_node, &am); @@ -1003,8 +1044,8 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); new_block = be_transform_node(block); - new_node = func(dbgi, current_ir_graph, new_block, new_op1, new_op2); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + new_node = func(dbgi, new_block, new_op1, new_op2); + SET_IA32_ORIG_NODE(new_node, node); /* lowered shift instruction may have a dependency operand, handle it here */ if (get_irn_arity(node) == 3) { @@ -1039,9 +1080,9 @@ static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); new_block = be_transform_node(block); - new_node = func(dbgi, current_ir_graph, new_block, new_op); + new_node = func(dbgi, new_block, new_op); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -1053,19 +1094,19 @@ static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, base = addr->base; if (base == NULL) { - base = ia32_new_NoReg_gp(env_cg); + base = noreg_GP; } else { base = be_transform_node(base); } index = addr->index; if (index == NULL) { - index = ia32_new_NoReg_gp(env_cg); + index = noreg_GP; } else { index = be_transform_node(index); } - res = new_rd_ia32_Lea(dbgi, current_ir_graph, block, base, index); + res = new_bd_ia32_Lea(dbgi, block, base, index); set_address(res, addr); return res; @@ -1086,7 +1127,8 @@ static int am_has_immediates(const ia32_address_t *addr) * * @return the created ia32 Add node */ -static ir_node *gen_Add(ir_node *node) { +static ir_node *gen_Add(ir_node *node) +{ ir_mode *mode = get_irn_mode(node); ir_node *op1 = get_Add_left(node); ir_node *op2 = get_Add_right(node); @@ -1097,11 +1139,10 @@ static ir_node *gen_Add(ir_node *node) { if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) - return gen_binop(node, op1, op2, new_rd_ia32_xAdd, + return gen_binop(node, op1, op2, new_bd_ia32_xAdd, match_commutative | match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, - match_commutative | match_am); + return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfadd); } ia32_mark_non_am(node); @@ -1117,7 +1158,7 @@ static ir_node *gen_Add(ir_node *node) { * 3. Otherwise -> Lea */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, node, /*force=*/1); + ia32_create_address_mode(&addr, node, ia32_create_am_force); add_immediate_op = NULL; dbgi = get_irn_dbg_info(node); @@ -1125,23 +1166,22 @@ static ir_node *gen_Add(ir_node *node) { new_block = be_transform_node(block); /* a constant? */ - if(addr.base == NULL && addr.index == NULL) { - ir_graph *irg = current_ir_graph; - new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent, + if (addr.base == NULL && addr.index == NULL) { + new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent, addr.symconst_sign, addr.offset); - add_irn_dep(new_node, get_irg_frame(irg)); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + be_dep_on_frame(new_node); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } /* add with immediate? */ - if(addr.index == NULL) { + if (addr.index == NULL) { add_immediate_op = addr.base; - } else if(addr.base == NULL && addr.scale == 0) { + } else if (addr.base == NULL && addr.scale == 0) { add_immediate_op = addr.index; } - if(add_immediate_op != NULL) { - if(!am_has_immediates(&addr)) { + if (add_immediate_op != NULL) { + if (!am_has_immediates(&addr)) { #ifdef DEBUG_libfirm ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n", node); @@ -1150,7 +1190,7 @@ static ir_node *gen_Add(ir_node *node) { } new_node = create_lea_from_address(dbgi, new_block, &addr); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -1160,13 +1200,12 @@ static ir_node *gen_Add(ir_node *node) { /* construct an Add with source address mode */ if (am.op_type == ia32_AddrModeS) { - ir_graph *irg = current_ir_graph; ia32_address_t *am_addr = &am.addr; - new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base, + new_node = new_bd_ia32_Add(dbgi, new_block, am_addr->base, am_addr->index, am_addr->mem, am.new_op1, am.new_op2); set_am_attributes(new_node, &am); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); new_node = fix_mem_proj(new_node, &am); @@ -1175,7 +1214,7 @@ static ir_node *gen_Add(ir_node *node) { /* otherwise construct a lea */ new_node = create_lea_from_address(dbgi, new_block, &addr); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -1184,20 +1223,20 @@ static ir_node *gen_Add(ir_node *node) { * * @return the created ia32 Mul node */ -static ir_node *gen_Mul(ir_node *node) { +static ir_node *gen_Mul(ir_node *node) +{ ir_node *op1 = get_Mul_left(node); ir_node *op2 = get_Mul_right(node); ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) - return gen_binop(node, op1, op2, new_rd_ia32_xMul, + return gen_binop(node, op1, op2, new_bd_ia32_xMul, match_commutative | match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, - match_commutative | match_am); + return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfmul); } - return gen_binop(node, op1, op2, new_rd_ia32_IMul, + return gen_binop(node, op1, op2, new_bd_ia32_IMul, match_commutative | match_am | match_mode_neutral | match_immediate | match_am_and_immediates); } @@ -1211,58 +1250,34 @@ static ir_node *gen_Mul(ir_node *node) { */ static ir_node *gen_Mulh(ir_node *node) { - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *op1 = get_Mulh_left(node); - ir_node *op2 = get_Mulh_right(node); - ir_node *proj_res_high; - ir_node *new_node; - ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; - - assert(!mode_is_float(mode) && "Mulh with float not supported"); - assert(get_mode_size_bits(mode) == 32); - - match_arguments(&am, block, op1, op2, NULL, match_commutative | match_am); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *op1 = get_Mulh_left(node); + ir_node *op2 = get_Mulh_right(node); + ir_mode *mode = get_irn_mode(node); + ir_node *new_node; + ir_node *proj_res_high; if (mode_is_signed(mode)) { - new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2); + new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am); + proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node, + mode_Iu, pn_ia32_IMul1OP_res_high); } else { - new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2); + new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am); + proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node, + mode_Iu, pn_ia32_Mul_res_high); } - - set_am_attributes(new_node, &am); - /* we can't use source address mode anymore when using immediates */ - if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) - set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - - assert(get_irn_mode(new_node) == mode_T); - - fix_mem_proj(new_node, &am); - - assert(pn_ia32_IMul1OP_res_high == pn_ia32_Mul_res_high); - proj_res_high = new_rd_Proj(dbgi, irg, block, new_node, - mode_Iu, pn_ia32_IMul1OP_res_high); - return proj_res_high; } - - /** * Creates an ia32 And. * * @return The created ia32 And node */ -static ir_node *gen_And(ir_node *node) { +static ir_node *gen_And(ir_node *node) +{ ir_node *op1 = get_And_left(node); ir_node *op2 = get_And_right(node); assert(! mode_is_float(get_irn_mode(node))); @@ -1278,7 +1293,7 @@ static ir_node *gen_And(ir_node *node) { ir_mode *src_mode; ir_node *res; - if(v == 0xFF) { + if (v == 0xFF) { src_mode = mode_Bu; } else { assert(v == 0xFFFF); @@ -1289,9 +1304,8 @@ static ir_node *gen_And(ir_node *node) { return res; } } - return gen_binop(node, op1, op2, new_rd_ia32_And, - match_commutative | match_mode_neutral | match_am - | match_immediate); + return gen_binop(node, op1, op2, new_bd_ia32_And, + match_commutative | match_mode_neutral | match_am | match_immediate); } @@ -1301,12 +1315,13 @@ static ir_node *gen_And(ir_node *node) { * * @return The created ia32 Or node */ -static ir_node *gen_Or(ir_node *node) { +static ir_node *gen_Or(ir_node *node) +{ ir_node *op1 = get_Or_left(node); ir_node *op2 = get_Or_right(node); assert (! mode_is_float(get_irn_mode(node))); - return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative + return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative | match_mode_neutral | match_am | match_immediate); } @@ -1317,12 +1332,13 @@ static ir_node *gen_Or(ir_node *node) { * * @return The created ia32 Eor node */ -static ir_node *gen_Eor(ir_node *node) { +static ir_node *gen_Eor(ir_node *node) +{ ir_node *op1 = get_Eor_left(node); ir_node *op2 = get_Eor_right(node); assert(! mode_is_float(get_irn_mode(node))); - return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative + return gen_binop(node, op1, op2, new_bd_ia32_Xor, match_commutative | match_mode_neutral | match_am | match_immediate); } @@ -1332,17 +1348,17 @@ static ir_node *gen_Eor(ir_node *node) { * * @return The created ia32 Sub node */ -static ir_node *gen_Sub(ir_node *node) { +static ir_node *gen_Sub(ir_node *node) +{ ir_node *op1 = get_Sub_left(node); ir_node *op2 = get_Sub_right(node); ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) - return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am); + return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, - match_am); + return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfsub); } if (is_Const(op2)) { @@ -1350,7 +1366,7 @@ static ir_node *gen_Sub(ir_node *node) { node); } - return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral + return gen_binop(node, op1, op2, new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate); } @@ -1375,6 +1391,9 @@ static ir_node *transform_AM_mem(ir_graph *const irg, ir_node *const block, NEW_ARR_A(ir_node*, ins, arity + 1); + /* NOTE: This sometimes produces dead-code because the old sync in + * src_mem might not be used anymore, we should detect this case + * and kill the sync... */ for (i = arity - 1; i >= 0; --i) { ir_node *const pred = get_Sync_pred(src_mem, i); @@ -1397,13 +1416,30 @@ static ir_node *transform_AM_mem(ir_graph *const irg, ir_node *const block, } } +static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block, + ir_node *val, const ir_node *orig) +{ + ir_node *res; + + (void)orig; + if (ia32_cg_config.use_short_sex_eax) { + ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block); + be_dep_on_frame(pval); + res = new_bd_ia32_Cltd(dbgi, block, val, pval); + } else { + ir_node *imm31 = create_Immediate(NULL, 0, 31); + res = new_bd_ia32_Sar(dbgi, block, val, imm31); + } + SET_IA32_ORIG_NODE(res, orig); + return res; +} + /** * Generates an ia32 DivMod with additional infrastructure for the * register allocator if needed. */ static ir_node *create_Div(ir_node *node) { - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); @@ -1446,22 +1482,17 @@ static ir_node *create_Div(ir_node *node) /* Beware: We don't need a Sync, if the memory predecessor of the Div node is the memory of the consumed address. We can have only the second op as address in Div nodes, so check only op2. */ - new_mem = transform_AM_mem(irg, block, op2, mem, addr->mem); + new_mem = transform_AM_mem(current_ir_graph, block, op2, mem, addr->mem); if (mode_is_signed(mode)) { - ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block); - add_irn_dep(produceval, get_irg_frame(irg)); - sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1, - produceval); - - new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base, - addr->index, new_mem, am.new_op2, - am.new_op1, sign_extension); + sign_extension = create_sex_32_64(dbgi, new_block, am.new_op1, node); + new_node = new_bd_ia32_IDiv(dbgi, new_block, addr->base, + addr->index, new_mem, am.new_op2, am.new_op1, sign_extension); } else { - sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0); - add_irn_dep(sign_extension, get_irg_frame(irg)); + sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0); + be_dep_on_frame(sign_extension); - new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base, + new_node = new_bd_ia32_Div(dbgi, new_block, addr->base, addr->index, new_mem, am.new_op2, am.new_op1, sign_extension); } @@ -1469,7 +1500,7 @@ static ir_node *create_Div(ir_node *node) set_irn_pinned(new_node, get_irn_pinned(node)); set_am_attributes(new_node, &am); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); new_node = fix_mem_proj(new_node, &am); @@ -1477,15 +1508,18 @@ static ir_node *create_Div(ir_node *node) } -static ir_node *gen_Mod(ir_node *node) { +static ir_node *gen_Mod(ir_node *node) +{ return create_Div(node); } -static ir_node *gen_Div(ir_node *node) { +static ir_node *gen_Div(ir_node *node) +{ return create_Div(node); } -static ir_node *gen_DivMod(ir_node *node) { +static ir_node *gen_DivMod(ir_node *node) +{ return create_Div(node); } @@ -1502,9 +1536,9 @@ static ir_node *gen_Quot(ir_node *node) ir_node *op2 = get_Quot_right(node); if (ia32_cg_config.use_sse2) { - return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am); + return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am); } else { - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am); + return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv); } } @@ -1514,11 +1548,12 @@ static ir_node *gen_Quot(ir_node *node) * * @return The created ia32 Shl node */ -static ir_node *gen_Shl(ir_node *node) { +static ir_node *gen_Shl(ir_node *node) +{ ir_node *left = get_Shl_left(node); ir_node *right = get_Shl_right(node); - return gen_shift_binop(node, left, right, new_rd_ia32_Shl, + return gen_shift_binop(node, left, right, new_bd_ia32_Shl, match_mode_neutral | match_immediate); } @@ -1527,11 +1562,12 @@ static ir_node *gen_Shl(ir_node *node) { * * @return The created ia32 Shr node */ -static ir_node *gen_Shr(ir_node *node) { +static ir_node *gen_Shr(ir_node *node) +{ ir_node *left = get_Shr_left(node); ir_node *right = get_Shr_right(node); - return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate); + return gen_shift_binop(node, left, right, new_bd_ia32_Shr, match_immediate); } @@ -1541,44 +1577,40 @@ static ir_node *gen_Shr(ir_node *node) { * * @return The created ia32 Shrs node */ -static ir_node *gen_Shrs(ir_node *node) { +static ir_node *gen_Shrs(ir_node *node) +{ ir_node *left = get_Shrs_left(node); ir_node *right = get_Shrs_right(node); - ir_mode *mode = get_irn_mode(node); - if(is_Const(right) && mode == mode_Is) { + if (is_Const(right)) { tarval *tv = get_Const_tarval(right); long val = get_tarval_long(tv); - if(val == 31) { + if (val == 31) { /* this is a sign extension */ - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op = left; - ir_node *new_op = be_transform_node(op); - ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block); - add_irn_dep(pval, get_irg_frame(irg)); + ir_node *new_op = be_transform_node(left); - return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval); + return create_sex_32_64(dbgi, block, new_op, node); } } /* 8 or 16 bit sign extension? */ - if(is_Const(right) && is_Shl(left) && mode == mode_Is) { + if (is_Const(right) && is_Shl(left)) { ir_node *shl_left = get_Shl_left(left); ir_node *shl_right = get_Shl_right(left); - if(is_Const(shl_right)) { + if (is_Const(shl_right)) { tarval *tv1 = get_Const_tarval(right); tarval *tv2 = get_Const_tarval(shl_right); - if(tv1 == tv2 && tarval_is_long(tv1)) { + if (tv1 == tv2 && tarval_is_long(tv1)) { long val = get_tarval_long(tv1); - if(val == 16 || val == 24) { + if (val == 16 || val == 24) { dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); ir_mode *src_mode; ir_node *res; - if(val == 24) { + if (val == 24) { src_mode = mode_Bs; } else { assert(val == 16); @@ -1593,7 +1625,7 @@ static ir_node *gen_Shrs(ir_node *node) { } } - return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate); + return gen_shift_binop(node, left, right, new_bd_ia32_Sar, match_immediate); } @@ -1605,8 +1637,9 @@ static ir_node *gen_Shrs(ir_node *node) { * @param op2 The second operator * @return The created ia32 RotL node */ -static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) { - return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate); +static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) +{ + return gen_shift_binop(node, op1, op2, new_bd_ia32_Rol, match_immediate); } @@ -1620,8 +1653,9 @@ static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) { * @param op2 The second operator * @return The created ia32 RotR node */ -static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) { - return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate); +static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) +{ + return gen_shift_binop(node, op1, op2, new_bd_ia32_Ror, match_immediate); } @@ -1631,7 +1665,8 @@ static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) { * * @return The created ia32 RotL or RotR node */ -static ir_node *gen_Rotl(ir_node *node) { +static ir_node *gen_Rotl(ir_node *node) +{ ir_node *rotate = NULL; ir_node *op1 = get_Rotl_left(node); ir_node *op2 = get_Rotl_right(node); @@ -1678,7 +1713,6 @@ static ir_node *gen_Minus(ir_node *node) { ir_node *op = get_Minus_op(node); ir_node *block = be_transform_node(get_nodes_block(node)); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); ir_entity *ent; @@ -1691,11 +1725,9 @@ static ir_node *gen_Minus(ir_node *node) /* TODO: non-optimal... if we have many xXors, then we should * rather create a load for the const and use that instead of * several AM nodes... */ - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg); - ir_node *nomem = new_rd_NoMem(irg); - new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, + new_node = new_bd_ia32_xXor(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, noreg_xmm); size = get_mode_size_bits(mode); @@ -1705,13 +1737,13 @@ static ir_node *gen_Minus(ir_node *node) set_ia32_op_type(new_node, ia32_AddrModeS); set_ia32_ls_mode(new_node, mode); } else { - new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op); + new_node = new_bd_ia32_vfchs(dbgi, block, new_op); } } else { - new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral); + new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral); } - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -1721,13 +1753,14 @@ static ir_node *gen_Minus(ir_node *node) * * @return The created ia32 Not node */ -static ir_node *gen_Not(ir_node *node) { +static ir_node *gen_Not(ir_node *node) +{ ir_node *op = get_Not_op(node); assert(get_irn_mode(node) != mode_b); /* should be lowered already */ assert (! mode_is_float(get_irn_mode(node))); - return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral); + return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral); } @@ -1742,11 +1775,8 @@ static ir_node *gen_Abs(ir_node *node) ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); ir_node *op = get_Abs_op(node); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *new_op; ir_node *new_node; int size; @@ -1757,7 +1787,7 @@ static ir_node *gen_Abs(ir_node *node) if (ia32_cg_config.use_sse2) { ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg); - new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp, + new_node = new_bd_ia32_xAnd(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, noreg_fp); size = get_mode_size_bits(mode); @@ -1765,16 +1795,16 @@ static ir_node *gen_Abs(ir_node *node) set_ia32_am_sc(new_node, ent); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); set_ia32_op_type(new_node, ia32_AddrModeS); set_ia32_ls_mode(new_node, mode); } else { - new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op); + SET_IA32_ORIG_NODE(new_node, node); } } else { - ir_node *xor, *pval, *sign_extension; + ir_node *xor, *sign_extension; if (get_mode_size_bits(mode) == 32) { new_op = be_transform_node(op); @@ -1782,20 +1812,15 @@ static ir_node *gen_Abs(ir_node *node) new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node); } - pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block); - sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, - new_op, pval); - - add_irn_dep(pval, get_irg_frame(irg)); - SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node)); + sign_extension = create_sex_32_64(dbgi, new_block, new_op, node); - xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp, + xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, sign_extension); - SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(xor, node); - new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp, + new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, xor, sign_extension); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); } return new_node; @@ -1804,14 +1829,15 @@ static ir_node *gen_Abs(ir_node *node) /** * Create a bt instruction for x & (1 << n) and place it into the block of cmp. */ -static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) { +static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) +{ dbg_info *dbgi = get_irn_dbg_info(cmp); ir_node *block = get_nodes_block(cmp); ir_node *new_block = be_transform_node(block); ir_node *op1 = be_transform_node(x); ir_node *op2 = be_transform_node(n); - return new_rd_ia32_Bt(dbgi, current_ir_graph, new_block, op1, op2); + return new_bd_ia32_Bt(dbgi, new_block, op1, op2); } /** @@ -1824,8 +1850,6 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) { ir_node *flags; ir_node *new_op; - ir_node *noreg; - ir_node *nomem; ir_node *new_block; dbg_info *dbgi; @@ -1880,10 +1904,8 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) dbgi = get_irn_dbg_info(node); new_block = be_transform_node(get_nodes_block(node)); new_op = be_transform_node(node); - noreg = ia32_new_NoReg_gp(env_cg); - nomem = new_NoMem(); - flags = new_rd_ia32_Test(dbgi, current_ir_graph, new_block, noreg, noreg, nomem, - new_op, new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0); + flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, + new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0); *pnc_out = pn_Cmp_Lg; return flags; } @@ -1893,7 +1915,8 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) * * @return the created ia32 Load node */ -static ir_node *gen_Load(ir_node *node) { +static ir_node *gen_Load(ir_node *node) +{ ir_node *old_block = get_nodes_block(node); ir_node *block = be_transform_node(old_block); ir_node *ptr = get_Load_ptr(node); @@ -1901,9 +1924,7 @@ static ir_node *gen_Load(ir_node *node) { ir_node *new_mem = be_transform_node(mem); ir_node *base; ir_node *index; - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_mode *mode = get_Load_mode(node); ir_mode *res_mode; ir_node *new_node; @@ -1911,29 +1932,29 @@ static ir_node *gen_Load(ir_node *node) { /* construct load address */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, ptr, /*force=*/0); + ia32_create_address_mode(&addr, ptr, 0); base = addr.base; index = addr.index; - if(base == NULL) { - base = noreg; + if (base == NULL) { + base = noreg_GP; } else { base = be_transform_node(base); } - if(index == NULL) { - index = noreg; + if (index == NULL) { + index = noreg_GP; } else { index = be_transform_node(index); } if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) { - new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem, + new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem, mode); res_mode = mode_xmm; } else { - new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem, + new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem, mode); res_mode = mode_vfp; } @@ -1941,11 +1962,11 @@ static ir_node *gen_Load(ir_node *node) { assert(mode != mode_b); /* create a conv node with address mode for smaller modes */ - if(get_mode_size_bits(mode) < 32) { - new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, - new_mem, noreg, mode); + if (get_mode_size_bits(mode) < 32) { + new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index, + new_mem, noreg_GP, mode); } else { - new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem); + new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem); } res_mode = mode_Iu; } @@ -1955,19 +1976,16 @@ static ir_node *gen_Load(ir_node *node) { set_ia32_ls_mode(new_node, mode); set_address(new_node, &addr); - if(get_irn_pinned(node) == op_pin_state_floats) { - add_ia32_flags(new_node, arch_irn_flags_rematerializable); - } - - /* make sure we are scheduled behind the initial IncSP/Barrier - * to avoid spills being placed before it - */ - if (block == get_irg_start_block(irg)) { - add_irn_dep(new_node, get_irg_frame(irg)); + if (get_irn_pinned(node) == op_pin_state_floats) { + assert(pn_ia32_xLoad_res == pn_ia32_vfld_res + && pn_ia32_vfld_res == pn_ia32_Load_res + && pn_ia32_Load_res == pn_ia32_res); + arch_irn_add_flags(new_node, arch_irn_flags_rematerializable); } - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); + be_dep_on_frame(new_node); return new_node; } @@ -2000,35 +2018,14 @@ static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem, return 0; } - if (is_Sync(mem)) { - int i; - - for (i = get_Sync_n_preds(mem) - 1; i >= 0; --i) { - ir_node *const pred = get_Sync_pred(mem, i); - - if (is_Proj(pred) && get_Proj_pred(pred) == load) - continue; - - if (get_nodes_block(pred) == block && - heights_reachable_in_block(heights, pred, load)) { - return 0; - } - } - } else { - /* Store should be attached to the load */ - if (!is_Proj(mem) || get_Proj_pred(mem) != load) - return 0; - } + if (prevents_AM(block, load, mem)) + return 0; + /* Store should be attached to the load via mem */ + assert(heights_reachable_in_block(heights, mem, load)); return 1; } -static void set_transformed_and_mark(ir_node *const old_node, ir_node *const new_node) -{ - mark_irn_visited(old_node); - be_set_transformed_node(old_node, new_node); -} - static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, ir_node *mem, ir_node *ptr, ir_mode *mode, construct_binop_dest_func *func, @@ -2037,8 +2034,6 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, { ir_node *src_block = get_nodes_block(node); ir_node *block; - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_graph *irg = current_ir_graph; dbg_info *dbgi; ir_node *new_mem; ir_node *new_node; @@ -2049,46 +2044,43 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, ia32_address_t *addr = &am.addr; memset(&am, 0, sizeof(am)); - assert(flags & match_dest_am); assert(flags & match_immediate); /* there is no destam node without... */ commutative = (flags & match_commutative) != 0; - if(use_dest_am(src_block, op1, mem, ptr, op2)) { - build_address(&am, op1); + if (use_dest_am(src_block, op1, mem, ptr, op2)) { + build_address(&am, op1, ia32_create_am_double_use); new_op = create_immediate_or_transform(op2, 0); - } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) { - build_address(&am, op2); + } else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) { + build_address(&am, op2, ia32_create_am_double_use); new_op = create_immediate_or_transform(op1, 0); } else { return NULL; } - if(addr->base == NULL) - addr->base = noreg_gp; - if(addr->index == NULL) - addr->index = noreg_gp; - if(addr->mem == NULL) - addr->mem = new_NoMem(); + if (addr->base == NULL) + addr->base = noreg_GP; + if (addr->index == NULL) + addr->index = noreg_GP; + if (addr->mem == NULL) + addr->mem = nomem; dbgi = get_irn_dbg_info(node); block = be_transform_node(src_block); - new_mem = transform_AM_mem(irg, block, am.am_node, mem, addr->mem); + new_mem = transform_AM_mem(current_ir_graph, block, am.am_node, mem, addr->mem); - if(get_mode_size_bits(mode) == 8) { - new_node = func8bit(dbgi, irg, block, addr->base, addr->index, - new_mem, new_op); + if (get_mode_size_bits(mode) == 8) { + new_node = func8bit(dbgi, block, addr->base, addr->index, new_mem, new_op); } else { - new_node = func(dbgi, irg, block, addr->base, addr->index, new_mem, - new_op); + new_node = func(dbgi, block, addr->base, addr->index, new_mem, new_op); } set_address(new_node, addr); set_ia32_op_type(new_node, ia32_AddrModeD); set_ia32_ls_mode(new_node, mode); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); - set_transformed_and_mark(get_Proj_pred(am.mem_proj), new_node); + be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node); mem_proj = be_transform_node(am.mem_proj); - set_transformed_and_mark(mem_proj ? mem_proj : am.mem_proj, new_node); + be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node); return new_node; } @@ -2097,7 +2089,6 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, ir_node *ptr, ir_mode *mode, construct_unop_dest_func *func) { - ir_graph *irg = current_ir_graph; ir_node *src_block = get_nodes_block(node); ir_node *block; dbg_info *dbgi; @@ -2106,34 +2097,34 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, ir_node *mem_proj; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - memset(&am, 0, sizeof(am)); - if(!use_dest_am(src_block, op, mem, ptr, NULL)) + if (!use_dest_am(src_block, op, mem, ptr, NULL)) return NULL; - build_address(&am, op); + memset(&am, 0, sizeof(am)); + build_address(&am, op, ia32_create_am_double_use); dbgi = get_irn_dbg_info(node); block = be_transform_node(src_block); - new_mem = transform_AM_mem(irg, block, am.am_node, mem, addr->mem); - new_node = func(dbgi, irg, block, addr->base, addr->index, new_mem); + new_mem = transform_AM_mem(current_ir_graph, block, am.am_node, mem, addr->mem); + new_node = func(dbgi, block, addr->base, addr->index, new_mem); set_address(new_node, addr); set_ia32_op_type(new_node, ia32_AddrModeD); set_ia32_ls_mode(new_node, mode); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); - set_transformed_and_mark(get_Proj_pred(am.mem_proj), new_node); + be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node); mem_proj = be_transform_node(am.mem_proj); - set_transformed_and_mark(mem_proj ? mem_proj : am.mem_proj, new_node); + be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node); return new_node; } -static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) { +static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) +{ ir_mode *mode = get_irn_mode(node); ir_node *mux_true = get_Mux_true(node); ir_node *mux_false = get_Mux_false(node); - ir_graph *irg; ir_node *cond; ir_node *new_mem; dbg_info *dbgi; @@ -2145,12 +2136,12 @@ static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) { pn_Cmp pnc; ia32_address_t addr; - if(get_mode_size_bits(mode) != 8) + if (get_mode_size_bits(mode) != 8) return NULL; - if(is_Const_1(mux_true) && is_Const_0(mux_false)) { + if (is_Const_1(mux_true) && is_Const_0(mux_false)) { negated = 0; - } else if(is_Const_0(mux_true) && is_Const_1(mux_false)) { + } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) { negated = 1; } else { return NULL; @@ -2158,24 +2149,24 @@ static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) { build_address_ptr(&addr, ptr, mem); - irg = current_ir_graph; dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); new_block = be_transform_node(block); cond = get_Mux_sel(node); flags = get_flags_node(cond, &pnc); new_mem = be_transform_node(mem); - new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base, + new_node = new_bd_ia32_SetMem(dbgi, new_block, addr.base, addr.index, addr.mem, flags, pnc, negated); set_address(new_node, &addr); set_ia32_op_type(new_node, ia32_AddrModeD); set_ia32_ls_mode(new_node, mode); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } -static ir_node *try_create_dest_am(ir_node *node) { +static ir_node *try_create_dest_am(ir_node *node) +{ ir_node *val = get_Store_value(node); ir_node *mem = get_Store_mem(node); ir_node *ptr = get_Store_ptr(node); @@ -2186,20 +2177,20 @@ static ir_node *try_create_dest_am(ir_node *node) { ir_node *new_node; /* handle only GP modes for now... */ - if(!ia32_mode_needs_gp_reg(mode)) + if (!ia32_mode_needs_gp_reg(mode)) return NULL; - while(1) { + for (;;) { /* store must be the only user of the val node */ - if(get_irn_n_edges(val) > 1) + if (get_irn_n_edges(val) > 1) return NULL; /* skip pointless convs */ - if(is_Conv(val)) { + if (is_Conv(val)) { ir_node *conv_op = get_Conv_op(val); ir_mode *pred_mode = get_irn_mode(conv_op); if (!ia32_mode_needs_gp_reg(pred_mode)) break; - if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) { + if (pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) { val = conv_op; continue; } @@ -2208,26 +2199,25 @@ static ir_node *try_create_dest_am(ir_node *node) { } /* value must be in the same block */ - if(get_nodes_block(node) != get_nodes_block(val)) + if (get_nodes_block(node) != get_nodes_block(val)) return NULL; switch (get_irn_opcode(val)) { case iro_Add: op1 = get_Add_left(val); op2 = get_Add_right(val); - if(is_Const_1(op2)) { - new_node = dest_am_unop(val, op1, mem, ptr, mode, - new_rd_ia32_IncMem); - break; - } else if(is_Const_Minus_1(op2)) { - new_node = dest_am_unop(val, op1, mem, ptr, mode, - new_rd_ia32_DecMem); - break; + if (ia32_cg_config.use_incdec) { + if (is_Const_1(op2)) { + new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_IncMem); + break; + } else if (is_Const_Minus_1(op2)) { + new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_DecMem); + break; + } } new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, - match_dest_am | match_commutative | - match_immediate); + new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit, + match_commutative | match_immediate); break; case iro_Sub: op1 = get_Sub_left(val); @@ -2236,61 +2226,57 @@ static ir_node *try_create_dest_am(ir_node *node) { ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n"); } new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, - match_dest_am | match_immediate | + new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit, match_immediate); break; case iro_And: op1 = get_And_left(val); op2 = get_And_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, - match_dest_am | match_commutative | - match_immediate); + new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit, + match_commutative | match_immediate); break; case iro_Or: op1 = get_Or_left(val); op2 = get_Or_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, - match_dest_am | match_commutative | - match_immediate); + new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit, + match_commutative | match_immediate); break; case iro_Eor: op1 = get_Eor_left(val); op2 = get_Eor_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, - match_dest_am | match_commutative | - match_immediate); + new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit, + match_commutative | match_immediate); break; case iro_Shl: op1 = get_Shl_left(val); op2 = get_Shl_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, - match_dest_am | match_immediate); + new_bd_ia32_ShlMem, new_bd_ia32_ShlMem, + match_immediate); break; case iro_Shr: op1 = get_Shr_left(val); op2 = get_Shr_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, - match_dest_am | match_immediate); + new_bd_ia32_ShrMem, new_bd_ia32_ShrMem, + match_immediate); break; case iro_Shrs: op1 = get_Shrs_left(val); op2 = get_Shrs_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_SarMem, new_rd_ia32_SarMem, - match_dest_am | match_immediate); + new_bd_ia32_SarMem, new_bd_ia32_SarMem, + match_immediate); break; case iro_Rotl: op1 = get_Rotl_left(val); op2 = get_Rotl_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_RolMem, new_rd_ia32_RolMem, - match_dest_am | match_immediate); + new_bd_ia32_RolMem, new_bd_ia32_RolMem, + match_immediate); break; /* TODO: match ROR patterns... */ case iro_Mux: @@ -2298,20 +2284,20 @@ static ir_node *try_create_dest_am(ir_node *node) { break; case iro_Minus: op1 = get_Minus_op(val); - new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem); + new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NegMem); break; case iro_Not: /* should be lowered already */ assert(mode != mode_b); op1 = get_Not_op(val); - new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem); + new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NotMem); break; default: return NULL; } - if(new_node != NULL) { - if(get_irn_pinned(new_node) != op_pin_state_pinned && + if (new_node != NULL) { + if (get_irn_pinned(new_node) != op_pin_state_pinned && get_irn_pinned(node) == op_pin_state_pinned) { set_irn_pinned(new_node, op_pin_state_pinned); } @@ -2320,32 +2306,41 @@ static ir_node *try_create_dest_am(ir_node *node) { return new_node; } -static int is_float_to_int32_conv(const ir_node *node) +static bool possible_int_mode_for_fp(ir_mode *mode) +{ + unsigned size; + + if (!mode_is_signed(mode)) + return false; + size = get_mode_size_bits(mode); + if (size != 16 && size != 32) + return false; + return true; +} + +static int is_float_to_int_conv(const ir_node *node) { ir_mode *mode = get_irn_mode(node); ir_node *conv_op; ir_mode *conv_mode; - if(get_mode_size_bits(mode) != 32 || !ia32_mode_needs_gp_reg(mode)) - return 0; - /* don't report unsigned as conv to 32bit, because we really need to do - * a vfist with 64bit signed in this case */ - if(!mode_is_signed(mode)) + if (!possible_int_mode_for_fp(mode)) return 0; - if(!is_Conv(node)) + if (!is_Conv(node)) return 0; conv_op = get_Conv_op(node); conv_mode = get_irn_mode(conv_op); - if(!mode_is_float(conv_mode)) + if (!mode_is_float(conv_mode)) return 0; return 1; } /** - * Transform a Store(floatConst). + * Transform a Store(floatConst) into a sequence of + * integer stores. * * @return the created ia32 Store node */ @@ -2358,7 +2353,6 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) ir_node *new_block = be_transform_node(block); ir_node *ptr = get_Store_ptr(node); ir_node *mem = get_Store_mem(node); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); int ofs = 0; size_t i = 0; @@ -2378,15 +2372,16 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) (get_tarval_sub_bits(tv, ofs + 3) << 24); ir_node *imm = create_Immediate(NULL, 0, val); - ir_node *new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base, + ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base, addr.index, addr.mem, imm); set_irn_pinned(new_node, get_irn_pinned(node)); set_ia32_op_type(new_node, ia32_AddrModeD); set_ia32_ls_mode(new_node, mode_Iu); set_address(new_node, &addr); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); + assert(i < 4); ins[i++] = new_node; size -= 4; @@ -2394,7 +2389,11 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) addr.offset += 4; } while (size != 0); - return i == 1 ? ins[0] : new_rd_Sync(dbgi, irg, new_block, i, ins); + if (i > 1) { + return new_rd_Sync(dbgi, current_ir_graph, new_block, i, ins); + } else { + return ins[0]; + } } /** @@ -2409,7 +2408,7 @@ static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied if other users exists */ const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp]; - ir_node *vfisttp = new_rd_ia32_vfisttp(dbgi, irg, block, base, index, mem, val); + ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val); ir_node *value = new_r_Proj(irg, block, vfisttp, mode_E, pn_ia32_vfisttp_res); be_new_Keep(reg_class, irg, block, 1, &value); @@ -2419,17 +2418,17 @@ static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); /* do a fist */ - new_node = new_rd_ia32_vfist(dbgi, irg, block, base, index, mem, val, trunc_mode); + new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode); *fist = new_node; } return new_node; } /** - * Transforms a normal Store. + * Transforms a general (no special case) Store. * * @return the created ia32 Store node */ -static ir_node *gen_normal_Store(ir_node *node) +static ir_node *gen_general_Store(ir_node *node) { ir_node *val = get_Store_value(node); ir_mode *mode = get_irn_mode(val); @@ -2437,9 +2436,7 @@ static ir_node *gen_normal_Store(ir_node *node) ir_node *new_block = be_transform_node(block); ir_node *ptr = get_Store_ptr(node); ir_node *mem = get_Store_mem(node); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_node *new_val, *new_node, *store; ia32_address_t addr; @@ -2450,16 +2447,16 @@ static ir_node *gen_normal_Store(ir_node *node) /* construct store address */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, ptr, /*force=*/0); + ia32_create_address_mode(&addr, ptr, 0); if (addr.base == NULL) { - addr.base = noreg; + addr.base = noreg_GP; } else { addr.base = be_transform_node(addr.base); } if (addr.index == NULL) { - addr.index = noreg; + addr.index = noreg_GP; } else { addr.index = be_transform_node(addr.index); } @@ -2476,14 +2473,14 @@ static ir_node *gen_normal_Store(ir_node *node) } new_val = be_transform_node(val); if (ia32_cg_config.use_sse2) { - new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base, + new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base, addr.index, addr.mem, new_val); } else { - new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base, + new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, mode); } store = new_node; - } else if (!ia32_cg_config.use_sse2 && is_float_to_int32_conv(val)) { + } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) { val = get_Conv_op(val); /* TODO: is this optimisation still necessary at all (middleend)? */ @@ -2497,16 +2494,16 @@ static ir_node *gen_normal_Store(ir_node *node) val = op; } new_val = be_transform_node(val); - new_node = gen_vfist(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val, &store); + new_node = gen_vfist(dbgi, current_ir_graph, new_block, addr.base, addr.index, addr.mem, new_val, &store); } else { new_val = create_immediate_or_transform(val, 0); assert(mode != mode_b); if (get_mode_size_bits(mode) == 8) { - new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base, + new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base, addr.index, addr.mem, new_val); } else { - new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base, + new_node = new_bd_ia32_Store(dbgi, new_block, addr.base, addr.index, addr.mem, new_val); } store = new_node; @@ -2517,7 +2514,7 @@ static ir_node *gen_normal_Store(ir_node *node) set_ia32_ls_mode(store, mode); set_address(store, &addr); - SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(store, node); return new_node; } @@ -2533,18 +2530,14 @@ static ir_node *gen_Store(ir_node *node) ir_mode *mode = get_irn_mode(val); if (mode_is_float(mode) && is_Const(val)) { - int transform; - - /* we are storing a floating point constant */ - if (ia32_cg_config.use_sse2) { - transform = !is_simple_sse_Const(val); - } else { - transform = !is_simple_x87_Const(val); - } - if (transform) - return gen_float_const_Store(node, val); + /* We can transform every floating const store + into a sequence of integer stores. + If the constant is already in a register, + it would be better to use it, but we don't + have this information here. */ + return gen_float_const_Store(node, val); } - return gen_normal_Store(node); + return gen_general_Store(node); } /** @@ -2554,13 +2547,12 @@ static ir_node *gen_Store(ir_node *node) */ static ir_node *create_Switch(ir_node *node) { - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *sel = get_Cond_selector(node); ir_node *new_sel = be_transform_node(sel); - int switch_min = INT_MAX; - int switch_max = INT_MIN; + long switch_min = LONG_MAX; + long switch_max = LONG_MIN; long default_pn = get_Cond_defaultProj(node); ir_node *new_node; const ir_edge_t *edge; @@ -2571,32 +2563,30 @@ static ir_node *create_Switch(ir_node *node) foreach_out_edge(node, edge) { ir_node *proj = get_edge_src_irn(edge); long pn = get_Proj_proj(proj); - if(pn == default_pn) + if (pn == default_pn) continue; - if(pn < switch_min) + if (pn < switch_min) switch_min = pn; - if(pn > switch_max) + if (pn > switch_max) switch_max = pn; } - if((unsigned) (switch_max - switch_min) > 256000) { + if ((unsigned long) (switch_max - switch_min) > 256000) { panic("Size of switch %+F bigger than 256000", node); } if (switch_min != 0) { - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - /* if smallest switch case is not 0 we need an additional sub */ - new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg); + new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg_GP); add_ia32_am_offs_int(new_sel, -switch_min); set_ia32_op_type(new_sel, ia32_AddrModeS); - SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_sel, node); } - new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, default_pn); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + new_node = new_bd_ia32_SwitchJmp(dbgi, block, new_sel, default_pn); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -2604,10 +2594,10 @@ static ir_node *create_Switch(ir_node *node) /** * Transform a Cond node. */ -static ir_node *gen_Cond(ir_node *node) { +static ir_node *gen_Cond(ir_node *node) +{ ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *sel = get_Cond_selector(node); ir_mode *sel_mode = get_irn_mode(sel); @@ -2622,8 +2612,8 @@ static ir_node *gen_Cond(ir_node *node) { /* we get flags from a Cmp */ flags = get_flags_node(sel, &pnc); - new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, pnc); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -2642,7 +2632,6 @@ static ir_node *gen_be_Copy(ir_node *node) static ir_node *create_Fucom(ir_node *node) { - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); @@ -2652,28 +2641,26 @@ static ir_node *create_Fucom(ir_node *node) ir_node *new_right; ir_node *new_node; - if(ia32_cg_config.use_fucomi) { + if (ia32_cg_config.use_fucomi) { new_right = be_transform_node(right); - new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, + new_node = new_bd_ia32_vFucomi(dbgi, new_block, new_left, new_right, 0); set_ia32_commutative(new_node); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); } else { - if(ia32_cg_config.use_ftst && is_Const_0(right)) { - new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, - 0); + if (ia32_cg_config.use_ftst && is_Const_0(right)) { + new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0); } else { new_right = be_transform_node(right); - new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left, - new_right, 0); + new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0); } set_ia32_commutative(new_node); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); - new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + new_node = new_bd_ia32_Sahf(dbgi, new_block, new_node); + SET_IA32_ORIG_NODE(new_node, node); } return new_node; @@ -2681,7 +2668,6 @@ static ir_node *create_Fucom(ir_node *node) static ir_node *create_Ucomi(ir_node *node) { - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *src_block = get_nodes_block(node); ir_node *new_block = be_transform_node(src_block); @@ -2694,12 +2680,12 @@ static ir_node *create_Ucomi(ir_node *node) match_arguments(&am, src_block, left, right, NULL, match_commutative | match_am); - new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index, + new_node = new_bd_ia32_Ucomi(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted); set_am_attributes(new_node, &am); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); new_node = fix_mem_proj(new_node, &am); @@ -2710,7 +2696,7 @@ static ir_node *create_Ucomi(ir_node *node) * helper function: checks whether all Cmp projs are Lg or Eq which is needed * to fold an and into a test node */ -static int can_fold_test_and(ir_node *node) +static bool can_fold_test_and(ir_node *node) { const ir_edge_t *edge; @@ -2718,11 +2704,91 @@ static int can_fold_test_and(ir_node *node) foreach_out_edge(node, edge) { ir_node *proj = get_edge_src_irn(edge); pn_Cmp pnc = get_Proj_proj(proj); - if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) - return 0; + if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) + return false; } - return 1; + return true; +} + +/** + * returns true if it is assured, that the upper bits of a node are "clean" + * which means for a 16 or 8 bit value, that the upper bits in the register + * are 0 for unsigned and a copy of the last significant bit for signed + * numbers. + */ +static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode) +{ + assert(ia32_mode_needs_gp_reg(mode)); + if (get_mode_size_bits(mode) >= 32) + return true; + + if (is_Proj(transformed_node)) + return upper_bits_clean(get_Proj_pred(transformed_node), mode); + + switch (get_ia32_irn_opcode(transformed_node)) { + case iro_ia32_Conv_I2I: + case iro_ia32_Conv_I2I8Bit: { + ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node); + if (mode_is_signed(smaller_mode) != mode_is_signed(mode)) + return false; + if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode)) + return false; + + return true; + } + + case iro_ia32_Shr: + if (mode_is_signed(mode)) { + return false; /* TODO handle signed modes */ + } else { + ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count); + if (is_ia32_Immediate(right) || is_ia32_Const(right)) { + const ia32_immediate_attr_t *attr + = get_ia32_immediate_attr_const(right); + if (attr->symconst == 0 && + (unsigned)attr->offset >= 32 - get_mode_size_bits(mode)) { + return true; + } + } + return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode); + } + + case iro_ia32_Sar: + /* TODO too conservative if shift amount is constant */ + return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Sar_val), mode); + + case iro_ia32_And: + if (!mode_is_signed(mode)) { + return + upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_right), mode) || + upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_left), mode); + } + /* TODO if one is known to be zero extended, then || is sufficient */ + /* FALLTHROUGH */ + case iro_ia32_Or: + case iro_ia32_Xor: + return + upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_right), mode) && + upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_left), mode); + + case iro_ia32_Const: + case iro_ia32_Immediate: { + const ia32_immediate_attr_t *attr = + get_ia32_immediate_attr_const(transformed_node); + if (mode_is_signed(mode)) { + long shifted = attr->offset >> (get_mode_size_bits(mode) - 1); + return shifted == 0 || shifted == -1; + } else { + unsigned long shifted = (unsigned long)attr->offset; + shifted >>= get_mode_size_bits(mode); + return shifted == 0; + } + } + + default: + return false; + } } /** @@ -2730,7 +2796,6 @@ static int can_fold_test_and(ir_node *node) */ static ir_node *gen_Cmp(ir_node *node) { - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); @@ -2742,7 +2807,7 @@ static ir_node *gen_Cmp(ir_node *node) ia32_address_t *addr = &am.addr; int cmp_unsigned; - if(mode_is_float(cmp_mode)) { + if (mode_is_float(cmp_mode)) { if (ia32_cg_config.use_sse2) { return create_Ucomi(node); } else { @@ -2761,44 +2826,58 @@ static ir_node *gen_Cmp(ir_node *node) /* Test(and_left, and_right) */ ir_node *and_left = get_And_left(left); ir_node *and_right = get_And_right(left); - ir_mode *mode = get_irn_mode(and_left); + + /* matze: code here used mode instead of cmd_mode, I think it is always + * the same as cmp_mode, but I leave this here to see if this is really + * true... + */ + assert(get_irn_mode(and_left) == cmp_mode); match_arguments(&am, block, and_left, and_right, NULL, match_commutative | match_am | match_8bit_am | match_16bit_am | - match_am_and_immediates | match_immediate | - match_8bit | match_16bit); - if (get_mode_size_bits(mode) == 8) { - new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2, am.ins_permuted, - cmp_unsigned); + match_am_and_immediates | match_immediate); + + /* use 32bit compare mode if possible since the opcode is smaller */ + if (upper_bits_clean(am.new_op1, cmp_mode) && + upper_bits_clean(am.new_op2, cmp_mode)) { + cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu; + } + + if (get_mode_size_bits(cmp_mode) == 8) { + new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base, + addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted, + cmp_unsigned); } else { - new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2, am.ins_permuted, cmp_unsigned); + new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index, + addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned); } } else { /* Cmp(left, right) */ match_arguments(&am, block, left, right, NULL, match_commutative | match_am | match_8bit_am | match_16bit_am | match_am_and_immediates | - match_immediate | match_8bit | match_16bit); + match_immediate); + /* use 32bit compare mode if possible since the opcode is smaller */ + if (upper_bits_clean(am.new_op1, cmp_mode) && + upper_bits_clean(am.new_op2, cmp_mode)) { + cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu; + } + if (get_mode_size_bits(cmp_mode) == 8) { - new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, + new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned); } else { - new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2, am.ins_permuted, cmp_unsigned); + new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index, + addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned); } } set_am_attributes(new_node, &am); set_ia32_ls_mode(new_node, cmp_mode); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); new_node = fix_mem_proj(new_node, &am); @@ -2808,14 +2887,12 @@ static ir_node *gen_Cmp(ir_node *node) static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, pn_Cmp pnc) { - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); ir_node *val_true = get_Mux_true(node); ir_node *val_false = get_Mux_false(node); ir_node *new_node; - match_flags_t match_flags; ia32_address_mode_t am; ia32_address_t *addr; @@ -2824,17 +2901,15 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, addr = &am.addr; - match_flags = match_commutative | match_am | match_16bit_am | - match_mode_neutral; + match_arguments(&am, block, val_false, val_true, flags, + match_commutative | match_am | match_16bit_am | match_mode_neutral); - match_arguments(&am, block, val_false, val_true, flags, match_flags); - - new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index, + new_node = new_bd_ia32_CMov(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, new_flags, am.ins_permuted, pnc); set_am_attributes(new_node, &am); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); new_node = fix_mem_proj(new_node, &am); @@ -2848,20 +2923,17 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, ir_node *flags, pn_Cmp pnc, ir_node *orig_node, int ins_permuted) { - ir_graph *irg = current_ir_graph; - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); - ir_mode *mode = get_irn_mode(orig_node); - ir_node *new_node; + ir_mode *mode = get_irn_mode(orig_node); + ir_node *new_node; - new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node)); + new_node = new_bd_ia32_Set(dbgi, new_block, flags, pnc, ins_permuted); + SET_IA32_ORIG_NODE(new_node, orig_node); /* we might need to conv the result up */ if (get_mode_size_bits(mode) > 8) { - new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, + new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, mode_Bu); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node)); + SET_IA32_ORIG_NODE(new_node, orig_node); } return new_node; @@ -2870,13 +2942,15 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, /** * Create instruction for an unsigned Difference or Zero. */ -static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) { +static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) +{ ir_graph *irg = current_ir_graph; ir_mode *mode = get_irn_mode(psi); - ir_node *new_node, *sub, *sbb, *eflags, *block, *noreg, *tmpreg, *nomem; + ir_node *new_node, *sub, *sbb, *eflags, *block; + dbg_info *dbgi; - new_node = gen_binop(psi, a, b, new_rd_ia32_Sub, + new_node = gen_binop(psi, a, b, new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate | match_two_users); block = get_nodes_block(new_node); @@ -2892,16 +2966,72 @@ static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) { eflags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags); dbgi = get_irn_dbg_info(psi); - noreg = ia32_new_NoReg_gp(env_cg); - tmpreg = new_rd_ia32_ProduceVal(dbgi, irg, block); - nomem = new_NoMem(); - sbb = new_rd_ia32_Sbb(dbgi, irg, block, noreg, noreg, nomem, tmpreg, tmpreg, eflags); + sbb = new_bd_ia32_Sbb0(dbgi, block, eflags); - new_node = new_rd_ia32_And(dbgi, irg, block, noreg, noreg, nomem, new_node, sbb); + new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, sbb); set_ia32_commutative(new_node); return new_node; } +/** + * Create an const array of two float consts. + * + * @param c0 the first constant + * @param c1 the second constant + * @param new_mode IN/OUT for the mode of the constants, if NULL + * smallest possible mode will be used + */ +static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **new_mode) { + ir_entity *ent; + ir_mode *mode = *new_mode; + ir_type *tp; + ir_initializer_t *initializer; + tarval *tv0 = get_Const_tarval(c0); + tarval *tv1 = get_Const_tarval(c1); + + if (mode == NULL) { + /* detect the best mode for the constants */ + mode = get_tarval_mode(tv0); + + if (mode != mode_F) { + if (tarval_ieee754_can_conv_lossless(tv0, mode_F) && + tarval_ieee754_can_conv_lossless(tv1, mode_F)) { + mode = mode_F; + tv0 = tarval_convert_to(tv0, mode); + tv1 = tarval_convert_to(tv1, mode); + } else if (mode != mode_D) { + if (tarval_ieee754_can_conv_lossless(tv0, mode_D) && + tarval_ieee754_can_conv_lossless(tv1, mode_D)) { + mode = mode_D; + tv0 = tarval_convert_to(tv0, mode); + tv1 = tarval_convert_to(tv1, mode); + } + } + } + + } + + tp = ia32_create_float_type(mode, 4); + tp = ia32_create_float_array(tp); + + ent = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp); + + set_entity_ld_ident(ent, get_entity_ident(ent)); + set_entity_visibility(ent, visibility_local); + set_entity_variability(ent, variability_constant); + set_entity_allocation(ent, allocation_static); + + initializer = create_initializer_compound(2); + + set_initializer_compound_value(initializer, 0, create_initializer_tarval(tv0)); + set_initializer_compound_value(initializer, 1, create_initializer_tarval(tv1)); + + set_entity_initializer(ent, initializer); + + *new_mode = mode; + return ent; +} + /** * Transforms a Mux node into CMov. * @@ -2916,6 +3046,8 @@ static ir_node *gen_Mux(ir_node *node) ir_node *mux_false = get_Mux_false(node); ir_node *cond = get_Mux_sel(node); ir_mode *mode = get_irn_mode(node); + ir_node *flags; + ir_node *new_node; pn_Cmp pnc; assert(get_irn_mode(cond) == mode_b); @@ -2931,42 +3063,111 @@ static ir_node *gen_Mux(ir_node *node) if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) { if (cmp_left == mux_true && cmp_right == mux_false) { /* Mux(a <= b, a, b) => MIN */ - return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin, + return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin, match_commutative | match_am | match_two_users); } else if (cmp_left == mux_false && cmp_right == mux_true) { /* Mux(a <= b, b, a) => MAX */ - return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax, + return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax, match_commutative | match_am | match_two_users); } } else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) { if (cmp_left == mux_true && cmp_right == mux_false) { /* Mux(a >= b, a, b) => MAX */ - return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax, + return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax, match_commutative | match_am | match_two_users); } else if (cmp_left == mux_false && cmp_right == mux_true) { /* Mux(a >= b, b, a) => MIN */ - return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin, + return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin, match_commutative | match_am | match_two_users); } } } - panic("cannot transform floating point Mux"); + if (is_Const(mux_true) && is_Const(mux_false)) { + ia32_address_mode_t am; + ir_node *load; + ir_mode *new_mode; + unsigned scale; - } else { - ir_node *flags; - ir_node *new_node; + flags = get_flags_node(cond, &pnc); + new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0); - assert(ia32_mode_needs_gp_reg(mode)); + if (ia32_cg_config.use_sse2) { + /* cannot load from different mode on SSE */ + new_mode = mode; + } else { + /* x87 can load any mode */ + new_mode = NULL; + } - if (is_Proj(cond)) { - ir_node *cmp = get_Proj_pred(cond); - if (is_Cmp(cmp)) { - ir_node *cmp_left = get_Cmp_left(cmp); - ir_node *cmp_right = get_Cmp_right(cmp); - pn_Cmp pnc = get_Proj_proj(cond); + am.addr.symconst_ent = ia32_create_const_array(mux_false, mux_true, &new_mode); - /* check for unsigned Doz first */ - if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) && + switch (get_mode_size_bytes(new_mode)) { + case 4: + scale = 2; + break; + case 8: + scale = 3; + break; + case 10: + /* use 2 * 5 */ + scale = 1; + new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); + set_ia32_am_scale(new_node, 2); + break; + case 12: + /* use 4 * 3 */ + scale = 2; + new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); + set_ia32_am_scale(new_node, 1); + break; + case 16: + /* arg, shift 16 NOT supported */ + scale = 3; + new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, new_node); + break; + default: + panic("Unsupported constant size"); + } + + am.ls_mode = new_mode; + am.addr.base = noreg_GP; + am.addr.index = new_node; + am.addr.mem = nomem; + am.addr.offset = 0; + am.addr.scale = scale; + am.addr.use_frame = 0; + am.addr.frame_entity = NULL; + am.addr.symconst_sign = 0; + am.mem_proj = am.addr.mem; + am.op_type = ia32_AddrModeS; + am.new_op1 = NULL; + am.new_op2 = NULL; + am.pinned = op_pin_state_floats; + am.commutative = 1; + am.ins_permuted = 0; + + if (ia32_cg_config.use_sse2) + load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode); + else + load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode); + set_am_attributes(load, &am); + + return new_rd_Proj(NULL, current_ir_graph, block, load, mode_vfp, pn_ia32_res); + } + panic("cannot transform floating point Mux"); + + } else { + assert(ia32_mode_needs_gp_reg(mode)); + + if (is_Proj(cond)) { + ir_node *cmp = get_Proj_pred(cond); + if (is_Cmp(cmp)) { + ir_node *cmp_left = get_Cmp_left(cmp); + ir_node *cmp_right = get_Cmp_right(cmp); + pn_Cmp pnc = get_Proj_proj(cond); + + /* check for unsigned Doz first */ + if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) && is_Const_0(mux_false) && is_Sub(mux_true) && get_Sub_left(mux_true) == cmp_left && get_Sub_right(mux_true) == cmp_right) { /* Mux(a >=u b, a - b, 0) unsigned Doz */ @@ -3004,18 +3205,17 @@ need_cmov: /** * Create a conversion from x87 state register to general purpose. */ -static ir_node *gen_x87_fp_to_gp(ir_node *node) { +static ir_node *gen_x87_fp_to_gp(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op = get_Conv_op(node); ir_node *new_op = be_transform_node(op); - ia32_code_gen_t *cg = env_cg; ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(cg); ir_mode *mode = get_irn_mode(node); ir_node *fist, *load, *mem; - mem = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, new_NoMem(), new_op, &fist); + mem = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist); set_irn_pinned(fist, op_pin_state_floats); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); @@ -3023,28 +3223,28 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) { assert(get_mode_size_bits(mode) <= 32); /* exception we can only store signed 32 bit integers, so for unsigned we store a 64bit (signed) integer and load the lower bits */ - if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) { + if (get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) { set_ia32_ls_mode(fist, mode_Ls); } else { set_ia32_ls_mode(fist, mode_Is); } - SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node)); + SET_IA32_ORIG_NODE(fist, node); /* do a Load */ - load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, mem); + load = new_bd_ia32_Load(dbgi, block, get_irg_frame(irg), noreg_GP, mem); set_irn_pinned(load, op_pin_state_floats); set_ia32_use_frame(load); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_ls_mode(load, mode_Is); - if(get_ia32_ls_mode(fist) == mode_Ls) { + if (get_ia32_ls_mode(fist) == mode_Ls) { ia32_attr_t *attr = get_ia32_attr(load); attr->data.need_64bit_stackent = 1; } else { ia32_attr_t *attr = get_ia32_attr(load); attr->data.need_32bit_stackent = 1; } - SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node)); + SET_IA32_ORIG_NODE(load, node); return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res); } @@ -3057,110 +3257,102 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) ir_node *block = get_nodes_block(node); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *frame = get_irg_frame(irg); ir_node *store, *load; ir_node *new_node; - store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node, - tgt_mode); + store = new_bd_ia32_vfst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode); set_ia32_use_frame(store); set_ia32_op_type(store, ia32_AddrModeD); - SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(store, node); - load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store, - tgt_mode); + load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store, tgt_mode); set_ia32_use_frame(load); set_ia32_op_type(load, ia32_AddrModeS); - SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(load, node); new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res); return new_node; } +static ir_node *create_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base, + ir_node *index, ir_node *mem, ir_node *val, ir_mode *mode) +{ + ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*); + + func = get_mode_size_bits(mode) == 8 ? + new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I; + return func(dbgi, block, base, index, mem, val, mode); +} + /** * Create a conversion from general purpose to x87 register */ -static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { +static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) +{ ir_node *src_block = get_nodes_block(node); ir_node *block = be_transform_node(src_block); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *op = get_Conv_op(node); ir_node *new_op = NULL; - ir_node *noreg; - ir_node *nomem; ir_mode *mode; ir_mode *store_mode; ir_node *fild; ir_node *store; ir_node *new_node; - int src_bits; - /* fild can use source AM if the operand is a signed 32bit integer */ - if (src_mode == mode_Is) { + /* fild can use source AM if the operand is a signed 16bit or 32bit integer */ + if (possible_int_mode_for_fp(src_mode)) { ia32_address_mode_t am; - match_arguments(&am, src_block, NULL, op, NULL, - match_am | match_try_am); + match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am); if (am.op_type == ia32_AddrModeS) { ia32_address_t *addr = &am.addr; - fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, - addr->index, addr->mem); - new_node = new_r_Proj(irg, block, fild, mode_vfp, - pn_ia32_vfild_res); + fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem); + new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); set_am_attributes(fild, &am); - SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(fild, node); fix_mem_proj(fild, &am); return new_node; } } - if(new_op == NULL) { + if (new_op == NULL) { new_op = be_transform_node(op); } - noreg = ia32_new_NoReg_gp(env_cg); - nomem = new_NoMem(); - mode = get_irn_mode(op); + mode = get_irn_mode(op); /* first convert to 32 bit signed if necessary */ - src_bits = get_mode_size_bits(src_mode); - if (src_bits == 8) { - new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem, - new_op, src_mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); - mode = mode_Is; - } else if (src_bits < 32) { - new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem, - new_op, src_mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); + if (get_mode_size_bits(src_mode) < 32) { + if (!upper_bits_clean(new_op, src_mode)) { + new_op = create_Conv_I2I(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, src_mode); + SET_IA32_ORIG_NODE(new_op, node); + } mode = mode_Is; } assert(get_mode_size_bits(mode) == 32); /* do a store */ - store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem, - new_op); + store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op); set_ia32_use_frame(store); set_ia32_op_type(store, ia32_AddrModeD); set_ia32_ls_mode(store, mode_Iu); /* exception for 32bit unsigned, do a 64bit spill+load */ - if(!mode_is_signed(mode)) { + if (!mode_is_signed(mode)) { ir_node *in[2]; /* store a zero */ ir_node *zero_const = create_Immediate(NULL, 0, 0); - ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, - get_irg_frame(irg), noreg, nomem, - zero_const); + ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), + noreg_GP, nomem, zero_const); set_ia32_use_frame(zero_store); set_ia32_op_type(zero_store, ia32_AddrModeD); @@ -3177,7 +3369,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { } /* do a fild */ - fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store); + fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store); set_ia32_use_frame(fild); set_ia32_op_type(fild, ia32_AddrModeS); @@ -3195,49 +3387,46 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, dbg_info *dbgi, ir_node *block, ir_node *op, ir_node *node) { - ir_graph *irg = current_ir_graph; - int src_bits = get_mode_size_bits(src_mode); - int tgt_bits = get_mode_size_bits(tgt_mode); - ir_node *new_block = be_transform_node(block); - ir_node *new_node; - ir_mode *smaller_mode; - int smaller_bits; + ir_node *new_block = be_transform_node(block); + ir_node *new_node; + ir_mode *smaller_mode; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; (void) node; - if (src_bits < tgt_bits) { + if (get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode)) { smaller_mode = src_mode; - smaller_bits = src_bits; } else { smaller_mode = tgt_mode; - smaller_bits = tgt_bits; } #ifdef DEBUG_libfirm - if(is_Const(op)) { + if (is_Const(op)) { ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n", op); } #endif match_arguments(&am, block, NULL, op, NULL, - match_8bit | match_16bit | match_am | match_8bit_am | match_16bit_am); - if (smaller_bits == 8) { - new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op2, - smaller_mode); - } else { - new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op2, - smaller_mode); + + if (upper_bits_clean(am.new_op2, smaller_mode)) { + /* unnecessary conv. in theory it shouldn't have been AM */ + assert(is_ia32_NoReg_GP(addr->base)); + assert(is_ia32_NoReg_GP(addr->index)); + assert(is_NoMem(addr->mem)); + assert(am.addr.offset == 0); + assert(am.addr.symconst_ent == NULL); + return am.new_op2; } + + new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index, + addr->mem, am.new_op2, smaller_mode); set_am_attributes(new_node, &am); /* match_arguments assume that out-mode = in-mode, this isn't true here * so fix it */ set_ia32_ls_mode(new_node, smaller_mode); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); new_node = fix_mem_proj(new_node, &am); return new_node; } @@ -3247,21 +3436,22 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, * * @return The created ia32 Conv node */ -static ir_node *gen_Conv(ir_node *node) { +static ir_node *gen_Conv(ir_node *node) +{ ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); ir_node *op = get_Conv_op(node); ir_node *new_op = NULL; - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *src_mode = get_irn_mode(op); ir_mode *tgt_mode = get_irn_mode(node); int src_bits = get_mode_size_bits(src_mode); int tgt_bits = get_mode_size_bits(tgt_mode); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_rd_NoMem(irg); ir_node *res = NULL; + assert(!mode_is_int(src_mode) || src_bits <= 32); + assert(!mode_is_int(tgt_mode) || tgt_bits <= 32); + if (src_mode == mode_b) { assert(mode_is_int(tgt_mode) || mode_is_reference(tgt_mode)); /* nothing to do, we already model bools as 0/1 ints */ @@ -3286,23 +3476,36 @@ static ir_node *gen_Conv(ir_node *node) { new_op = be_transform_node(op); /* we convert from float ... */ if (mode_is_float(tgt_mode)) { - if(src_mode == mode_E && tgt_mode == mode_D +#if 0 + /* Matze: I'm a bit unsure what the following is for? seems wrong + * to me... */ + if (src_mode == mode_E && tgt_mode == mode_D && !get_Conv_strict(node)) { DB((dbg, LEVEL_1, "killed Conv(mode, mode) ...")); return new_op; } +#endif /* ... to float */ if (ia32_cg_config.use_sse2) { DB((dbg, LEVEL_1, "create Conv(float, float) ...")); - res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg, + res = new_bd_ia32_Conv_FP2FP(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op); set_ia32_ls_mode(res, tgt_mode); } else { - if(get_Conv_strict(node)) { - res = gen_x87_strict_conv(tgt_mode, new_op); - SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node)); - return res; + if (get_Conv_strict(node)) { + /* if fp_no_float_fold is not set then we assume that we + * don't have any float operations in a non + * mode_float_arithmetic mode and can skip strict upconvs */ + if (src_bits < tgt_bits + && !(get_irg_fp_model(current_ir_graph) & fp_no_float_fold)) { + DB((dbg, LEVEL_1, "killed Conv(float, float) ...")); + return new_op; + } else { + res = gen_x87_strict_conv(tgt_mode, new_op); + SET_IA32_ORIG_NODE(get_Proj_pred(res), node); + return res; + } } DB((dbg, LEVEL_1, "killed Conv(float, float) ...")); return new_op; @@ -3311,7 +3514,7 @@ static ir_node *gen_Conv(ir_node *node) { /* ... to int */ DB((dbg, LEVEL_1, "create Conv(float, int) ...")); if (ia32_cg_config.use_sse2) { - res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg, + res = new_bd_ia32_Conv_FP2I(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op); set_ia32_ls_mode(res, src_mode); } else { @@ -3325,32 +3528,23 @@ static ir_node *gen_Conv(ir_node *node) { DB((dbg, LEVEL_1, "create Conv(int, float) ...")); if (ia32_cg_config.use_sse2) { new_op = be_transform_node(op); - res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg, + res = new_bd_ia32_Conv_I2FP(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op); set_ia32_ls_mode(res, tgt_mode); } else { + unsigned int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0); + unsigned float_mantissa = tarval_ieee754_get_mantissa_size(tgt_mode); res = gen_x87_gp_to_fp(node, src_mode); - if(get_Conv_strict(node)) { - /* The strict-Conv is only necessary, if the int mode has more bits - * than the float mantissa */ - size_t int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0); - size_t float_mantissa; - /* FIXME There is no way to get the mantissa size of a mode */ - switch (get_mode_size_bits(tgt_mode)) { - case 32: float_mantissa = 23 + 1; break; // + 1 for implicit 1 - case 64: float_mantissa = 52 + 1; break; - case 80: - case 96: float_mantissa = 64; break; - default: float_mantissa = 0; break; - } - if (float_mantissa < int_mantissa) { - res = gen_x87_strict_conv(tgt_mode, res); - SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node)); - } + + /* we need a strict-Conv, if the int mode has more bits than the + * float mantissa */ + if (float_mantissa < int_mantissa) { + res = gen_x87_strict_conv(tgt_mode, res); + SET_IA32_ORIG_NODE(get_Proj_pred(res), node); } return res; } - } else if(tgt_mode == mode_b) { + } else if (tgt_mode == mode_b) { /* mode_b lowering already took care that we only have 0/1 values */ DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode)); @@ -3384,20 +3578,19 @@ static ir_node *create_immediate_or_transform(ir_node *node, /** * Transforms a FrameAddr into an ia32 Add. */ -static ir_node *gen_be_FrameAddr(ir_node *node) { +static ir_node *gen_be_FrameAddr(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *op = be_get_FrameAddr_frame(node); ir_node *new_op = be_transform_node(op); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_node *new_node; - new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg); - set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node)); + new_node = new_bd_ia32_Lea(dbgi, block, new_op, noreg_GP); + set_ia32_frame_ent(new_node, arch_get_frame_entity(node)); set_ia32_use_frame(new_node); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -3405,7 +3598,8 @@ static ir_node *gen_be_FrameAddr(ir_node *node) { /** * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return. */ -static ir_node *gen_be_Return(ir_node *node) { +static ir_node *gen_be_Return(ir_node *node) +{ ir_graph *irg = current_ir_graph; ir_node *ret_val = get_irn_n(node, be_pos_Return_val); ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem); @@ -3417,7 +3611,6 @@ static ir_node *gen_be_Return(ir_node *node) { ir_mode *mode; ir_node *frame, *sse_store, *fld, *mproj, *barrier; ir_node *new_barrier, *new_ret_val, *new_ret_mem; - ir_node *noreg; ir_node **in; int pn_ret_val, pn_ret_mem, arity, i; @@ -3458,17 +3651,15 @@ static ir_node *gen_be_Return(ir_node *node) { dbgi = get_irn_dbg_info(barrier); block = be_transform_node(get_nodes_block(barrier)); - noreg = ia32_new_NoReg_gp(env_cg); - /* store xmm0 onto stack */ - sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, + sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg_GP, new_ret_mem, new_ret_val); set_ia32_ls_mode(sse_store, mode); set_ia32_op_type(sse_store, ia32_AddrModeD); set_ia32_use_frame(sse_store); /* load into x87 register */ - fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode); + fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, sse_store, mode); set_ia32_op_type(fld, ia32_AddrModeS); set_ia32_use_frame(fld); @@ -3477,7 +3668,7 @@ static ir_node *gen_be_Return(ir_node *node) { /* create a new barrier */ arity = get_irn_arity(barrier); - in = alloca(arity * sizeof(in[0])); + in = ALLOCAN(ir_node*, arity); for (i = 0; i < arity; ++i) { ir_node *new_in; @@ -3498,7 +3689,6 @@ static ir_node *gen_be_Return(ir_node *node) { copy_node_attr(barrier, new_barrier); be_duplicate_deps(barrier, new_barrier); be_set_transformed_node(barrier, new_barrier); - mark_irn_visited(barrier); /* transform normally */ return be_duplicate_node(node); @@ -3512,7 +3702,8 @@ static ir_node *gen_be_AddSP(ir_node *node) ir_node *sz = get_irn_n(node, be_pos_AddSP_size); ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); - return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am); + return gen_binop(node, sp, sz, new_bd_ia32_SubSP, + match_am | match_immediate); } /** @@ -3523,25 +3714,27 @@ static ir_node *gen_be_SubSP(ir_node *node) ir_node *sz = get_irn_n(node, be_pos_SubSP_size); ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); - return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am); + return gen_binop(node, sp, sz, new_bd_ia32_AddSP, + match_am | match_immediate); } /** * Change some phi modes */ -static ir_node *gen_Phi(ir_node *node) { +static ir_node *gen_Phi(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); ir_node *phi; - if(ia32_mode_needs_gp_reg(mode)) { + if (ia32_mode_needs_gp_reg(mode)) { /* we shouldn't have any 64bit stuff around anymore */ assert(get_mode_size_bits(mode) <= 32); /* all integer operations are on 32bit registers now */ mode = mode_Iu; - } else if(mode_is_float(mode)) { + } else if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) { mode = mode_xmm; } else { @@ -3556,7 +3749,6 @@ static ir_node *gen_Phi(ir_node *node) { copy_node_attr(node, phi); be_duplicate_deps(node, phi); - be_set_transformed_node(node, phi); be_enqueue_preds(node); return phi; @@ -3577,15 +3769,12 @@ static ir_node *gen_IJmp(ir_node *node) assert(get_irn_mode(op) == mode_P); - match_arguments(&am, block, NULL, op, NULL, - match_am | match_8bit_am | match_16bit_am | - match_immediate | match_8bit | match_16bit); + match_arguments(&am, block, NULL, op, NULL, match_am | match_immediate); - new_node = new_rd_ia32_IJmp(dbgi, current_ir_graph, new_block, - addr->base, addr->index, addr->mem, - am.new_op2); + new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index, + addr->mem, am.new_op2); set_am_attributes(new_node, &am); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); new_node = fix_mem_proj(new_node, &am); @@ -3607,7 +3796,7 @@ static ir_node *gen_Bound(ir_node *node) ir_graph *irg = current_ir_graph; res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node), - new_rd_ia32_Sub, match_mode_neutral | match_am | match_immediate); + new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate); block = get_nodes_block(res); if (! is_Proj(res)) { @@ -3618,8 +3807,8 @@ static ir_node *gen_Bound(ir_node *node) sub = get_Proj_pred(res); } flags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags); - new_node = new_rd_ia32_Jcc(dbgi, irg, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + new_node = new_bd_ia32_Jcc(dbgi, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned); + SET_IA32_ORIG_NODE(new_node, node); } else { panic("generic Bound not supported in ia32 Backend"); } @@ -3632,7 +3821,7 @@ static ir_node *gen_ia32_l_ShlDep(ir_node *node) ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val); ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count); - return gen_shift_binop(node, left, right, new_rd_ia32_Shl, + return gen_shift_binop(node, left, right, new_bd_ia32_Shl, match_immediate | match_mode_neutral); } @@ -3640,7 +3829,7 @@ static ir_node *gen_ia32_l_ShrDep(ir_node *node) { ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val); ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count); - return gen_shift_binop(node, left, right, new_rd_ia32_Shr, + return gen_shift_binop(node, left, right, new_bd_ia32_Shr, match_immediate); } @@ -3648,18 +3837,19 @@ static ir_node *gen_ia32_l_SarDep(ir_node *node) { ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val); ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count); - return gen_shift_binop(node, left, right, new_rd_ia32_Sar, + return gen_shift_binop(node, left, right, new_bd_ia32_Sar, match_immediate); } -static ir_node *gen_ia32_l_Add(ir_node *node) { +static ir_node *gen_ia32_l_Add(ir_node *node) +{ ir_node *left = get_irn_n(node, n_ia32_l_Add_left); ir_node *right = get_irn_n(node, n_ia32_l_Add_right); - ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, + ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Add, match_commutative | match_am | match_immediate | match_mode_neutral); - if(is_Proj(lowered)) { + if (is_Proj(lowered)) { lowered = get_Proj_pred(lowered); } else { assert(is_ia32_Add(lowered)); @@ -3671,7 +3861,7 @@ static ir_node *gen_ia32_l_Add(ir_node *node) { static ir_node *gen_ia32_l_Adc(ir_node *node) { - return gen_binop_flags(node, new_rd_ia32_Adc, + return gen_binop_flags(node, new_bd_ia32_Adc, match_commutative | match_am | match_immediate | match_mode_neutral); } @@ -3681,11 +3871,12 @@ static ir_node *gen_ia32_l_Adc(ir_node *node) * * @return the created ia32 Mul node */ -static ir_node *gen_ia32_l_Mul(ir_node *node) { +static ir_node *gen_ia32_l_Mul(ir_node *node) +{ ir_node *left = get_binop_left(node); ir_node *right = get_binop_right(node); - return gen_binop(node, left, right, new_rd_ia32_Mul, + return gen_binop(node, left, right, new_bd_ia32_Mul, match_commutative | match_am | match_mode_neutral); } @@ -3694,21 +3885,23 @@ static ir_node *gen_ia32_l_Mul(ir_node *node) { * * @return the created ia32 IMul1OP node */ -static ir_node *gen_ia32_l_IMul(ir_node *node) { +static ir_node *gen_ia32_l_IMul(ir_node *node) +{ ir_node *left = get_binop_left(node); ir_node *right = get_binop_right(node); - return gen_binop(node, left, right, new_rd_ia32_IMul1OP, + return gen_binop(node, left, right, new_bd_ia32_IMul1OP, match_commutative | match_am | match_mode_neutral); } -static ir_node *gen_ia32_l_Sub(ir_node *node) { +static ir_node *gen_ia32_l_Sub(ir_node *node) +{ ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend); ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend); - ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, + ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Sub, match_am | match_immediate | match_mode_neutral); - if(is_Proj(lowered)) { + if (is_Proj(lowered)) { lowered = get_Proj_pred(lowered); } else { assert(is_ia32_Sub(lowered)); @@ -3718,8 +3911,9 @@ static ir_node *gen_ia32_l_Sub(ir_node *node) { return lowered; } -static ir_node *gen_ia32_l_Sbb(ir_node *node) { - return gen_binop_flags(node, new_rd_ia32_Sbb, +static ir_node *gen_ia32_l_Sbb(ir_node *node) +{ + return gen_binop_flags(node, new_bd_ia32_Sbb, match_am | match_immediate | match_mode_neutral); } @@ -3735,7 +3929,6 @@ static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high, { ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_high = be_transform_node(high); ir_node *new_low = be_transform_node(low); @@ -3753,13 +3946,13 @@ static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high, new_count = create_immediate_or_transform(count, 0); if (is_ia32_l_ShlD(node)) { - new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low, + new_node = new_bd_ia32_ShlD(dbgi, new_block, new_high, new_low, new_count); } else { - new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low, + new_node = new_bd_ia32_ShrD(dbgi, new_block, new_high, new_low, new_count); } - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -3780,35 +3973,32 @@ static ir_node *gen_ia32_l_ShrD(ir_node *node) return gen_lowered_64bit_shifts(node, high, low, count); } -static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) { +static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) +{ ir_node *src_block = get_nodes_block(node); ir_node *block = be_transform_node(src_block); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *frame = get_irg_frame(irg); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low); ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high); ir_node *new_val_low = be_transform_node(val_low); ir_node *new_val_high = be_transform_node(val_high); ir_node *in[2]; - ir_node *sync; - ir_node *fild; - ir_node *store_low; - ir_node *store_high; + ir_node *sync, *fild, *res; + ir_node *store_low, *store_high; - if(!mode_is_signed(get_irn_mode(val_high))) { - panic("unsigned long long -> float not supported yet (%+F)", node); + if (ia32_cg_config.use_sse2) { + panic("ia32_l_LLtoFloat not implemented for SSE2"); } /* do a store */ - store_low = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem, + store_low = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem, new_val_low); - store_high = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem, + store_high = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem, new_val_high); - SET_IA32_ORIG_NODE(store_low, ia32_get_old_node_name(env_cg, node)); - SET_IA32_ORIG_NODE(store_high, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(store_low, node); + SET_IA32_ORIG_NODE(store_high, node); set_ia32_use_frame(store_low); set_ia32_use_frame(store_high); @@ -3823,31 +4013,63 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) { sync = new_rd_Sync(dbgi, irg, block, 2, in); /* do a fild */ - fild = new_rd_ia32_vfild(dbgi, irg, block, frame, noreg, sync); + fild = new_bd_ia32_vfild(dbgi, block, frame, noreg_GP, sync); set_ia32_use_frame(fild); set_ia32_op_type(fild, ia32_AddrModeS); set_ia32_ls_mode(fild, mode_Ls); - SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node)); - - return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); + SET_IA32_ORIG_NODE(fild, node); + + res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); + + if (! mode_is_signed(get_irn_mode(val_high))) { + ia32_address_mode_t am; + + ir_node *count = create_Immediate(NULL, 0, 31); + ir_node *fadd; + + am.addr.base = noreg_GP; + am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count); + am.addr.mem = nomem; + am.addr.offset = 0; + am.addr.scale = 2; + am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS); + am.addr.use_frame = 0; + am.addr.frame_entity = NULL; + am.addr.symconst_sign = 0; + am.ls_mode = mode_F; + am.mem_proj = nomem; + am.op_type = ia32_AddrModeS; + am.new_op1 = res; + am.new_op2 = ia32_new_NoReg_vfp(env_cg); + am.pinned = op_pin_state_floats; + am.commutative = 1; + am.ins_permuted = 0; + + fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, + am.new_op1, am.new_op2, get_fpcw()); + set_am_attributes(fadd, &am); + + set_irn_mode(fadd, mode_T); + res = new_rd_Proj(NULL, irg, block, fadd, mode_vfp, pn_ia32_res); + } + return res; } -static ir_node *gen_ia32_l_FloattoLL(ir_node *node) { +static ir_node *gen_ia32_l_FloattoLL(ir_node *node) +{ ir_node *src_block = get_nodes_block(node); ir_node *block = be_transform_node(src_block); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *frame = get_irg_frame(irg); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val); ir_node *new_val = be_transform_node(val); ir_node *fist, *mem; - mem = gen_vfist(dbgi, irg, block, frame, noreg, nomem, new_val, &fist); - SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node)); + mem = gen_vfist(dbgi, irg, block, frame, noreg_GP, nomem, new_val, &fist); + SET_IA32_ORIG_NODE(fist, node); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); set_ia32_ls_mode(fist, mode_Ls); @@ -3858,26 +4080,27 @@ static ir_node *gen_ia32_l_FloattoLL(ir_node *node) { /** * the BAD transformer. */ -static ir_node *bad_transform(ir_node *node) { +static ir_node *bad_transform(ir_node *node) +{ panic("No transform function for %+F available.", node); return NULL; } -static ir_node *gen_Proj_l_FloattoLL(ir_node *node) { +static ir_node *gen_Proj_l_FloattoLL(ir_node *node) +{ ir_graph *irg = current_ir_graph; ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); ir_node *frame = get_irg_frame(irg); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); dbg_info *dbgi = get_irn_dbg_info(node); long pn = get_Proj_proj(node); ir_node *load; ir_node *proj; ia32_attr_t *attr; - load = new_rd_ia32_Load(dbgi, irg, block, frame, noreg, new_pred); - SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); + load = new_bd_ia32_Load(dbgi, block, frame, noreg_GP, new_pred); + SET_IA32_ORIG_NODE(load, node); set_ia32_use_frame(load); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_ls_mode(load, mode_Iu); @@ -3900,7 +4123,8 @@ static ir_node *gen_Proj_l_FloattoLL(ir_node *node) { /** * Transform the Projs of an AddSP. */ -static ir_node *gen_Proj_be_AddSP(ir_node *node) { +static ir_node *gen_Proj_be_AddSP(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); @@ -3911,23 +4135,23 @@ static ir_node *gen_Proj_be_AddSP(ir_node *node) { if (proj == pn_be_AddSP_sp) { ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack); - arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]); + arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); return res; - } else if(proj == pn_be_AddSP_res) { + } else if (proj == pn_be_AddSP_res) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_addr); } else if (proj == pn_be_AddSP_M) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M); } - assert(0); - return new_rd_Unknown(irg, get_irn_mode(node)); + panic("No idea how to transform proj->AddSP"); } /** * Transform the Projs of a SubSP. */ -static ir_node *gen_Proj_be_SubSP(ir_node *node) { +static ir_node *gen_Proj_be_SubSP(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); @@ -3938,20 +4162,20 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node) { if (proj == pn_be_SubSP_sp) { ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack); - arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]); + arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); return res; } else if (proj == pn_be_SubSP_M) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M); } - assert(0); - return new_rd_Unknown(irg, get_irn_mode(node)); + panic("No idea how to transform proj->SubSP"); } /** * Transform and renumber the Projs from a Load. */ -static ir_node *gen_Proj_Load(ir_node *node) { +static ir_node *gen_Proj_Load(ir_node *node) +{ ir_node *new_pred; ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); @@ -4043,20 +4267,19 @@ static ir_node *gen_Proj_Load(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1); } - assert(0); - return new_rd_Unknown(irg, get_irn_mode(node)); + panic("No idea how to transform proj"); } /** * Transform and renumber the Projs from a DivMod like instruction. */ -static ir_node *gen_Proj_DivMod(ir_node *node) { +static ir_node *gen_Proj_DivMod(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); long proj = get_Proj_proj(node); assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)); @@ -4111,23 +4334,22 @@ static ir_node *gen_Proj_DivMod(ir_node *node) { break; } - assert(0); - return new_rd_Unknown(irg, mode); + panic("No idea how to transform proj->DivMod"); } /** * Transform and renumber the Projs from a CopyB. */ -static ir_node *gen_Proj_CopyB(ir_node *node) { +static ir_node *gen_Proj_CopyB(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); long proj = get_Proj_proj(node); - switch(proj) { + switch (proj) { case pn_CopyB_M_regular: if (is_ia32_CopyB_i(new_pred)) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M); @@ -4139,23 +4361,22 @@ static ir_node *gen_Proj_CopyB(ir_node *node) { break; } - assert(0); - return new_rd_Unknown(irg, mode); + panic("No idea how to transform proj->CopyB"); } /** * Transform and renumber the Projs from a Quot. */ -static ir_node *gen_Proj_Quot(ir_node *node) { +static ir_node *gen_Proj_Quot(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); long proj = get_Proj_proj(node); - switch(proj) { + switch (proj) { case pn_Quot_M: if (is_ia32_xDiv(new_pred)) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M); @@ -4176,18 +4397,32 @@ static ir_node *gen_Proj_Quot(ir_node *node) { break; } - assert(0); - return new_rd_Unknown(irg, mode); + panic("No idea how to transform proj->Quot"); } -static ir_node *gen_be_Call(ir_node *node) { - ir_node *res = be_duplicate_node(node); - ir_type *call_tp; - - be_node_add_flags(res, -1, arch_irn_flags_modify_flags); +static ir_node *gen_be_Call(ir_node *node) +{ + dbg_info *const dbgi = get_irn_dbg_info(node); + ir_graph *const irg = current_ir_graph; + ir_node *const src_block = get_nodes_block(node); + ir_node *const block = be_transform_node(src_block); + ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem); + ir_node *const src_sp = get_irn_n(node, be_pos_Call_sp); + ir_node *const sp = be_transform_node(src_sp); + ir_node *const src_ptr = get_irn_n(node, be_pos_Call_ptr); + ia32_address_mode_t am; + ia32_address_t *const addr = &am.addr; + ir_node * mem; + ir_node * call; + int i; + ir_node * fpcw; + ir_node * eax = noreg_GP; + ir_node * ecx = noreg_GP; + ir_node * edx = noreg_GP; + unsigned const pop = be_Call_get_pop(node); + ir_type *const call_tp = be_Call_get_type(node); /* Run the x87 simulator if the call returns a float value */ - call_tp = be_Call_get_type(node); if (get_method_n_ress(call_tp) > 0) { ir_type *const res_type = get_method_res_type(call_tp, 0); ir_mode *const res_mode = get_type_mode(res_type); @@ -4197,12 +4432,572 @@ static ir_node *gen_be_Call(ir_node *node) { } } - return res; + /* We do not want be_Call direct calls */ + assert(be_Call_get_entity(node) == NULL); + + match_arguments(&am, src_block, NULL, src_ptr, src_mem, + match_am | match_immediate); + + i = get_irn_arity(node) - 1; + fpcw = be_transform_node(get_irn_n(node, i--)); + for (; i >= be_pos_Call_first_arg; --i) { + arch_register_req_t const *const req = arch_get_register_req(node, i); + ir_node *const reg_parm = be_transform_node(get_irn_n(node, i)); + + assert(req->type == arch_register_req_type_limited); + assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]); + + switch (*req->limited) { + case 1 << REG_EAX: assert(eax == noreg_GP); eax = reg_parm; break; + case 1 << REG_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break; + case 1 << REG_EDX: assert(edx == noreg_GP); edx = reg_parm; break; + default: panic("Invalid GP register for register parameter"); + } + } + + mem = transform_AM_mem(irg, block, src_ptr, src_mem, addr->mem); + call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem, + am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp); + set_am_attributes(call, &am); + call = fix_mem_proj(call, &am); + + if (get_irn_pinned(node) == op_pin_state_pinned) + set_irn_pinned(call, op_pin_state_pinned); + + SET_IA32_ORIG_NODE(call, node); + return call; +} + +/** + * Transform Builtin trap + */ +static ir_node *gen_trap(ir_node *node) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *mem = be_transform_node(get_Builtin_mem(node)); + + return new_bd_ia32_UD2(dbgi, block, mem); +} + +/** + * Transform Builtin debugbreak + */ +static ir_node *gen_debugbreak(ir_node *node) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *mem = be_transform_node(get_Builtin_mem(node)); + + return new_bd_ia32_Breakpoint(dbgi, block, mem); +} + +/** + * Transform Builtin return_address + */ +static ir_node *gen_return_address(ir_node *node) { + ir_node *param = get_Builtin_param(node, 0); + ir_node *frame = get_Builtin_param(node, 1); + dbg_info *dbgi = get_irn_dbg_info(node); + tarval *tv = get_Const_tarval(param); + unsigned long value = get_tarval_long(tv); + + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *ptr = be_transform_node(frame); + ir_node *load; + + if (value > 0) { + ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block); + ir_node *res = new_bd_ia32_ProduceVal(dbgi, block); + ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value); + } + + /* load the return address from this frame */ + load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem); + + set_irn_pinned(load, get_irn_pinned(node)); + set_ia32_op_type(load, ia32_AddrModeS); + set_ia32_ls_mode(load, mode_Iu); + + set_ia32_am_offs_int(load, 0); + set_ia32_use_frame(load); + set_ia32_frame_ent(load, ia32_get_return_address_entity()); + + if (get_irn_pinned(node) == op_pin_state_floats) { + assert(pn_ia32_xLoad_res == pn_ia32_vfld_res + && pn_ia32_vfld_res == pn_ia32_Load_res + && pn_ia32_Load_res == pn_ia32_res); + arch_irn_add_flags(load, arch_irn_flags_rematerializable); + } + + SET_IA32_ORIG_NODE(load, node); + return new_r_Proj(current_ir_graph, block, load, mode_Iu, pn_ia32_Load_res); } -static ir_node *gen_be_IncSP(ir_node *node) { +/** + * Transform Builtin frame_address + */ +static ir_node *gen_frame_address(ir_node *node) { + ir_node *param = get_Builtin_param(node, 0); + ir_node *frame = get_Builtin_param(node, 1); + dbg_info *dbgi = get_irn_dbg_info(node); + tarval *tv = get_Const_tarval(param); + unsigned long value = get_tarval_long(tv); + + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *ptr = be_transform_node(frame); + ir_node *load; + ir_entity *ent; + + if (value > 0) { + ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block); + ir_node *res = new_bd_ia32_ProduceVal(dbgi, block); + ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value); + } + + /* load the frame address from this frame */ + load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem); + + set_irn_pinned(load, get_irn_pinned(node)); + set_ia32_op_type(load, ia32_AddrModeS); + set_ia32_ls_mode(load, mode_Iu); + + ent = ia32_get_frame_address_entity(); + if (ent != NULL) { + set_ia32_am_offs_int(load, 0); + set_ia32_use_frame(load); + set_ia32_frame_ent(load, ent); + } else { + /* will fail anyway, but gcc does this: */ + set_ia32_am_offs_int(load, 0); + } + + if (get_irn_pinned(node) == op_pin_state_floats) { + assert(pn_ia32_xLoad_res == pn_ia32_vfld_res + && pn_ia32_vfld_res == pn_ia32_Load_res + && pn_ia32_Load_res == pn_ia32_res); + arch_irn_add_flags(load, arch_irn_flags_rematerializable); + } + + SET_IA32_ORIG_NODE(load, node); + return new_r_Proj(current_ir_graph, block, load, mode_Iu, pn_ia32_Load_res); +} + +/** + * Transform Builtin frame_address + */ +static ir_node *gen_prefetch(ir_node *node) { + dbg_info *dbgi; + ir_node *ptr, *block, *mem, *base, *index; + ir_node *param, *new_node; + long rw, locality; + tarval *tv; + ia32_address_t addr; + + if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) { + /* no prefetch at all, route memory */ + return be_transform_node(get_Builtin_mem(node)); + } + + param = get_Builtin_param(node, 1); + tv = get_Const_tarval(param); + rw = get_tarval_long(tv); + + /* construct load address */ + memset(&addr, 0, sizeof(addr)); + ptr = get_Builtin_param(node, 0); + ia32_create_address_mode(&addr, ptr, 0); + base = addr.base; + index = addr.index; + + if (base == NULL) { + base = noreg_GP; + } else { + base = be_transform_node(base); + } + + if (index == NULL) { + index = noreg_GP; + } else { + index = be_transform_node(index); + } + + dbgi = get_irn_dbg_info(node); + block = be_transform_node(get_nodes_block(node)); + mem = be_transform_node(get_Builtin_mem(node)); + + if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) { + /* we have 3DNow!, this was already checked above */ + new_node = new_bd_ia32_PrefetchW(dbgi, block, base, index, mem); + } else if (ia32_cg_config.use_sse_prefetch) { + /* note: rw == 1 is IGNORED in that case */ + param = get_Builtin_param(node, 2); + tv = get_Const_tarval(param); + locality = get_tarval_long(tv); + + /* SSE style prefetch */ + switch (locality) { + case 0: + new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, index, mem); + break; + case 1: + new_node = new_bd_ia32_Prefetch2(dbgi, block, base, index, mem); + break; + case 2: + new_node = new_bd_ia32_Prefetch1(dbgi, block, base, index, mem); + break; + default: + new_node = new_bd_ia32_Prefetch0(dbgi, block, base, index, mem); + break; + } + } else { + assert(ia32_cg_config.use_3dnow_prefetch); + /* 3DNow! style prefetch */ + new_node = new_bd_ia32_Prefetch(dbgi, block, base, index, mem); + } + + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode_Bu); + set_address(new_node, &addr); + + SET_IA32_ORIG_NODE(new_node, node); + + be_dep_on_frame(new_node); + return new_r_Proj(current_ir_graph, block, new_node, mode_M, pn_ia32_Prefetch_M); +} + +/** + * Transform bsf like node + */ +static ir_node *gen_unop_AM(ir_node *node, construct_binop_dest_func *func) +{ + ir_node *param = get_Builtin_param(node, 0); + dbg_info *dbgi = get_irn_dbg_info(node); + + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; + ir_node *cnt; + + match_arguments(&am, block, NULL, param, NULL, match_am); + + cnt = func(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2); + set_am_attributes(cnt, &am); + set_ia32_ls_mode(cnt, get_irn_mode(param)); + + SET_IA32_ORIG_NODE(cnt, node); + return fix_mem_proj(cnt, &am); +} + +/** + * Transform builtin ffs. + */ +static ir_node *gen_ffs(ir_node *node) +{ + ir_node *bsf = gen_unop_AM(node, new_bd_ia32_Bsf); + ir_node *real = skip_Proj(bsf); + dbg_info *dbgi = get_irn_dbg_info(real); + ir_node *block = get_nodes_block(real); + ir_node *flag, *set, *conv, *neg, *or; + + /* bsf x */ + if (get_irn_mode(real) != mode_T) { + set_irn_mode(real, mode_T); + bsf = new_r_Proj(current_ir_graph, block, real, mode_Iu, pn_ia32_res); + } + + flag = new_r_Proj(current_ir_graph, block, real, mode_b, pn_ia32_flags); + + /* sete */ + set = new_bd_ia32_Set(dbgi, block, flag, pn_Cmp_Eq, 0); + SET_IA32_ORIG_NODE(set, node); + + /* conv to 32bit */ + conv = new_bd_ia32_Conv_I2I8Bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu); + SET_IA32_ORIG_NODE(conv, node); + + /* neg */ + neg = new_bd_ia32_Neg(dbgi, block, conv); + + /* or */ + or = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg); + set_ia32_commutative(or); + + /* add 1 */ + return new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP, nomem, or, create_Immediate(NULL, 0, 1)); +} + +/** + * Transform builtin clz. + */ +static ir_node *gen_clz(ir_node *node) +{ + ir_node *bsr = gen_unop_AM(node, new_bd_ia32_Bsr); + ir_node *real = skip_Proj(bsr); + dbg_info *dbgi = get_irn_dbg_info(real); + ir_node *block = get_nodes_block(real); + ir_node *imm = create_Immediate(NULL, 0, 31); + + return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm); +} + +/** + * Transform builtin ctz. + */ +static ir_node *gen_ctz(ir_node *node) +{ + return gen_unop_AM(node, new_bd_ia32_Bsf); +} + +/** + * Transform builtin parity. + */ +static ir_node *gen_parity(ir_node *node) +{ + ir_node *param = get_Builtin_param(node, 0); + dbg_info *dbgi = get_irn_dbg_info(node); + + ir_node *block = get_nodes_block(node); + + ir_node *new_block = be_transform_node(block); + ir_node *imm, *cmp, *new_node; + + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; + + + /* cmp param, 0 */ + match_arguments(&am, block, NULL, param, NULL, match_am); + imm = create_Immediate(NULL, 0, 0); + cmp = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index, + addr->mem, imm, am.new_op2, am.ins_permuted, 0); + set_am_attributes(cmp, &am); + set_ia32_ls_mode(cmp, mode_Iu); + + SET_IA32_ORIG_NODE(cmp, node); + + cmp = fix_mem_proj(cmp, &am); + + /* setp */ + new_node = new_bd_ia32_Set(dbgi, new_block, cmp, ia32_pn_Cmp_parity, 0); + SET_IA32_ORIG_NODE(new_node, node); + + /* conv to 32bit */ + new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP, + nomem, new_node, mode_Bu); + SET_IA32_ORIG_NODE(new_node, node); + return new_node; +} + +/** + * Transform builtin popcount + */ +static ir_node *gen_popcount(ir_node *node) { + ir_node *param = get_Builtin_param(node, 0); + dbg_info *dbgi = get_irn_dbg_info(node); + + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + + ir_node *new_param; + ir_node *imm, *simm, *m1, *s1, *s2, *s3, *s4, *s5, *m2, *m3, *m4, *m5, *m6, *m7, *m8, *m9, *m10, *m11, *m12, *m13; + + /* check for SSE4.2 or SSE4a and use the popcnt instruction */ + if (ia32_cg_config.use_popcnt) { + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; + ir_node *cnt; + + match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am); + + cnt = new_bd_ia32_Popcnt(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2); + set_am_attributes(cnt, &am); + set_ia32_ls_mode(cnt, get_irn_mode(param)); + + SET_IA32_ORIG_NODE(cnt, node); + return fix_mem_proj(cnt, &am); + } + + new_param = be_transform_node(param); + + /* do the standard popcount algo */ + + /* m1 = x & 0x55555555 */ + imm = create_Immediate(NULL, 0, 0x55555555); + m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_param, imm); + + /* s1 = x >> 1 */ + simm = create_Immediate(NULL, 0, 1); + s1 = new_bd_ia32_Shl(dbgi, new_block, new_param, simm); + + /* m2 = s1 & 0x55555555 */ + m2 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s1, imm); + + /* m3 = m1 + m2 */ + m3 = new_bd_ia32_Lea(dbgi, new_block, m2, m1); + + /* m4 = m3 & 0x33333333 */ + imm = create_Immediate(NULL, 0, 0x33333333); + m4 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m3, imm); + + /* s2 = m3 >> 2 */ + simm = create_Immediate(NULL, 0, 2); + s2 = new_bd_ia32_Shl(dbgi, new_block, m3, simm); + + /* m5 = s2 & 0x33333333 */ + m5 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, imm); + + /* m6 = m4 + m5 */ + m6 = new_bd_ia32_Lea(dbgi, new_block, m4, m5); + + /* m7 = m6 & 0x0F0F0F0F */ + imm = create_Immediate(NULL, 0, 0x0F0F0F0F); + m7 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m6, imm); + + /* s3 = m6 >> 4 */ + simm = create_Immediate(NULL, 0, 4); + s3 = new_bd_ia32_Shl(dbgi, new_block, m6, simm); + + /* m8 = s3 & 0x0F0F0F0F */ + m8 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, imm); + + /* m9 = m7 + m8 */ + m9 = new_bd_ia32_Lea(dbgi, new_block, m7, m8); + + /* m10 = m9 & 0x00FF00FF */ + imm = create_Immediate(NULL, 0, 0x00FF00FF); + m10 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m9, imm); + + /* s4 = m9 >> 8 */ + simm = create_Immediate(NULL, 0, 8); + s4 = new_bd_ia32_Shl(dbgi, new_block, m9, simm); + + /* m11 = s4 & 0x00FF00FF */ + m11 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s4, imm); + + /* m12 = m10 + m11 */ + m12 = new_bd_ia32_Lea(dbgi, new_block, m10, m11); + + /* m13 = m12 & 0x0000FFFF */ + imm = create_Immediate(NULL, 0, 0x0000FFFF); + m13 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m12, imm); + + /* s5 = m12 >> 16 */ + simm = create_Immediate(NULL, 0, 16); + s5 = new_bd_ia32_Shl(dbgi, new_block, m12, simm); + + /* res = m13 + s5 */ + return new_bd_ia32_Lea(dbgi, new_block, m13, s5); +} + +/** + * Transform builtin byte swap. + */ +static ir_node *gen_bswap(ir_node *node) { + ir_node *param = be_transform_node(get_Builtin_param(node, 0)); + dbg_info *dbgi = get_irn_dbg_info(node); + + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_mode *mode = get_irn_mode(param); + unsigned size = get_mode_size_bits(mode); + ir_node *m1, *m2, *m3, *m4, *s1, *s2, *s3, *s4; + + switch (size) { + case 32: + if (ia32_cg_config.use_i486) { + /* swap available */ + return new_bd_ia32_Bswap(dbgi, new_block, param); + } + s1 = new_bd_ia32_Shl(dbgi, new_block, param, create_Immediate(NULL, 0, 24)); + s2 = new_bd_ia32_Shl(dbgi, new_block, param, create_Immediate(NULL, 0, 8)); + + m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, create_Immediate(NULL, 0, 0xFF00)); + m2 = new_bd_ia32_Lea(dbgi, new_block, s1, m1); + + s3 = new_bd_ia32_Shr(dbgi, new_block, param, create_Immediate(NULL, 0, 8)); + + m3 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, create_Immediate(NULL, 0, 0xFF0000)); + m4 = new_bd_ia32_Lea(dbgi, new_block, m2, m3); + + s4 = new_bd_ia32_Shr(dbgi, new_block, param, create_Immediate(NULL, 0, 24)); + return new_bd_ia32_Lea(dbgi, new_block, m4, s4); + + case 16: + /* swap16 always available */ + return new_bd_ia32_Bswap16(dbgi, new_block, param); + + default: + panic("Invalid bswap size (%d)", size); + } +} + +/** + * Transform Builtin node. + */ +static ir_node *gen_Builtin(ir_node *node) { + ir_builtin_kind kind = get_Builtin_kind(node); + + switch (kind) { + case ir_bk_trap: + return gen_trap(node); + case ir_bk_debugbreak: + return gen_debugbreak(node); + case ir_bk_return_address: + return gen_return_address(node); + case ir_bk_frame_addess: + return gen_frame_address(node); + case ir_bk_prefetch: + return gen_prefetch(node); + case ir_bk_ffs: + return gen_ffs(node); + case ir_bk_clz: + return gen_clz(node); + case ir_bk_ctz: + return gen_ctz(node); + case ir_bk_parity: + return gen_parity(node); + case ir_bk_popcount: + return gen_popcount(node); + case ir_bk_bswap: + return gen_bswap(node); + } + panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind)); +} + +/** + * Transform Proj(Builtin) node. + */ +static ir_node *gen_Proj_Builtin(ir_node *proj) { + ir_node *node = get_Proj_pred(proj); + ir_node *new_node = be_transform_node(node); + ir_builtin_kind kind = get_Builtin_kind(node); + + switch (kind) { + case ir_bk_return_address: + case ir_bk_frame_addess: + case ir_bk_ffs: + case ir_bk_clz: + case ir_bk_ctz: + case ir_bk_parity: + case ir_bk_popcount: + case ir_bk_bswap: + assert(get_Proj_proj(proj) == pn_Builtin_1_result); + return new_node; + case ir_bk_trap: + case ir_bk_debugbreak: + case ir_bk_prefetch: + assert(get_Proj_proj(proj) == pn_Builtin_M); + return new_node; + } + panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind)); +} + +static ir_node *gen_be_IncSP(ir_node *node) +{ ir_node *res = be_duplicate_node(node); - be_node_add_flags(res, -1, arch_irn_flags_modify_flags); + arch_irn_add_flags(res, arch_irn_flags_modify_flags); return res; } @@ -4210,7 +5005,8 @@ static ir_node *gen_be_IncSP(ir_node *node) { /** * Transform the Projs from a be_Call. */ -static ir_node *gen_Proj_be_Call(ir_node *node) { +static ir_node *gen_Proj_be_Call(ir_node *node) +{ ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *call = get_Proj_pred(node); ir_node *new_call = be_transform_node(call); @@ -4221,7 +5017,7 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { long proj = get_Proj_proj(node); ir_mode *mode = get_irn_mode(node); ir_node *sse_load; - const arch_register_class_t *cls; + ir_node *res; /* The following is kinda tricky: If we're using SSE, then we have to * move the result value of the call in floating point registers to an @@ -4240,9 +5036,9 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { call_res_pred = get_Proj_pred(call_res_new); } - if (call_res_pred == NULL || be_is_Call(call_res_pred)) { + if (call_res_pred == NULL || is_ia32_Call(call_res_pred)) { return new_rd_Proj(dbgi, irg, block, new_call, mode_M, - pn_be_Call_M_regular); + n_ia32_Call_mem); } else { assert(is_ia32_xLoad(call_res_pred)); return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, @@ -4253,7 +5049,6 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)) { ir_node *fstp; ir_node *frame = get_irg_frame(irg); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); //ir_node *p; ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular); ir_node *call_res; @@ -4266,14 +5061,13 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { pn_be_Call_first_res); /* store st(0) onto stack */ - fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem, + fstp = new_bd_ia32_vfst(dbgi, block, frame, noreg_GP, call_mem, call_res, mode); set_ia32_op_type(fstp, ia32_AddrModeD); set_ia32_use_frame(fstp); /* load into SSE register */ - sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp, - mode); + sse_load = new_bd_ia32_xLoad(dbgi, block, frame, noreg_GP, fstp, mode); set_ia32_op_type(sse_load, ia32_AddrModeS); set_ia32_use_frame(sse_load); @@ -4285,11 +5079,51 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { /* transform call modes */ if (mode_is_data(mode)) { - cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1); + const arch_register_class_t *cls = arch_get_irn_reg_class_out(node); mode = cls->mode; } - return new_rd_Proj(dbgi, irg, block, new_call, mode, proj); + /* Map from be_Call to ia32_Call proj number */ + if (proj == pn_be_Call_sp) { + proj = pn_ia32_Call_stack; + } else if (proj == pn_be_Call_M_regular) { + proj = pn_ia32_Call_M; + } else { + arch_register_req_t const *const req = arch_get_register_req_out(node); + int const n_outs = arch_irn_get_n_outs(new_call); + int i; + + assert(proj >= pn_be_Call_first_res); + assert(req->type & arch_register_req_type_limited); + + for (i = 0; i < n_outs; ++i) { + arch_register_req_t const *const new_req = get_ia32_out_req(new_call, i); + + if (!(new_req->type & arch_register_req_type_limited) || + new_req->cls != req->cls || + *new_req->limited != *req->limited) + continue; + + proj = i; + break; + } + assert(i < n_outs); + } + + res = new_rd_Proj(dbgi, irg, block, new_call, mode, proj); + + /* TODO arch_set_irn_register() only operates on Projs, need variant with index */ + switch (proj) { + case pn_ia32_Call_stack: + arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); + break; + + case pn_ia32_Call_fpcw: + arch_set_irn_register(res, &ia32_fp_cw_regs[REG_FPCW]); + break; + } + + return res; } /** @@ -4330,24 +5164,30 @@ static ir_node *gen_Proj_Bound(ir_node *node) static ir_node *gen_Proj_ASM(ir_node *node) { - ir_node *pred; - ir_node *new_pred; - ir_node *block; - - if (get_irn_mode(node) != mode_M) - return be_duplicate_node(node); + ir_mode *mode = get_irn_mode(node); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + ir_node *block = get_nodes_block(new_pred); + long pos = get_Proj_proj(node); + + if (mode == mode_M) { + pos = arch_irn_get_n_outs(new_pred) + 1; + } else if (mode_is_int(mode) || mode_is_reference(mode)) { + mode = mode_Iu; + } else if (mode_is_float(mode)) { + mode = mode_E; + } else { + panic("unexpected proj mode at ASM"); + } - pred = get_Proj_pred(node); - new_pred = be_transform_node(pred); - block = get_nodes_block(new_pred); - return new_r_Proj(current_ir_graph, block, new_pred, mode_M, - get_ia32_n_res(new_pred) + 1); + return new_r_Proj(current_ir_graph, block, new_pred, mode, pos); } /** * Transform and potentially renumber Proj nodes. */ -static ir_node *gen_Proj(ir_node *node) { +static ir_node *gen_Proj(ir_node *node) +{ ir_node *pred = get_Proj_pred(node); long proj; @@ -4357,13 +5197,14 @@ static ir_node *gen_Proj(ir_node *node) { if (proj == pn_Store_M) { return be_transform_node(pred); } else { - assert(0); - return new_r_Bad(current_ir_graph); + panic("No idea how to transform proj->Store"); } case iro_Load: return gen_Proj_Load(node); case iro_ASM: return gen_Proj_ASM(node); + case iro_Builtin: + return gen_Proj_Builtin(node); case iro_Div: case iro_Mod: case iro_DivMod: @@ -4384,18 +5225,19 @@ static ir_node *gen_Proj(ir_node *node) { return gen_Proj_Bound(node); case iro_Start: proj = get_Proj_proj(node); - if (proj == pn_Start_X_initial_exec) { - ir_node *block = get_nodes_block(pred); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *jump; - - /* we exchange the ProjX with a jump */ - block = be_transform_node(block); - jump = new_rd_Jmp(dbgi, current_ir_graph, block); - return jump; - } - if (node == be_get_old_anchor(anchor_tls)) { - return gen_Proj_tls(node); + switch (proj) { + case pn_Start_X_initial_exec: { + ir_node *block = get_nodes_block(pred); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + /* we exchange the ProjX with a jump */ + ir_node *jump = new_rd_Jmp(dbgi, current_ir_graph, new_block); + + return jump; + } + + case pn_Start_P_tls: + return gen_Proj_tls(node); } break; @@ -4428,8 +5270,6 @@ static ir_node *gen_Proj(ir_node *node) { */ static void register_transformers(void) { - ir_op *op_Mulh; - /* first clear the generic function pointer for all ops */ clear_irp_opcodes_generic_func(); @@ -4439,6 +5279,7 @@ static void register_transformers(void) GEN(Add); GEN(Sub); GEN(Mul); + GEN(Mulh); GEN(And); GEN(Or); GEN(Eor); @@ -4506,6 +5347,9 @@ static void register_transformers(void) BAD(EndReg); BAD(EndExcept); + /* handle builtins */ + GEN(Builtin); + /* handle generic backend nodes */ GEN(be_FrameAddr); GEN(be_Call); @@ -4515,10 +5359,6 @@ static void register_transformers(void) GEN(be_SubSP); GEN(be_Copy); - op_Mulh = get_op_Mulh(); - if (op_Mulh) - GEN(Mulh); - #undef GEN #undef BAD } @@ -4526,8 +5366,9 @@ static void register_transformers(void) /** * Pre-transform all unknown and noreg nodes. */ -static void ia32_pretransform_node(void *arch_cg) { - ia32_code_gen_t *cg = arch_cg; +static void ia32_pretransform_node(void) +{ + ia32_code_gen_t *cg = env_cg; cg->unknown_gp = be_pre_transform_node(cg->unknown_gp); cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp); @@ -4535,6 +5376,10 @@ static void ia32_pretransform_node(void *arch_cg) { cg->noreg_gp = be_pre_transform_node(cg->noreg_gp); cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp); cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm); + + nomem = get_irg_no_mem(current_ir_graph); + noreg_GP = ia32_new_NoReg_gp(cg); + get_fpcw(); } @@ -4550,25 +5395,30 @@ static void add_missing_keep_walker(ir_node *node, void *data) ir_mode *mode = get_irn_mode(node); ir_node *last_keep; (void) data; - if(mode != mode_T) + if (mode != mode_T) return; - if(!is_ia32_irn(node)) + if (!is_ia32_irn(node)) return; - n_outs = get_ia32_n_res(node); - if(n_outs <= 0) + n_outs = arch_irn_get_n_outs(node); + if (n_outs <= 0) return; - if(is_ia32_SwitchJmp(node)) + if (is_ia32_SwitchJmp(node)) return; assert(n_outs < (int) sizeof(unsigned) * 8); foreach_out_edge(node, edge) { ir_node *proj = get_edge_src_irn(edge); - int pn = get_Proj_proj(proj); + int pn; + + /* The node could be kept */ + if (is_End(proj)) + continue; if (get_irn_mode(proj) == mode_M) continue; + pn = get_Proj_proj(proj); assert(pn < n_outs); found_projs |= 1 << pn; } @@ -4576,33 +5426,33 @@ static void add_missing_keep_walker(ir_node *node, void *data) /* are keeps missing? */ last_keep = NULL; - for(i = 0; i < n_outs; ++i) { + for (i = 0; i < n_outs; ++i) { ir_node *block; ir_node *in[1]; const arch_register_req_t *req; const arch_register_class_t *cls; - if(found_projs & (1 << i)) { + if (found_projs & (1 << i)) { continue; } req = get_ia32_out_req(node, i); cls = req->cls; - if(cls == NULL) { + if (cls == NULL) { continue; } - if(cls == &ia32_reg_classes[CLASS_ia32_flags]) { + if (cls == &ia32_reg_classes[CLASS_ia32_flags]) { continue; } block = get_nodes_block(node); in[0] = new_r_Proj(current_ir_graph, block, node, arch_register_class_mode(cls), i); - if(last_keep != NULL) { + if (last_keep != NULL) { be_Keep_add_node(last_keep, cls, in[0]); } else { last_keep = be_new_Keep(cls, current_ir_graph, block, 1, in); - if(sched_is_scheduled(node)) { + if (sched_is_scheduled(node)) { sched_add_after(node, last_keep); } } @@ -4620,16 +5470,16 @@ void ia32_add_missing_keeps(ia32_code_gen_t *cg) } /* do the transformation */ -void ia32_transform_graph(ia32_code_gen_t *cg) { +void ia32_transform_graph(ia32_code_gen_t *cg) +{ int cse_last; - ir_graph *irg = cg->irg; register_transformers(); env_cg = cg; initial_fpcw = NULL; BE_TIMER_PUSH(t_heights); - heights = heights_new(irg); + heights = heights_new(cg->irg); BE_TIMER_POP(t_heights); ia32_calculate_non_address_mode_nodes(cg->birg); @@ -4638,7 +5488,7 @@ void ia32_transform_graph(ia32_code_gen_t *cg) { cse_last = get_opt_cse(); set_opt_cse(0); - be_transform_graph(cg->birg, ia32_pretransform_node, cg); + be_transform_graph(cg->birg, ia32_pretransform_node); set_opt_cse(cse_last);