X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=a381cbc4fdc45c8724829e4deb303054ecd36460;hb=b678beb76378c541ac15b40dab86a844e81f59bb;hp=2c9f75ad7a25e48b46fff0585ebfcfd56ccbd7e4;hpb=b77d3a47774fd137aa76b086339fe2394dc84477;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 2c9f75ad7..a381cbc4f 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -55,6 +55,7 @@ #include "../beutil.h" #include "../beirg_t.h" #include "../betranshlp.h" +#include "../be_t.h" #include "bearch_ia32_t.h" #include "ia32_nodes_attr.h" @@ -65,6 +66,7 @@ #include "ia32_optimize.h" #include "ia32_util.h" #include "ia32_address_mode.h" +#include "ia32_architecture.h" #include "gen_ia32_regalloc_if.h" @@ -95,7 +97,6 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) static ia32_code_gen_t *env_cg = NULL; static ir_node *initial_fpcw = NULL; static heights_t *heights = NULL; -static transform_config_t transform_config; extern ir_op *get_op_Mulh(void); @@ -124,16 +125,6 @@ typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg, typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *op); -/**************************************************************************************************** - * _ _ __ _ _ - * | | | | / _| | | (_) - * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __ - * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \ - * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | | - * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_| - * - ****************************************************************************************************/ - static ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type); @@ -191,20 +182,63 @@ static ir_type *get_prim_type(pmap *types, ir_mode *mode) } /** - * Get an atomic entity that is initialized with a tarval + * Creates an immediate. + * + * @param symconst if set, create a SymConst immediate + * @param symconst_sign sign for the symconst + * @param val integer value for the immediate + */ +static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val) +{ + ir_graph *irg = current_ir_graph; + ir_node *start_block = get_irg_start_block(irg); + ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, + symconst, symconst_sign, val); + arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]); + + return immediate; +} + +/** + * Get an atomic entity that is initialized with a tarval forming + * a given constant. + * + * @param cnst the node representing the constant */ static ir_entity *create_float_const_entity(ir_node *cnst) { ia32_isa_t *isa = env_cg->isa; - tarval *tv = get_Const_tarval(cnst); - pmap_entry *e = pmap_find(isa->tv_ent, tv); + tarval *key = get_Const_tarval(cnst); + pmap_entry *e = pmap_find(isa->tv_ent, key); ir_entity *res; ir_graph *rem; - if (! e) { - ir_mode *mode = get_irn_mode(cnst); - ir_type *tp = get_Const_type(cnst); - if (tp == firm_unknown_type) + if (e == NULL) { + tarval *tv = key; + ir_mode *mode = get_tarval_mode(tv); + ir_type *tp; + + if (! ia32_cg_config.use_sse2) { + /* try to reduce the mode to produce smaller sized entities */ + if (mode != mode_F) { + if (tarval_ieee754_can_conv_lossless(tv, mode_F)) { + mode = mode_F; + tv = tarval_convert_to(tv, mode); + } else if (mode != mode_D) { + if (tarval_ieee754_can_conv_lossless(tv, mode_D)) { + mode = mode_D; + tv = tarval_convert_to(tv, mode); + } + } + } + } + + if (mode == get_irn_mode(cnst)) { + /* mode was not changed */ + tp = get_Const_type(cnst); + if (tp == firm_unknown_type) + tp = get_prim_type(isa->types, mode); + } else tp = get_prim_type(isa->types, mode); res = new_entity(get_glob_type(), unique_id(".LC%u"), tp); @@ -221,7 +255,7 @@ static ir_entity *create_float_const_entity(ir_node *cnst) set_atomic_ent_value(res, new_Const_type(tv, tp)); current_ir_graph = rem; - pmap_insert(isa->tv_ent, tv, res); + pmap_insert(isa->tv_ent, key, res); } else { res = e->value; } @@ -247,10 +281,37 @@ static int is_Const_Minus_1(ir_node *node) { static int is_simple_x87_Const(ir_node *node) { tarval *tv = get_Const_tarval(node); + if (tarval_is_null(tv) || tarval_is_one(tv)) + return 1; - if(tarval_is_null(tv) || tarval_is_one(tv)) + /* TODO: match all the other float constants */ + return 0; +} + +/** + * returns true if constant can be created with a simple float command + */ +static int is_simple_sse_Const(ir_node *node) +{ + tarval *tv = get_Const_tarval(node); + ir_mode *mode = get_tarval_mode(tv); + + if (mode == mode_F) return 1; + if (tarval_is_null(tv) || tarval_is_one(tv)) + return 1; + + if (mode == mode_D) { + unsigned val = get_tarval_sub_bits(tv, 0) | + (get_tarval_sub_bits(tv, 1) << 8) | + (get_tarval_sub_bits(tv, 2) << 16) | + (get_tarval_sub_bits(tv, 3) << 24); + if (val == 0) + /* lower 32bit are zero, really a 32bit constant */ + return 1; + } + /* TODO: match all the other float constants */ return 0; } @@ -265,6 +326,8 @@ static ir_node *gen_Const(ir_node *node) { dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); + assert(is_Const(node)); + if (mode_is_float(mode)) { ir_node *res = NULL; ir_node *noreg = ia32_new_NoReg_gp(env_cg); @@ -272,16 +335,63 @@ static ir_node *gen_Const(ir_node *node) { ir_node *load; ir_entity *floatent; - if (USE_SSE2(env_cg)) { - if (is_Const_null(node)) { + if (ia32_cg_config.use_sse2) { + tarval *tv = get_Const_tarval(node); + if (tarval_is_null(tv)) { load = new_rd_ia32_xZero(dbgi, irg, block); set_ia32_ls_mode(load, mode); res = load; + } else if (tarval_is_one(tv)) { + int cnst = mode == mode_F ? 26 : 55; + ir_node *imm1 = create_Immediate(NULL, 0, cnst); + ir_node *imm2 = create_Immediate(NULL, 0, 2); + ir_node *pslld, *psrld; + + load = new_rd_ia32_xAllOnes(dbgi, irg, block); + set_ia32_ls_mode(load, mode); + pslld = new_rd_ia32_xPslld(dbgi, irg, block, load, imm1); + set_ia32_ls_mode(pslld, mode); + psrld = new_rd_ia32_xPsrld(dbgi, irg, block, pslld, imm2); + set_ia32_ls_mode(psrld, mode); + res = psrld; + } else if (mode == mode_F) { + /* we can place any 32bit constant by using a movd gp, sse */ + unsigned val = get_tarval_sub_bits(tv, 0) | + (get_tarval_sub_bits(tv, 1) << 8) | + (get_tarval_sub_bits(tv, 2) << 16) | + (get_tarval_sub_bits(tv, 3) << 24); + ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val); + load = new_rd_ia32_xMovd(dbgi, irg, block, cnst); + set_ia32_ls_mode(load, mode); + res = load; } else { + if (mode == mode_D) { + unsigned val = get_tarval_sub_bits(tv, 0) | + (get_tarval_sub_bits(tv, 1) << 8) | + (get_tarval_sub_bits(tv, 2) << 16) | + (get_tarval_sub_bits(tv, 3) << 24); + if (val == 0) { + ir_node *imm32 = create_Immediate(NULL, 0, 32); + ir_node *cnst, *psllq; + + /* fine, lower 32bit are zero, produce 32bit value */ + val = get_tarval_sub_bits(tv, 4) | + (get_tarval_sub_bits(tv, 5) << 8) | + (get_tarval_sub_bits(tv, 6) << 16) | + (get_tarval_sub_bits(tv, 7) << 24); + cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val); + load = new_rd_ia32_xMovd(dbgi, irg, block, cnst); + set_ia32_ls_mode(load, mode); + psllq = new_rd_ia32_xPsllq(dbgi, irg, block, load, imm32); + set_ia32_ls_mode(psllq, mode); + res = psllq; + goto end; + } + } floatent = create_float_const_entity(node); load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, - mode); + mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable); @@ -291,9 +401,11 @@ static ir_node *gen_Const(ir_node *node) { if (is_Const_null(node)) { load = new_rd_ia32_vfldz(dbgi, irg, block); res = load; + set_ia32_ls_mode(load, mode); } else if (is_Const_one(node)) { load = new_rd_ia32_vfld1(dbgi, irg, block); res = load; + set_ia32_ls_mode(load, mode); } else { floatent = create_float_const_entity(node); @@ -302,12 +414,11 @@ static ir_node *gen_Const(ir_node *node) { set_ia32_am_sc(load, floatent); set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable); res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res); + /* take the mode from the entity */ + set_ia32_ls_mode(load, get_type_mode(get_entity_type(floatent))); } - set_ia32_ls_mode(load, mode); } - - SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); - +end: /* Const Nodes before the initial IncSP are a bad idea, because * they could be spilled and we have no SP ready at that point yet. * So add a dependency to the initial frame pointer calculation to @@ -319,15 +430,15 @@ static ir_node *gen_Const(ir_node *node) { SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); return res; - } else { + } else { /* non-float mode */ ir_node *cnst; tarval *tv = get_Const_tarval(node); long val; tv = tarval_convert_to(tv, mode_Iu); - if(tv == get_tarval_bad() || tv == get_tarval_undefined() - || tv == NULL) { + if (tv == get_tarval_bad() || tv == get_tarval_undefined() || + tv == NULL) { panic("couldn't convert constant tarval (%+F)", node); } val = get_tarval_long(tv); @@ -359,7 +470,7 @@ static ir_node *gen_SymConst(ir_node *node) { ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_node *nomem = new_NoMem(); - if (USE_SSE2(env_cg)) + if (ia32_cg_config.use_sse2) cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E); else cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E); @@ -463,41 +574,58 @@ const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) { } #endif /* NDEBUG */ -int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other) +/** + * return true if the node is a Proj(Load) and could be used in source address + * mode for another node. Will return only true if the @p other node is not + * dependent on the memory of the Load (for binary operations use the other + * input here, for unary operations use NULL). + */ +static int ia32_use_source_address_mode(ir_node *block, ir_node *node, + ir_node *other, ir_node *other2) { - ir_mode *mode = get_irn_mode(node); ir_node *load; long pn; /* float constants are always available */ - if(is_Const(node) && mode_is_float(mode)) { - if(!is_simple_x87_Const(node)) - return 0; - if(get_irn_n_edges(node) > 1) - return 0; - return 1; + if (is_Const(node)) { + ir_mode *mode = get_irn_mode(node); + if (mode_is_float(mode)) { + if (ia32_cg_config.use_sse2) { + if (is_simple_sse_Const(node)) + return 0; + } else { + if (is_simple_x87_Const(node)) + return 0; + } + if (get_irn_n_edges(node) > 1) + return 0; + return 1; + } } - if(!is_Proj(node)) + if (!is_Proj(node)) return 0; load = get_Proj_pred(node); pn = get_Proj_proj(node); - if(!is_Load(load) || pn != pn_Load_res) + if (!is_Load(load) || pn != pn_Load_res) return 0; - if(get_nodes_block(load) != block) + if (get_nodes_block(load) != block) return 0; /* we only use address mode if we're the only user of the load */ - if(get_irn_n_edges(node) > 1) + if (get_irn_n_edges(node) > 1) return 0; /* in some edge cases with address mode we might reach the load normally * and through some AM sequence, if it is already materialized then we * can't create an AM node from it */ - if(be_is_transformed(node)) + if (be_is_transformed(node)) return 0; /* don't do AM if other node inputs depend on the load (via mem-proj) */ - if(other != NULL && get_nodes_block(other) == block - && heights_reachable_in_block(heights, other, load)) + if (other != NULL && get_nodes_block(other) == block && + heights_reachable_in_block(heights, other, load)) + return 0; + if (other2 != NULL && get_nodes_block(other2) == block && + heights_reachable_in_block(heights, other2, load)) return 0; return 1; @@ -518,23 +646,15 @@ struct ia32_address_mode_t { static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem) { - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); + ir_node *noreg_gp; /* construct load address */ memset(addr, 0, sizeof(addr[0])); ia32_create_address_mode(addr, ptr, /*force=*/0); - if(addr->base == NULL) { - addr->base = noreg_gp; - } else { - addr->base = be_transform_node(addr->base); - } - - if(addr->index == NULL) { - addr->index = noreg_gp; - } else { - addr->index = be_transform_node(addr->index); - } + noreg_gp = ia32_new_NoReg_gp(env_cg); + addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp; + addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp; addr->mem = be_transform_node(mem); } @@ -546,17 +666,15 @@ static void build_address(ia32_address_mode_t *am, ir_node *node) ir_node *ptr; ir_node *mem; ir_node *new_mem; - ir_node *base; - ir_node *index; - if(is_Const(node)) { + if (is_Const(node)) { ir_entity *entity = create_float_const_entity(node); addr->base = noreg_gp; addr->index = noreg_gp; addr->mem = new_NoMem(); addr->symconst_ent = entity; addr->use_frame = 1; - am->ls_mode = get_irn_mode(node); + am->ls_mode = get_type_mode(get_entity_type(entity)); am->pinned = op_pin_state_floats; return; } @@ -571,23 +689,9 @@ static void build_address(ia32_address_mode_t *am, ir_node *node) /* construct load address */ ia32_create_address_mode(addr, ptr, /*force=*/0); - base = addr->base; - index = addr->index; - if(base == NULL) { - base = noreg_gp; - } else { - base = be_transform_node(base); - } - - if(index == NULL) { - index = noreg_gp; - } else { - index = be_transform_node(index); - } - - addr->base = base; - addr->index = index; + addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp; + addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp; addr->mem = new_mem; } @@ -603,16 +707,19 @@ static void set_address(ir_node *node, const ia32_address_t *addr) set_ia32_frame_ent(node, addr->frame_entity); } +/** + * Apply attributes of a given address mode to a node. + */ static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am) { set_address(node, &am->addr); set_ia32_op_type(node, am->op_type); set_ia32_ls_mode(node, am->ls_mode); - if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) { + if (am->pinned == op_pin_state_pinned) { set_irn_pinned(node, am->pinned); } - if(am->commutative) + if (am->commutative) set_ia32_commutative(node); } @@ -673,19 +780,29 @@ static ir_node *create_upconv(ir_node *node, ir_node *orig_node) } #endif +/** + * matches operands of a node into ia32 addressing/operand modes. This covers + * usage of source address mode, immediates, operations with non 32-bit modes, + * ... + * The resulting data is filled into the @p am struct. block is the block + * of the node whose arguments are matched. op1, op2 are the first and second + * input that are matched (op1 may be NULL). other_op is another unrelated + * input that is not matched! but which is needed sometimes to check if AM + * for op1/op2 is legal. + * @p flags describes the supported modes of the operation in detail. + */ static void match_arguments(ia32_address_mode_t *am, ir_node *block, - ir_node *op1, ir_node *op2, match_flags_t flags) + ir_node *op1, ir_node *op2, ir_node *other_op, + match_flags_t flags) { - ia32_address_t *addr = &am->addr; - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_node *new_op1; - ir_node *new_op2; - ir_mode *mode = get_irn_mode(op2); + ia32_address_t *addr = &am->addr; + ir_mode *mode = get_irn_mode(op2); + int mode_bits = get_mode_size_bits(mode); + ir_node *noreg_gp, *new_op1, *new_op2; int use_am; unsigned commutative; int use_am_and_immediates; int use_immediate; - int mode_bits = get_mode_size_bits(mode); memset(am, 0, sizeof(am[0])); @@ -697,52 +814,61 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, assert(op2 != NULL); assert(!commutative || op1 != NULL); + assert(use_am || !(flags & match_8bit_am)); + assert(use_am || !(flags & match_16bit_am)); - if(mode_bits == 8) { - if (! (flags & match_8bit_am)) + if (mode_bits == 8) { + if (!(flags & match_8bit_am)) use_am = 0; + /* we don't automatically add upconvs yet */ assert((flags & match_mode_neutral) || (flags & match_8bit)); - } else if(mode_bits == 16) { - if(! (flags & match_16bit_am)) + } else if (mode_bits == 16) { + if (!(flags & match_16bit_am)) use_am = 0; + /* we don't automatically add upconvs yet */ assert((flags & match_mode_neutral) || (flags & match_16bit)); } /* we can simply skip downconvs for mode neutral nodes: the upper bits * can be random for these operations */ - if(flags & match_mode_neutral) { + if (flags & match_mode_neutral) { op2 = ia32_skip_downconv(op2); - if(op1 != NULL) { + if (op1 != NULL) { op1 = ia32_skip_downconv(op1); } } - if(! (flags & match_try_am) && use_immediate) + /* match immediates. firm nodes are normalized: constants are always on the + * op2 input */ + new_op2 = NULL; + if (!(flags & match_try_am) && use_immediate) { new_op2 = try_create_Immediate(op2, 0); - else - new_op2 = NULL; + } - if(new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1)) { + noreg_gp = ia32_new_NoReg_gp(env_cg); + if (new_op2 == NULL && + use_am && ia32_use_source_address_mode(block, op2, op1, other_op)) { build_address(am, op2); new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); - if(mode_is_float(mode)) { + if (mode_is_float(mode)) { new_op2 = ia32_new_NoReg_vfp(env_cg); } else { new_op2 = noreg_gp; } am->op_type = ia32_AddrModeS; - } else if(commutative && (new_op2 == NULL || use_am_and_immediates) && - use_am && ia32_use_source_address_mode(block, op1, op2)) { + } else if (commutative && (new_op2 == NULL || use_am_and_immediates) && + use_am && + ia32_use_source_address_mode(block, op1, op2, other_op)) { ir_node *noreg; build_address(am, op1); - if(mode_is_float(mode)) { + if (mode_is_float(mode)) { noreg = ia32_new_NoReg_vfp(env_cg); } else { noreg = noreg_gp; } - if(new_op2 != NULL) { + if (new_op2 != NULL) { new_op1 = noreg; } else { new_op1 = be_transform_node(op2); @@ -751,7 +877,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } am->op_type = ia32_AddrModeS; } else { - if(flags & match_try_am) { + if (flags & match_try_am) { am->new_op1 = NULL; am->new_op2 = NULL; am->op_type = ia32_Normal; @@ -759,18 +885,18 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); - if(new_op2 == NULL) + if (new_op2 == NULL) new_op2 = be_transform_node(op2); am->op_type = ia32_Normal; am->ls_mode = get_irn_mode(op2); - if(flags & match_mode_neutral) + if (flags & match_mode_neutral) am->ls_mode = mode_Iu; } - if(addr->base == NULL) + if (addr->base == NULL) addr->base = noreg_gp; - if(addr->index == NULL) + if (addr->index == NULL) addr->index = noreg_gp; - if(addr->mem == NULL) + if (addr->mem == NULL) addr->mem = new_NoMem(); am->new_op1 = new_op1; @@ -780,11 +906,10 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) { - ir_graph *irg = current_ir_graph; ir_mode *mode; ir_node *load; - if(am->mem_proj == NULL) + if (am->mem_proj == NULL) return node; /* we have to create a mode_T so the old MemProj can attach to us */ @@ -794,9 +919,9 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) mark_irn_visited(load); be_set_transformed_node(load, node); - if(mode != mode_T) { + if (mode != mode_T) { set_irn_mode(node, mode_T); - return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res); + return new_rd_Proj(NULL, current_ir_graph, get_nodes_block(node), node, mode, pn_ia32_res); } else { return node; } @@ -813,21 +938,22 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2, construct_binop_func *func, match_flags_t flags) { - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_block, *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - match_arguments(&am, block, op1, op2, flags); + block = get_nodes_block(node); + match_arguments(&am, block, op1, op2, NULL, flags); - new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem, - am.new_op1, am.new_op2); + dbgi = get_irn_dbg_info(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, + addr->base, addr->index, addr->mem, + am.new_op1, am.new_op2); set_am_attributes(new_node, &am); /* we can't use source address mode anymore when using immediates */ - if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) + if (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -841,12 +967,12 @@ enum { n_ia32_l_binop_right, n_ia32_l_binop_eflags }; -COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left) -COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right) -COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags) -COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left) -COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right) -COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags) +COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left) +COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right) +COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags) +COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_minuend, n_Sbb_minuend) +COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend) +COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags) /** * Construct a binary operation which also consumes the eflags. @@ -860,21 +986,21 @@ static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, match_flags_t flags) { ir_node *src_block = get_nodes_block(node); - ir_node *block = be_transform_node(src_block); ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left); ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right); - ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags); - ir_node *new_eflags = be_transform_node(eflags); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_node, *eflags, *new_eflags; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - match_arguments(&am, src_block, op1, op2, flags); + match_arguments(&am, src_block, op1, op2, NULL, flags); - new_node = func(dbgi, irg, block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, new_eflags); + dbgi = get_irn_dbg_info(node); + block = be_transform_node(src_block); + eflags = get_irn_n(node, n_ia32_l_binop_eflags); + new_eflags = be_transform_node(eflags); + new_node = func(dbgi, current_ir_graph, block, addr->base, addr->index, + addr->mem, am.new_op1, am.new_op2, new_eflags); set_am_attributes(new_node, &am); /* we can't use source address mode anymore when using immediates */ if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) @@ -889,7 +1015,7 @@ static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, static ir_node *get_fpcw(void) { ir_node *fpcw; - if(initial_fpcw != NULL) + if (initial_fpcw != NULL) return initial_fpcw; fpcw = be_abi_get_ignore_irn(env_cg->birg->abi, @@ -911,18 +1037,24 @@ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, construct_binop_float_func *func, match_flags_t flags) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *new_node; + ir_mode *mode = get_irn_mode(node); + dbg_info *dbgi; + ir_node *block, *new_block, *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - match_arguments(&am, block, op1, op2, flags); + /* cannot use address mode with long double on x87 */ + if (get_mode_size_bits(mode) > 64) + flags &= ~match_am; + + block = get_nodes_block(node); + match_arguments(&am, block, op1, op2, NULL, flags); - new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem, - am.new_op1, am.new_op2, get_fpcw()); + dbgi = get_irn_dbg_info(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, + addr->base, addr->index, addr->mem, + am.new_op1, am.new_op2, get_fpcw()); set_am_attributes(new_node, &am); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -944,21 +1076,17 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, construct_shift_func *func, match_flags_t flags) { - dbg_info *dbgi = get_irn_dbg_info(node); - ir_graph *irg = current_ir_graph; - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_mode *mode = get_irn_mode(node); - ir_node *new_op1; - ir_node *new_op2; - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_block, *new_op1, *new_op2, *new_node; - assert(! mode_is_float(mode)); + assert(! mode_is_float(get_irn_mode(node))); assert(flags & match_immediate); assert((flags & ~(match_mode_neutral | match_immediate)) == 0); - if(flags & match_mode_neutral) { + if (flags & match_mode_neutral) { op1 = ia32_skip_downconv(op1); + } else if (get_mode_size_bits(get_irn_mode(node)) != 32) { + panic("right shifting of non-32bit values not supported, yet"); } new_op1 = be_transform_node(op1); @@ -970,7 +1098,10 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, } new_op2 = create_immediate_or_transform(op2, 0); - new_node = func(dbgi, irg, new_block, new_op1, new_op2); + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, new_op1, new_op2); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); /* lowered shift instruction may have a dependency operand, handle it here */ @@ -994,20 +1125,19 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, match_flags_t flags) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *new_op; - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_block, *new_op, *new_node; assert(flags == 0 || flags == match_mode_neutral); - if(flags & match_mode_neutral) { + if (flags & match_mode_neutral) { op = ia32_skip_downconv(op); } - new_op = be_transform_node(op); - new_node = func(dbgi, irg, new_block, new_op); + new_op = be_transform_node(op); + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, new_op); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -1017,29 +1147,32 @@ static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, ia32_address_t *addr) { - ir_graph *irg = current_ir_graph; - ir_node *base = addr->base; - ir_node *index = addr->index; - ir_node *res; + ir_node *base, *index, *res; - if(base == NULL) { + base = addr->base; + if (base == NULL) { base = ia32_new_NoReg_gp(env_cg); } else { base = be_transform_node(base); } - if(index == NULL) { + index = addr->index; + if (index == NULL) { index = ia32_new_NoReg_gp(env_cg); } else { index = be_transform_node(index); } - res = new_rd_ia32_Lea(dbgi, irg, block, base, index); + res = new_rd_ia32_Lea(dbgi, current_ir_graph, block, base, index); set_address(res, addr); return res; } +/** + * Returns non-zero if a given address mode has a symbolic or + * numerical offset != 0. + */ static int am_has_immediates(const ia32_address_t *addr) { return addr->offset != 0 || addr->symconst_ent != NULL @@ -1052,20 +1185,16 @@ static int am_has_immediates(const ia32_address_t *addr) * @return the created ia32 Add node */ static ir_node *gen_Add(ir_node *node) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *op1 = get_Add_left(node); - ir_node *op2 = get_Add_right(node); - ir_mode *mode = get_irn_mode(node); - ir_node *new_node; - ir_node *add_immediate_op; + ir_mode *mode = get_irn_mode(node); + ir_node *op1 = get_Add_left(node); + ir_node *op2 = get_Add_right(node); + dbg_info *dbgi; + ir_node *block, *new_block, *new_node, *add_immediate_op; ia32_address_t addr; ia32_address_mode_t am; if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) + if (ia32_cg_config.use_sse2) return gen_binop(node, op1, op2, new_rd_ia32_xAdd, match_commutative | match_am); else @@ -1088,8 +1217,14 @@ static ir_node *gen_Add(ir_node *node) { memset(&addr, 0, sizeof(addr)); ia32_create_address_mode(&addr, node, /*force=*/1); add_immediate_op = NULL; + + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + new_block = be_transform_node(block); + /* a constant? */ if(addr.base == NULL && addr.index == NULL) { + ir_graph *irg = current_ir_graph; new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent, addr.symconst_sign, addr.offset); add_irn_dep(new_node, get_irg_frame(irg)); @@ -1118,11 +1253,12 @@ static ir_node *gen_Add(ir_node *node) { } /* test if we can use source address mode */ - match_arguments(&am, block, op1, op2, match_commutative + match_arguments(&am, block, op1, op2, NULL, match_commutative | match_mode_neutral | match_am | match_immediate | match_try_am); /* construct an Add with source address mode */ if (am.op_type == ia32_AddrModeS) { + ir_graph *irg = current_ir_graph; ia32_address_t *am_addr = &am.addr; new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base, am_addr->index, am_addr->mem, am.new_op1, @@ -1152,19 +1288,13 @@ static ir_node *gen_Mul(ir_node *node) { ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) + if (ia32_cg_config.use_sse2) return gen_binop(node, op1, op2, new_rd_ia32_xMul, match_commutative | match_am); else return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, match_commutative | match_am); } - - /* - for the lower 32bit of the result it doesn't matter whether we use - signed or unsigned multiplication so we use IMul as it has fewer - constraints - */ return gen_binop(node, op1, op2, new_rd_ia32_IMul, match_commutative | match_am | match_mode_neutral | match_immediate | match_am_and_immediates); @@ -1186,18 +1316,15 @@ static ir_node *gen_Mulh(ir_node *node) ir_mode *mode = get_irn_mode(node); ir_node *op1 = get_Mulh_left(node); ir_node *op2 = get_Mulh_right(node); - ir_node *proj_EDX; + ir_node *proj_res_high; ir_node *new_node; - match_flags_t flags; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - flags = match_commutative | match_am; - assert(!mode_is_float(mode) && "Mulh with float not supported"); assert(get_mode_size_bits(mode) == 32); - match_arguments(&am, block, op1, op2, flags); + match_arguments(&am, block, op1, op2, NULL, match_commutative | match_am); if (mode_is_signed(mode)) { new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base, @@ -1219,11 +1346,11 @@ static ir_node *gen_Mulh(ir_node *node) fix_mem_proj(new_node, &am); - assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX); - proj_EDX = new_rd_Proj(dbgi, irg, block, new_node, - mode_Iu, pn_ia32_IMul1OP_EDX); + assert(pn_ia32_IMul1OP_res_high == pn_ia32_Mul_res_high); + proj_res_high = new_rd_Proj(dbgi, irg, block, new_node, + mode_Iu, pn_ia32_IMul1OP_res_high); - return proj_EDX; + return proj_res_high; } @@ -1260,7 +1387,6 @@ static ir_node *gen_And(ir_node *node) { return res; } } - return gen_binop(node, op1, op2, new_rd_ia32_And, match_commutative | match_mode_neutral | match_am | match_immediate); @@ -1310,14 +1436,14 @@ static ir_node *gen_Sub(ir_node *node) { ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) + if (ia32_cg_config.use_sse2) return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am); else return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, match_am); } - if(is_Const(op2)) { + if (is_Const(op2)) { ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n", node); } @@ -1343,41 +1469,39 @@ static ir_node *create_Div(ir_node *node) ir_node *new_node; ir_mode *mode; ir_node *sign_extension; - int has_exc; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; /* the upper bits have random contents for smaller modes */ - has_exc = 0; switch (get_irn_opcode(node)) { case iro_Div: op1 = get_Div_left(node); op2 = get_Div_right(node); mem = get_Div_mem(node); mode = get_Div_resmode(node); - has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL; break; case iro_Mod: op1 = get_Mod_left(node); op2 = get_Mod_right(node); mem = get_Mod_mem(node); mode = get_Mod_resmode(node); - has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL; break; case iro_DivMod: op1 = get_DivMod_left(node); op2 = get_DivMod_right(node); mem = get_DivMod_mem(node); mode = get_DivMod_resmode(node); - has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL; break; default: panic("invalid divmod node %+F", node); } - match_arguments(&am, block, op1, op2, match_am); + match_arguments(&am, block, op1, op2, NULL, match_am); - if(!is_NoMem(mem)) { + /* Beware: We don't need a Sync, if the memory predecessor of the Div node + is the memory of the consumed address. We can have only the second op as address + in Div nodes, so check only op2. */ + if(!is_NoMem(mem) && skip_Proj(mem) != skip_Proj(op2)) { new_mem = be_transform_node(mem); if(!is_NoMem(addr->mem)) { ir_node *in[2]; @@ -1396,18 +1520,17 @@ static ir_node *create_Div(ir_node *node) produceval); new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base, - addr->index, new_mem, am.new_op1, - sign_extension, am.new_op2); + addr->index, new_mem, am.new_op2, + am.new_op1, sign_extension); } else { sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0); add_irn_dep(sign_extension, get_irg_frame(irg)); new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base, - addr->index, new_mem, am.new_op1, - sign_extension, am.new_op2); + addr->index, new_mem, am.new_op2, + am.new_op1, sign_extension); } - set_ia32_exc_label(new_node, has_exc); set_irn_pinned(new_node, get_irn_pinned(node)); set_am_attributes(new_node, &am); @@ -1440,10 +1563,10 @@ static ir_node *gen_DivMod(ir_node *node) { */ static ir_node *gen_Quot(ir_node *node) { - ir_node *op1 = get_Quot_left(node); - ir_node *op2 = get_Quot_right(node); + ir_node *op1 = get_Quot_left(node); + ir_node *op2 = get_Quot_right(node); - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am); } else { return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am); @@ -1629,7 +1752,7 @@ static ir_node *gen_Minus(ir_node *node) if (mode_is_float(mode)) { ir_node *new_op = be_transform_node(op); - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { /* TODO: non-optimal... if we have many xXors, then we should * rather create a load for the const and use that instead of * several AM nodes... */ @@ -1681,22 +1804,25 @@ static ir_node *gen_Not(ir_node *node) { */ static ir_node *gen_Abs(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op = get_Abs_op(node); - ir_node *new_op = be_transform_node(op); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg); - ir_node *nomem = new_NoMem(); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *op = get_Abs_op(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); + ir_node *nomem = new_NoMem(); + ir_node *new_op; ir_node *new_node; int size; ir_entity *ent; if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) { - new_node = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, + new_op = be_transform_node(op); + + if (ia32_cg_config.use_sse2) { + ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg); + new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp); size = get_mode_size_bits(mode); @@ -1709,35 +1835,58 @@ static ir_node *gen_Abs(ir_node *node) set_ia32_op_type(new_node, ia32_AddrModeS); set_ia32_ls_mode(new_node, mode); } else { - new_node = new_rd_ia32_vfabs(dbgi, irg, block, new_op); + new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); } } else { - ir_node *xor; - ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block); - ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op, - pval); + ir_node *xor, *pval, *sign_extension; + + if (get_mode_size_bits(mode) == 32) { + new_op = be_transform_node(op); + } else { + new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node); + } - assert(get_mode_size_bits(mode) == 32); + pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block); + sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, + new_op, pval); add_irn_dep(pval, get_irg_frame(irg)); SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node)); - xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, - new_op, sign_extension); + xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp, + nomem, new_op, sign_extension); SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node)); - new_node = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, - xor, sign_extension); + new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp, + nomem, xor, sign_extension); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); } return new_node; } +/** + * Create a bt instruction for x & (1 << n) and place it into the block of cmp. + */ +static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) { + dbg_info *dbgi = get_irn_dbg_info(cmp); + ir_node *block = get_nodes_block(cmp); + ir_node *new_block = be_transform_node(block); + ir_node *op1 = be_transform_node(x); + ir_node *op2 = be_transform_node(n); + + return new_rd_ia32_Bt(dbgi, current_ir_graph, new_block, op1, op2); +} + +/** + * Transform a node returning a "flag" result. + * + * @param node the node to transform + * @param pnc_out the compare mode to use + */ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) { - ir_graph *irg = current_ir_graph; ir_node *flags; ir_node *new_op; ir_node *noreg; @@ -1746,11 +1895,48 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) dbg_info *dbgi; /* we have a Cmp as input */ - if(is_Proj(node)) { + if (is_Proj(node)) { ir_node *pred = get_Proj_pred(node); - if(is_Cmp(pred)) { + if (is_Cmp(pred)) { + pn_Cmp pnc = get_Proj_proj(node); + if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) { + ir_node *l = get_Cmp_left(pred); + ir_node *r = get_Cmp_right(pred); + if (is_And(l)) { + ir_node *la = get_And_left(l); + ir_node *ra = get_And_right(l); + if (is_Shl(la)) { + ir_node *c = get_Shl_left(la); + if (is_Const_1(c) && (is_Const_0(r) || r == la)) { + /* (1 << n) & ra) */ + ir_node *n = get_Shl_right(la); + flags = gen_bt(pred, ra, n); + /* we must generate a Jc/Jnc jump */ + pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge; + if (r == la) + pnc ^= pn_Cmp_Leg; + *pnc_out = ia32_pn_Cmp_unsigned | pnc; + return flags; + } + } + if (is_Shl(ra)) { + ir_node *c = get_Shl_left(ra); + if (is_Const_1(c) && (is_Const_0(r) || r == ra)) { + /* la & (1 << n)) */ + ir_node *n = get_Shl_right(ra); + flags = gen_bt(pred, la, n); + /* we must generate a Jc/Jnc jump */ + pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge; + if (r == ra) + pnc ^= pn_Cmp_Leg; + *pnc_out = ia32_pn_Cmp_unsigned | pnc; + return flags; + } + } + } + } flags = be_transform_node(pred); - *pnc_out = get_Proj_proj(node); + *pnc_out = pnc; return flags; } } @@ -1761,8 +1947,8 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) new_op = be_transform_node(node); noreg = ia32_new_NoReg_gp(env_cg); nomem = new_NoMem(); - flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem, - new_op, new_op, 0, 0); + flags = new_rd_ia32_Test(dbgi, current_ir_graph, new_block, noreg, noreg, nomem, + new_op, new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0); *pnc_out = pn_Cmp_Lg; return flags; } @@ -1807,7 +1993,7 @@ static ir_node *gen_Load(ir_node *node) { } if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem, mode); res_mode = mode_xmm; @@ -1834,6 +2020,10 @@ static ir_node *gen_Load(ir_node *node) { set_ia32_ls_mode(new_node, mode); set_address(new_node, &addr); + if(get_irn_pinned(node) == op_pin_state_floats) { + add_ia32_flags(new_node, arch_irn_flags_rematerializable); + } + /* make sure we are scheduled behind the initial IncSP/Barrier * to avoid spills being placed before it */ @@ -1841,8 +2031,6 @@ static ir_node *gen_Load(ir_node *node) { add_irn_dep(new_node, get_irg_frame(irg)); } - set_ia32_exc_label(new_node, - be_get_Proj_for_pn(node, pn_Load_X_except) != NULL); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); return new_node; @@ -2017,7 +2205,7 @@ static ir_node *try_create_dest_am(ir_node *node) { ir_node *mem = get_Store_mem(node); ir_node *ptr = get_Store_ptr(node); ir_mode *mode = get_irn_mode(val); - int bits = get_mode_size_bits(mode); + unsigned bits = get_mode_size_bits(mode); ir_node *op1; ir_node *op2; ir_node *new_node; @@ -2177,41 +2365,143 @@ static int is_float_to_int32_conv(const ir_node *node) } /** - * Transforms a Store. + * Transform a Store(floatConst). * * @return the created ia32 Store node */ -static ir_node *gen_Store(ir_node *node) -{ +static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) { + ir_mode *mode = get_irn_mode(cns); + int size = get_mode_size_bits(mode); + tarval *tv = get_Const_tarval(cns); ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); ir_node *ptr = get_Store_ptr(node); - ir_node *val = get_Store_value(node); ir_node *mem = get_Store_mem(node); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *noreg = ia32_new_NoReg_gp(env_cg); + int ofs = 4; + ir_node *new_node; + ia32_address_t addr; + + unsigned val = get_tarval_sub_bits(tv, 0) | + (get_tarval_sub_bits(tv, 1) << 8) | + (get_tarval_sub_bits(tv, 2) << 16) | + (get_tarval_sub_bits(tv, 3) << 24); + ir_node *imm = create_Immediate(NULL, 0, val); + + /* construct store address */ + memset(&addr, 0, sizeof(addr)); + ia32_create_address_mode(&addr, ptr, /*force=*/0); + + if (addr.base == NULL) { + addr.base = noreg; + } else { + addr.base = be_transform_node(addr.base); + } + + if (addr.index == NULL) { + addr.index = noreg; + } else { + addr.index = be_transform_node(addr.index); + } + addr.mem = be_transform_node(mem); + + new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base, + addr.index, addr.mem, imm); + + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeD); + set_ia32_ls_mode(new_node, mode_Iu); + + set_address(new_node, &addr); + + /** add more stores if needed */ + while (size > 32) { + unsigned val = get_tarval_sub_bits(tv, ofs) | + (get_tarval_sub_bits(tv, ofs + 1) << 8) | + (get_tarval_sub_bits(tv, ofs + 2) << 16) | + (get_tarval_sub_bits(tv, ofs + 3) << 24); + ir_node *imm = create_Immediate(NULL, 0, val); + + addr.offset += 4; + addr.mem = new_node; + + new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base, + addr.index, addr.mem, imm); + + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeD); + set_ia32_ls_mode(new_node, mode_Iu); + + set_address(new_node, &addr); + size -= 32; + ofs += 4; + } + + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + return new_node; +} + +/** + * Generate a vfist or vfisttp instruction. + */ +static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, + ir_node *mem, ir_node *val) +{ + ir_node *new_node; + + if (ia32_cg_config.use_fisttp) { + /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied + if other users exists */ + const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp]; + val = be_new_Copy(reg_class, irg, block, val); + + new_node = new_rd_ia32_vfisttp(dbgi, irg, block, base, index, mem, val); + } else { + ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); + + /* do a fist */ + new_node = new_rd_ia32_vfist(dbgi, irg, block, base, index, mem, val, trunc_mode); + } + return new_node; +} +/** + * Transforms a normal Store. + * + * @return the created ia32 Store node + */ +static ir_node *gen_normal_Store(ir_node *node) +{ + ir_node *val = get_Store_value(node); ir_mode *mode = get_irn_mode(val); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *ptr = get_Store_ptr(node); + ir_node *mem = get_Store_mem(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_node *new_val; ir_node *new_node; ia32_address_t addr; /* check for destination address mode */ new_node = try_create_dest_am(node); - if(new_node != NULL) + if (new_node != NULL) return new_node; /* construct store address */ memset(&addr, 0, sizeof(addr)); ia32_create_address_mode(&addr, ptr, /*force=*/0); - if(addr.base == NULL) { + if (addr.base == NULL) { addr.base = noreg; } else { addr.base = be_transform_node(addr.base); } - if(addr.index == NULL) { + if (addr.index == NULL) { addr.index = noreg; } else { addr.index = be_transform_node(addr.index); @@ -2221,19 +2511,18 @@ static ir_node *gen_Store(ir_node *node) if (mode_is_float(mode)) { /* convs (and strict-convs) before stores are unnecessary if the mode is the same */ - while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) { + while (is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) { val = get_Conv_op(val); } new_val = be_transform_node(val); - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val); } else { new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val, mode); } - } else if(is_float_to_int32_conv(val)) { - ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); + } else if (is_float_to_int32_conv(val)) { val = get_Conv_op(val); /* convs (and strict-convs) before stores are unnecessary if the mode @@ -2241,10 +2530,8 @@ static ir_node *gen_Store(ir_node *node) while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) { val = get_Conv_op(val); } - new_val = be_transform_node(val); - - new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base, - addr.index, addr.mem, new_val, trunc_mode); + new_val = be_transform_node(val); + new_node = gen_vfist(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val); } else { new_val = create_immediate_or_transform(val, 0); assert(mode != mode_b); @@ -2262,22 +2549,52 @@ static ir_node *gen_Store(ir_node *node) set_ia32_op_type(new_node, ia32_AddrModeD); set_ia32_ls_mode(new_node, mode); - set_ia32_exc_label(new_node, - be_get_Proj_for_pn(node, pn_Store_X_except) != NULL); set_address(new_node, &addr); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); return new_node; } +/** + * Transforms a Store. + * + * @return the created ia32 Store node + */ +static ir_node *gen_Store(ir_node *node) +{ + ir_node *val = get_Store_value(node); + ir_mode *mode = get_irn_mode(val); + + if (mode_is_float(mode) && is_Const(val)) { + int transform = 1; + + /* we are storing a floating point constant */ + if (ia32_cg_config.use_sse2) { + transform = !is_simple_sse_Const(val); + } else { + transform = !is_simple_x87_Const(val); + } + if (transform) + return gen_float_const_Store(node, val); + } + return gen_normal_Store(node); +} + +/** + * Transforms a Switch. + * + * @return the created ia32 SwitchJmp node + */ static ir_node *create_Switch(ir_node *node) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *sel = get_Cond_selector(node); - ir_node *new_sel = be_transform_node(sel); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *sel = get_Cond_selector(node); + ir_node *new_sel = be_transform_node(sel); int switch_min = INT_MAX; + int switch_max = INT_MIN; + long default_pn = get_Cond_defaultProj(node); ir_node *new_node; const ir_edge_t *edge; @@ -2286,9 +2603,18 @@ static ir_node *create_Switch(ir_node *node) /* determine the smallest switch case value */ foreach_out_edge(node, edge) { ir_node *proj = get_edge_src_irn(edge); - int pn = get_Proj_proj(proj); + long pn = get_Proj_proj(proj); + if(pn == default_pn) + continue; + if(pn < switch_min) switch_min = pn; + if(pn > switch_max) + switch_max = pn; + } + + if((unsigned) (switch_max - switch_min) > 256000) { + panic("Size of switch %+F bigger than 256000", node); } if (switch_min != 0) { @@ -2302,13 +2628,15 @@ static ir_node *create_Switch(ir_node *node) SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node)); } - new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, - get_Cond_defaultProj(node)); + new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, default_pn); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); return new_node; } +/** + * Transform a Cond node. + */ static ir_node *gen_Cond(ir_node *node) { ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); @@ -2324,7 +2652,7 @@ static ir_node *gen_Cond(ir_node *node) { return create_Switch(node); } - /* we get flags from a cmp */ + /* we get flags from a Cmp */ flags = get_flags_node(sel, &pnc); new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc); @@ -2333,8 +2661,6 @@ static ir_node *gen_Cond(ir_node *node) { return new_node; } - - /** * Transforms a CopyB node. * @@ -2401,14 +2727,14 @@ static ir_node *create_Fucom(ir_node *node) ir_node *new_right; ir_node *new_node; - if(transform_config.use_fucomi) { + if(ia32_cg_config.use_fucomi) { new_right = be_transform_node(right); new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0); set_ia32_commutative(new_node); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); } else { - if(transform_config.use_ftst && is_Const_null(right)) { + if(ia32_cg_config.use_ftst && is_Const_0(right)) { new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0); } else { @@ -2440,7 +2766,8 @@ static ir_node *create_Ucomi(ir_node *node) ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - match_arguments(&am, src_block, left, right, match_commutative | match_am); + match_arguments(&am, src_block, left, right, NULL, + match_commutative | match_am); new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, @@ -2473,6 +2800,9 @@ static int can_fold_test_and(ir_node *node) return 1; } +/** + * Generate code for a Cmp. + */ static ir_node *gen_Cmp(ir_node *node) { ir_graph *irg = current_ir_graph; @@ -2488,7 +2818,7 @@ static ir_node *gen_Cmp(ir_node *node) int cmp_unsigned; if(mode_is_float(cmp_mode)) { - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { return create_Ucomi(node); } else { return create_Fucom(node); @@ -2509,7 +2839,8 @@ static ir_node *gen_Cmp(ir_node *node) ir_node *and_right = get_And_right(left); ir_mode *mode = get_irn_mode(and_left); - match_arguments(&am, block, and_left, and_right, match_commutative | + match_arguments(&am, block, and_left, and_right, NULL, + match_commutative | match_am | match_8bit_am | match_16bit_am | match_am_and_immediates | match_immediate | match_8bit | match_16bit); @@ -2524,8 +2855,9 @@ static ir_node *gen_Cmp(ir_node *node) am.new_op2, am.ins_permuted, cmp_unsigned); } } else { - match_arguments(&am, block, NULL, left, match_am | match_8bit_am | - match_16bit_am | match_8bit | match_16bit); + match_arguments(&am, block, NULL, left, NULL, + match_am | match_8bit_am | match_16bit_am | + match_8bit | match_16bit); if (am.op_type == ia32_AddrModeS) { /* Cmp(AM, 0) */ ir_node *imm_zero = try_create_Immediate(right, 0); @@ -2556,8 +2888,9 @@ static ir_node *gen_Cmp(ir_node *node) } } else { /* Cmp(left, right) */ - match_arguments(&am, block, left, right, match_commutative | match_am | - match_8bit_am | match_16bit_am | match_am_and_immediates | + match_arguments(&am, block, left, right, NULL, + match_commutative | match_am | match_8bit_am | + match_16bit_am | match_am_and_immediates | match_immediate | match_8bit | match_16bit); if (get_mode_size_bits(cmp_mode) == 8) { new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, @@ -2581,7 +2914,8 @@ static ir_node *gen_Cmp(ir_node *node) return new_node; } -static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc) +static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, + pn_Cmp pnc) { ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); @@ -2594,7 +2928,7 @@ static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc) ia32_address_mode_t am; ia32_address_t *addr; - assert(transform_config.use_cmov); + assert(ia32_cg_config.use_cmov); assert(mode_needs_gp_reg(get_irn_mode(val_true))); addr = &am.addr; @@ -2602,7 +2936,7 @@ static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc) match_flags = match_commutative | match_am | match_16bit_am | match_mode_neutral; - match_arguments(&am, block, val_false, val_true, match_flags); + match_arguments(&am, block, val_false, val_true, flags, match_flags); new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, new_flags, @@ -2669,7 +3003,7 @@ static ir_node *gen_Psi(ir_node *node) } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) { new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1); } else { - new_node = create_CMov(node, flags, pnc); + new_node = create_CMov(node, cond, flags, pnc); } return new_node; } @@ -2686,14 +3020,10 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) { ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *noreg = ia32_new_NoReg_gp(cg); - ir_node *trunc_mode = ia32_new_Fpu_truncate(cg); ir_mode *mode = get_irn_mode(node); ir_node *fist, *load; - /* do a fist */ - fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, - new_NoMem(), new_op, trunc_mode); - + fist = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, new_NoMem(), new_op); set_irn_pinned(fist, op_pin_state_floats); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); @@ -2757,17 +3087,6 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) return new_node; } -static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val) -{ - ir_graph *irg = current_ir_graph; - ir_node *start_block = get_irg_start_block(irg); - ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, - symconst, symconst_sign, val); - arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]); - - return immediate; -} - /** * Create a conversion from general purpose to x87 register */ @@ -2791,7 +3110,8 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { if (src_mode == mode_Is) { ia32_address_mode_t am; - match_arguments(&am, src_block, NULL, op, match_am | match_try_am); + match_arguments(&am, src_block, NULL, op, NULL, + match_am | match_try_am); if (am.op_type == ia32_AddrModeS) { ia32_address_t *addr = &am.addr; @@ -2893,6 +3213,7 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, ia32_address_mode_t am; ia32_address_t *addr = &am.addr; + (void) node; if (src_bits < tgt_bits) { smaller_mode = src_mode; smaller_bits = src_bits; @@ -2908,8 +3229,9 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, } #endif - match_arguments(&am, block, NULL, op, - match_8bit | match_16bit | match_8bit_am | match_16bit_am); + match_arguments(&am, block, NULL, op, NULL, + match_8bit | match_16bit | + match_am | match_8bit_am | match_16bit_am); if (smaller_bits == 8) { new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base, addr->index, addr->mem, am.new_op2, @@ -2949,14 +3271,14 @@ static ir_node *gen_Conv(ir_node *node) { ir_node *res = NULL; if (src_mode == mode_b) { - assert(mode_is_int(tgt_mode)); + assert(mode_is_int(tgt_mode) || mode_is_reference(tgt_mode)); /* nothing to do, we already model bools as 0/1 ints */ return be_transform_node(op); } if (src_mode == tgt_mode) { if (get_Conv_strict(node)) { - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { /* when we are in SSE mode, we can kill all strict no-op conversion */ return be_transform_node(op); } @@ -2979,7 +3301,7 @@ static ir_node *gen_Conv(ir_node *node) { } /* ... to float */ - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { DB((dbg, LEVEL_1, "create Conv(float, float) ...")); res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg, nomem, new_op); @@ -2996,7 +3318,7 @@ static ir_node *gen_Conv(ir_node *node) { } else { /* ... to int */ DB((dbg, LEVEL_1, "create Conv(float, int) ...")); - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg, nomem, new_op); set_ia32_ls_mode(res, src_mode); @@ -3009,7 +3331,7 @@ static ir_node *gen_Conv(ir_node *node) { if (mode_is_float(tgt_mode)) { /* ... to float */ DB((dbg, LEVEL_1, "create Conv(int, float) ...")); - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { new_op = be_transform_node(op); res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg, nomem, new_op); @@ -3187,8 +3509,8 @@ static const arch_register_req_t no_register_req = { arch_register_req_type_none, NULL, /* regclass */ NULL, /* limit bitset */ - { -1, -1 }, /* same pos */ - -1 /* different pos */ + 0, /* same pos */ + 0 /* different pos */ }; /** @@ -3214,7 +3536,7 @@ static void parse_asm_constraint(int pos, constraint_t *constraint, const char * ir_graph *irg = current_ir_graph; struct obstack *obst = get_irg_obstack(irg); arch_register_req_t *req; - unsigned *limited_ptr; + unsigned *limited_ptr = NULL; int p; int same_as = -1; @@ -3224,7 +3546,7 @@ static void parse_asm_constraint(int pos, constraint_t *constraint, const char * /* a memory constraint: no need to do anything in backend about it * (the dependencies are already respected by the memory edge of * the node) */ - constraint->req = &no_register_req; + constraint->req = &no_register_req; return; } @@ -3406,9 +3728,8 @@ static void parse_asm_constraint(int pos, constraint_t *constraint, const char * req->cls = other_constr->cls; req->type = arch_register_req_type_should_be_same; req->limited = NULL; - req->other_same[0] = pos; - req->other_same[1] = -1; - req->other_different = -1; + req->other_same = 1U << pos; + req->other_different = 0; /* switch constraints. This is because in firm we have same_as * constraints on the output constraints while in the gcc asm syntax @@ -3454,13 +3775,53 @@ static void parse_asm_constraint(int pos, constraint_t *constraint, const char * } static void parse_clobber(ir_node *node, int pos, constraint_t *constraint, - const char *c) + const char *clobber) { - (void) node; + ir_graph *irg = get_irn_irg(node); + struct obstack *obst = get_irg_obstack(irg); + const arch_register_t *reg = NULL; + int c; + size_t r; + arch_register_req_t *req; + const arch_register_class_t *cls; + unsigned *limited; + (void) pos; - (void) constraint; - (void) c; - panic("Clobbers not supported yet"); + + /* TODO: construct a hashmap instead of doing linear search for clobber + * register */ + for(c = 0; c < N_CLASSES; ++c) { + cls = & ia32_reg_classes[c]; + for(r = 0; r < cls->n_regs; ++r) { + const arch_register_t *temp_reg = arch_register_for_index(cls, r); + if(strcmp(temp_reg->name, clobber) == 0 + || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) { + reg = temp_reg; + break; + } + } + if(reg != NULL) + break; + } + if(reg == NULL) { + panic("Register '%s' mentioned in asm clobber is unknown\n", clobber); + return; + } + + assert(reg->index < 32); + + limited = obstack_alloc(obst, sizeof(limited[0])); + *limited = 1 << reg->index; + + req = obstack_alloc(obst, sizeof(req[0])); + memset(req, 0, sizeof(req[0])); + req->type = arch_register_req_type_limited; + req->cls = cls; + req->limited = limited; + + constraint->req = req; + constraint->immediate_possible = 0; + constraint->immediate_type = 0; } static int is_memory_op(const ir_asm_constraint *constraint) @@ -3509,6 +3870,9 @@ static ir_node *gen_ASM(ir_node *node) n_out_constraints = get_ASM_n_output_constraints(node); n_clobbers = get_ASM_n_clobbers(node); out_arity = n_out_constraints + n_clobbers; + /* hack to keep space for mem proj */ + if(n_clobbers > 0) + out_arity += 1; in_constraints = get_ASM_input_constraints(node); out_constraints = get_ASM_output_constraints(node); @@ -3531,14 +3895,19 @@ static ir_node *gen_ASM(ir_node *node) if(constraint->pos > reg_map_size) reg_map_size = constraint->pos; - } else { + + out_reg_reqs[i] = parsed_constraint.req; + } else if(i < out_arity - 1) { ident *glob_id = clobbers [i - n_out_constraints]; + assert(glob_id != NULL); c = get_id_str(glob_id); parse_clobber(node, i, &parsed_constraint, c); - } - out_reg_reqs[i] = parsed_constraint.req; + out_reg_reqs[i+1] = parsed_constraint.req; + } } + if(n_clobbers > 1) + out_reg_reqs[n_out_constraints] = &no_register_req; /* construct input constraints */ in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0])); @@ -3613,16 +3982,6 @@ static ir_node *gen_ASM(ir_node *node) return new_node; } -/******************************************** - * _ _ - * | | | | - * | |__ ___ _ __ ___ __| | ___ ___ - * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __| - * | |_) | __/ | | | (_) | (_| | __/\__ \ - * |_.__/ \___|_| |_|\___/ \__,_|\___||___/ - * - ********************************************/ - /** * Transforms a FrameAddr into an ia32 Add. */ @@ -3664,7 +4023,7 @@ static ir_node *gen_be_Return(ir_node *node) { int pn_ret_val, pn_ret_mem, arity, i; assert(ret_val != NULL); - if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) { + if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) { return be_duplicate_node(node); } @@ -3777,14 +4136,22 @@ static ir_node *gen_Unknown(ir_node *node) { ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { return ia32_new_Unknown_xmm(env_cg); } else { - /* Unknown nodes are buggy in x87 sim, use zero for now... */ + /* Unknown nodes are buggy in x87 simulator, use zero for now... */ ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_irg_start_block(irg); - return new_rd_ia32_vfldz(dbgi, irg, block); + ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block); + + /* Const Nodes before the initial IncSP are a bad idea, because + * they could be spilled and we have no SP ready at that point yet. + * So add a dependency to the initial frame pointer calculation to + * avoid that situation. + */ + add_irn_dep(ret, get_irg_frame(irg)); + return ret; } } else if (mode_needs_gp_reg(mode)) { return ia32_new_Unknown_gp(env_cg); @@ -3810,7 +4177,7 @@ static ir_node *gen_Phi(ir_node *node) { /* all integer operations are on 32bit registers now */ mode = mode_Iu; } else if(mode_is_float(mode)) { - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { mode = mode_xmm; } else { mode = mode_vfp; @@ -3846,7 +4213,7 @@ static ir_node *gen_IJmp(ir_node *node) assert(get_irn_mode(op) == mode_P); - match_arguments(&am, block, NULL, op, + match_arguments(&am, block, NULL, op, NULL, match_am | match_8bit_am | match_16bit_am | match_immediate | match_8bit | match_16bit); @@ -3860,19 +4227,6 @@ static ir_node *gen_IJmp(ir_node *node) return new_node; } - -/********************************************************************** - * _ _ _ - * | | | | | | - * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___ - * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __| - * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \ - * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/ - * - **********************************************************************/ - -/* These nodes are created in intrinsic lowering (64bit -> 32bit) */ - typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \ ir_node *mem); @@ -3950,8 +4304,8 @@ static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func) static ir_node *gen_ia32_l_ShlDep(ir_node *node) { - ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_left); - ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_right); + ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val); + ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count); return gen_shift_binop(node, left, right, new_rd_ia32_Shl, match_immediate | match_mode_neutral); @@ -3959,16 +4313,16 @@ static ir_node *gen_ia32_l_ShlDep(ir_node *node) static ir_node *gen_ia32_l_ShrDep(ir_node *node) { - ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_left); - ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_right); + ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val); + ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count); return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate); } static ir_node *gen_ia32_l_SarDep(ir_node *node) { - ir_node *left = get_irn_n(node, n_ia32_l_SarDep_left); - ir_node *right = get_irn_n(node, n_ia32_l_SarDep_right); + ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val); + ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count); return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate); } @@ -4045,13 +4399,10 @@ static ir_node *gen_ia32_l_vfist(ir_node *node) { dbg_info *dbgi = get_irn_dbg_info(node); ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_mode *mode = get_ia32_ls_mode(node); - ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); ir_node *new_op; long am_offs; - new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem, - new_val, trunc_mode); - + new_op = gen_vfist(dbgi, irg, block, new_ptr, noreg, new_mem, new_val); am_offs = get_ia32_am_offs_int(node); add_ia32_am_offs_int(new_op, am_offs); @@ -4084,16 +4435,16 @@ static ir_node *gen_ia32_l_Mul(ir_node *node) { * @return the created ia32 IMul1OP node */ static ir_node *gen_ia32_l_IMul(ir_node *node) { - ir_node *left = get_binop_left(node); - ir_node *right = get_binop_right(node); + ir_node *left = get_binop_left(node); + ir_node *right = get_binop_right(node); return gen_binop(node, left, right, new_rd_ia32_IMul1OP, match_commutative | match_am | match_mode_neutral); } static ir_node *gen_ia32_l_Sub(ir_node *node) { - ir_node *left = get_irn_n(node, n_ia32_l_Sub_left); - ir_node *right = get_irn_n(node, n_ia32_l_Sub_right); + ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend); + ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend); ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, match_am | match_immediate | match_mode_neutral); @@ -4153,131 +4504,93 @@ static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high, static ir_node *gen_ia32_l_ShlD(ir_node *node) { - ir_node *high = get_irn_n(node, n_ia32_l_ShlD_high); - ir_node *low = get_irn_n(node, n_ia32_l_ShlD_low); + ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high); + ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low); ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count); return gen_lowered_64bit_shifts(node, high, low, count); } static ir_node *gen_ia32_l_ShrD(ir_node *node) { - ir_node *high = get_irn_n(node, n_ia32_l_ShrD_high); - ir_node *low = get_irn_n(node, n_ia32_l_ShrD_low); + ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high); + ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low); ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count); return gen_lowered_64bit_shifts(node, high, low, count); } -/** - * In case SSE Unit is used, the node is transformed into a vfst + xLoad. - */ -static ir_node *gen_ia32_l_X87toSSE(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *val = get_irn_n(node, 1); - ir_node *new_val = be_transform_node(val); - ia32_code_gen_t *cg = env_cg; - ir_node *res = NULL; - ir_graph *irg = current_ir_graph; - dbg_info *dbgi; - ir_node *noreg, *new_ptr, *new_mem; - ir_node *ptr, *mem; - - if (USE_SSE2(cg)) { - return new_val; - } - - mem = get_irn_n(node, 2); - new_mem = be_transform_node(mem); - ptr = get_irn_n(node, 0); - new_ptr = be_transform_node(ptr); - noreg = ia32_new_NoReg_gp(cg); - dbgi = get_irn_dbg_info(node); - - /* Store x87 -> MEM */ - res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val, - get_ia32_ls_mode(node)); - set_ia32_frame_ent(res, get_ia32_frame_ent(node)); - set_ia32_use_frame(res); - set_ia32_ls_mode(res, get_ia32_ls_mode(node)); - set_ia32_op_type(res, ia32_AddrModeD); - - /* Load MEM -> SSE */ - res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res, - get_ia32_ls_mode(node)); - set_ia32_frame_ent(res, get_ia32_frame_ent(node)); - set_ia32_use_frame(res); - set_ia32_op_type(res, ia32_AddrModeS); - res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res); +static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) { + ir_node *src_block = get_nodes_block(node); + ir_node *block = be_transform_node(src_block); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *frame = get_irg_frame(irg); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + ir_node *nomem = new_NoMem(); + ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low); + ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high); + ir_node *new_val_low = be_transform_node(val_low); + ir_node *new_val_high = be_transform_node(val_high); + ir_node *in[2]; + ir_node *sync; + ir_node *fild; + ir_node *store_low; + ir_node *store_high; - return res; -} + if(!mode_is_signed(get_irn_mode(val_high))) { + panic("unsigned long long -> float not supported yet (%+F)", node); + } -/** - * In case SSE Unit is used, the node is transformed into a xStore + vfld. - */ -static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *val = get_irn_n(node, 1); - ir_node *new_val = be_transform_node(val); - ia32_code_gen_t *cg = env_cg; - ir_graph *irg = current_ir_graph; - ir_node *res = NULL; - ir_entity *fent = get_ia32_frame_ent(node); - ir_mode *lsmode = get_ia32_ls_mode(node); - int offs = 0; - ir_node *noreg, *new_ptr, *new_mem; - ir_node *ptr, *mem; - dbg_info *dbgi; - - if (! USE_SSE2(cg)) { - /* SSE unit is not used -> skip this node. */ - return new_val; - } - - ptr = get_irn_n(node, 0); - new_ptr = be_transform_node(ptr); - mem = get_irn_n(node, 2); - new_mem = be_transform_node(mem); - noreg = ia32_new_NoReg_gp(cg); - dbgi = get_irn_dbg_info(node); - - /* Store SSE -> MEM */ - if (is_ia32_xLoad(skip_Proj(new_val))) { - ir_node *ld = skip_Proj(new_val); - - /* we can vfld the value directly into the fpu */ - fent = get_ia32_frame_ent(ld); - ptr = get_irn_n(ld, 0); - offs = get_ia32_am_offs_int(ld); - } else { - res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem, - new_val); - set_ia32_frame_ent(res, fent); - set_ia32_use_frame(res); - set_ia32_ls_mode(res, lsmode); - set_ia32_op_type(res, ia32_AddrModeD); - mem = res; - } - - /* Load MEM -> x87 */ - res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode); - set_ia32_frame_ent(res, fent); - set_ia32_use_frame(res); - add_ia32_am_offs_int(res, offs); - set_ia32_op_type(res, ia32_AddrModeS); - res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res); + /* do a store */ + store_low = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem, + new_val_low); + store_high = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem, + new_val_high); + SET_IA32_ORIG_NODE(store_low, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(store_high, ia32_get_old_node_name(env_cg, node)); + + set_ia32_use_frame(store_low); + set_ia32_use_frame(store_high); + set_ia32_op_type(store_low, ia32_AddrModeD); + set_ia32_op_type(store_high, ia32_AddrModeD); + set_ia32_ls_mode(store_low, mode_Iu); + set_ia32_ls_mode(store_high, mode_Is); + add_ia32_am_offs_int(store_high, 4); + + in[0] = store_low; + in[1] = store_high; + sync = new_rd_Sync(dbgi, irg, block, 2, in); - return res; + /* do a fild */ + fild = new_rd_ia32_vfild(dbgi, irg, block, frame, noreg, sync); + + set_ia32_use_frame(fild); + set_ia32_op_type(fild, ia32_AddrModeS); + set_ia32_ls_mode(fild, mode_Ls); + + SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node)); + + return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); } -/********************************************************* - * _ _ _ - * (_) | | (_) - * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __ - * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__| - * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ | - * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_| - * - *********************************************************/ +static ir_node *gen_ia32_l_FloattoLL(ir_node *node) { + ir_node *src_block = get_nodes_block(node); + ir_node *block = be_transform_node(src_block); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *frame = get_irg_frame(irg); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + ir_node *nomem = new_NoMem(); + ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val); + ir_node *new_val = be_transform_node(val); + + ir_node *fist = gen_vfist(dbgi, irg, block, frame, noreg, nomem, new_val); + SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node)); + set_ia32_use_frame(fist); + set_ia32_op_type(fist, ia32_AddrModeD); + set_ia32_ls_mode(fist, mode_Ls); + + return fist; +} /** * the BAD transformer. @@ -4287,6 +4600,40 @@ static ir_node *bad_transform(ir_node *node) { return NULL; } +static ir_node *gen_Proj_l_FloattoLL(ir_node *node) { + ir_graph *irg = current_ir_graph; + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + ir_node *frame = get_irg_frame(irg); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + dbg_info *dbgi = get_irn_dbg_info(node); + long pn = get_Proj_proj(node); + ir_node *load; + ir_node *proj; + ia32_attr_t *attr; + + load = new_rd_ia32_Load(dbgi, irg, block, frame, noreg, new_pred); + SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); + set_ia32_use_frame(load); + set_ia32_op_type(load, ia32_AddrModeS); + set_ia32_ls_mode(load, mode_Iu); + /* we need a 64bit stackslot (fist stores 64bit) even though we only load + * 32 bit from it with this particular load */ + attr = get_ia32_attr(load); + attr->data.need_64bit_stackent = 1; + + if (pn == pn_ia32_l_FloattoLL_res_high) { + add_ia32_am_offs_int(load, 4); + } else { + assert(pn == pn_ia32_l_FloattoLL_res_low); + } + + proj = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res); + + return proj; +} + /** * Transform the Projs of an AddSP. */ @@ -4371,15 +4718,22 @@ static ir_node *gen_Proj_Load(ir_node *node) { /* renumber the proj */ new_pred = be_transform_node(pred); if (is_ia32_Load(new_pred)) { - if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, - pn_ia32_Load_res); - } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, - pn_ia32_Load_M); + switch (proj) { + case pn_Load_res: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res); + case pn_Load_M: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M); + case pn_Load_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Load_X_exc); + default: + break; } - } else if(is_ia32_Conv_I2I(new_pred) - || is_ia32_Conv_I2I8Bit(new_pred)) { + } else if (is_ia32_Conv_I2I(new_pred) || + is_ia32_Conv_I2I8Bit(new_pred)) { set_irn_mode(new_pred, mode_T); if (proj == pn_Load_res) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res); @@ -4387,20 +4741,34 @@ static ir_node *gen_Proj_Load(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem); } } else if (is_ia32_xLoad(new_pred)) { - if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, - pn_ia32_xLoad_res); - } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, - pn_ia32_xLoad_M); + switch (proj) { + case pn_Load_res: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res); + case pn_Load_M: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M); + case pn_Load_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); + default: + break; } } else if (is_ia32_vfld(new_pred)) { - if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, - pn_ia32_vfld_res); - } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, - pn_ia32_vfld_M); + switch (proj) { + case pn_Load_res: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res); + case pn_Load_M: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M); + case pn_Load_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); + default: + break; } } else { /* can happen for ProJMs when source address mode happened for the @@ -4409,7 +4777,7 @@ static ir_node *gen_Proj_Load(ir_node *node) { /* however it should not be the result proj, as that would mean the load had multiple users and should not have been used for SourceAM */ - if(proj != pn_Load_M) { + if (proj != pn_Load_M) { panic("internal error: transformed node not a Load"); } return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1); @@ -4440,6 +4808,11 @@ static ir_node *gen_Proj_DivMod(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Div_res: return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); + case pn_Div_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Div_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4450,6 +4823,9 @@ static ir_node *gen_Proj_DivMod(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Mod_res: return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + case pn_Mod_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4462,6 +4838,11 @@ static ir_node *gen_Proj_DivMod(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); case pn_DivMod_res_mod: return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + case pn_DivMod_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_DivMod_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4529,6 +4910,8 @@ static ir_node *gen_Proj_Quot(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res); } break; + case pn_Quot_X_regular: + case pn_Quot_X_except: default: break; } @@ -4605,9 +4988,8 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { pn_ia32_xLoad_M); } } - if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res - && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode) - && USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2 && proj >= pn_be_Call_first_res + && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)) { ir_node *fstp; ir_node *frame = get_irg_frame(irg); ir_node *noreg = ia32_new_NoReg_gp(env_cg); @@ -4654,41 +5036,23 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { */ static ir_node *gen_Proj_Cmp(ir_node *node) { - (void) node; - panic("not all mode_b nodes are lowered"); - -#if 0 - /* normally Cmps are processed when looking at Cond nodes, but this case - * can happen in complicated Psi conditions */ - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *cmp = get_Proj_pred(node); - ir_node *new_cmp = be_transform_node(cmp); - long pnc = get_Proj_proj(node); - ir_node *res; - - res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0); - - return res; -#endif + /* this probably means not all mode_b nodes were lowered... */ + panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)", + node); } /** * Transform and potentially renumber Proj nodes. */ static ir_node *gen_Proj(ir_node *node) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); ir_node *pred = get_Proj_pred(node); - long proj = get_Proj_proj(node); - if (is_Store(pred)) { + long proj = get_Proj_proj(node); if (proj == pn_Store_M) { return be_transform_node(pred); } else { assert(0); - return new_r_Bad(irg); + return new_r_Bad(current_ir_graph); } } else if (is_Load(pred)) { return gen_Proj_Load(node); @@ -4707,29 +5071,33 @@ static ir_node *gen_Proj(ir_node *node) { } else if (is_Cmp(pred)) { return gen_Proj_Cmp(node); } else if (get_irn_op(pred) == op_Start) { + long proj = get_Proj_proj(node); if (proj == pn_Start_X_initial_exec) { ir_node *block = get_nodes_block(pred); + dbg_info *dbgi = get_irn_dbg_info(node); ir_node *jump; /* we exchange the ProjX with a jump */ block = be_transform_node(block); - jump = new_rd_Jmp(dbgi, irg, block); + jump = new_rd_Jmp(dbgi, current_ir_graph, block); return jump; } if (node == be_get_old_anchor(anchor_tls)) { return gen_Proj_tls(node); } + } else if (is_ia32_l_FloattoLL(pred)) { + return gen_Proj_l_FloattoLL(node); #ifdef FIRM_EXT_GRS } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization #else } else { #endif - ir_node *new_pred = be_transform_node(pred); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_mode *mode = get_irn_mode(node); + ir_mode *mode = get_irn_mode(node); if (mode_needs_gp_reg(mode)) { - ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu, - get_Proj_proj(node)); + ir_node *new_pred = be_transform_node(pred); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *new_proj = new_r_Proj(current_ir_graph, block, new_pred, + mode_Iu, get_Proj_proj(node)); #ifdef DEBUG_libfirm new_proj->node_nr = node->node_nr; #endif @@ -4805,8 +5173,8 @@ static void register_transformers(void) GEN(ia32_l_Load); GEN(ia32_l_vfist); GEN(ia32_l_Store); - GEN(ia32_l_X87toSSE); - GEN(ia32_l_SSEtoX87); + GEN(ia32_l_LLtoFloat); + GEN(ia32_l_FloattoLL); GEN(Const); GEN(SymConst); @@ -4941,24 +5309,15 @@ void ia32_add_missing_keeps(ia32_code_gen_t *cg) void ia32_transform_graph(ia32_code_gen_t *cg) { int cse_last; ir_graph *irg = cg->irg; - int opt_arch = cg->isa->opt_arch; - int arch = cg->isa->arch; - - /* TODO: look at cpu and fill transform config in with that... */ - transform_config.use_incdec = 1; - transform_config.use_sse2 = 0; - transform_config.use_ffreep = ARCH_ATHLON(opt_arch); - transform_config.use_ftst = 0; - transform_config.use_femms = ARCH_ATHLON(opt_arch) && ARCH_MMX(arch) && ARCH_AMD(arch); - transform_config.use_fucomi = 1; - transform_config.use_cmov = IS_P6_ARCH(arch); register_transformers(); env_cg = cg; initial_fpcw = NULL; +BE_TIMER_PUSH(t_heights); heights = heights_new(irg); - ia32_calculate_non_address_mode_nodes(irg); +BE_TIMER_POP(t_heights); + ia32_calculate_non_address_mode_nodes(cg->birg); /* the transform phase is not safe for CSE (yet) because several nodes get * attributes set after their creation */