X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=a07a024021595654b5e16d915d377ced7b1e3983;hb=08fe790a5784b31964a8783f6af1d14d62c366c4;hp=aba81c487c50bf19e217fa8abfbef09f3278c0dc;hpb=e629e6d582dcf7d83989409bd5701d1725b6c6c1;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index aba81c487..a07a02402 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -1,19 +1,33 @@ +/** + * This file implements the IR transformation from firm into + * ia32-Firm. + * + * $Id$ + */ + #ifdef HAVE_CONFIG_H #include "config.h" #endif +#include + +#include "irargs_t.h" #include "irnode_t.h" #include "irgraph_t.h" #include "irmode_t.h" +#include "iropt_t.h" +#include "irop_t.h" +#include "irprog_t.h" +#include "iredges_t.h" #include "irgmod.h" -#include "iredges.h" #include "irvrfy.h" #include "ircons.h" #include "dbginfo.h" -#include "iropt_t.h" #include "debug.h" #include "../benode_t.h" +#include "../besched.h" + #include "bearch_ia32_t.h" #include "ia32_nodes_attr.h" @@ -24,9 +38,32 @@ #include "gen_ia32_regalloc_if.h" +#define SFP_SIGN "0x80000000" +#define DFP_SIGN "0x8000000000000000" +#define SFP_ABS "0x7FFFFFFF" +#define DFP_ABS "0x7FFFFFFFFFFFFFFF" + +#define TP_SFP_SIGN "ia32_sfp_sign" +#define TP_DFP_SIGN "ia32_dfp_sign" +#define TP_SFP_ABS "ia32_sfp_abs" +#define TP_DFP_ABS "ia32_dfp_abs" + +#define ENT_SFP_SIGN "IA32_SFP_SIGN" +#define ENT_DFP_SIGN "IA32_DFP_SIGN" +#define ENT_SFP_ABS "IA32_SFP_ABS" +#define ENT_DFP_ABS "IA32_DFP_ABS" + extern ir_op *get_op_Mulh(void); +typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \ + ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode); + +typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \ + ir_node *op, ir_node *mem, ir_mode *mode); +typedef enum { + ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max +} ia32_known_const_t; /**************************************************************************************************** * _ _ __ _ _ @@ -38,18 +75,301 @@ extern ir_op *get_op_Mulh(void); * ****************************************************************************************************/ +/** + * Gets the Proj with number pn from irn. + */ +static ir_node *get_proj_for_pn(const ir_node *irn, long pn) { + const ir_edge_t *edge; + ir_node *proj; + assert(get_irn_mode(irn) == mode_T && "need mode_T"); + foreach_out_edge(irn, edge) { + proj = get_edge_src_irn(edge); + + if (get_Proj_proj(proj) == pn) + return proj; + } + + return NULL; +} + +/* Generates an entity for a known FP const (used for FP Neg + Abs) */ +static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) { + static const struct { + const char *tp_name; + const char *ent_name; + const char *cnst_str; + } names [ia32_known_const_max] = { + { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */ + { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */ + { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */ + { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */ + }; + static struct entity *ent_cache[ia32_known_const_max]; + + const char *tp_name, *ent_name, *cnst_str; + ir_type *tp; + ir_node *cnst; + ir_graph *rem; + entity *ent; + tarval *tv; + + ent_name = names[kct].ent_name; + if (! ent_cache[kct]) { + tp_name = names[kct].tp_name; + cnst_str = names[kct].cnst_str; + + tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode); + tp = new_type_primitive(new_id_from_str(tp_name), mode); + ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp); + + set_entity_ld_ident(ent, get_entity_ident(ent)); + set_entity_visibility(ent, visibility_local); + set_entity_variability(ent, variability_constant); + set_entity_allocation(ent, allocation_static); + + /* we create a new entity here: It's initialization must resist on the + const code irg */ + rem = current_ir_graph; + current_ir_graph = get_const_code_irg(); + cnst = new_Const(mode, tv); + current_ir_graph = rem; + + set_atomic_ent_value(ent, cnst); + + /* cache the entry */ + ent_cache[kct] = ent; + } + + return get_entity_ident(ent_cache[kct]); +} + +#ifndef NDEBUG +/** + * Prints the old node name on cg obst and returns a pointer to it. + */ +const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) { + ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa; + + lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn); + obstack_1grow(isa->name_obst, 0); + isa->name_obst_size += obstack_object_size(isa->name_obst); + return obstack_finish(isa->name_obst); +} +#endif /* NDEBUG */ /* determine if one operator is an Imm */ static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) { if (op1) - return is_ia32_Const(op1) ? op1 : (is_ia32_Const(op2) ? op2 : NULL); - else return is_ia32_Const(op2) ? op2 : NULL; + return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL); + else return is_ia32_Cnst(op2) ? op2 : NULL; } /* determine if one operator is not an Imm */ static ir_node *get_expr_op(ir_node *op1, ir_node *op2) { - return !is_ia32_Const(op1) ? op1 : (!is_ia32_Const(op2) ? op2 : NULL); + return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL); +} + + +/** + * Construct a standard binary operation, set AM and immediate if required. + * + * @param env The transformation environment + * @param op1 The first operand + * @param op2 The second operand + * @param func The node constructor function + * @return The constructed ia32 node. + */ +static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) { + ir_node *new_op = NULL; + ir_mode *mode = env->mode; + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg); + ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg); + ir_node *nomem = new_NoMem(); + ir_node *expr_op, *imm_op; + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) + + /* Check if immediate optimization is on and */ + /* if it's an operation with immediate. */ + if (! env->cg->opt.immops) { + expr_op = op1; + imm_op = NULL; + } + else if (is_op_commutative(get_irn_op(env->irn))) { + imm_op = get_immediate_op(op1, op2); + expr_op = get_expr_op(op1, op2); + } + else { + imm_op = get_immediate_op(NULL, op2); + expr_op = get_expr_op(op1, op2); + } + + assert((expr_op || imm_op) && "invalid operands"); + + if (!expr_op) { + /* We have two consts here: not yet supported */ + imm_op = NULL; + } + + if (mode_is_float(mode)) { + /* floating point operations */ + if (imm_op) { + DB((mod, LEVEL_1, "FP with immediate ...")); + new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T); + set_ia32_Immop_attr(new_op, imm_op); + set_ia32_am_support(new_op, ia32_am_None); + } + else { + DB((mod, LEVEL_1, "FP binop ...")); + new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T); + set_ia32_am_support(new_op, ia32_am_Source); + } + } + else { + /* integer operations */ + if (imm_op) { + /* This is expr + const */ + DB((mod, LEVEL_1, "INT with immediate ...")); + new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T); + set_ia32_Immop_attr(new_op, imm_op); + + /* set AM support */ + set_ia32_am_support(new_op, ia32_am_Dest); + } + else { + DB((mod, LEVEL_1, "INT binop ...")); + /* This is a normal operation */ + new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T); + + /* set AM support */ + set_ia32_am_support(new_op, ia32_am_Full); + } + } + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + set_ia32_res_mode(new_op, mode); + + if (is_op_commutative(get_irn_op(env->irn))) { + set_ia32_commutative(new_op); + } + + return new_rd_Proj(dbg, irg, block, new_op, mode, 0); +} + + + +/** + * Construct a shift/rotate binary operation, sets AM and immediate if required. + * + * @param env The transformation environment + * @param op1 The first operand + * @param op2 The second operand + * @param func The node constructor function + * @return The constructed ia32 node. + */ +static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) { + ir_node *new_op = NULL; + ir_mode *mode = env->mode; + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *nomem = new_NoMem(); + ir_node *expr_op, *imm_op; + tarval *tv; + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) + + assert(! mode_is_float(mode) && "Shift/Rotate with float not supported"); + + /* Check if immediate optimization is on and */ + /* if it's an operation with immediate. */ + imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL; + expr_op = get_expr_op(op1, op2); + + assert((expr_op || imm_op) && "invalid operands"); + + if (!expr_op) { + /* We have two consts here: not yet supported */ + imm_op = NULL; + } + + /* Limit imm_op within range imm8 */ + if (imm_op) { + tv = get_ia32_Immop_tarval(imm_op); + + if (tv) { + tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu)); + } + else { + imm_op = NULL; + } + } + + /* integer operations */ + if (imm_op) { + /* This is shift/rot with const */ + DB((mod, LEVEL_1, "Shift/Rot with immediate ...")); + + new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T); + set_ia32_Immop_attr(new_op, imm_op); + } + else { + /* This is a normal shift/rot */ + DB((mod, LEVEL_1, "Shift/Rot binop ...")); + new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T); + } + + /* set AM support */ + set_ia32_am_support(new_op, ia32_am_Dest); + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + set_ia32_res_mode(new_op, mode); + set_ia32_emit_cl(new_op); + + return new_rd_Proj(dbg, irg, block, new_op, mode, 0); +} + + +/** + * Construct a standard unary operation, set AM and immediate if required. + * + * @param env The transformation environment + * @param op The operand + * @param func The node constructor function + * @return The constructed ia32 node. + */ +static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) { + ir_node *new_op = NULL; + ir_mode *mode = env->mode; + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *nomem = new_NoMem(); + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) + + new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T); + + if (mode_is_float(mode)) { + DB((mod, LEVEL_1, "FP unop ...")); + /* floating point operations don't support implicit store */ + set_ia32_am_support(new_op, ia32_am_None); + } + else { + DB((mod, LEVEL_1, "INT unop ...")); + set_ia32_am_support(new_op, ia32_am_Dest); + } + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + set_ia32_res_mode(new_op, mode); + + return new_rd_Proj(dbg, irg, block, new_op, mode, 0); } @@ -57,45 +377,45 @@ static ir_node *get_expr_op(ir_node *op1, ir_node *op2) { /** * Creates an ia32 Add with immediate. * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 Add_i node + * @param env The transformation environment + * @param expr_op The expression operator + * @param const_op The constant + * @return the created ia32 Add node */ static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { - ir_node *new_op; - tarval *tv = get_ia32_Immop_tarval(const_op); - int normal_add = 0; + ir_node *new_op = NULL; + tarval *tv = get_ia32_Immop_tarval(const_op); + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *nomem = new_NoMem(); + int normal_add = 1; tarval_classification_t class_tv, class_negtv; - firm_dbg_module_t *mod = env->mod; - dbg_info *dbg = env->dbg; - ir_mode *mode = env->mode; - ir_graph *irg = env->irg; - ir_node *block = env->block; - - /* const_op: tarval or SymConst? */ - if (tv) { + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) + + /* try to optimize to inc/dec */ + if (env->cg->opt.incdec && tv) { /* optimize tarvals */ class_tv = classify_tarval(tv); class_negtv = classify_tarval(tarval_neg(tv)); if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */ DB((env->mod, LEVEL_2, "Add(1) to Inc ... ")); - new_op = new_rd_ia32_Inc(dbg, irg, block, expr_op, mode); + new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T); + normal_add = 0; } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */ DB((mod, LEVEL_2, "Add(-1) to Dec ... ")); - new_op = new_rd_ia32_Dec(dbg, irg, block, expr_op, mode); + new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T); + normal_add = 0; } - else - normal_add = 1; } - else - normal_add = 1; - if (normal_add) - new_op = new_rd_ia32_Lea_i(dbg, irg, block, expr_op, mode); + if (normal_add) { + new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T); + set_ia32_Immop_attr(new_op, const_op); + } return new_op; } @@ -111,128 +431,93 @@ static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node * @return the created ia32 Add node */ static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - ir_node *shli_op; - ir_node *expr_op; - ir_node *new_op; - int normal_add = 0; - dbg_info *dbg = env->dbg; - ir_mode *mode = env->mode; - ir_graph *irg = env->irg; - ir_node *block = env->block; - - if (mode_is_float(mode)) { - return new_rd_ia32_fAdd(dbg, irg, block, op1, op2, mode); - } - - /* try to optimize with LEA */ - - shli_op = is_ia32_Shl_i(op1) ? op1 : (is_ia32_Shl_i(op2) ? op2 : NULL); - expr_op = shli_op == op1 ? op2 : (shli_op == op2 ? op1 : NULL); - - if (shli_op) { - tarval *tv = get_ia32_Immop_tarval(shli_op); - tarval *offs = NULL; - if (tv) { - switch (get_tarval_long(tv)) { - case 1: - case 2: - case 3: - // If the other operand of the LEA is an LEA_i (that means LEA ofs(%regop1)), - // we can skip it and transform the whole sequence into LEA ofs(%regop1, %regop2, shl_val), - if (is_ia32_Lea_i(expr_op)) { - offs = get_ia32_Immop_tarval(expr_op); - expr_op = get_irn_n(expr_op, 0); - } + ir_node *new_op = NULL; + dbg_info *dbg = env->dbg; + ir_mode *mode = env->mode; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *nomem = new_NoMem(); + ir_node *expr_op, *imm_op; + + /* Check if immediate optimization is on and */ + /* if it's an operation with immediate. */ + imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL; + expr_op = get_expr_op(op1, op2); - new_op = new_rd_ia32_Lea(dbg, irg, block, expr_op, get_irn_n(shli_op, 0), mode); - set_ia32_Immop_tarval(new_op, tv); - set_ia32_am_offs(new_op, offs); + assert((expr_op || imm_op) && "invalid operands"); - break; - default: - normal_add = 1; - break; - } - } + if (mode_is_float(mode)) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + return gen_binop(env, op1, op2, new_rd_ia32_fAdd); else - normal_add = 1; - } - else - normal_add = 1; - - if (normal_add) { - new_op = new_rd_ia32_Lea(dbg, irg, block, op1, op2, mode); - set_ia32_Immop_tarval(new_op, get_tarval_null(mode_Iu)); - set_ia32_am_offs(new_op, NULL); + return gen_binop(env, op1, op2, new_rd_ia32_vfadd); } + else { + /* integer ADD */ + if (!expr_op) { + /* No expr_op means, that we have two const - one symconst and */ + /* one tarval or another symconst - because this case is not */ + /* covered by constant folding */ + /* We need to check for: */ + /* 1) symconst + const -> becomes a LEA */ + /* 2) symconst + symconst -> becomes a const + LEA as the elf */ + /* linker doesn't support two symconsts */ + + if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) { + /* this is the 2nd case */ + new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode); + set_ia32_am_sc(new_op, get_ia32_id_cnst(op2)); + set_ia32_am_flavour(new_op, ia32_am_OB); + } + else { + /* this is the 1st case */ + new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode); - return new_op; -} + if (get_ia32_op_type(op1) == ia32_SymConst) { + set_ia32_am_sc(new_op, get_ia32_id_cnst(op1)); + add_ia32_am_offs(new_op, get_ia32_cnst(op2)); + } + else { + add_ia32_am_offs(new_op, get_ia32_cnst(op1)); + set_ia32_am_sc(new_op, get_ia32_id_cnst(op2)); + } + set_ia32_am_flavour(new_op, ia32_am_O); + } + /* set AM support */ + set_ia32_am_support(new_op, ia32_am_Source); + set_ia32_op_type(new_op, ia32_AddrModeS); + /* Lea doesn't need a Proj */ + return new_op; + } + else if (imm_op) { + /* This is expr + const */ + new_op = gen_imm_Add(env, expr_op, imm_op); -/** - * Generates an ia32 Mul node. - * - * @param env The transformation environment - * @param op1 The first faktor - * @param op2 The second factor - * @param mul_flav flavour_Mul/Mulh - * @return The ready-to-go Mul node - */ -ir_node *generate_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, op_flavour_t mul_flav, int is_imm_op) { - ir_node *in_keep[1], *res; - long pn_good, pn_bad; - dbg_info *dbg = env->dbg; - ir_graph *irg = env->irg; - ir_node *block = env->block; - ir_mode *mode = env->mode; - ir_node *mul; - - /* create the mul */ - if (is_imm_op) { - mul = new_rd_ia32_Mul_i(dbg, irg, block, op1, mode_T); - set_ia32_Immop_attr(mul, op2); - } - else { - mul = new_rd_ia32_Mul(dbg, irg, block, op1, op2, mode_T); - } - set_ia32_flavour(mul, mul_flav); + /* set AM support */ + set_ia32_am_support(new_op, ia32_am_Dest); + } + else { + /* This is a normal add */ + new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T); - /* create the mul infrastructure */ - if (mul_flav == flavour_Mul) { - pn_good = pn_EAX; - pn_bad = pn_EDX; - } - else { /* Mulh */ - pn_good = pn_EDX; - pn_bad = pn_EAX; + /* set AM support */ + set_ia32_am_support(new_op, ia32_am_Full); + } } - res = new_rd_Proj(dbg, irg, block, mul, mode, pn_good); - in_keep[0] = new_rd_Proj(dbg, irg, block, mul, mode, pn_bad); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); - be_new_Keep(&ia32_reg_classes[CLASS_ia32_general_purpose], irg, block, 1, in_keep); + set_ia32_res_mode(new_op, mode); - return res; + return new_rd_Proj(dbg, irg, block, new_op, mode, 0); } -/** - * Creates an ia32 Mul with immediate. - * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 Mul_i node - */ -static ir_node *gen_imm_Mul(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { - /* Mul with immediate only possible with int, so we don't need to check for float */ - return generate_Mul(env, expr_op, const_op, flavour_Mul, 1); -} - /** * Creates an ia32 Mul. * @@ -243,133 +528,107 @@ static ir_node *gen_imm_Mul(ia32_transform_env_t *env, ir_node *expr_op, ir_node * @param mode node mode * @return the created ia32 Mul node */ -ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { +static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { + ir_node *new_op; + if (mode_is_float(env->mode)) { - return new_rd_ia32_fMul(env->dbg, env->irg, env->block, op1, op2, env->mode); + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul); + else + new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul); } else { - return generate_Mul(env, op1, op2, flavour_Mul, 0); + new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul); } -} + return new_op; +} -/** - * Creates an ia32 Mulh with immediate. - * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of - * this result while Mul returns the lower 32 bit. - * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 Mulh_i node - */ -static ir_node *gen_imm_Mulh(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { - return generate_Mul(env, expr_op, const_op, flavour_Mulh, 1); -} /** * Creates an ia32 Mulh. * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of * this result while Mul returns the lower 32 bit. * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator * @return the created ia32 Mulh node */ static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return generate_Mul(env, op1, op2, flavour_Mulh, 0); -} + ir_node *proj_EAX, *proj_EDX, *mulh; + ir_node *in[1]; + assert(!mode_is_float(env->mode) && "Mulh with float not supported"); + proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh); + mulh = get_Proj_pred(proj_EAX); + proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX); + /* to be on the save side */ + set_Proj_proj(proj_EAX, pn_EAX); -/** - * Creates an ia32 And with immediate. - * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 And_i node - */ -static ir_node *gen_imm_And(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { - return new_rd_ia32_And_i(env->dbg, env->irg, env->block, expr_op, env->mode); + if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) { + /* Mulh with const cannot have AM */ + set_ia32_am_support(mulh, ia32_am_None); + } + else { + /* Mulh cannot have AM for destination */ + set_ia32_am_support(mulh, ia32_am_Source); + } + + in[0] = proj_EAX; + + /* keep EAX */ + be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in); + + return proj_EDX; } + + /** * Creates an ia32 And. * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 And node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 And node */ static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return new_rd_ia32_And(env->dbg, env->irg, env->block, op1, op2, env->mode); + assert (! mode_is_float(env->mode)); + return gen_binop(env, op1, op2, new_rd_ia32_And); } -/** - * Creates an ia32 Or with immediate. - * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 Or_i node - */ -static ir_node *gen_imm_Or(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { - return new_rd_ia32_Or_i(env->dbg, env->irg, env->block, expr_op, env->mode); -} - /** * Creates an ia32 Or. * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 Or node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 Or node */ static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return new_rd_ia32_Or(env->dbg, env->irg, env->block, op1, op2, env->mode); + assert (! mode_is_float(env->mode)); + return gen_binop(env, op1, op2, new_rd_ia32_Or); } -/** - * Creates an ia32 Eor with immediate. - * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 Eor_i node - */ -static ir_node *gen_imm_Eor(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { - return new_rd_ia32_Eor_i(env->dbg, env->irg, env->block, expr_op, env->mode); -} - /** * Creates an ia32 Eor. * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 Eor node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 Eor node */ static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return new_rd_ia32_Eor(env->dbg, env->irg, env->block, op1, op2, env->mode); + assert(! mode_is_float(env->mode)); + return gen_binop(env, op1, op2, new_rd_ia32_Eor); } @@ -377,14 +636,29 @@ static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { /** * Creates an ia32 Max. * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 Max node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return the created ia32 Max node */ static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode); + ir_node *new_op; + + if (mode_is_float(env->mode)) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax); + else { + assert(0); + } + } + else { + new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode); + set_ia32_am_support(new_op, ia32_am_None); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + } + + return new_op; } @@ -392,14 +666,29 @@ static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { /** * Creates an ia32 Min. * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 Min node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return the created ia32 Min node */ static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode); + ir_node *new_op; + + if (mode_is_float(env->mode)) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin); + else { + assert(0); + } + } + else { + new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode); + set_ia32_am_support(new_op, ia32_am_None); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + } + + return new_op; } @@ -407,45 +696,45 @@ static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { /** * Creates an ia32 Sub with immediate. * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 Sub_i node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 Sub node */ static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { - ir_node *new_op; - tarval *tv = get_ia32_Immop_tarval(const_op); - int normal_sub = 0; + ir_node *new_op = NULL; + tarval *tv = get_ia32_Immop_tarval(const_op); + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *nomem = new_NoMem(); + int normal_sub = 1; tarval_classification_t class_tv, class_negtv; - firm_dbg_module_t *mod = env->mod; - dbg_info *dbg = env->dbg; - ir_mode *mode = env->mode; - ir_graph *irg = env->irg; - ir_node *block = env->block; - - /* const_op: tarval or SymConst? */ - if (tv) { + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) + + /* try to optimize to inc/dec */ + if (env->cg->opt.incdec && tv) { /* optimize tarvals */ class_tv = classify_tarval(tv); class_negtv = classify_tarval(tarval_neg(tv)); if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */ DB((mod, LEVEL_2, "Sub(1) to Dec ... ")); - new_op = new_rd_ia32_Dec(dbg, irg, block, expr_op, mode); + new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T); + normal_sub = 0; } else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */ DB((mod, LEVEL_2, "Sub(-1) to Inc ... ")); - new_op = new_rd_ia32_Inc(dbg, irg, block, expr_op, mode); + new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T); + normal_sub = 0; } - else - normal_sub = 1; } - else - normal_sub = 1; - if (normal_sub) - new_op = new_rd_ia32_Sub_i(dbg, irg, block, expr_op, mode); + if (normal_sub) { + new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T); + set_ia32_Immop_attr(new_op, const_op); + } return new_op; } @@ -453,18 +742,97 @@ static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node /** * Creates an ia32 Sub. * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 Sub node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 Sub node */ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - if (mode_is_float(env->mode)) { - return new_rd_ia32_fSub(env->dbg, env->irg, env->block, op1, op2, env->mode); + ir_node *new_op = NULL; + dbg_info *dbg = env->dbg; + ir_mode *mode = env->mode; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *nomem = new_NoMem(); + ir_node *expr_op, *imm_op; + + /* Check if immediate optimization is on and */ + /* if it's an operation with immediate. */ + imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL; + expr_op = get_expr_op(op1, op2); + + assert((expr_op || imm_op) && "invalid operands"); + + if (mode_is_float(mode)) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + return gen_binop(env, op1, op2, new_rd_ia32_fSub); + else + return gen_binop(env, op1, op2, new_rd_ia32_vfsub); + } + else { + /* integer SUB */ + if (!expr_op) { + /* No expr_op means, that we have two const - one symconst and */ + /* one tarval or another symconst - because this case is not */ + /* covered by constant folding */ + /* We need to check for: */ + /* 1) symconst + const -> becomes a LEA */ + /* 2) symconst + symconst -> becomes a const + LEA as the elf */ + /* linker doesn't support two symconsts */ + + if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) { + /* this is the 2nd case */ + new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode); + set_ia32_am_sc(new_op, get_ia32_id_cnst(op2)); + set_ia32_am_sc_sign(new_op); + set_ia32_am_flavour(new_op, ia32_am_OB); + } + else { + /* this is the 1st case */ + new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode); + + if (get_ia32_op_type(op1) == ia32_SymConst) { + set_ia32_am_sc(new_op, get_ia32_id_cnst(op1)); + sub_ia32_am_offs(new_op, get_ia32_cnst(op2)); + } + else { + add_ia32_am_offs(new_op, get_ia32_cnst(op1)); + set_ia32_am_sc(new_op, get_ia32_id_cnst(op2)); + set_ia32_am_sc_sign(new_op); + } + set_ia32_am_flavour(new_op, ia32_am_O); + } + + /* set AM support */ + set_ia32_am_support(new_op, ia32_am_Source); + set_ia32_op_type(new_op, ia32_AddrModeS); + + /* Lea doesn't need a Proj */ + return new_op; + } + else if (imm_op) { + /* This is expr - const */ + new_op = gen_imm_Sub(env, expr_op, imm_op); + + /* set AM support */ + set_ia32_am_support(new_op, ia32_am_Dest); + } + else { + /* This is a normal sub */ + new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T); + + /* set AM support */ + set_ia32_am_support(new_op, ia32_am_Full); + } } - return new_rd_ia32_Sub(env->dbg, env->irg, env->block, op1, op2, env->mode); + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + set_ia32_res_mode(new_op, mode); + + return new_rd_Proj(dbg, irg, block, new_op, mode, 0); } @@ -479,7 +847,7 @@ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { * @param dm_flav flavour_Div/Mod/DivMod * @return The created ia32 DivMod node */ -static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, op_flavour_t dm_flav) { +static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) { ir_node *res, *proj; ir_node *edx_node, *cltd; ir_node *in_keep[1]; @@ -488,21 +856,38 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir ir_node *block = env->block; ir_mode *mode = env->mode; ir_node *irn = env->irn; - ir_node *mem = get_DivMod_mem(irn); + ir_node *mem; + + switch (dm_flav) { + case flavour_Div: + mem = get_Div_mem(irn); + mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res)); + break; + case flavour_Mod: + mem = get_Mod_mem(irn); + mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res)); + break; + case flavour_DivMod: + mem = get_DivMod_mem(irn); + mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div)); + break; + default: + assert(0); + } if (mode_is_signed(mode)) { /* in signed mode, we need to sign extend the dividend */ - cltd = new_rd_ia32_Cltd(dbg, irg, block, dividend, mode_T); + cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T); dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX); edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX); } else { edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu); - set_ia32_Const_type(edx_node, asmop_Const); + set_ia32_Const_type(edx_node, ia32_Const); set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu)); } - res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode); + res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T); set_ia32_flavour(res, dm_flav); set_ia32_n_res(res, 2); @@ -521,9 +906,13 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div); } - be_new_Keep(&ia32_reg_classes[CLASS_ia32_general_purpose], irg, block, 1, in_keep); + be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep); } + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); + + set_ia32_res_mode(res, mode_Is); + return res; } @@ -558,102 +947,78 @@ static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2 /** * Creates an ia32 floating Div. * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 fDiv node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 fDiv node */ static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return new_rd_ia32_fDiv(env->dbg, env->irg, env->block, op1, op2, env->mode); -} + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *new_op; + ir_node *nomem = new_rd_NoMem(env->irg); + if (USE_SSE2(env->cg)) { + if (is_ia32_fConst(op2)) { + new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem, mode_T); + set_ia32_am_support(new_op, ia32_am_None); + set_ia32_Immop_attr(new_op, op2); + } + else { + new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T); + set_ia32_am_support(new_op, ia32_am_Source); + } + } + else { + new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T); + set_ia32_am_support(new_op, ia32_am_Source); + } + set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res))); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); -/** - * Creates an ia32 Shl with immediate. - * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 Shl_i node - */ -static ir_node *gen_imm_Shl(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { - return new_rd_ia32_Shl_i(env->dbg, env->irg, env->block, expr_op, env->mode); + return new_op; } + + /** * Creates an ia32 Shl. * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 Shl node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 Shl node */ static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return new_rd_ia32_Shl(env->dbg, env->irg, env->block, op1, op2, env->mode); + return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl); } -/** - * Creates an ia32 Shr with immediate. - * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 Shr_i node - */ -static ir_node *gen_imm_Shr(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { - return new_rd_ia32_Shr_i(env->dbg, env->irg, env->block, expr_op, env->mode); -} - /** * Creates an ia32 Shr. * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 Shr node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 Shr node */ static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return new_rd_ia32_Shr(env->dbg, env->irg, env->block, op1, op2, env->mode); + return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr); } -/** - * Creates an ia32 Shrs with immediate. - * - * @param dbg firm dbg - * @param block the block the new node should belong to - * @param expr_op operator - * @param mode node mode - * @return the created ia23 Shrs_i node - */ -static ir_node *gen_imm_Shrs(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { - return new_rd_ia32_Shrs_i(env->dbg, env->irg, env->block, expr_op, env->mode); -} - /** * Creates an ia32 Shrs. * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 Shrs node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 Shrs node */ static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return new_rd_ia32_Shrs(env->dbg, env->irg, env->block, op1, op2, env->mode); + return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs); } @@ -661,15 +1026,13 @@ static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) /** * Creates an ia32 RotL. * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 RotL node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 RotL node */ static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return new_rd_ia32_RotL(env->dbg, env->irg, env->block, op1, op2, env->mode); + return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL); } @@ -679,43 +1042,24 @@ static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) * NOTE: There is no RotR with immediate because this would always be a RotL * "imm-mode_size_bits" which can be pre-calculated. * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 RotR node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 RotR node */ static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { - return new_rd_ia32_RotR(env->dbg, env->irg, env->block, op1, op2, env->mode); + return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR); } -/** - * Transforms a Rot with immediate into an ia32 RotL with immediate - * as the Firm Rot is a RotL (see NOTE on RotR with immediate above). - * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 RotL node - */ -static ir_node *gen_imm_Rot(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { - return new_rd_ia32_RotL_i(env->dbg, env->irg, env->block, expr_op, env->mode); -} - /** * Creates an ia32 RotR or RotL (depending on the found pattern). * - * @param dbg firm node dbg - * @param block the block the new node should belong to - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @return the created ia32 RotL or RotR node + * @param env The transformation environment + * @param op1 The first operator + * @param op2 The second operator + * @return The created ia32 RotL or RotR node */ static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { ir_node *rotate = NULL; @@ -724,22 +1068,32 @@ static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e", that means we can create a RotR instead of an Add and a RotL */ - if (is_ia32_Add_i(op2)) { - ir_node *minus = get_irn_n(op2, 0); // is there an op_Minus? + if (is_Proj(op2)) { + ir_node *pred = get_Proj_pred(op2); + + if (is_ia32_Add(pred)) { + ir_node *pred_pred = get_irn_n(pred, 2); + tarval *tv = get_ia32_Immop_tarval(pred); + long bits = get_mode_size_bits(env->mode); - if (is_ia32_Minus(minus)) { - tarval *tv = get_ia32_Immop_tarval(op2); - long bits = get_mode_size_bits(env->mode); + if (is_Proj(pred_pred)) { + pred_pred = get_Proj_pred(pred_pred); + } - if (tarval_is_long(tv) && get_tarval_long(tv) == bits) { + if (is_ia32_Minus(pred_pred) && + tarval_is_long(tv) && + get_tarval_long(tv) == bits) + { DB((env->mod, LEVEL_1, "RotL into RotR ... ")); - rotate = gen_RotR(env, op1, get_irn_n(minus, 0)); + rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2)); } + } } - if (!rotate) + if (!rotate) { rotate = gen_RotL(env, op1, op2); + } return rotate; } @@ -747,171 +1101,47 @@ static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { /** - * Transforms commutative operations (op_Add, op_And, op_Or, op_Eor) - * and non-commutative operations with com == 0 (op_Sub, op_Shl, op_Shr, op_Shrs, op_Rot) + * Transforms a Minus node. * - * @param mod the debug module - * @param block the block node belongs to - * @param node the node to transform - * @param op1 first operator - * @param op2 second operator - * @param mode node mode - * @param com flag if op is commutative - * @return the created assembler node + * @param env The transformation environment + * @param op The operator + * @return The created ia32 Minus node */ -static ir_node *gen_arith_Op(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, int com) { - firm_dbg_module_t *mod = env->mod; - ir_node *node = env->irn; - ir_node *imm_op = NULL; - ir_node *expr_op = NULL; - ir_node *asm_node = NULL; - opcode opc = get_irn_opcode(node); - ir_op *op = get_irn_op(node); - -#undef GENOP -#undef GENOPI -#undef GENOPI_SETATTR -#define GENOP(a) case iro_##a: asm_node = gen_##a(env, op1, op2); break -#define GENOPI(a) case iro_##a: asm_node = gen_imm_##a(env, expr_op, imm_op); break -#define GENOPI_SETATTR(a) case iro_##a: asm_node = gen_imm_##a(env, expr_op, imm_op); set_ia32_Immop_attr(asm_node, imm_op); break - - if (com) - imm_op = get_immediate_op(op1, op2); - else - imm_op = get_immediate_op(NULL, op2); +static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) { + ident *name; + ir_node *new_op; + ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg); + ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg); + ir_node *nomem = new_rd_NoMem(env->irg); + int size; - expr_op = get_expr_op(op1, op2); + if (mode_is_float(env->mode)) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) { + new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T); - /* TODO: Op(Const, Const) support */ - if (is_ia32_Const(op1) && is_ia32_Const(op2)) { - DB((mod, LEVEL_2, "%+F(Const, Const) -> binop ... ", get_irn_opname(node))); - imm_op = NULL; - } + size = get_mode_size_bits(env->mode); + name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN); - /* There are arithmetic operations which can't take an immediate */ - switch(opc) { - case iro_Div: - case iro_Mod: - case iro_DivMod: - DB((mod, LEVEL_2, "Div/Mod/DivMod imm -> binop ... ")); - imm_op = NULL; - break; - default: - if (op == get_op_Min() || op == get_op_Max()) { - DB((mod, LEVEL_2, "MIN/MAX imm -> binop ... ")); - imm_op = NULL; - } - break; - } - - DB((mod, LEVEL_1, "(%+F -- %+F) ... ", op1, op2)); + set_ia32_sc(new_op, name); - if (!mode_is_float(env->mode) && imm_op) { - DB((mod, LEVEL_1, "immop ... ")); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); - switch(opc) { - GENOPI_SETATTR(Add); - GENOPI(Mul); - GENOPI_SETATTR(And); - GENOPI_SETATTR(Or); - GENOPI_SETATTR(Eor); + set_ia32_res_mode(new_op, env->mode); + set_ia32_immop_type(new_op, ia32_ImmSymConst); - GENOPI_SETATTR(Sub); - GENOPI_SETATTR(Shl); - GENOPI_SETATTR(Shr); - GENOPI_SETATTR(Shrs); - GENOPI_SETATTR(Rot); - default: - if (op == get_op_Mulh()) { - asm_node = gen_imm_Mulh(env, expr_op, imm_op); - } - else { - assert("binop_i: THIS SHOULD NOT HAPPEN"); - } + new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0); } - } - else { - DB((mod, LEVEL_1, "binop ... ")); - - switch(opc) { - GENOP(Add); - GENOP(Mul); - GENOP(And); - GENOP(Or); - GENOP(Eor); - - GENOP(Quot); - - GENOP(Div); - GENOP(Mod); - GENOP(DivMod); - - GENOP(Sub); - GENOP(Shl); - GENOP(Shr); - GENOP(Shrs); - GENOP(Rot); - default: - if (op == get_op_Max()) { - asm_node = gen_Max(env, op1, op2); - } - else if (op == get_op_Min()) { - asm_node = gen_Min(env, op1, op2); - } - else if (op == get_op_Mulh()) { - asm_node = gen_Mulh(env, op1, op2); - } - else { - assert("binop: THIS SHOULD NOT HAPPEN"); - } + else { + new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); } } - - return asm_node; -} -#undef GENOP -#undef GENOPI -#undef GENOPI_SETATTR - - - -/** - * Transforms a Minus node. - * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Minus node - * @param op operator - * @param mode node mode - * @return the created ia32 Minus node - */ -static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) { - if (is_ia32_Minus(op) || is_ia32_fMinus(op)) { - DB((env->mod, LEVEL_1, "--(e) to e ...")); - return get_irn_n(op, 0); - } else { - if (mode_is_float(env->mode)) { - return new_rd_ia32_fMinus(env->dbg, env->irg, env->block, op, env->mode); - } - return new_rd_ia32_Minus(env->dbg, env->irg, env->block, op, env->mode); + new_op = gen_unop(env, op, new_rd_ia32_Minus); } -} - - -/** - * Transforms a Conv node. - * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Conv node - * @param op operator - * @param mode node mode - * @return the created ia32 Conv node - */ -static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) { - return new_rd_ia32_Conv(env->dbg, env->irg, env->block, op, env->mode); + return new_op; } @@ -919,15 +1149,13 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) { /** * Transforms a Not node. * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Not node - * @param op operator - * @param mode node mode - * @return the created ia32 Not node + * @param env The transformation environment + * @param op The operator + * @return The created ia32 Not node */ static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) { - return new_rd_ia32_Not(env->dbg, env->irg, env->block, op, env->mode); + assert (! mode_is_float(env->mode)); + return gen_unop(env, op, new_rd_ia32_Not); } @@ -935,25 +1163,64 @@ static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) { /** * Transforms an Abs node. * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Abs node - * @param op operator - * @param mode node mode - * @return the created ia32 Abs node + * @param env The transformation environment + * @param op The operator + * @return The created ia32 Abs node */ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) { ir_node *res, *p_eax, *p_edx; - dbg_info *dbg = env->dbg; - ir_mode *mode = env->mode; - ir_graph *irg = env->irg; - ir_node *block = env->block; + dbg_info *dbg = env->dbg; + ir_mode *mode = env->mode; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg); + ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg); + ir_node *nomem = new_NoMem(); + int size; + ident *name; + + if (mode_is_float(mode)) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) { + res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T); + + size = get_mode_size_bits(mode); + name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS); + + set_ia32_sc(res, name); - res = new_rd_ia32_Cltd(dbg, irg, block, op, mode_T); - p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX); - p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX); - res = new_rd_ia32_Eor(dbg, irg, block, p_eax, p_edx, mode); - res = new_rd_ia32_Sub(dbg, irg, block, res, p_edx, mode); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); + + set_ia32_res_mode(res, mode); + set_ia32_immop_type(res, ia32_ImmSymConst); + + res = new_rd_Proj(dbg, irg, block, res, mode, 0); + } + else { + res = new_rd_ia32_vfabs(dbg, irg, block, op, mode); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); + } + } + else { + res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); + set_ia32_res_mode(res, mode); + + p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX); + p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX); + + res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); + set_ia32_res_mode(res, mode); + + res = new_rd_Proj(dbg, irg, block, res, mode, 0); + + res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); + set_ia32_res_mode(res, mode); + + res = new_rd_Proj(dbg, irg, block, res, mode, 0); + } return res; } @@ -970,163 +1237,167 @@ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) { * @return the created ia32 Load node */ static ir_node *gen_Load(ia32_transform_env_t *env) { - ir_node *node = env->irn; + ir_node *node = env->irn; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *ptr = get_Load_ptr(node); + ir_node *lptr = ptr; + ir_mode *mode = get_Load_mode(node); + int is_imm = 0; + ir_node *new_op; + ia32_am_flavour_t am_flav = ia32_B; - if (mode_is_float(env->mode)) { - return new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode); + /* address might be a constant (symconst or absolute address) */ + if (is_ia32_Const(ptr)) { + lptr = noreg; + is_imm = 1; } - return new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode); -} - + if (mode_is_float(mode)) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode); + else + new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode); + } + else { + new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode); + } -/** - * Transforms a Store. - * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Store node - * @param mode node mode - * @return the created ia32 Store node - */ -ir_node *gen_Store(ia32_transform_env_t *env) { - ir_node *node = env->irn; + /* base is an constant address */ + if (is_imm) { + if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) { + set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr)); + } + else { + add_ia32_am_offs(new_op, get_ia32_cnst(ptr)); + } - if (mode_is_float(env->mode)) { - return new_rd_ia32_fStore(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode); + am_flav = ia32_O; } - return new_rd_ia32_Store(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode); + + set_ia32_am_support(new_op, ia32_am_Source); + set_ia32_op_type(new_op, ia32_AddrModeS); + set_ia32_am_flavour(new_op, am_flav); + set_ia32_ls_mode(new_op, mode); + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + return new_op; } /** - * Transforms a Call and its arguments corresponding to the calling convention. + * Transforms a Store. * * @param mod the debug module * @param block the block the new node should belong to - * @param node the ir Call node - * @param dummy mode doesn't matter - * @return the created ia32 Call node + * @param node the ir Store node + * @param mode node mode + * @return the created ia32 Store node */ -static ir_node *gen_Call(ia32_transform_env_t *env) { - const ia32_register_req_t **in_req; - ir_node **in; - ir_node *new_call, *sync; - int i, j, n_new_call_in, ignore = 0; - asmop_attr *attr; - dbg_info *dbg = env->dbg; - ir_graph *irg = env->irg; - ir_node *block = env->block; - ir_node *call = env->irn; - ir_node **stack_param = NULL; - ir_node **param = get_Call_param_arr(call); - ir_node *call_Mem = get_Call_mem(call); - unsigned cc = get_method_calling_convention(get_Call_type(call)); - int n = get_Call_n_params(call); - int stack_idx = 0; - int biggest_n = -1; - - if (cc & cc_reg_param) - biggest_n = ia32_get_n_regparam_class(n, param, &ignore, &ignore); - - /* remember: biggest_n = x means we can pass (x + 1) parameters in register */ - - /* do we need to pass arguments on stack? */ - if (biggest_n + 1 < n) - stack_param = calloc(n - biggest_n - 1, sizeof(ir_node *)); - - /* we need at least one in, either for the stack params or the call_Mem */ - n_new_call_in = biggest_n + 2; - - /* the call has one IN for all stack parameter and one IN for each reg param */ - in = calloc(n_new_call_in, sizeof(ir_node *)); - in_req = calloc(n_new_call_in, sizeof(arch_register_req_t *)); - - /* loop over all parameters and set the register requirements */ - for (i = 0; i <= biggest_n && (cc & cc_reg_param); i++) { - in_req[i] = ia32_get_RegParam_req(n, param, i, cc); - } - stack_idx = i; - - /* create remaining stack parameters */ - if (cc & cc_last_on_top) { - for (i = stack_idx; i < n; i++) { - /* pass it on stack */ - if (mode_is_float(get_irn_mode(param[i]))) { - stack_param[i - stack_idx] = new_rd_ia32_fStackArg(get_irn_dbg_info(param[i]), irg, - block, call_Mem, param[i], mode_M); - } - else { - stack_param[i - stack_idx] = new_rd_ia32_StackArg(get_irn_dbg_info(param[i]), irg, - block, call_Mem, param[i], mode_M); +static ir_node *gen_Store(ia32_transform_env_t *env) { + ir_node *node = env->irn; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *val = get_Store_value(node); + ir_node *ptr = get_Store_ptr(node); + ir_node *sptr = ptr; + ir_node *mem = get_Store_mem(node); + ir_mode *mode = get_irn_mode(val); + ir_node *sval = val; + int is_imm = 0; + ir_node *new_op; + ia32_am_flavour_t am_flav = ia32_B; + ia32_immop_type_t immop = ia32_ImmNone; + + if (! mode_is_float(mode)) { + /* in case of storing a const (but not a symconst) -> make it an attribute */ + if (is_ia32_Cnst(val)) { + switch (get_ia32_op_type(val)) { + case ia32_Const: + immop = ia32_ImmConst; + break; + case ia32_SymConst: + immop = ia32_ImmSymConst; + break; + default: + assert(0 && "unsupported Const type"); } + sval = noreg; } } - else { - for (i = n - 1, j = 0; i >= stack_idx; i--, j++) { - /* pass it on stack */ - if (mode_is_float(get_irn_mode(param[i]))) { - stack_param[j] = new_rd_ia32_fStackArg(get_irn_dbg_info(param[i]), irg, - block, call_Mem, param[i], mode_M); - } - else { - stack_param[j] = new_rd_ia32_StackArg(get_irn_dbg_info(param[i]), irg, - block, call_Mem, param[i], mode_M); - } - } + + /* address might be a constant (symconst or absolute address) */ + if (is_ia32_Const(ptr)) { + sptr = noreg; + is_imm = 0; } - if (stack_param) { - sync = new_r_Sync(irg, block, n - biggest_n - 1, stack_param); - in[n_new_call_in - 1] = sync; + if (mode_is_float(mode)) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T); + else + new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T); + } + else if (get_mode_size_bits(mode) == 8) { + new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T); } else { - in[n_new_call_in - 1] = call_Mem; + new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T); + } + + /* stored const is an attribute (saves a register) */ + if (! mode_is_float(mode) && is_ia32_Cnst(val)) { + set_ia32_Immop_attr(new_op, val); } - /* create the new node */ - new_call = new_rd_ia32_Call(dbg, irg, block, n_new_call_in, in); - set_ia32_Immop_attr(new_call, get_Call_ptr(call)); - set_ia32_n_res(new_call, 1); + /* base is an constant address */ + if (is_imm) { + if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) { + set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr)); + } + else { + add_ia32_am_offs(new_op, get_ia32_cnst(ptr)); + } + + am_flav = ia32_O; + } - /* set register requirements for in and out */ - attr = get_ia32_attr(new_call); - attr->in_req = in_req; - attr->out_req = calloc(2, sizeof(ia32_register_req_t *)); - attr->out_req[0] = &ia32_default_req_ia32_general_purpose_eax; - attr->out_req[1] = &ia32_default_req_ia32_general_purpose_edx; - attr->slots = calloc(2, sizeof(arch_register_t *)); + set_ia32_am_support(new_op, ia32_am_Dest); + set_ia32_op_type(new_op, ia32_AddrModeD); + set_ia32_am_flavour(new_op, am_flav); + set_ia32_ls_mode(new_op, get_irn_mode(val)); + set_ia32_immop_type(new_op, immop); - /* stack parameter has no OUT register */ - attr->in_req[n_new_call_in - 1] = &ia32_default_req_none; + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); - return new_call; + return new_op; } /** - * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i + * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Cond node - * @param mode mode of the Cond + * @param env The transformation environment * @return The transformed node. */ static ir_node *gen_Cond(ia32_transform_env_t *env) { - dbg_info *dbg = env->dbg; - ir_graph *irg = env->irg; - ir_node *block = env->block; - ir_node *node = env->irn; - ir_node *sel = get_Cond_selector(node); - ir_mode *sel_mode = get_irn_mode(sel); - ir_node *res = NULL; - ir_node *pred = NULL; - ir_node *cmp_a, *cmp_b, *cnst, *expr; + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *node = env->irn; + ir_node *sel = get_Cond_selector(node); + ir_mode *sel_mode = get_irn_mode(sel); + ir_node *res = NULL; + ir_node *pred = NULL; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *cmp_a, *cmp_b, *cnst, *expr; if (is_Proj(sel) && sel_mode == mode_b) { + ir_node *nomem = new_NoMem(); + pred = get_Proj_pred(sel); /* get both compare operators */ @@ -1134,153 +1405,472 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) { cmp_b = get_Cmp_right(pred); /* check if we can use a CondJmp with immediate */ - cnst = get_immediate_op(cmp_a, cmp_b); + cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL; expr = get_expr_op(cmp_a, cmp_b); if (cnst && expr) { - res = new_rd_ia32_CondJmp_i(dbg, irg, block, expr, mode_T); + pn_Cmp pnc = get_Proj_proj(sel); + + if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) { + if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) { + /* a Cmp A =/!= 0 */ + ir_node *op1 = expr; + ir_node *op2 = expr; + ir_node *and = skip_Proj(expr); + const char *cnst = NULL; + + /* check, if expr is an only once used And operation */ + if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) { + op1 = get_irn_n(and, 2); + op2 = get_irn_n(and, 3); + + cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL; + } + res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T); + set_ia32_pncode(res, get_Proj_proj(sel)); + set_ia32_res_mode(res, get_irn_mode(op1)); + + if (cnst) { + copy_ia32_Immop_attr(res, and); + } + + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); + return res; + } + } + + if (mode_is_float(get_irn_mode(expr))) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T); + else { + assert(0); + } + } + else { + res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T); + } set_ia32_Immop_attr(res, cnst); + set_ia32_res_mode(res, get_irn_mode(expr)); } else { - res = new_rd_ia32_CondJmp(dbg, irg, block, cmp_a, cmp_b, mode_T); + if (mode_is_float(get_irn_mode(cmp_a))) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T); + else { + assert(0); + } + } + else { + res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T); + } + set_ia32_res_mode(res, get_irn_mode(cmp_a)); } set_ia32_pncode(res, get_Proj_proj(sel)); + set_ia32_am_support(res, ia32_am_Source); } else { - res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T); + /* determine the smallest switch case value */ + int switch_min = INT_MAX; + const ir_edge_t *edge; + char buf[64]; + + foreach_out_edge(node, edge) { + int pn = get_Proj_proj(get_edge_src_irn(edge)); + switch_min = pn < switch_min ? pn : switch_min; + } + + if (switch_min) { + /* if smallest switch case is not 0 we need an additional sub */ + snprintf(buf, sizeof(buf), "%d", switch_min); + res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); + sub_ia32_am_offs(res, buf); + set_ia32_am_flavour(res, ia32_am_OB); + set_ia32_am_support(res, ia32_am_Source); + set_ia32_op_type(res, ia32_AddrModeS); + } + + res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T); set_ia32_pncode(res, get_Cond_defaultProj(node)); + set_ia32_res_mode(res, get_irn_mode(sel)); } + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); return res; } /** - * Transform the argument projs from a start node corresponding to the - * calling convention. - * It transforms "Proj Arg x -> ProjT -> Start <- ProjM" into - * "RegParam x -> ProjT -> Start" OR - * "StackParam x -> ProjM -> Start" - * whether parameter is passed in register or on stack. + * Transforms a CopyB node. * - * @param mod the debug module - * @param block the block the nodes should belong to - * @param proj the ProjT node which points to Start - * @param start the Start node - * @return Should be always NULL + * @param env The transformation environment + * @return The transformed node. */ -static ir_node *gen_Proj_Start(ia32_transform_env_t *env, ir_node *proj, ir_node *start) { - const ia32_register_req_t *temp_req; - const ir_edge_t *edge; - ir_node *succ, *irn; - ir_node **projargs; - ir_mode *mode; - int n, i; - unsigned cc; - ir_node *proj_M = get_irg_initial_mem(current_ir_graph); - entity *irg_ent = get_irg_entity(current_ir_graph); - ir_type *tp = get_entity_type(irg_ent); - int cur_pn = 0; - ir_graph *irg = env->irg; - ir_node *block = env->block; - - assert(is_Method_type(tp) && "irg type is not a method"); - - switch(get_Proj_proj(proj)) { - case pn_Start_T_args: - /* We cannot use get_method_n_params here as the function might - be variadic or one argument is not used. */ - n = get_irn_n_edges(proj); - - /* Allocate memory for all non variadic parameters in advance to be on the save side */ - env->cg->reg_param_req = calloc(get_method_n_params(tp), sizeof(ia32_register_req_t *)); - - /* we are done here when there are no parameters */ - if (n < 1) - break; +static ir_node *gen_CopyB(ia32_transform_env_t *env) { + ir_node *res = NULL; + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_mode *mode = env->mode; + ir_node *block = env->block; + ir_node *node = env->irn; + ir_node *src = get_CopyB_src(node); + ir_node *dst = get_CopyB_dst(node); + ir_node *mem = get_CopyB_mem(node); + int size = get_type_size_bytes(get_CopyB_type(node)); + int rem; + + /* If we have to copy more than 16 bytes, we use REP MOVSx and */ + /* then we need the size explicitly in ECX. */ + if (size >= 16 * 4) { + rem = size & 0x3; /* size % 4 */ + size >>= 2; + + res = new_rd_ia32_Const(dbg, irg, block, mode_Is); + set_ia32_op_type(res, ia32_Const); + set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is)); + + res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode); + set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is)); + } + else { + res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode); + set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is)); + set_ia32_immop_type(res, ia32_ImmConst); + } - /* temporary remember all proj arg x */ - projargs = calloc(n, sizeof(ir_node *)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); + + return res; +} + + + +/** + * Transforms a Mux node into CMov. + * + * @param env The transformation environment + * @return The transformed node. + */ +static ir_node *gen_Mux(ia32_transform_env_t *env) { + ir_node *node = env->irn; + ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \ + get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode); + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + return new_op; +} - i = 0; - foreach_out_edge((const ir_node *)proj, edge) { - succ = get_edge_src_irn(edge); - assert(is_Proj(succ) && "non-Proj from a Proj_T (pn_Start_T_args)."); - projargs[i++] = succ; - } - cc = get_method_calling_convention(tp); +/** + * Following conversion rules apply: + * + * INT -> INT + * ============ + * 1) n bit -> m bit n > m (downscale) + * a) target is signed: movsx + * b) target is unsigned: and with lower bits sets + * 2) n bit -> m bit n == m (sign change) + * always ignored + * 3) n bit -> m bit n < m (upscale) + * a) source is signed: movsx + * b) source is unsigned: and with lower bits sets + * + * INT -> FLOAT + * ============== + * SSE(1/2) convert to float or double (cvtsi2ss/sd) + * + * FLOAT -> INT + * ============== + * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si) + * if target mode < 32bit: additional INT -> INT conversion (see above) + * + * FLOAT -> FLOAT + * ================ + * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss) + * x87 is mode_E internally, conversions happen only at load and store + * in non-strict semantic + */ - /* loop over all parameters and check whether its a int or float */ - for (i = 0; i < n; i++) { - mode = get_irn_mode(projargs[i]); - cur_pn = get_Proj_proj(projargs[i]); +//static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op, +// ir_mode *src_mode, ir_mode *tgt_mode) +//{ +// int n = get_mode_size_bits(src_mode); +// int m = get_mode_size_bits(tgt_mode); +// dbg_info *dbg = env->dbg; +// ir_graph *irg = env->irg; +// ir_node *block = env->block; +// ir_node *noreg = ia32_new_NoReg_gp(env->cg); +// ir_node *nomem = new_rd_NoMem(irg); +// ir_node *new_op, *proj; +// assert(n > m && "downscale expected"); +// if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) { +// /* ASHL Sn, n - m */ +// new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T); +// proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0); +// set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is)); +// set_ia32_am_support(new_op, ia32_am_Source); +// SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); +// /* ASHR Sn, n - m */ +// new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T); +// set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is)); +// } +// else { +// new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T); +// set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is)); +// } +// return new_op; +//} - if (cc & cc_reg_param) { - temp_req = ia32_get_RegParam_req(n, projargs, cur_pn, cc); +/** + * Transforms a Conv node. + * + * @param env The transformation environment + * @param op The operator + * @return The created ia32 Conv node + */ +static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) { + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_mode *src_mode = get_irn_mode(op); + ir_mode *tgt_mode = env->mode; + int src_bits = get_mode_size_bits(src_mode); + int tgt_bits = get_mode_size_bits(tgt_mode); + ir_node *block = env->block; + ir_node *new_op = NULL; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *nomem = new_rd_NoMem(irg); + ir_node *proj; + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) + + if (src_mode == tgt_mode) { + /* this can happen when changing mode_P to mode_Is */ + DB((mod, LEVEL_1, "killed Conv(mode, mode) ...")); + edges_reroute(env->irn, op, irg); + } + else if (mode_is_float(src_mode)) { + /* we convert from float ... */ + if (mode_is_float(tgt_mode)) { + /* ... to float */ + if (USE_SSE2(env->cg)) { + DB((mod, LEVEL_1, "create Conv(float, float) ...")); + new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T); + } + else { + DB((mod, LEVEL_1, "killed Conv(float, float) ...")); + edges_reroute(env->irn, op, irg); + } + } + else { + /* ... to int */ + DB((mod, LEVEL_1, "create Conv(float, int) ...")); + new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T); + /* if target mode is not int: add an additional downscale convert */ + if (tgt_bits < 32) { + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + set_ia32_am_support(new_op, ia32_am_Source); + set_ia32_tgt_mode(new_op, tgt_mode); + set_ia32_src_mode(new_op, src_mode); + + proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0); + + if (tgt_bits == 8 || src_bits == 8) { + new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem, mode_T); } else { - temp_req = NULL; + new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem, mode_T); } - - if (temp_req) { - /* passed in register */ - env->cg->reg_param_req[cur_pn] = temp_req; + } + } + } + else { + /* we convert from int ... */ + if (mode_is_float(tgt_mode)) { + /* ... to float */ + DB((mod, LEVEL_1, "create Conv(int, float) ...")); + new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T); + } + else { + /* ... to int */ + if (get_mode_size_bits(src_mode) == tgt_bits) { + DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode)); + edges_reroute(env->irn, op, irg); + } + else { + DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode)); + if (tgt_bits == 8 || src_bits == 8) { + new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem, mode_T); } else { - /* passed on stack */ - if (mode_is_float(mode)) - irn = new_rd_ia32_fStackParam(get_irn_dbg_info(projargs[i]), irg, block, proj_M, mode); - else - irn = new_rd_ia32_StackParam(get_irn_dbg_info(projargs[i]), irg, block, proj_M, mode); - - set_ia32_pncode(irn, cur_pn); - - /* kill the old "Proj Arg" and replace with the new stack param */ - exchange(projargs[i], irn); + new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T); } } + } + } - free(projargs); + if (new_op) { + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + set_ia32_tgt_mode(new_op, tgt_mode); + set_ia32_src_mode(new_op, src_mode); - break; - case pn_Start_P_frame_base: - case pn_Start_X_initial_exec: - case pn_Start_M: - case pn_Start_P_globals: - case pn_Start_P_value_arg_base: - break; - default: - assert(0 && "unsupported Proj(Start)"); + set_ia32_am_support(new_op, ia32_am_Source); + + new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0); } - return NULL; + return new_op; } -/** - * Transform some Proj's (Proj_Proj, Proj_Start, Proj_Cmp, Proj_Cond, Proj_Call). - * All others are ignored. + + +/******************************************** + * _ _ + * | | | | + * | |__ ___ _ __ ___ __| | ___ ___ + * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __| + * | |_) | __/ | | | (_) | (_| | __/\__ \ + * |_.__/ \___|_| |_|\___/ \__,_|\___||___/ * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Proj node - * @param mode mode of the Proj - * @return The transformed node. + ********************************************/ + +static ir_node *gen_StackParam(ia32_transform_env_t *env) { + ir_node *new_op = NULL; + ir_node *node = env->irn; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *mem = new_rd_NoMem(env->irg); + ir_node *ptr = get_irn_n(node, 0); + entity *ent = be_get_frame_entity(node); + ir_mode *mode = env->mode; + +// /* If the StackParam has only one user -> */ +// /* put it in the Block where the user resides */ +// if (get_irn_n_edges(node) == 1) { +// env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node))); +// } + + if (mode_is_float(mode)) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); + else + new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); + } + else { + new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); + } + + set_ia32_frame_ent(new_op, ent); + set_ia32_use_frame(new_op); + + set_ia32_am_support(new_op, ia32_am_Source); + set_ia32_op_type(new_op, ia32_AddrModeS); + set_ia32_am_flavour(new_op, ia32_B); + set_ia32_ls_mode(new_op, mode); + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0); +} + +/** + * Transforms a FrameAddr into an ia32 Add. */ -static ir_node *gen_Proj(ia32_transform_env_t *env) { - ir_node *new_node = NULL; - ir_node *pred = get_Proj_pred(env->irn); +static ir_node *gen_FrameAddr(ia32_transform_env_t *env) { + ir_node *new_op = NULL; + ir_node *node = env->irn; + ir_node *op = get_irn_n(node, 0); + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *nomem = new_rd_NoMem(env->irg); + + new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T); + set_ia32_frame_ent(new_op, be_get_frame_entity(node)); + set_ia32_am_support(new_op, ia32_am_Full); + set_ia32_use_frame(new_op); + set_ia32_immop_type(new_op, ia32_ImmConst); + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0); +} + +/** + * Transforms a FrameLoad into an ia32 Load. + */ +static ir_node *gen_FrameLoad(ia32_transform_env_t *env) { + ir_node *new_op = NULL; + ir_node *node = env->irn; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *mem = get_irn_n(node, 0); + ir_node *ptr = get_irn_n(node, 1); + entity *ent = be_get_frame_entity(node); + ir_mode *mode = get_type_mode(get_entity_type(ent)); + + if (mode_is_float(mode)) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); + else + new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); + } + else + new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); + + set_ia32_frame_ent(new_op, ent); + set_ia32_use_frame(new_op); + + set_ia32_am_support(new_op, ia32_am_Source); + set_ia32_op_type(new_op, ia32_AddrModeS); + set_ia32_am_flavour(new_op, ia32_B); + set_ia32_ls_mode(new_op, mode); + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + return new_op; +} + - if (env->mode == mode_M) - return NULL; +/** + * Transforms a FrameStore into an ia32 Store. + */ +static ir_node *gen_FrameStore(ia32_transform_env_t *env) { + ir_node *new_op = NULL; + ir_node *node = env->irn; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *mem = get_irn_n(node, 0); + ir_node *ptr = get_irn_n(node, 1); + ir_node *val = get_irn_n(node, 2); + entity *ent = be_get_frame_entity(node); + ir_mode *mode = get_irn_mode(val); - if (get_irn_op(pred) == op_Start) { - new_node = gen_Proj_Start(env, env->irn, pred); + if (mode_is_float(mode)) { + FP_USED(env->cg); + if (USE_SSE2(env->cg)) + new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); + else + new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); } + else if (get_mode_size_bits(mode) == 8) { + new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); + } + else { + new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); + } + + set_ia32_frame_ent(new_op, ent); + set_ia32_use_frame(new_op); - return new_node; + set_ia32_am_support(new_op, ia32_am_Dest); + set_ia32_op_type(new_op, ia32_AddrModeD); + set_ia32_am_flavour(new_op, ia32_B); + set_ia32_ls_mode(new_op, mode); + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + return new_op; } @@ -1295,7 +1885,185 @@ static ir_node *gen_Proj(ia32_transform_env_t *env) { * *********************************************************/ +/** + * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG. + * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION. + */ +void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { + ia32_transform_env_t tenv; + ir_node *in1, *in2, *noreg, *nomem, *res; + const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots; + + /* Return if AM node or not a Sub or fSub */ + if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn))) + return; + + noreg = ia32_new_NoReg_gp(cg); + nomem = new_rd_NoMem(cg->irg); + in1 = get_irn_n(irn, 2); + in2 = get_irn_n(irn, 3); + in1_reg = arch_get_irn_register(cg->arch_env, in1); + in2_reg = arch_get_irn_register(cg->arch_env, in2); + out_reg = get_ia32_out_reg(irn, 0); + + tenv.block = get_nodes_block(irn); + tenv.dbg = get_irn_dbg_info(irn); + tenv.irg = cg->irg; + tenv.irn = irn; + DEBUG_ONLY(tenv.mod = cg->mod;) + tenv.mode = get_ia32_res_mode(irn); + tenv.cg = cg; + + /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */ + if (REGS_ARE_EQUAL(out_reg, in2_reg)) { + /* generate the neg src2 */ + res = gen_Minus(&tenv, in2); + arch_set_irn_register(cg->arch_env, res, in2_reg); + + /* add to schedule */ + sched_add_before(irn, res); + + /* generate the add */ + if (mode_is_float(tenv.mode)) { + res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T); + set_ia32_am_support(res, ia32_am_Source); + } + else { + res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T); + set_ia32_am_support(res, ia32_am_Full); + } + + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn)); + /* copy register */ + slots = get_ia32_slots(res); + slots[0] = in2_reg; + + /* add to schedule */ + sched_add_before(irn, res); + + /* remove the old sub */ + sched_remove(irn); + + /* exchange the add and the sub */ + exchange(irn, res); + } +} + +/** + * Transforms a LEA into an Add if possible + * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION. + */ +void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) { + ia32_am_flavour_t am_flav; + int imm = 0; + ir_node *res = NULL; + ir_node *nomem, *noreg, *base, *index, *op1, *op2; + char *offs; + ia32_transform_env_t tenv; + const arch_register_t *out_reg, *base_reg, *index_reg; + + /* must be a LEA */ + if (! is_ia32_Lea(irn)) + return; + + am_flav = get_ia32_am_flavour(irn); + + /* only some LEAs can be transformed to an Add */ + if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI) + return; + + noreg = ia32_new_NoReg_gp(cg); + nomem = new_rd_NoMem(cg->irg); + op1 = noreg; + op2 = noreg; + base = get_irn_n(irn, 0); + index = get_irn_n(irn,1); + + offs = get_ia32_am_offs(irn); + + /* offset has a explicit sign -> we need to skip + */ + if (offs && offs[0] == '+') + offs++; + + out_reg = arch_get_irn_register(cg->arch_env, irn); + base_reg = arch_get_irn_register(cg->arch_env, base); + index_reg = arch_get_irn_register(cg->arch_env, index); + + tenv.block = get_nodes_block(irn); + tenv.dbg = get_irn_dbg_info(irn); + tenv.irg = cg->irg; + tenv.irn = irn; + DEBUG_ONLY(tenv.mod = cg->mod;) + tenv.mode = get_irn_mode(irn); + tenv.cg = cg; + + switch(get_ia32_am_flavour(irn)) { + case ia32_am_B: + /* out register must be same as base register */ + if (! REGS_ARE_EQUAL(out_reg, base_reg)) + return; + + op1 = base; + break; + case ia32_am_OB: + /* out register must be same as base register */ + if (! REGS_ARE_EQUAL(out_reg, base_reg)) + return; + + op1 = base; + imm = 1; + break; + case ia32_am_OI: + /* out register must be same as index register */ + if (! REGS_ARE_EQUAL(out_reg, index_reg)) + return; + + op1 = index; + imm = 1; + break; + case ia32_am_BI: + /* out register must be same as one in register */ + if (REGS_ARE_EQUAL(out_reg, base_reg)) { + op1 = base; + op2 = index; + } + else if (REGS_ARE_EQUAL(out_reg, index_reg)) { + op1 = index; + op2 = base; + } + else { + /* in registers a different from out -> no Add possible */ + return; + } + default: + break; + } + + res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T); + arch_set_irn_register(cg->arch_env, res, out_reg); + set_ia32_op_type(res, ia32_Normal); + + if (imm) { + set_ia32_cnst(res, offs); + set_ia32_immop_type(res, ia32_ImmConst); + } + + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn)); + + /* add Add to schedule */ + sched_add_before(irn, res); + + res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0); + + /* add result Proj to schedule */ + sched_add_before(irn, res); + /* remove the old LEA */ + sched_remove(irn); + + /* exchange the Add and the LEA */ + exchange(irn, res); +} /** * Transforms the given firm node (and maybe some other related nodes) @@ -1306,47 +2074,58 @@ static ir_node *gen_Proj(ia32_transform_env_t *env) { */ void ia32_transform_node(ir_node *node, void *env) { ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env; - opcode code = get_irn_opcode(node); + opcode code; ir_node *asm_node = NULL; ia32_transform_env_t tenv; if (is_Block(node)) return; - tenv.arch_env = cgenv->arch_env; tenv.block = get_nodes_block(node); tenv.dbg = get_irn_dbg_info(node); tenv.irg = current_ir_graph; tenv.irn = node; - tenv.mod = cgenv->mod; + DEBUG_ONLY(tenv.mod = cgenv->mod;) tenv.mode = get_irn_mode(node); tenv.cg = cgenv; -#define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break -#define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break -#define BINOP_COM(a) case iro_##a: asm_node = gen_arith_Op(&tenv, get_##a##_left(node), get_##a##_right(node), 1); break -#define BINOP_NCOM(a) case iro_##a: asm_node = gen_arith_Op(&tenv, get_##a##_left(node), get_##a##_right(node), 0); break -#define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break -#define IGN(a) case iro_##a: break -#define BAD(a) case iro_##a: goto bad +#define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break +#define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break +#define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break +#define IGN(a) case iro_##a: break +#define BAD(a) case iro_##a: goto bad +#define OTHER_BIN(a) \ + if (get_irn_op(node) == get_op_##a()) { \ + asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \ + break; \ + } +#define BE_GEN(a) \ + if (be_is_##a(node)) { \ + asm_node = gen_##a(&tenv); \ + break; \ + } DBG((tenv.mod, LEVEL_1, "check %+F ... ", node)); + code = get_irn_opcode(node); switch (code) { - BINOP_COM(Add); - BINOP_COM(Mul); - BINOP_COM(And); - BINOP_COM(Or); - BINOP_COM(Eor); - - BINOP_NCOM(Sub); - BINOP_NCOM(Shl); - BINOP_NCOM(Shr); - BINOP_NCOM(Shrs); - BINOP_NCOM(Quot); - BINOP_NCOM(Div); - BINOP_NCOM(Mod); - BINOP_NCOM(DivMod); + BINOP(Add); + BINOP(Sub); + BINOP(Mul); + BINOP(And); + BINOP(Or); + BINOP(Eor); + + BINOP(Shl); + BINOP(Shr); + BINOP(Shrs); + BINOP(Rot); + + BINOP(Quot); + + BINOP(Div); + BINOP(Mod); + BINOP(DivMod); UNOP(Minus); UNOP(Conv); @@ -1355,11 +2134,15 @@ void ia32_transform_node(ir_node *node, void *env) { GEN(Load); GEN(Store); - GEN(Call); GEN(Cond); - GEN(Proj); + GEN(CopyB); + GEN(Mux); + + IGN(Call); + IGN(Alloc); + IGN(Proj); IGN(Block); IGN(Start); IGN(End); @@ -1369,17 +2152,17 @@ void ia32_transform_node(ir_node *node, void *env) { IGN(Break); IGN(Cmp); IGN(Unknown); + /* constant transformation happens earlier */ IGN(Const); IGN(SymConst); + IGN(Sync); - BAD(Alloc); BAD(Raise); BAD(Sel); BAD(InstOf); BAD(Cast); BAD(Free); - BAD(Sync); BAD(Tuple); BAD(Id); BAD(Bad); @@ -1388,22 +2171,23 @@ void ia32_transform_node(ir_node *node, void *env) { BAD(CallBegin); BAD(EndReg); BAD(EndExcept); - BAD(Mux); - BAD(CopyB); default: - if (get_irn_op(node) == get_op_Max() || - get_irn_op(node) == get_op_Min() || - get_irn_op(node) == get_op_Mulh()) - { - asm_node = gen_arith_Op(&tenv, get_irn_n(node, 0), get_irn_n(node, 1), 1); - } + OTHER_BIN(Max); + OTHER_BIN(Min); + OTHER_BIN(Mulh); + + BE_GEN(FrameAddr); + BE_GEN(FrameLoad); + BE_GEN(FrameStore); + BE_GEN(StackParam); break; bad: fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node)); assert(0); } + /* exchange nodes if a new one was generated */ if (asm_node) { exchange(node, asm_node); DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node)); @@ -1411,4 +2195,12 @@ bad: else { DB((tenv.mod, LEVEL_1, "ignored\n")); } + +#undef UNOP +#undef BINOP +#undef GEN +#undef IGN +#undef BAD +#undef OTHER_BIN +#undef BE_GEN }