X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=a07a024021595654b5e16d915d377ced7b1e3983;hb=08fe790a5784b31964a8783f6af1d14d62c366c4;hp=4cdcfa5f24cc6f433f57e08a62d979d8539965fe;hpb=84e0212853c864d291cc7fb23071a3560dbe0c3d;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 4cdcfa5f2..a07a02402 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -9,6 +9,8 @@ #include "config.h" #endif +#include + #include "irargs_t.h" #include "irnode_t.h" #include "irgraph_t.h" @@ -146,10 +148,10 @@ static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) { /** * Prints the old node name on cg obst and returns a pointer to it. */ -const char *ia32_get_old_node_name(ia32_transform_env_t *env) { - ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa; +const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) { + ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa; - lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn); + lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn); obstack_1grow(isa->name_obst, 0); isa->name_obst_size += obstack_object_size(isa->name_obst); return obstack_finish(isa->name_obst); @@ -184,11 +186,11 @@ static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, dbg_info *dbg = env->dbg; ir_graph *irg = env->irg; ir_node *block = env->block; - firm_dbg_module_t *mod = env->mod; ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg); ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg); ir_node *nomem = new_NoMem(); ir_node *expr_op, *imm_op; + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) /* Check if immediate optimization is on and */ /* if it's an operation with immediate. */ @@ -247,7 +249,7 @@ static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, } } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(new_op, mode); @@ -275,11 +277,11 @@ static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node dbg_info *dbg = env->dbg; ir_graph *irg = env->irg; ir_node *block = env->block; - firm_dbg_module_t *mod = env->mod; ir_node *noreg = ia32_new_NoReg_gp(env->cg); ir_node *nomem = new_NoMem(); ir_node *expr_op, *imm_op; tarval *tv; + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) assert(! mode_is_float(mode) && "Shift/Rotate with float not supported"); @@ -324,7 +326,7 @@ static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node /* set AM support */ set_ia32_am_support(new_op, ia32_am_Dest); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(new_op, mode); set_ia32_emit_cl(new_op); @@ -345,11 +347,11 @@ static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_ ir_node *new_op = NULL; ir_mode *mode = env->mode; dbg_info *dbg = env->dbg; - firm_dbg_module_t *mod = env->mod; ir_graph *irg = env->irg; ir_node *block = env->block; ir_node *noreg = ia32_new_NoReg_gp(env->cg); ir_node *nomem = new_NoMem(); + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T); @@ -363,7 +365,7 @@ static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_ set_ia32_am_support(new_op, ia32_am_Dest); } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(new_op, mode); @@ -383,7 +385,6 @@ static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_ static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { ir_node *new_op = NULL; tarval *tv = get_ia32_Immop_tarval(const_op); - firm_dbg_module_t *mod = env->mod; dbg_info *dbg = env->dbg; ir_graph *irg = env->irg; ir_node *block = env->block; @@ -391,6 +392,7 @@ static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node ir_node *nomem = new_NoMem(); int normal_add = 1; tarval_classification_t class_tv, class_negtv; + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) /* try to optimize to inc/dec */ if (env->cg->opt.incdec && tv) { @@ -446,12 +448,11 @@ static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { assert((expr_op || imm_op) && "invalid operands"); if (mode_is_float(mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) return gen_binop(env, op1, op2, new_rd_ia32_fAdd); - else { - env->cg->used_x87 = 1; + else return gen_binop(env, op1, op2, new_rd_ia32_vfadd); - } } else { /* integer ADD */ @@ -508,7 +509,7 @@ static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { } } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(new_op, mode); @@ -531,12 +532,11 @@ static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { ir_node *new_op; if (mode_is_float(env->mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul); - else { - env->cg->used_x87 = 1; + else new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul); - } } else { new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul); @@ -645,17 +645,17 @@ static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { ir_node *new_op; if (mode_is_float(env->mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax); else { - env->cg->used_x87 = 1; assert(0); } } else { new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode); set_ia32_am_support(new_op, ia32_am_None); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); } return new_op; @@ -675,17 +675,17 @@ static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { ir_node *new_op; if (mode_is_float(env->mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin); else { - env->cg->used_x87 = 1; assert(0); } } else { new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode); set_ia32_am_support(new_op, ia32_am_None); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); } return new_op; @@ -704,7 +704,6 @@ static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) { ir_node *new_op = NULL; tarval *tv = get_ia32_Immop_tarval(const_op); - firm_dbg_module_t *mod = env->mod; dbg_info *dbg = env->dbg; ir_graph *irg = env->irg; ir_node *block = env->block; @@ -712,6 +711,7 @@ static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node ir_node *nomem = new_NoMem(); int normal_sub = 1; tarval_classification_t class_tv, class_negtv; + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) /* try to optimize to inc/dec */ if (env->cg->opt.incdec && tv) { @@ -765,12 +765,11 @@ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { assert((expr_op || imm_op) && "invalid operands"); if (mode_is_float(mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) return gen_binop(env, op1, op2, new_rd_ia32_fSub); - else { - env->cg->used_x87 = 1; + else return gen_binop(env, op1, op2, new_rd_ia32_vfsub); - } } else { /* integer SUB */ @@ -829,7 +828,7 @@ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { } } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(new_op, mode); @@ -910,7 +909,7 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(res, mode_Is); @@ -975,7 +974,7 @@ static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) set_ia32_am_support(new_op, ia32_am_Source); } set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res))); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); return new_op; } @@ -1117,6 +1116,7 @@ static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) { int size; if (mode_is_float(env->mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) { new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T); @@ -1125,7 +1125,7 @@ static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) { set_ia32_sc(new_op, name); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(new_op, env->mode); set_ia32_immop_type(new_op, ia32_ImmSymConst); @@ -1133,9 +1133,8 @@ static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) { new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0); } else { - env->cg->used_x87 = 1; new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); } } else { @@ -1181,6 +1180,7 @@ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) { ident *name; if (mode_is_float(mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) { res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T); @@ -1189,7 +1189,7 @@ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) { set_ia32_sc(res, name); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(res, mode); set_ia32_immop_type(res, ia32_ImmSymConst); @@ -1197,27 +1197,26 @@ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) { res = new_rd_Proj(dbg, irg, block, res, mode, 0); } else { - env->cg->used_x87 = 1; res = new_rd_ia32_vfabs(dbg, irg, block, op, mode); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); } } else { res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(res, mode); p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX); p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX); res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(res, mode); res = new_rd_Proj(dbg, irg, block, res, mode, 0); res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(res, mode); res = new_rd_Proj(dbg, irg, block, res, mode, 0); @@ -1254,12 +1253,11 @@ static ir_node *gen_Load(ia32_transform_env_t *env) { } if (mode_is_float(mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode); - else { - env->cg->used_x87 = 1; + else new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode); - } } else { new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode); @@ -1282,7 +1280,7 @@ static ir_node *gen_Load(ia32_transform_env_t *env) { set_ia32_am_flavour(new_op, am_flav); set_ia32_ls_mode(new_op, mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); return new_op; } @@ -1336,12 +1334,11 @@ static ir_node *gen_Store(ia32_transform_env_t *env) { } if (mode_is_float(mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T); - else { - env->cg->used_x87 = 1; + else new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T); - } } else if (get_mode_size_bits(mode) == 8) { new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T); @@ -1373,7 +1370,7 @@ static ir_node *gen_Store(ia32_transform_env_t *env) { set_ia32_ls_mode(new_op, get_irn_mode(val)); set_ia32_immop_type(new_op, immop); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); return new_op; } @@ -1437,16 +1434,16 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) { copy_ia32_Immop_attr(res, and); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); return res; } } if (mode_is_float(get_irn_mode(expr))) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T); else { - env->cg->used_x87 = 1; assert(0); } } @@ -1458,10 +1455,10 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) { } else { if (mode_is_float(get_irn_mode(cmp_a))) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T); else { - env->cg->used_x87 = 1; assert(0); } } @@ -1475,12 +1472,33 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) { set_ia32_am_support(res, ia32_am_Source); } else { - res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T); + /* determine the smallest switch case value */ + int switch_min = INT_MAX; + const ir_edge_t *edge; + char buf[64]; + + foreach_out_edge(node, edge) { + int pn = get_Proj_proj(get_edge_src_irn(edge)); + switch_min = pn < switch_min ? pn : switch_min; + } + + if (switch_min) { + /* if smallest switch case is not 0 we need an additional sub */ + snprintf(buf, sizeof(buf), "%d", switch_min); + res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); + sub_ia32_am_offs(res, buf); + set_ia32_am_flavour(res, ia32_am_OB); + set_ia32_am_support(res, ia32_am_Source); + set_ia32_op_type(res, ia32_AddrModeS); + } + + res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T); set_ia32_pncode(res, get_Cond_defaultProj(node)); set_ia32_res_mode(res, get_irn_mode(sel)); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); return res; } @@ -1524,7 +1542,7 @@ static ir_node *gen_CopyB(ia32_transform_env_t *env) { set_ia32_immop_type(res, ia32_ImmConst); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); return res; } @@ -1542,7 +1560,7 @@ static ir_node *gen_Mux(ia32_transform_env_t *env) { ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \ get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); return new_op; } @@ -1596,7 +1614,7 @@ static ir_node *gen_Mux(ia32_transform_env_t *env) { // proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0); // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is)); // set_ia32_am_support(new_op, ia32_am_Source); -// SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); +// SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); // /* ASHR Sn, n - m */ // new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T); // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is)); @@ -1626,8 +1644,8 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) { ir_node *new_op = NULL; ir_node *noreg = ia32_new_NoReg_gp(env->cg); ir_node *nomem = new_rd_NoMem(irg); - firm_dbg_module_t *mod = env->mod; ir_node *proj; + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) if (src_mode == tgt_mode) { /* this can happen when changing mode_P to mode_Is */ @@ -1653,11 +1671,12 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) { new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T); /* if target mode is not int: add an additional downscale convert */ if (tgt_bits < 32) { - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); - set_ia32_res_mode(new_op, tgt_mode); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_am_support(new_op, ia32_am_Source); + set_ia32_tgt_mode(new_op, tgt_mode); + set_ia32_src_mode(new_op, src_mode); - proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0); + proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0); if (tgt_bits == 8 || src_bits == 8) { new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem, mode_T); @@ -1694,8 +1713,9 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) { } if (new_op) { - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); - set_ia32_res_mode(new_op, tgt_mode); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + set_ia32_tgt_mode(new_op, tgt_mode); + set_ia32_src_mode(new_op, src_mode); set_ia32_am_support(new_op, ia32_am_Source); @@ -1733,12 +1753,11 @@ static ir_node *gen_StackParam(ia32_transform_env_t *env) { // } if (mode_is_float(mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); - else { - env->cg->used_x87 = 1; + else new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); - } } else { new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); @@ -1752,7 +1771,7 @@ static ir_node *gen_StackParam(ia32_transform_env_t *env) { set_ia32_am_flavour(new_op, ia32_B); set_ia32_ls_mode(new_op, mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0); } @@ -1773,7 +1792,7 @@ static ir_node *gen_FrameAddr(ia32_transform_env_t *env) { set_ia32_use_frame(new_op); set_ia32_immop_type(new_op, ia32_ImmConst); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0); } @@ -1791,16 +1810,14 @@ static ir_node *gen_FrameLoad(ia32_transform_env_t *env) { ir_mode *mode = get_type_mode(get_entity_type(ent)); if (mode_is_float(mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); - else { - env->cg->used_x87 = 1; + else new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); - } } - else { + else new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); - } set_ia32_frame_ent(new_op, ent); set_ia32_use_frame(new_op); @@ -1810,7 +1827,7 @@ static ir_node *gen_FrameLoad(ia32_transform_env_t *env) { set_ia32_am_flavour(new_op, ia32_B); set_ia32_ls_mode(new_op, mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); return new_op; } @@ -1830,12 +1847,11 @@ static ir_node *gen_FrameStore(ia32_transform_env_t *env) { ir_mode *mode = get_irn_mode(val); if (mode_is_float(mode)) { + FP_USED(env->cg); if (USE_SSE2(env->cg)) new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); - else { - env->cg->used_x87 = 1; + else new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); - } } else if (get_mode_size_bits(mode) == 8) { new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); @@ -1852,7 +1868,7 @@ static ir_node *gen_FrameStore(ia32_transform_env_t *env) { set_ia32_am_flavour(new_op, ia32_B); set_ia32_ls_mode(new_op, mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); return new_op; } @@ -1894,7 +1910,7 @@ void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { tenv.dbg = get_irn_dbg_info(irn); tenv.irg = cg->irg; tenv.irn = irn; - tenv.mod = cg->mod; + DEBUG_ONLY(tenv.mod = cg->mod;) tenv.mode = get_ia32_res_mode(irn); tenv.cg = cg; @@ -1917,7 +1933,7 @@ void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { set_ia32_am_support(res, ia32_am_Full); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(&tenv)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn)); /* copy register */ slots = get_ia32_slots(res); slots[0] = in2_reg; @@ -1977,7 +1993,7 @@ void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) { tenv.dbg = get_irn_dbg_info(irn); tenv.irg = cg->irg; tenv.irn = irn; - tenv.mod = cg->mod; + DEBUG_ONLY(tenv.mod = cg->mod;) tenv.mode = get_irn_mode(irn); tenv.cg = cg; @@ -2032,7 +2048,7 @@ void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) { set_ia32_immop_type(res, ia32_ImmConst); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(&tenv)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn)); /* add Add to schedule */ sched_add_before(irn, res); @@ -2069,7 +2085,7 @@ void ia32_transform_node(ir_node *node, void *env) { tenv.dbg = get_irn_dbg_info(node); tenv.irg = current_ir_graph; tenv.irn = node; - tenv.mod = cgenv->mod; + DEBUG_ONLY(tenv.mod = cgenv->mod;) tenv.mode = get_irn_mode(node); tenv.cg = cgenv;