X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=9f789d9f20ff773c3a909b7eb0ad57d58bccb129;hb=09480efeccb17e980766b3ca092bb0f6ebc0a44f;hp=bcf287a24f1d73c942bbb8893f7f78e8637efd4d;hpb=86997185c0e4d9a49b8f036a8a6fbb5e470ff2b2;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index bcf287a24..9f789d9f2 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -25,13 +25,12 @@ #include "irprintf.h" #include "debug.h" #include "irdom.h" +#include "archop.h" /* we need this for Min and Max nodes */ #include "../benode_t.h" #include "../besched.h" #include "../beabi.h" -#include "../arch/archop.h" /* we need this for Min and Max nodes */ - #include "bearch_ia32_t.h" #include "ia32_nodes_attr.h" #include "ia32_transform.h" @@ -247,7 +246,11 @@ static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, /* Check if immediate optimization is on and */ /* if it's an operation with immediate. */ - if (! (env->cg->opt & IA32_OPT_IMMOPS)) { + /* MulS and Mulh don't support immediates */ + if (! (env->cg->opt & IA32_OPT_IMMOPS) || + func == new_rd_ia32_Mulh || + func == new_rd_ia32_MulS) + { expr_op = op1; imm_op = NULL; } @@ -357,6 +360,7 @@ static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node if (tv) { tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu)); + set_ia32_Immop_tarval(imm_op, tv); } else { imm_op = NULL; @@ -963,11 +967,11 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir if (get_irn_op(irn) == op_Div) { set_Proj_proj(proj, pn_DivMod_res_div); - in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod); + in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_mod); } else { set_Proj_proj(proj, pn_DivMod_res_mod); - in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div); + in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_div); } be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep); @@ -975,7 +979,7 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); - set_ia32_res_mode(res, mode_Is); + set_ia32_res_mode(res, mode); return res; } @@ -1301,12 +1305,12 @@ static ir_node *gen_Abs(ia32_transform_env_t *env) { * @return the created ia32 Load node */ static ir_node *gen_Load(ia32_transform_env_t *env) { - ir_node *node = env->irn; - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *ptr = get_Load_ptr(node); - ir_node *lptr = ptr; - ir_mode *mode = get_Load_mode(node); - int is_imm = 0; + ir_node *node = env->irn; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *ptr = get_Load_ptr(node); + ir_node *lptr = ptr; + ir_mode *mode = get_Load_mode(node); + int is_imm = 0; ir_node *new_op; ia32_am_flavour_t am_flav = ia32_B; @@ -1344,6 +1348,16 @@ static ir_node *gen_Load(ia32_transform_env_t *env) { set_ia32_am_flavour(new_op, am_flav); set_ia32_ls_mode(new_op, mode); + /* + check for special case: the loaded value might not be used (optimized, volatile, ...) + we add a Proj + Keep for volatile loads and ignore all other cases + */ + if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) { + /* add a result proj and a Keep to produce a pseudo use */ + ir_node *proj = new_r_Proj(env->irg, env->block, new_op, mode, pn_ia32_Load_res); + be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), env->irg, env->block, 1, &proj); + } + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); return new_op; @@ -1364,7 +1378,7 @@ static ir_node *gen_Store(ia32_transform_env_t *env) { ir_node *ptr = get_Store_ptr(node); ir_node *sptr = ptr; ir_node *mem = get_Store_mem(node); - ir_mode *mode = get_irn_mode(val); + ir_mode *mode = get_irn_link(node); ir_node *sval = val; int is_imm = 0; ir_node *new_op; @@ -1428,7 +1442,7 @@ static ir_node *gen_Store(ia32_transform_env_t *env) { set_ia32_am_support(new_op, ia32_am_Dest); set_ia32_op_type(new_op, ia32_AddrModeD); set_ia32_am_flavour(new_op, am_flav); - set_ia32_ls_mode(new_op, get_irn_mode(val)); + set_ia32_ls_mode(new_op, mode); set_ia32_immop_type(new_op, immop); SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); @@ -1473,7 +1487,9 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) { pn_Cmp pnc = get_Proj_proj(sel); if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) { - if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) { + if (get_ia32_op_type(cnst) == ia32_Const && + classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) + { /* a Cmp A =/!= 0 */ ir_node *op1 = expr; ir_node *op2 = expr; @@ -1757,7 +1773,7 @@ static ir_node *gen_Psi(ia32_transform_env_t *env) { /* second case for SETcc: default is 1, set to 0 iff condition is true: */ /* we invert condition and set default to 0 */ new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode); - set_ia32_pncode(new_op, get_negated_pnc(pnc, mode)); + set_ia32_pncode(new_op, get_inversed_pnc(pnc)); } else { /* otherwise: use CMOVcc */ @@ -1779,7 +1795,7 @@ static ir_node *gen_Psi(ia32_transform_env_t *env) { /* second case for SETcc: default is 1, set to 0 iff condition is true: */ /* we invert condition and set default to 0 */ new_op = gen_binop(env, cmp_a, cmp_b, set_func); - set_ia32_pncode(get_Proj_pred(new_op), get_negated_pnc(pnc, mode)); + set_ia32_pncode(get_Proj_pred(new_op), get_inversed_pnc(pnc)); set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source); } else { @@ -1851,7 +1867,7 @@ static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) { set_ia32_am_support(fist, ia32_am_Dest); set_ia32_op_type(fist, ia32_AddrModeD); set_ia32_am_flavour(fist, ia32_B); - set_ia32_ls_mode(fist, mode_E); + set_ia32_ls_mode(fist, mode_F); mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M); @@ -1920,9 +1936,9 @@ static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) { set_ia32_am_support(fild, ia32_am_Source); set_ia32_op_type(fild, ia32_AddrModeS); set_ia32_am_flavour(fild, ia32_B); - set_ia32_ls_mode(fild, mode_E); + set_ia32_ls_mode(fild, mode_F); - return new_r_Proj(irg, block, fild, mode_E, 0); + return new_r_Proj(irg, block, fild, mode_F, 0); } /** @@ -2246,6 +2262,352 @@ static ir_node *gen_Unknown(ia32_transform_env_t *env) { return NULL; } +/********************************************************************** + * _ _ _ + * | | | | | | + * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___ + * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __| + * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \ + * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/ + * + **********************************************************************/ + +/* These nodes are created in intrinsic lowering (64bit -> 32bit) */ + +typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \ + ir_node *mem); + +typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \ + ir_node *val, ir_node *mem); + +/** + * Transforms a lowered Load into a "real" one. + */ +static ir_node *gen_lowered_Load(ia32_transform_env_t *env, construct_load_func func, char fp_unit) { + ir_node *node = env->irn; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_mode *mode = get_ia32_ls_mode(node); + ir_node *new_op; + char *am_offs; + ia32_am_flavour_t am_flav = ia32_B; + + /* + Could be that we have SSE2 unit, but due to 64Bit Div/Conv + lowering we have x87 nodes, so we need to enforce simulation. + */ + if (mode_is_float(mode)) { + FP_USED(env->cg); + if (fp_unit == fp_x87) + FORCE_x87(env->cg); + } + + new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1)); + am_offs = get_ia32_am_offs(node); + + if (am_offs) { + am_flav |= ia32_O; + add_ia32_am_offs(new_op, am_offs); + } + + set_ia32_am_support(new_op, ia32_am_Source); + set_ia32_op_type(new_op, ia32_AddrModeS); + set_ia32_am_flavour(new_op, am_flav); + set_ia32_ls_mode(new_op, mode); + set_ia32_frame_ent(new_op, get_ia32_frame_ent(node)); + set_ia32_use_frame(new_op); + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + + return new_op; +} + +/** +* Transforms a lowered Store into a "real" one. +*/ +static ir_node *gen_lowered_Store(ia32_transform_env_t *env, construct_store_func func, char fp_unit) { + ir_node *node = env->irn; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_mode *mode = get_ia32_ls_mode(node); + ir_node *new_op; + char *am_offs; + ia32_am_flavour_t am_flav = ia32_B; + + /* + Could be that we have SSE2 unit, but due to 64Bit Div/Conv + lowering we have x87 nodes, so we need to enforce simulation. + */ + if (mode_is_float(mode)) { + FP_USED(env->cg); + if (fp_unit == fp_x87) + FORCE_x87(env->cg); + } + + new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1), get_irn_n(node, 2)); + + if (am_offs = get_ia32_am_offs(node)) { + am_flav |= ia32_O; + add_ia32_am_offs(new_op, am_offs); + } + + set_ia32_am_support(new_op, ia32_am_Dest); + set_ia32_op_type(new_op, ia32_AddrModeD); + set_ia32_am_flavour(new_op, am_flav); + set_ia32_ls_mode(new_op, mode); + set_ia32_frame_ent(new_op, get_ia32_frame_ent(node)); + set_ia32_use_frame(new_op); + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + + return new_op; +} + + +/** + * Transforms an ia32_l_XXX into a "real" XXX node + * + * @param env The transformation environment + * @return the created ia32 XXX node + */ +#define GEN_LOWERED_OP(op) \ + static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \ + if (mode_is_float(env->mode)) \ + FP_USED(env->cg); \ + return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \ + } + +#define GEN_LOWERED_x87_OP(op) \ + static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \ + ir_node *new_op; \ + FORCE_x87(env->cg); \ + new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \ + set_ia32_am_support(get_Proj_pred(new_op), ia32_am_None); \ + return new_op; \ + } + +#define GEN_LOWERED_UNOP(op) \ + static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \ + return gen_unop(env, get_unop_op(env->irn), new_rd_ia32_##op); \ + } + +#define GEN_LOWERED_SHIFT_OP(op) \ + static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \ + return gen_shift_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \ + } + +#define GEN_LOWERED_LOAD(op, fp_unit) \ + static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \ + return gen_lowered_Load(env, new_rd_ia32_##op, fp_unit); \ + } + +#define GEN_LOWERED_STORE(op, fp_unit) \ + static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \ + return gen_lowered_Store(env, new_rd_ia32_##op, fp_unit); \ +} + +GEN_LOWERED_OP(AddC) +GEN_LOWERED_OP(Add) +GEN_LOWERED_OP(SubC) +GEN_LOWERED_OP(Sub) +GEN_LOWERED_OP(Mul) +GEN_LOWERED_OP(Eor) +GEN_LOWERED_x87_OP(vfdiv) +GEN_LOWERED_x87_OP(vfmul) +GEN_LOWERED_x87_OP(vfsub) + +GEN_LOWERED_UNOP(Minus) + +GEN_LOWERED_LOAD(vfild, fp_x87) +GEN_LOWERED_LOAD(Load, fp_none) +GEN_LOWERED_STORE(vfist, fp_x87) +GEN_LOWERED_STORE(Store, fp_none) + +/** + * Transforms a l_MulS into a "real" MulS node. + * + * @param env The transformation environment + * @return the created ia32 MulS node + */ +static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env) { + + /* l_MulS is already a mode_T node, so we create the MulS in the normal way */ + /* and then skip the result Proj, because all needed Projs are already there. */ + + ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS); + ir_node *muls = get_Proj_pred(new_op); + + /* MulS cannot have AM for destination */ + if (get_ia32_am_support(muls) != ia32_am_None) + set_ia32_am_support(muls, ia32_am_Source); + + return muls; +} + +GEN_LOWERED_SHIFT_OP(Shl) +GEN_LOWERED_SHIFT_OP(Shr) +GEN_LOWERED_SHIFT_OP(Shrs) + +/** + * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs: + * op1 - target to be shifted + * op2 - contains bits to be shifted into target + * op3 - shift count + * Only op3 can be an immediate. + */ +static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, ir_node *count) { + ir_node *new_op = NULL; + ir_mode *mode = env->mode; + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *nomem = new_NoMem(); + ir_node *imm_op; + tarval *tv; + DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) + + assert(! mode_is_float(mode) && "Shift/Rotate with float not supported"); + + /* Check if immediate optimization is on and */ + /* if it's an operation with immediate. */ + imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, count) : NULL; + + /* Limit imm_op within range imm8 */ + if (imm_op) { + tv = get_ia32_Immop_tarval(imm_op); + + if (tv) { + tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu)); + set_ia32_Immop_tarval(imm_op, tv); + } + else { + imm_op = NULL; + } + } + + /* integer operations */ + if (imm_op) { + /* This is ShiftD with const */ + DB((mod, LEVEL_1, "ShiftD with immediate ...")); + + if (is_ia32_l_ShlD(env->irn)) + new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem); + else + new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem); + set_ia32_Immop_attr(new_op, imm_op); + } + else { + /* This is a normal ShiftD */ + DB((mod, LEVEL_1, "ShiftD binop ...")); + if (is_ia32_l_ShlD(env->irn)) + new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem); + else + new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem); + } + + /* set AM support */ + set_ia32_am_support(new_op, ia32_am_Dest); + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + set_ia32_res_mode(new_op, mode); + set_ia32_emit_cl(new_op); + + return new_rd_Proj(dbg, irg, block, new_op, mode, 0); +} + +static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env) { + return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2)); +} + +static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env) { + return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2)); +} + +/** + * In case SSE Unit is used, the node is transformed into a vfst + xLoad. + */ +static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env) { + ia32_code_gen_t *cg = env->cg; + ir_node *res = NULL; + ir_node *ptr = get_irn_n(env->irn, 0); + ir_node *val = get_irn_n(env->irn, 1); + ir_node *mem = get_irn_n(env->irn, 2); + + if (USE_SSE2(cg)) { + ir_node *noreg = ia32_new_NoReg_gp(cg); + + /* Store x87 -> MEM */ + res = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem); + set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn)); + set_ia32_use_frame(res); + set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn)); + set_ia32_am_support(res, ia32_am_Dest); + set_ia32_am_flavour(res, ia32_B); + res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_vfst_M); + + /* Load MEM -> SSE */ + res = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, res); + set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn)); + set_ia32_use_frame(res); + set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn)); + set_ia32_am_support(res, ia32_am_Source); + set_ia32_am_flavour(res, ia32_B); + res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_xLoad_res); + } + else { + /* SSE unit is not used -> skip this node. */ + int i; + + edges_reroute(env->irn, val, env->irg); + for (i = get_irn_arity(env->irn) - 1; i >= 0; i--) + set_irn_n(env->irn, i, get_irg_bad(env->irg)); + } + + return res; +} + +/** + * In case SSE Unit is used, the node is transformed into a xStore + vfld. + */ +static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env) { + ia32_code_gen_t *cg = env->cg; + ir_node *res = NULL; + ir_node *ptr = get_irn_n(env->irn, 0); + ir_node *val = get_irn_n(env->irn, 1); + ir_node *mem = get_irn_n(env->irn, 2); + + if (USE_SSE2(cg)) { + ir_node *noreg = ia32_new_NoReg_gp(cg); + + /* Store SSE -> MEM */ + res = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem); + set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn)); + set_ia32_use_frame(res); + set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn)); + set_ia32_am_support(res, ia32_am_Dest); + set_ia32_am_flavour(res, ia32_B); + res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_xStore_M); + + /* Load MEM -> x87 */ + res = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem); + set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn)); + set_ia32_use_frame(res); + set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn)); + set_ia32_am_support(res, ia32_am_Source); + set_ia32_am_flavour(res, ia32_B); + res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_vfld_res); + } + else { + /* SSE unit is not used -> skip this node. */ + int i; + + edges_reroute(env->irn, val, env->irg); + for (i = get_irn_arity(env->irn) - 1; i >= 0; i--) + set_irn_n(env->irn, i, get_irg_bad(env->irg)); + } + + return res; +} /********************************************************* * _ _ _ @@ -2344,6 +2706,9 @@ void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) { am_flav = get_ia32_am_flavour(irn); + if (get_ia32_am_sc(irn)) + return; + /* only some LEAs can be transformed to an Add */ if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI) return; @@ -2498,6 +2863,30 @@ void ia32_register_transformers(void) { GEN(Mux); GEN(Psi); + /* transform ops from intrinsic lowering */ + GEN(ia32_l_Add); + GEN(ia32_l_AddC); + GEN(ia32_l_Sub); + GEN(ia32_l_SubC); + GEN(ia32_l_Minus); + GEN(ia32_l_Mul); + GEN(ia32_l_Eor); + GEN(ia32_l_MulS); + GEN(ia32_l_Shl); + GEN(ia32_l_Shr); + GEN(ia32_l_Shrs); + GEN(ia32_l_ShlD); + GEN(ia32_l_ShrD); + GEN(ia32_l_vfdiv); + GEN(ia32_l_vfmul); + GEN(ia32_l_vfsub); + GEN(ia32_l_vfild); + GEN(ia32_l_Load); + GEN(ia32_l_vfist); + GEN(ia32_l_Store); + GEN(ia32_l_X87toSSE); + GEN(ia32_l_SSEtoX87); + IGN(Call); IGN(Alloc); @@ -2609,7 +2998,12 @@ void ia32_transform_node(ir_node *node, void *env) { static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) { int i; + /* if the mode is target mode, we have already seen this part of the tree */ + if (get_irn_mode(cond) == mode) + return; + assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b"); + set_irn_mode(cond, mode); for (i = get_irn_arity(cond) - 1; i >= 0; i--) { @@ -2687,8 +3081,8 @@ static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source); } - /* exchange with old compare */ - exchange(in, new_op); + /* the the new compare as in */ + set_irn_n(cond, i, new_op); } else { /* another complex condition */