X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=9f789d9f20ff773c3a909b7eb0ad57d58bccb129;hb=09480efeccb17e980766b3ca092bb0f6ebc0a44f;hp=2284a3f11f0eb40882136790f9a34da9e49357bc;hpb=82ae33d5f06da493af71ebed0e9e22cd9d23e6fd;p=libfirm

diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c
index 2284a3f11..9f789d9f2 100644
--- a/ir/be/ia32/ia32_transform.c
+++ b/ir/be/ia32/ia32_transform.c
@@ -246,7 +246,11 @@ static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2,
 
 	/* Check if immediate optimization is on and */
 	/* if it's an operation with immediate.      */
-	if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
+	/* MulS and Mulh don't support immediates    */
+	if (! (env->cg->opt & IA32_OPT_IMMOPS) ||
+		func == new_rd_ia32_Mulh           ||
+		func == new_rd_ia32_MulS)
+	{
 		expr_op = op1;
 		imm_op  = NULL;
 	}
@@ -963,11 +967,11 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir
 
 		if (get_irn_op(irn) == op_Div) {
 			set_Proj_proj(proj, pn_DivMod_res_div);
-			in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
+			in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_mod);
 		}
 		else {
 			set_Proj_proj(proj, pn_DivMod_res_mod);
-			in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
+			in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_div);
 		}
 
 		be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
@@ -975,7 +979,7 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir
 
 	SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
 
-	set_ia32_res_mode(res, mode_Is);
+	set_ia32_res_mode(res, mode);
 
 	return res;
 }
@@ -1301,12 +1305,12 @@ static ir_node *gen_Abs(ia32_transform_env_t *env) {
  * @return the created ia32 Load node
  */
 static ir_node *gen_Load(ia32_transform_env_t *env) {
-	ir_node    *node  = env->irn;
-	ir_node    *noreg = ia32_new_NoReg_gp(env->cg);
-	ir_node    *ptr   = get_Load_ptr(node);
-	ir_node    *lptr  = ptr;
-	ir_mode    *mode  = get_Load_mode(node);
-	int        is_imm = 0;
+	ir_node *node  = env->irn;
+	ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+	ir_node *ptr   = get_Load_ptr(node);
+	ir_node *lptr  = ptr;
+	ir_mode *mode  = get_Load_mode(node);
+	int     is_imm = 0;
 	ir_node *new_op;
 	ia32_am_flavour_t am_flav = ia32_B;
 
@@ -1344,6 +1348,16 @@ static ir_node *gen_Load(ia32_transform_env_t *env) {
 	set_ia32_am_flavour(new_op, am_flav);
 	set_ia32_ls_mode(new_op, mode);
 
+	/*
+		check for special case: the loaded value might not be used (optimized, volatile, ...)
+		we add a Proj + Keep for volatile loads and ignore all other cases
+	*/
+	if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
+		/* add a result proj and a Keep to produce a pseudo use */
+		ir_node *proj = new_r_Proj(env->irg, env->block, new_op, mode, pn_ia32_Load_res);
+		be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), env->irg, env->block, 1, &proj);
+	}
+
 	SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
 
 	return new_op;
@@ -1364,7 +1378,7 @@ static ir_node *gen_Store(ia32_transform_env_t *env) {
 	ir_node *ptr     = get_Store_ptr(node);
 	ir_node *sptr    = ptr;
 	ir_node *mem     = get_Store_mem(node);
-	ir_mode *mode    = get_irn_mode(val);
+	ir_mode *mode    = get_irn_link(node);
 	ir_node *sval    = val;
 	int      is_imm  = 0;
 	ir_node *new_op;
@@ -1428,7 +1442,7 @@ static ir_node *gen_Store(ia32_transform_env_t *env) {
 	set_ia32_am_support(new_op, ia32_am_Dest);
 	set_ia32_op_type(new_op, ia32_AddrModeD);
 	set_ia32_am_flavour(new_op, am_flav);
-	set_ia32_ls_mode(new_op, get_irn_mode(val));
+	set_ia32_ls_mode(new_op, mode);
 	set_ia32_immop_type(new_op, immop);
 
 	SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
@@ -1473,7 +1487,9 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) {
 			pn_Cmp pnc = get_Proj_proj(sel);
 
 			if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
-				if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
+				if (get_ia32_op_type(cnst) == ia32_Const &&
+					classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
+				{
 					/* a Cmp A =/!= 0 */
 					ir_node    *op1  = expr;
 					ir_node    *op2  = expr;
@@ -1757,7 +1773,7 @@ static ir_node *gen_Psi(ia32_transform_env_t *env) {
 				/* second case for SETcc: default is 1, set to 0 iff condition is true: */
 				/*                        we invert condition and set default to 0      */
 				new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
-				set_ia32_pncode(new_op, get_negated_pnc(pnc, mode));
+				set_ia32_pncode(new_op, get_inversed_pnc(pnc));
 			}
 			else {
 				/* otherwise: use CMOVcc */
@@ -1779,7 +1795,7 @@ static ir_node *gen_Psi(ia32_transform_env_t *env) {
 				/* second case for SETcc: default is 1, set to 0 iff condition is true: */
 				/*                        we invert condition and set default to 0      */
 				new_op = gen_binop(env, cmp_a, cmp_b, set_func);
-				set_ia32_pncode(get_Proj_pred(new_op), get_negated_pnc(pnc, mode));
+				set_ia32_pncode(get_Proj_pred(new_op), get_inversed_pnc(pnc));
 				set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
 			}
 			else {
@@ -1851,7 +1867,7 @@ static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
 	set_ia32_am_support(fist, ia32_am_Dest);
 	set_ia32_op_type(fist, ia32_AddrModeD);
 	set_ia32_am_flavour(fist, ia32_B);
-	set_ia32_ls_mode(fist, mode_E);
+	set_ia32_ls_mode(fist, mode_F);
 
 	mem  = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
 
@@ -1920,9 +1936,9 @@ static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
 	set_ia32_am_support(fild, ia32_am_Source);
 	set_ia32_op_type(fild, ia32_AddrModeS);
 	set_ia32_am_flavour(fild, ia32_B);
-	set_ia32_ls_mode(fild, mode_E);
+	set_ia32_ls_mode(fild, mode_F);
 
-	return new_r_Proj(irg, block, fild, mode_E, 0);
+	return new_r_Proj(irg, block, fild, mode_F, 0);
 }
 
 /**
@@ -2285,9 +2301,10 @@ static ir_node *gen_lowered_Load(ia32_transform_env_t *env, construct_load_func
 			FORCE_x87(env->cg);
 	}
 
-	new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
+	new_op  = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
+	am_offs = get_ia32_am_offs(node);
 
-	if (am_offs = get_ia32_am_offs(node)) {
+	if (am_offs) {
 		am_flav |= ia32_O;
 		add_ia32_am_offs(new_op, am_offs);
 	}
@@ -2416,7 +2433,13 @@ static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env) {
 	/* and then skip the result Proj, because all needed Projs are already there. */
 
 	ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS);
-	return get_Proj_pred(new_op);
+	ir_node *muls   = get_Proj_pred(new_op);
+
+	/* MulS cannot have AM for destination */
+	if (get_ia32_am_support(muls) != ia32_am_None)
+		set_ia32_am_support(muls, ia32_am_Source);
+
+	return muls;
 }
 
 GEN_LOWERED_SHIFT_OP(Shl)