X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=90194922d2476e8294e17239495a7021cefe7049;hb=7f81d2a2c9293cf34e4db08fc402a5c33ef919eb;hp=005311f67dc20295beb949a9d50561bc45ee17c9;hpb=87965f5c94d561cb15233b80711123f6edc80b30;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 005311f67..90194922d 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -1,10 +1,30 @@ +/* + * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. + * + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. + * + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + /** - * This file implements the IR transformation from firm into ia32-Firm. - * @author Christian Wuerdig - * $Id$ + * @file + * @brief This file implements the IR transformation from firm into ia32-Firm. + * @author Christian Wuerdig, Matthias Braun + * @version $Id$ */ #ifdef HAVE_CONFIG_H -#include +#include "config.h" #endif #include @@ -25,9 +45,7 @@ #include "irprintf.h" #include "debug.h" #include "irdom.h" -#include "type.h" -#include "entity.h" -#include "archop.h" /* we need this for Min and Max nodes */ +#include "archop.h" #include "error.h" #include "cgana.h" #include "irouts.h" @@ -38,6 +56,7 @@ #include "../besched.h" #include "../beabi.h" #include "../beutil.h" +#include "../beirg_t.h" #include "bearch_ia32_t.h" #include "ia32_nodes_attr.h" @@ -65,6 +84,11 @@ #define ENT_SFP_ABS "IA32_SFP_ABS" #define ENT_DFP_ABS "IA32_DFP_ABS" +#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode) +#define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode) + +DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) + typedef struct ia32_transform_env_t { ir_graph *irg; /**< The irg, the node should be created in */ ia32_code_gen_t *cg; /**< The code generator */ @@ -73,9 +97,10 @@ typedef struct ia32_transform_env_t { pdeq *worklist; /**< worklist of nodes that still need to be transformed */ ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/ - DEBUG_ONLY(firm_dbg_module_t *mod;) /**< The firm debugger */ } ia32_transform_env_t; +static ia32_transform_env_t env; + extern ir_op *get_op_Mulh(void); typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, @@ -86,7 +111,7 @@ typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *op, ir_node *mem); -typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node); +typedef ir_node *(transform_func)(ir_node *node); /**************************************************************************************************** * _ _ __ _ _ @@ -98,10 +123,17 @@ typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node); * ****************************************************************************************************/ -static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node); -static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node); -static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node, - ir_node *new_node); +static ir_node *duplicate_node(ir_node *node); +static ir_node *transform_node(ir_node *node); +static void duplicate_deps(ir_node *old_node, ir_node *new_node); + +static INLINE int mode_needs_gp_reg(ir_mode *mode) +{ + if(mode == mode_fpcw) + return 0; + + return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode); +} static INLINE void set_new_node(ir_node *old_node, ir_node *new_node) { @@ -225,79 +257,78 @@ static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst) current_ir_graph = rem; pmap_insert(cg->isa->tv_ent, tv, res); - } - else + } else { res = e->value; + } + return res; } /** * Transforms a Const. - * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Const node - * @param mode mode of the Const - * @return the created ia32 Const node */ -static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); +static ir_node *gen_Const(ir_node *node) { + ir_graph *irg = env.irg; + ir_node *block = transform_node(get_nodes_block(node)); + dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); - ir_node *block = transform_node(env, get_nodes_block(node)); if (mode_is_float(mode)) { - ir_node *res = NULL; + ir_node *res = NULL; + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *nomem = new_NoMem(); + ir_node *load; ir_entity *floatent; - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *nomem = new_NoMem(); - ir_node *load; - FP_USED(env->cg); - if (! USE_SSE2(env->cg)) { + FP_USED(env.cg); + if (! USE_SSE2(env.cg)) { cnst_classify_t clss = classify_Const(node); if (clss == CNST_NULL) { - load = new_rd_ia32_vfldz(dbg, irg, block); - res = load; + load = new_rd_ia32_vfldz(dbgi, irg, block); + res = load; } else if (clss == CNST_ONE) { - load = new_rd_ia32_vfld1(dbg, irg, block); - res = load; + load = new_rd_ia32_vfld1(dbgi, irg, block); + res = load; } else { - floatent = get_entity_for_tv(env->cg, node); + floatent = get_entity_for_tv(env.cg, node); - load = new_rd_ia32_vfld(dbg, irg, block, noreg, noreg, nomem); + load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem); set_ia32_am_support(load, ia32_am_Source); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_flavour(load, ia32_am_N); - set_ia32_am_sc(load, ia32_get_ent_ident(floatent)); - res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res); + set_ia32_am_sc(load, floatent); + res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res); } + set_ia32_ls_mode(load, mode); } else { - floatent = get_entity_for_tv(env->cg, node); + floatent = get_entity_for_tv(env.cg, node); - load = new_rd_ia32_xLoad(dbg, irg, block, noreg, noreg, nomem); + load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem); set_ia32_am_support(load, ia32_am_Source); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_flavour(load, ia32_am_N); - set_ia32_am_sc(load, ia32_get_ent_ident(floatent)); - res = new_r_Proj(irg, block, load, mode_E, pn_ia32_xLoad_res); + set_ia32_am_sc(load, floatent); + set_ia32_ls_mode(load, mode); + + res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res); } - set_ia32_ls_mode(load, mode); - SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env.cg, node)); /* Const Nodes before the initial IncSP are a bad idea, because - * they could be spilled and we have no SP ready at that point yet + * they could be spilled and we have no SP ready at that point yet. + * So add a dependency to the initial frame pointer calculation to + * avoid that situation. */ if (get_irg_start_block(irg) == block) { add_irn_dep(load, get_irg_frame(irg)); } - SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env.cg, node)); return res; } else { - ir_node *cnst = new_rd_ia32_Const(dbg, irg, block); + ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block); /* see above */ if (get_irg_start_block(irg) == block) { @@ -305,7 +336,7 @@ static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) { } set_ia32_Const_attr(cnst, node); - SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env.cg, node)); return cnst; } @@ -315,29 +346,23 @@ static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) { /** * Transforms a SymConst. - * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir SymConst node - * @param mode mode of the SymConst - * @return the created ia32 Const node */ -static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); +static ir_node *gen_SymConst(ir_node *node) { + ir_graph *irg = env.irg; + ir_node *block = transform_node(get_nodes_block(node)); + dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); - ir_node *block = transform_node(env, get_nodes_block(node)); ir_node *cnst; if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) - cnst = new_rd_ia32_xConst(dbg, irg, block); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) + cnst = new_rd_ia32_xConst(dbgi, irg, block); else - cnst = new_rd_ia32_vfConst(dbg, irg, block); + cnst = new_rd_ia32_vfConst(dbgi, irg, block); set_ia32_ls_mode(cnst, mode); } else { - cnst = new_rd_ia32_Const(dbg, irg, block); + cnst = new_rd_ia32_Const(dbgi, irg, block); } /* Const Nodes before the initial IncSP are a bad idea, because @@ -348,7 +373,7 @@ static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) { } set_ia32_Const_attr(cnst, node); - SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env.cg, node)); return cnst; } @@ -356,19 +381,19 @@ static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) { /** * SSE convert of an integer node into a floating point node. */ -static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, +static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *in, ir_node *old_node, ir_mode *tgt_mode) { - ir_node *noreg = ia32_new_NoReg_gp(cg); - ir_node *nomem = new_rd_NoMem(irg); + ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *nomem = new_rd_NoMem(irg); ir_node *old_pred = get_Cmp_left(old_node); - ir_mode *in_mode = get_irn_mode(old_pred); - int in_bits = get_mode_size_bits(in_mode); + ir_mode *in_mode = get_irn_mode(old_pred); + int in_bits = get_mode_size_bits(in_mode); + ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem); - ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem); set_ia32_ls_mode(conv, tgt_mode); - if(in_bits == 32) { + if (in_bits == 32) { set_ia32_am_support(conv, ia32_am_Source); } SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node)); @@ -377,25 +402,25 @@ static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, } /** -* SSE convert of an float node into a double node. -*/ -static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg, + * SSE convert of an float node into a double node. + */ +static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *in, ir_node *old_node) { ir_node *noreg = ia32_new_NoReg_gp(cg); ir_node *nomem = new_rd_NoMem(irg); + ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem); - ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem); set_ia32_am_support(conv, ia32_am_Source); - set_ia32_ls_mode(conv, mode_E); + set_ia32_ls_mode(conv, mode_xmm); SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node)); return conv; } /* Generates an entity for a known FP const (used for FP Neg + Abs) */ -ident *ia32_gen_fp_known_const(ia32_known_const_t kct) { +ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) { static const struct { const char *tp_name; const char *ent_name; @@ -421,8 +446,8 @@ ident *ia32_gen_fp_known_const(ia32_known_const_t kct) { tp_name = names[kct].tp_name; cnst_str = names[kct].cnst_str; - //mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu; - mode = mode_LLu; + mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu; + //mode = mode_xmm; tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode); tp = new_type_primitive(new_id_from_str(tp_name), mode); ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp); @@ -445,7 +470,7 @@ ident *ia32_gen_fp_known_const(ia32_known_const_t kct) { ent_cache[kct] = ent; } - return get_entity_ident(ent_cache[kct]); + return ent_cache[kct]; } #ifndef NDEBUG @@ -463,9 +488,11 @@ const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) { /* determine if one operator is an Imm */ static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) { - if (op1) + if (op1) { return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL); - else return is_ia32_Cnst(op2) ? op2 : NULL; + } else { + return is_ia32_Cnst(op2) ? op2 : NULL; + } } /* determine if one operator is not an Imm */ @@ -473,25 +500,25 @@ static ir_node *get_expr_op(ir_node *op1, ir_node *op2) { return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL); } -static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) { +static void fold_immediate(ir_node *node, int in1, int in2) { ir_node *left; ir_node *right; - if(! (env->cg->opt & IA32_OPT_IMMOPS)) + if (!(env.cg->opt & IA32_OPT_IMMOPS)) return; left = get_irn_n(node, in1); right = get_irn_n(node, in2); - if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) { + if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) { /* we can only set right operand to immediate */ if(!is_ia32_commutative(node)) return; /* exchange left/right */ set_irn_n(node, in1, right); - set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2)); + set_irn_n(node, in2, ia32_get_admissible_noreg(env.cg, node, in2)); copy_ia32_Immop_attr(node, left); } else if(is_ia32_Cnst(right)) { - set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2)); + set_irn_n(node, in2, ia32_get_admissible_noreg(env.cg, node, in2)); copy_ia32_Immop_attr(node, right); } else { return; @@ -503,36 +530,35 @@ static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, in /** * Construct a standard binary operation, set AM and immediate if required. * - * @param env The transformation environment * @param op1 The first operand * @param op2 The second operand * @param func The node constructor function * @return The constructed ia32 node. */ -static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node, - ir_node *op1, ir_node *op2, - construct_binop_func *func) { +static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2, + construct_binop_func *func) +{ + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *new_op1 = transform_node(op1); + ir_node *new_op2 = transform_node(op2); ir_node *new_node = NULL; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg); ir_node *nomem = new_NoMem(); - ir_node *new_op1 = transform_node(env, op1); - ir_node *new_op2 = transform_node(env, op2); - new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem); - if(func == new_rd_ia32_IMul) { + new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem); + if (func == new_rd_ia32_IMul) { set_ia32_am_support(new_node, ia32_am_Source); } else { set_ia32_am_support(new_node, ia32_am_Full); } - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env.cg, node)); if (is_op_commutative(get_irn_op(node))) { set_ia32_commutative(new_node); } - fold_immediate(env, new_node, 2, 3); + fold_immediate(new_node, 2, 3); return new_node; } @@ -540,36 +566,34 @@ static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node, /** * Construct a standard binary operation, set AM and immediate if required. * - * @param env The transformation environment * @param op1 The first operand * @param op2 The second operand * @param func The node constructor function * @return The constructed ia32 node. */ -static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node, - ir_node *op1, ir_node *op2, +static ir_node *gen_binop_float(ir_node *node, ir_node *op1, ir_node *op2, construct_binop_func *func) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *new_op1 = transform_node(op1); + ir_node *new_op2 = transform_node(op2); ir_node *new_node = NULL; - dbg_info *dbg = get_irn_dbg_info(node); - ir_graph *irg = env->irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_graph *irg = env.irg; ir_mode *mode = get_irn_mode(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg); + ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg); ir_node *nomem = new_NoMem(); - ir_node *new_op1 = transform_node(env, op1); - ir_node *new_op2 = transform_node(env, op2); - new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem); + new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem); set_ia32_am_support(new_node, ia32_am_Source); if (is_op_commutative(get_irn_op(node))) { set_ia32_commutative(new_node); } - if (USE_SSE2(env->cg)) { + if (USE_SSE2(env.cg)) { set_ia32_ls_mode(new_node, mode); } - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env.cg, node)); return new_node; } @@ -578,34 +602,32 @@ static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node, /** * Construct a shift/rotate binary operation, sets AM and immediate if required. * - * @param env The transformation environment * @param op1 The first operand * @param op2 The second operand * @param func The node constructor function * @return The constructed ia32 node. */ -static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node, - ir_node *op1, ir_node *op2, - construct_binop_func *func) { - ir_node *new_op = NULL; - dbg_info *dbg = get_irn_dbg_info(node); - ir_graph *irg = env->irg; - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *nomem = new_NoMem(); - ir_node *expr_op; - ir_node *imm_op; - DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) - ir_node *new_op1 = transform_node(env, op1); - ir_node *new_op2 = transform_node(env, op2); - tarval *tv; +static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, + construct_binop_func *func) +{ + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *new_op1 = transform_node(op1); + ir_node *new_op2 = transform_node(op2); + ir_node *new_op = NULL; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_graph *irg = env.irg; + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *nomem = new_NoMem(); + ir_node *expr_op; + ir_node *imm_op; + tarval *tv; assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported"); /* Check if immediate optimization is on and */ /* if it's an operation with immediate. */ - imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL; + imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL; expr_op = get_expr_op(new_op1, new_op2); assert((expr_op || imm_op) && "invalid operands"); @@ -631,20 +653,20 @@ static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node, /* integer operations */ if (imm_op) { /* This is shift/rot with const */ - DB((mod, LEVEL_1, "Shift/Rot with immediate ...")); + DB((dbg, LEVEL_1, "Shift/Rot with immediate ...")); - new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem); + new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem); copy_ia32_Immop_attr(new_op, imm_op); } else { /* This is a normal shift/rot */ - DB((mod, LEVEL_1, "Shift/Rot binop ...")); - new_op = func(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem); + DB((dbg, LEVEL_1, "Shift/Rot binop ...")); + new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem); } /* set AM support */ set_ia32_am_support(new_op, ia32_am_Dest); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); set_ia32_emit_cl(new_op); @@ -655,27 +677,25 @@ static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node, /** * Construct a standard unary operation, set AM and immediate if required. * - * @param env The transformation environment * @param op The operand * @param func The node constructor function * @return The constructed ia32 node. */ -static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op, - construct_unop_func *func) { - ir_node *new_node = NULL; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *nomem = new_NoMem(); - ir_node *new_op = transform_node(env, op); - DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) - - new_node = func(dbg, irg, block, noreg, noreg, new_op, nomem); - DB((mod, LEVEL_1, "INT unop ...")); +static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func) +{ + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *new_op = transform_node(op); + ir_node *new_node = NULL; + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *nomem = new_NoMem(); + + new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem); + DB((dbg, LEVEL_1, "INT unop ...")); set_ia32_am_support(new_node, ia32_am_Dest); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env.cg, node)); return new_node; } @@ -684,40 +704,39 @@ static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op, /** * Creates an ia32 Add. * - * @param env The transformation environment * @return the created ia32 Add node */ -static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) { - ir_node *new_op = NULL; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *nomem = new_NoMem(); +static ir_node *gen_Add(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *op1 = get_Add_left(node); + ir_node *new_op1 = transform_node(op1); + ir_node *op2 = get_Add_right(node); + ir_node *new_op2 = transform_node(op2); + ir_node *new_op = NULL; + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *nomem = new_NoMem(); ir_node *expr_op, *imm_op; - ir_node *op1 = get_Add_left(node); - ir_node *op2 = get_Add_right(node); - ir_node *new_op1 = transform_node(env, op1); - ir_node *new_op2 = transform_node(env, op2); /* Check if immediate optimization is on and */ /* if it's an operation with immediate. */ - imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL; + imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL; expr_op = get_expr_op(new_op1, new_op2); assert((expr_op || imm_op) && "invalid operands"); if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) - return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) + return gen_binop_float(node, op1, op2, new_rd_ia32_xAdd); else - return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd); + return gen_binop_float(node, op1, op2, new_rd_ia32_vfadd); } /* integer ADD */ - if (!expr_op) { + if (! expr_op) { ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1); ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2); @@ -731,7 +750,7 @@ static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) { if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) { /* this is the 2nd case */ - new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg); + new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg); set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2)); set_ia32_am_flavour(new_op, ia32_am_OB); set_ia32_am_support(new_op, ia32_am_Source); @@ -742,7 +761,8 @@ static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) { tarval *tv = get_ia32_Immop_tarval(new_op2); long offs = get_tarval_long(tv); - new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg); + new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg); + add_irn_dep(new_op, get_irg_frame(irg)); DBG_OPT_LEA3(new_op1, new_op2, node, new_op); set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1)); @@ -754,7 +774,8 @@ static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) { tarval *tv = get_ia32_Immop_tarval(new_op1); long offs = get_tarval_long(tv); - new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg); + new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg); + add_irn_dep(new_op, get_irg_frame(irg)); DBG_OPT_LEA3(new_op1, new_op2, node, new_op); add_ia32_am_offs_int(new_op, offs); @@ -769,15 +790,15 @@ static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) { DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node)); - new_op = new_rd_ia32_Const(dbg, irg, block); + new_op = new_rd_ia32_Const(dbgi, irg, block); set_ia32_Const_tarval(new_op, restv); DBG_OPT_LEA3(new_op1, new_op2, node, new_op); } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } else if (imm_op) { - if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) { + if ((env.cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) { tarval_classification_t class_tv, class_negtv; tarval *tv = get_ia32_Immop_tarval(imm_op); @@ -786,53 +807,53 @@ static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) { class_negtv = classify_tarval(tarval_neg(tv)); if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */ - DB((env->mod, LEVEL_2, "Add(1) to Inc ... ")); - new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + DB((dbg, LEVEL_2, "Add(1) to Inc ... ")); + new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */ - DB((env->mod, LEVEL_2, "Add(-1) to Dec ... ")); - new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + DB((dbg, LEVEL_2, "Add(-1) to Dec ... ")); + new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } } } /* This is a normal add */ - new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem); + new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem); /* set AM support */ set_ia32_am_support(new_op, ia32_am_Full); set_ia32_commutative(new_op); - fold_immediate(env, new_op, 2, 3); + fold_immediate(new_op, 2, 3); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } #if 0 -static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); +static ir_node *create_ia32_Mul(ir_node *node) { + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = transform_node(get_nodes_block(node)); ir_node *op1 = get_Mul_left(node); ir_node *op2 = get_Mul_right(node); - ir_node *new_op1 = transform_node(env, op1); - ir_node *new_op2 = transform_node(env, op2); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *new_op1 = transform_node(op1); + ir_node *new_op2 = transform_node(op2); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); ir_node *proj_EAX, *proj_EDX, *res; ir_node *in[1]; - res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem()); + res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem()); set_ia32_commutative(res); set_ia32_am_support(res, ia32_am_Source); /* imediates are not supported, so no fold_immediate */ - proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX); - proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX); + proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX); + proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX); /* keep EAX */ in[0] = proj_EDX; @@ -840,32 +861,33 @@ static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) { return proj_EAX; } -#endif +#endif /* if 0 */ /** * Creates an ia32 Mul. * - * @param env The transformation environment * @return the created ia32 Mul node */ -static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) { - ir_node *op1 = get_Mul_left(node); - ir_node *op2 = get_Mul_right(node); +static ir_node *gen_Mul(ir_node *node) { + ir_node *op1 = get_Mul_left(node); + ir_node *op2 = get_Mul_right(node); ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) - return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) + return gen_binop_float(node, op1, op2, new_rd_ia32_xMul); else - return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul); + return gen_binop_float(node, op1, op2, new_rd_ia32_vfmul); } - // for the lower 32bit of the result it doesn't matter whether we use - // signed or unsigned multiplication so we use IMul as it has fewer - // constraints - return gen_binop(env, node, op1, op2, new_rd_ia32_IMul); + /* + for the lower 32bit of the result it doesn't matter whether we use + signed or unsigned multiplication so we use IMul as it has fewer + constraints + */ + return gen_binop(node, op1, op2, new_rd_ia32_IMul); } /** @@ -873,27 +895,26 @@ static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) { * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of * this result while Mul returns the lower 32 bit. * - * @param env The transformation environment * @return the created ia32 Mulh node */ -static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *op1 = get_irn_n(node, 0); - ir_node *op2 = get_irn_n(node, 1); - ir_node *new_op1 = transform_node(env, op1); - ir_node *new_op2 = transform_node(env, op2); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *proj_EAX, *proj_EDX, *res; - ir_mode *mode = get_irn_mode(node); - ir_node *in[1]; +static ir_node *gen_Mulh(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *op1 = get_irn_n(node, 0); + ir_node *new_op1 = transform_node(op1); + ir_node *op2 = get_irn_n(node, 1); + ir_node *new_op2 = transform_node(op2); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_mode *mode = get_irn_mode(node); + ir_node *proj_EAX, *proj_EDX, *res; + ir_node *in[1]; assert(!mode_is_float(mode) && "Mulh with float not supported"); - if(mode_is_signed(mode)) { - res = new_rd_ia32_IMul1OP(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem()); + if (mode_is_signed(mode)) { + res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem()); } else { - res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem()); + res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem()); } set_ia32_commutative(res); @@ -901,8 +922,8 @@ static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) { set_ia32_am_support(res, ia32_am_Source); - proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX); - proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX); + proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX); + proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX); /* keep EAX */ in[0] = proj_EAX; @@ -916,15 +937,14 @@ static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) { /** * Creates an ia32 And. * - * @param env The transformation environment * @return The created ia32 And node */ -static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) { +static ir_node *gen_And(ir_node *node) { ir_node *op1 = get_And_left(node); ir_node *op2 = get_And_right(node); assert (! mode_is_float(get_irn_mode(node))); - return gen_binop(env, node, op1, op2, new_rd_ia32_And); + return gen_binop(node, op1, op2, new_rd_ia32_And); } @@ -932,15 +952,14 @@ static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) { /** * Creates an ia32 Or. * - * @param env The transformation environment * @return The created ia32 Or node */ -static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) { +static ir_node *gen_Or(ir_node *node) { ir_node *op1 = get_Or_left(node); ir_node *op2 = get_Or_right(node); assert (! mode_is_float(get_irn_mode(node))); - return gen_binop(env, node, op1, op2, new_rd_ia32_Or); + return gen_binop(node, op1, op2, new_rd_ia32_Or); } @@ -948,16 +967,14 @@ static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) { /** * Creates an ia32 Eor. * - * @param env The transformation environment * @return The created ia32 Eor node */ -static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) { +static ir_node *gen_Eor(ir_node *node) { ir_node *op1 = get_Eor_left(node); ir_node *op2 = get_Eor_right(node); - ir_mode *mode = get_irn_mode(node); - assert(! mode_is_float(mode)); - return gen_binop(env, node, op1, op2, new_rd_ia32_Xor); + assert(! mode_is_float(get_irn_mode(node))); + return gen_binop(node, op1, op2, new_rd_ia32_Xor); } @@ -965,41 +982,39 @@ static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) { /** * Creates an ia32 Max. * - * @param env The transformation environment * @return the created ia32 Max node */ -static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - ir_node *new_op; - ir_mode *mode = get_irn_mode(node); - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *op1 = get_irn_n(node, 0); - ir_node *op2 = get_irn_n(node, 1); - ir_node *new_op1 = transform_node(env, op1); - ir_node *new_op2 = transform_node(env, op2); - ir_mode *op_mode = get_irn_mode(op1); +static ir_node *gen_Max(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *op1 = get_irn_n(node, 0); + ir_node *new_op1 = transform_node(op1); + ir_node *op2 = get_irn_n(node, 1); + ir_node *new_op2 = transform_node(op2); + ir_graph *irg = env.irg; + ir_mode *mode = get_irn_mode(node); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *op_mode = get_irn_mode(op1); + ir_node *new_op; assert(get_mode_size_bits(mode) == 32); if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) - new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax); - else { - assert(0); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { + new_op = gen_binop_float(node, new_op1, new_op2, new_rd_ia32_xMax); + } else { + panic("Can't create Max node"); } - } - else { + } else { long pnc = pn_Cmp_Gt; - if(!mode_is_signed(op_mode)) { + if (! mode_is_signed(op_mode)) { pnc |= ia32_pn_Cmp_Unsigned; } - new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2); + new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2); set_ia32_pncode(new_op, pnc); set_ia32_am_support(new_op, ia32_am_None); } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -1007,41 +1022,39 @@ static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) { /** * Creates an ia32 Min. * - * @param env The transformation environment * @return the created ia32 Min node */ -static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - ir_node *new_op; - ir_mode *mode = get_irn_mode(node); - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *op1 = get_irn_n(node, 0); - ir_node *op2 = get_irn_n(node, 1); - ir_node *new_op1 = transform_node(env, op1); - ir_node *new_op2 = transform_node(env, op2); - ir_mode *op_mode = get_irn_mode(op1); +static ir_node *gen_Min(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *op1 = get_irn_n(node, 0); + ir_node *new_op1 = transform_node(op1); + ir_node *op2 = get_irn_n(node, 1); + ir_node *new_op2 = transform_node(op2); + ir_graph *irg = env.irg; + ir_mode *mode = get_irn_mode(node); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *op_mode = get_irn_mode(op1); + ir_node *new_op; assert(get_mode_size_bits(mode) == 32); if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) - new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin); - else { - assert(0); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { + new_op = gen_binop_float(node, op1, op2, new_rd_ia32_xMin); + } else { + panic("can't create Min node"); } - } - else { + } else { long pnc = pn_Cmp_Lt; - if(!mode_is_signed(op_mode)) { + if (! mode_is_signed(op_mode)) { pnc |= ia32_pn_Cmp_Unsigned; } - new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2); + new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2); set_ia32_pncode(new_op, pnc); set_ia32_am_support(new_op, ia32_am_None); } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -1050,36 +1063,35 @@ static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) { /** * Creates an ia32 Sub. * - * @param env The transformation environment * @return The created ia32 Sub node */ -static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) { - ir_node *new_op = NULL; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *nomem = new_NoMem(); - ir_node *op1 = get_Sub_left(node); - ir_node *op2 = get_Sub_right(node); - ir_node *new_op1 = transform_node(env, op1); - ir_node *new_op2 = transform_node(env, op2); +static ir_node *gen_Sub(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *op1 = get_Sub_left(node); + ir_node *new_op1 = transform_node(op1); + ir_node *op2 = get_Sub_right(node); + ir_node *new_op2 = transform_node(op2); + ir_node *new_op = NULL; + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *nomem = new_NoMem(); ir_node *expr_op, *imm_op; /* Check if immediate optimization is on and */ /* if it's an operation with immediate. */ - imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL; + imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL; expr_op = get_expr_op(new_op1, new_op2); assert((expr_op || imm_op) && "invalid operands"); if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) - return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) + return gen_binop_float(node, op1, op2, new_rd_ia32_xSub); else - return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub); + return gen_binop_float(node, op1, op2, new_rd_ia32_vfsub); } /* integer SUB */ @@ -1096,7 +1108,7 @@ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) { /* linker doesn't support two symconsts */ if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) { /* this is the 2nd case */ - new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg); + new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg); set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2)); set_ia32_am_sc_sign(new_op); set_ia32_am_flavour(new_op, ia32_am_OB); @@ -1106,7 +1118,8 @@ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) { tarval *tv = get_ia32_Immop_tarval(new_op2); long offs = get_tarval_long(tv); - new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg); + new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg); + add_irn_dep(new_op, get_irg_frame(irg)); DBG_OPT_LEA3(op1, op2, node, new_op); set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1)); @@ -1118,7 +1131,8 @@ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) { tarval *tv = get_ia32_Immop_tarval(new_op1); long offs = get_tarval_long(tv); - new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg); + new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg); + add_irn_dep(new_op, get_irg_frame(irg)); DBG_OPT_LEA3(op1, op2, node, new_op); add_ia32_am_offs_int(new_op, offs); @@ -1134,15 +1148,15 @@ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) { DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node)); - new_op = new_rd_ia32_Const(dbg, irg, block); + new_op = new_rd_ia32_Const(dbgi, irg, block); set_ia32_Const_tarval(new_op, restv); DBG_OPT_LEA3(new_op1, new_op2, node, new_op); } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } else if (imm_op) { - if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) { + if ((env.cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) { tarval_classification_t class_tv, class_negtv; tarval *tv = get_ia32_Immop_tarval(imm_op); @@ -1151,28 +1165,28 @@ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) { class_negtv = classify_tarval(tarval_neg(tv)); if (class_tv == TV_CLASSIFY_ONE) { - DB((env->mod, LEVEL_2, "Sub(1) to Dec ... ")); - new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + DB((dbg, LEVEL_2, "Sub(1) to Dec ... ")); + new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { - DB((env->mod, LEVEL_2, "Sub(-1) to Inc ... ")); - new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + DB((dbg, LEVEL_2, "Sub(-1) to Inc ... ")); + new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } } } /* This is a normal sub */ - new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem); + new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem); /* set AM support */ set_ia32_am_support(new_op, ia32_am_Full); - fold_immediate(env, new_op, 2, 3); + fold_immediate(new_op, 2, 3); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -1183,119 +1197,98 @@ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) { * Generates an ia32 DivMod with additional infrastructure for the * register allocator if needed. * - * @param env The transformation environment * @param dividend -no comment- :) * @param divisor -no comment- :) * @param dm_flav flavour_Div/Mod/DivMod * @return The created ia32 DivMod node */ -static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node, - ir_node *dividend, ir_node *divisor, - ia32_op_flavour_t dm_flav) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *block = transform_node(env, get_nodes_block(node)); +static ir_node *generate_DivMod(ir_node *node, ir_node *dividend, + ir_node *divisor, ia32_op_flavour_t dm_flav) +{ + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *new_dividend = transform_node(dividend); + ir_node *new_divisor = transform_node(divisor); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); ir_node *res, *proj_div, *proj_mod; ir_node *edx_node, *cltd; - ir_node *in_keep[1]; + ir_node *in_keep[2]; ir_node *mem, *new_mem; ir_node *projs[pn_DivMod_max]; - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *new_dividend = transform_node(env, dividend); - ir_node *new_divisor = transform_node(env, divisor); + int i, has_exc; ia32_collect_Projs(node, projs, pn_DivMod_max); + proj_div = proj_mod = NULL; + has_exc = 0; switch (dm_flav) { case flavour_Div: mem = get_Div_mem(node); - mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res)); + mode = get_Div_resmode(node); + proj_div = be_get_Proj_for_pn(node, pn_Div_res); + has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL; break; case flavour_Mod: mem = get_Mod_mem(node); - mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res)); + mode = get_Mod_resmode(node); + proj_mod = be_get_Proj_for_pn(node, pn_Mod_res); + has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL; break; case flavour_DivMod: - mem = get_DivMod_mem(node); + mem = get_DivMod_mem(node); + mode = get_DivMod_resmode(node); proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div); proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod); - mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod); + has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL; break; default: - assert(0); + panic("invalid divmod flavour!"); } - new_mem = transform_node(env, mem); + new_mem = transform_node(mem); if (mode_is_signed(mode)) { /* in signed mode, we need to sign extend the dividend */ - cltd = new_rd_ia32_Cltd(dbg, irg, block, new_dividend); - new_dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX); - edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX); + cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend); + new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX); + edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX); } else { - edx_node = new_rd_ia32_Const(dbg, irg, block); - add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi)); + edx_node = new_rd_ia32_Const(dbgi, irg, block); + add_irn_dep(edx_node, be_abi_get_start_barrier(env.cg->birg->abi)); set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu)); } - if(mode_is_signed(mode)) { - res = new_rd_ia32_IDiv(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav); + if (mode_is_signed(mode)) { + res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav); } else { - res = new_rd_ia32_Div(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav); + res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav); } + set_ia32_exc_label(res, has_exc); + /* Matze: code can't handle this at the moment... */ #if 0 /* set AM support */ set_ia32_am_support(res, ia32_am_Source); #endif - set_ia32_n_res(res, 2); - - /* Only one proj is used -> We must add a second proj and */ - /* connect this one to a Keep node to eat up the second */ - /* destroyed register. */ - /* We also renumber the Firm projs into ia32 projs. */ - - switch (get_irn_opcode(node)) { - case iro_Div: - /* add Proj-Keep for mod res */ - in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res); - be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep); - break; - case iro_Mod: - /* add Proj-Keep for div res */ - in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res); - be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep); - break; - case iro_DivMod: - /* check, which Proj-Keep, we need to add */ - proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div); - proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod); - - if (proj_div && proj_mod) { - /* nothing to be done */ - } - else if (! proj_div && ! proj_mod) { - assert(0 && "Missing DivMod result proj"); - } - else if (! proj_div) { - /* We have only mod result: add div res Proj-Keep */ - in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res); - be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep); - } - else { - /* We have only div result: add mod res Proj-Keep */ - in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res); - be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep); - } - break; - default: - assert(0 && "Div, Mod, or DivMod expected."); - break; + /* check, which Proj-Keep, we need to add */ + i = 0; + if (proj_div == NULL) { + /* We have only mod result: add div res Proj-Keep */ + in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res); + ++i; + } + if (proj_mod == NULL) { + /* We have only div result: add mod res Proj-Keep */ + in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res); + ++i; } + if(i > 0) + be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); return res; } @@ -1304,28 +1297,26 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node, /** * Wrapper for generate_DivMod. Sets flavour_Mod. * - * @param env The transformation environment */ -static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) { - return generate_DivMod(env, node, get_Mod_left(node), +static ir_node *gen_Mod(ir_node *node) { + return generate_DivMod(node, get_Mod_left(node), get_Mod_right(node), flavour_Mod); } /** * Wrapper for generate_DivMod. Sets flavour_Div. * - * @param env The transformation environment */ -static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) { - return generate_DivMod(env, node, get_Div_left(node), +static ir_node *gen_Div(ir_node *node) { + return generate_DivMod(node, get_Div_left(node), get_Div_right(node), flavour_Div); } /** * Wrapper for generate_DivMod. Sets flavour_DivMod. */ -static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) { - return generate_DivMod(env, node, get_DivMod_left(node), +static ir_node *gen_DivMod(ir_node *node) { + return generate_DivMod(node, get_DivMod_left(node), get_DivMod_right(node), flavour_DivMod); } @@ -1334,40 +1325,39 @@ static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) { /** * Creates an ia32 floating Div. * - * @param env The transformation environment * @return The created ia32 xDiv node */ -static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *new_op; - ir_node *nomem = new_rd_NoMem(env->irg); - ir_node *op1 = get_Quot_left(node); - ir_node *op2 = get_Quot_right(node); - ir_node *new_op1 = transform_node(env, op1); - ir_node *new_op2 = transform_node(env, op2); - - FP_USED(env->cg); - if (USE_SSE2(env->cg)) { +static ir_node *gen_Quot(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *op1 = get_Quot_left(node); + ir_node *new_op1 = transform_node(op1); + ir_node *op2 = get_Quot_right(node); + ir_node *new_op2 = transform_node(op2); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *nomem = new_rd_NoMem(env.irg); + ir_node *new_op; + + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { ir_mode *mode = get_irn_mode(op1); if (is_ia32_xConst(new_op2)) { - new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, noreg, nomem); + new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem); set_ia32_am_support(new_op, ia32_am_None); copy_ia32_Immop_attr(new_op, new_op2); } else { - new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem); + new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem); // Matze: disabled for now, spillslot coalescer fails //set_ia32_am_support(new_op, ia32_am_Source); } set_ia32_ls_mode(new_op, mode); } else { - new_op = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem); + new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem); // Matze: disabled for now (spillslot coalescer fails) //set_ia32_am_support(new_op, ia32_am_Source); } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -1375,11 +1365,10 @@ static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) { /** * Creates an ia32 Shl. * - * @param env The transformation environment * @return The created ia32 Shl node */ -static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) { - return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node), +static ir_node *gen_Shl(ir_node *node) { + return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node), new_rd_ia32_Shl); } @@ -1388,11 +1377,10 @@ static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) { /** * Creates an ia32 Shr. * - * @param env The transformation environment * @return The created ia32 Shr node */ -static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) { - return gen_shift_binop(env, node, get_Shr_left(node), +static ir_node *gen_Shr(ir_node *node) { + return gen_shift_binop(node, get_Shr_left(node), get_Shr_right(node), new_rd_ia32_Shr); } @@ -1401,11 +1389,10 @@ static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) { /** * Creates an ia32 Sar. * - * @param env The transformation environment * @return The created ia32 Shrs node */ -static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) { - return gen_shift_binop(env, node, get_Shrs_left(node), +static ir_node *gen_Shrs(ir_node *node) { + return gen_shift_binop(node, get_Shrs_left(node), get_Shrs_right(node), new_rd_ia32_Sar); } @@ -1414,14 +1401,13 @@ static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) { /** * Creates an ia32 RotL. * - * @param env The transformation environment * @param op1 The first operator * @param op2 The second operator * @return The created ia32 RotL node */ -static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node, +static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) { - return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol); + return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol); } @@ -1431,14 +1417,13 @@ static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node, * NOTE: There is no RotR with immediate because this would always be a RotL * "imm-mode_size_bits" which can be pre-calculated. * - * @param env The transformation environment * @param op1 The first operator * @param op2 The second operator * @return The created ia32 RotR node */ -static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1, +static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) { - return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror); + return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror); } @@ -1446,10 +1431,9 @@ static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1, /** * Creates an ia32 RotR or RotL (depending on the found pattern). * - * @param env The transformation environment * @return The created ia32 RotL or RotR node */ -static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) { +static ir_node *gen_Rot(ir_node *node) { ir_node *rotate = NULL; ir_node *op1 = get_Rot_left(node); ir_node *op2 = get_Rot_right(node); @@ -1463,22 +1447,22 @@ static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) { ir_node *left = get_Add_left(add); ir_node *right = get_Add_right(add); if (is_Const(right)) { - tarval *tv = get_Const_tarval(right); - ir_mode *mode = get_irn_mode(node); - long bits = get_mode_size_bits(mode); + tarval *tv = get_Const_tarval(right); + ir_mode *mode = get_irn_mode(node); + long bits = get_mode_size_bits(mode); if (get_irn_op(left) == op_Minus && tarval_is_long(tv) && get_tarval_long(tv) == bits) { - DB((env->mod, LEVEL_1, "RotL into RotR ... ")); - rotate = gen_RotR(env, node, op1, get_Minus_op(left)); + DB((dbg, LEVEL_1, "RotL into RotR ... ")); + rotate = gen_RotR(node, op1, get_Minus_op(left)); } } } if (rotate == NULL) { - rotate = gen_RotL(env, node, op1, op2); + rotate = gen_RotL(node, op1, op2); } return rotate; @@ -1489,43 +1473,42 @@ static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) { /** * Transforms a Minus node. * - * @param env The transformation environment * @param op The Minus operand * @return The created ia32 Minus node */ -ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) { - ident *name; - ir_node *res; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_mode *mode = get_irn_mode(node); - int size; +ir_node *gen_Minus_ex(ir_node *node, ir_node *op) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_entity *ent; + ir_node *res; + int size; if (mode_is_float(mode)) { - ir_node *new_op = transform_node(env, op); - FP_USED(env->cg); - if (USE_SSE2(env->cg)) { - ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg); - ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg); + ir_node *new_op = transform_node(op); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { + ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg); + ir_node *noreg_fp = ia32_new_NoReg_fp(env.cg); ir_node *nomem = new_rd_NoMem(irg); - res = new_rd_ia32_xXor(dbg, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem); + res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem); - size = get_mode_size_bits(mode); - name = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN); + size = get_mode_size_bits(mode); + ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN); - set_ia32_am_sc(res, name); + set_ia32_am_sc(res, ent); set_ia32_op_type(res, ia32_AddrModeS); set_ia32_ls_mode(res, mode); } else { - res = new_rd_ia32_vfchs(dbg, irg, block, new_op); + res = new_rd_ia32_vfchs(dbgi, irg, block, new_op); } } else { - res = gen_unop(env, node, op, new_rd_ia32_Neg); + res = gen_unop(node, op, new_rd_ia32_Neg); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); return res; } @@ -1533,26 +1516,23 @@ ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) { /** * Transforms a Minus node. * - * @param env The transformation environment * @return The created ia32 Minus node */ -static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) { - return gen_Minus_ex(env, node, get_Minus_op(node)); +static ir_node *gen_Minus(ir_node *node) { + return gen_Minus_ex(node, get_Minus_op(node)); } /** * Transforms a Not node. * - * @param env The transformation environment * @return The created ia32 Not node */ -static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) { - ir_mode *mode = get_irn_mode(node); +static ir_node *gen_Not(ir_node *node) { ir_node *op = get_Not_op(node); - assert (! mode_is_float(mode)); - return gen_unop(env, node, op, new_rd_ia32_Not); + assert (! mode_is_float(get_irn_mode(node))); + return gen_unop(node, op, new_rd_ia32_Not); } @@ -1560,55 +1540,54 @@ static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) { /** * Transforms an Abs node. * - * @param env The transformation environment * @return The created ia32 Abs node */ -static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) { - ir_node *res, *p_eax, *p_edx; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_mode *mode = get_irn_mode(node); - ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg); - ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg); - ir_node *nomem = new_NoMem(); - ir_node *op = get_Abs_op(node); - ir_node *new_op = transform_node(env, op); +static ir_node *gen_Abs(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *op = get_Abs_op(node); + ir_node *new_op = transform_node(op); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg); + ir_node *noreg_fp = ia32_new_NoReg_fp(env.cg); + ir_node *nomem = new_NoMem(); + ir_node *res, *p_eax, *p_edx; int size; - ident *name; + ir_entity *ent; if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) { - res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { + res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem); - size = get_mode_size_bits(mode); - name = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS); + size = get_mode_size_bits(mode); + ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS); - set_ia32_am_sc(res, name); + set_ia32_am_sc(res, ent); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); set_ia32_op_type(res, ia32_AddrModeS); set_ia32_ls_mode(res, mode); } else { - res = new_rd_ia32_vfabs(dbg, irg, block, new_op); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + res = new_rd_ia32_vfabs(dbgi, irg, block, new_op); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); } } else { - res = new_rd_ia32_Cltd(dbg, irg, block, new_op); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + res = new_rd_ia32_Cltd(dbgi, irg, block, new_op); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); - p_eax = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX); - p_edx = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX); + p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX); + p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX); - res = new_rd_ia32_Xor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); - res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); } return res; @@ -1619,24 +1598,23 @@ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) { /** * Transforms a Load. * - * @param env The transformation environment * @return the created ia32 Load node */ -static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_mode *mode = get_Load_mode(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *ptr = get_Load_ptr(node); - ir_node *new_ptr = transform_node(env, ptr); - ir_node *lptr = new_ptr; - ir_node *mem = get_Load_mem(node); - ir_node *new_mem = transform_node(env, mem); - int is_imm = 0; - ir_node *new_op; +static ir_node *gen_Load(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *ptr = get_Load_ptr(node); + ir_node *new_ptr = transform_node(ptr); + ir_node *mem = get_Load_mem(node); + ir_node *new_mem = transform_node(mem); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_mode *mode = get_Load_mode(node); + ir_node *lptr = new_ptr; + int is_imm = 0; + ir_node *new_op; + ir_node *projs[pn_Load_max]; ia32_am_flavour_t am_flav = ia32_am_B; - ir_node *projs[pn_Load_max]; ia32_collect_Projs(node, projs, pn_Load_max); @@ -1647,7 +1625,7 @@ static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) { if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) { /* add a result proj and a Keep to produce a pseudo use */ ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res); - be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj); + be_new_Keep(arch_get_irn_reg_class(env.cg->arch_env, proj, -1), irg, block, 1, &proj); } /* address might be a constant (symconst or absolute address) */ @@ -1657,14 +1635,14 @@ static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) { } if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) { - new_op = new_rd_ia32_xLoad(dbg, irg, block, lptr, noreg, new_mem); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { + new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem); } else { - new_op = new_rd_ia32_vfld(dbg, irg, block, lptr, noreg, new_mem); + new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem); } } else { - new_op = new_rd_ia32_Load(dbg, irg, block, lptr, noreg, new_mem); + new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem); } /* base is a constant address */ @@ -1686,14 +1664,15 @@ static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) { set_ia32_am_flavour(new_op, am_flav); set_ia32_ls_mode(new_op, mode); - /* make sure we are scheduled behind the intial IncSP/Barrier + /* make sure we are scheduled behind the initial IncSP/Barrier * to avoid spills being placed before it */ - if(block == get_irg_start_block(irg)) { + if (block == get_irg_start_block(irg)) { add_irn_dep(new_op, get_irg_frame(irg)); } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -1703,25 +1682,24 @@ static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) { /** * Transforms a Store. * - * @param env The transformation environment * @return the created ia32 Store node */ -static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *ptr = get_Store_ptr(node); - ir_node *new_ptr = transform_node(env, ptr); - ir_node *sptr = new_ptr; - ir_node *val = get_Store_value(node); - ir_node *new_val = transform_node(env, val); - ir_node *mem = get_Store_mem(node); - ir_node *new_mem = transform_node(env, mem); - ir_mode *mode = get_irn_mode(val); - ir_node *sval = new_val; - int is_imm = 0; - ir_node *new_op; +static ir_node *gen_Store(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *ptr = get_Store_ptr(node); + ir_node *new_ptr = transform_node(ptr); + ir_node *val = get_Store_value(node); + ir_node *new_val = transform_node(val); + ir_node *mem = get_Store_mem(node); + ir_node *new_mem = transform_node(mem); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *sptr = new_ptr; + ir_mode *mode = get_irn_mode(val); + ir_node *sval = new_val; + int is_imm = 0; + ir_node *new_op; ia32_am_flavour_t am_flav = ia32_am_B; if (is_ia32_Const(new_val)) { @@ -1736,16 +1714,16 @@ static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) { } if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) { - new_op = new_rd_ia32_xStore(dbg, irg, block, sptr, noreg, sval, new_mem); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { + new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem); } else { - new_op = new_rd_ia32_vfst(dbg, irg, block, sptr, noreg, sval, new_mem); + new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem); } } else if (get_mode_size_bits(mode) == 8) { - new_op = new_rd_ia32_Store8Bit(dbg, irg, block, sptr, noreg, sval, new_mem); + new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem); } else { - new_op = new_rd_ia32_Store(dbg, irg, block, sptr, noreg, sval, new_mem); + new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem); } /* stored const is an immediate value */ @@ -1773,7 +1751,8 @@ static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) { set_ia32_am_flavour(new_op, am_flav); set_ia32_ls_mode(new_op, mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -1783,27 +1762,26 @@ static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) { /** * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp * - * @param env The transformation environment * @return The transformed node. */ -static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); +static ir_node *gen_Cond(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); ir_node *sel = get_Cond_selector(node); ir_mode *sel_mode = get_irn_mode(sel); ir_node *res = NULL; - ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); ir_node *cnst, *expr; if (is_Proj(sel) && sel_mode == mode_b) { - ir_node *nomem = new_NoMem(); - ir_node *pred = get_Proj_pred(sel); - ir_node *cmp_a = get_Cmp_left(pred); - ir_node *new_cmp_a = transform_node(env, cmp_a); - ir_node *cmp_b = get_Cmp_right(pred); - ir_node *new_cmp_b = transform_node(env, cmp_b); - ir_mode *cmp_mode = get_irn_mode(cmp_a); + ir_node *pred = get_Proj_pred(sel); + ir_node *cmp_a = get_Cmp_left(pred); + ir_node *new_cmp_a = transform_node(cmp_a); + ir_node *cmp_b = get_Cmp_right(pred); + ir_node *new_cmp_b = transform_node(cmp_b); + ir_mode *cmp_mode = get_irn_mode(cmp_a); + ir_node *nomem = new_NoMem(); int pnc = get_Proj_proj(sel); if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) { @@ -1811,7 +1789,7 @@ static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) { } /* check if we can use a CondJmp with immediate */ - cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL; + cnst = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL; expr = get_expr_op(new_cmp_a, new_cmp_b); if (cnst != NULL && expr != NULL) { @@ -1820,7 +1798,7 @@ static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) { pnc = get_inversed_pnc(pnc); } - if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) { + if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) { if (get_ia32_immop_type(cnst) == ia32_ImmConst && classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) { @@ -1836,29 +1814,30 @@ static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) { is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr)); } - res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2); + res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2); set_ia32_pncode(res, pnc); if (is_and) { copy_ia32_Immop_attr(res, expr); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); return res; } } if (mode_is_float(cmp_mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) { - res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { + res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem); set_ia32_ls_mode(res, cmp_mode); } else { assert(0); } } else { - res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem); + assert(get_mode_size_bits(cmp_mode) == 32); + res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem); } copy_ia32_Immop_attr(res, cnst); } @@ -1866,19 +1845,20 @@ static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) { ir_mode *cmp_mode = get_irn_mode(cmp_a); if (mode_is_float(cmp_mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) { - res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { + res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem); set_ia32_ls_mode(res, cmp_mode); } else { ir_node *proj_eax; - res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem); + res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem); proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax); be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax); } } else { - res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem); + assert(get_mode_size_bits(cmp_mode) == 32); + res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem); set_ia32_commutative(res); } } @@ -1892,9 +1872,9 @@ static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) { } else { /* determine the smallest switch case value */ + ir_node *new_sel = transform_node(sel); int switch_min = INT_MAX; const ir_edge_t *edge; - ir_node *new_sel = transform_node(env, sel); foreach_out_edge(node, edge) { int pn = get_Proj_proj(get_edge_src_irn(edge)); @@ -1903,19 +1883,19 @@ static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) { if (switch_min) { /* if smallest switch case is not 0 we need an additional sub */ - res = new_rd_ia32_Lea(dbg, irg, block, new_sel, noreg); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); add_ia32_am_offs_int(res, -switch_min); set_ia32_am_flavour(res, ia32_am_OB); set_ia32_am_support(res, ia32_am_Source); set_ia32_op_type(res, ia32_AddrModeS); } - res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : new_sel, mode_T); + res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T); set_ia32_pncode(res, get_Cond_defaultProj(node)); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); return res; } @@ -1924,20 +1904,19 @@ static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) { /** * Transforms a CopyB node. * - * @param env The transformation environment * @return The transformed node. */ -static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) { - ir_node *res = NULL; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); +static ir_node *gen_CopyB(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); ir_node *src = get_CopyB_src(node); - ir_node *new_src = transform_node(env, src); + ir_node *new_src = transform_node(src); ir_node *dst = get_CopyB_dst(node); - ir_node *new_dst = transform_node(env, dst); + ir_node *new_dst = transform_node(dst); ir_node *mem = get_CopyB_mem(node); - ir_node *new_mem = transform_node(env, mem); + ir_node *new_mem = transform_node(mem); + ir_node *res = NULL; + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); int size = get_type_size_bytes(get_CopyB_type(node)); ir_mode *dst_mode = get_irn_mode(dst); ir_mode *src_mode = get_irn_mode(src); @@ -1950,11 +1929,11 @@ static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) { rem = size & 0x3; /* size % 4 */ size >>= 2; - res = new_rd_ia32_Const(dbg, irg, block); - add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi)); + res = new_rd_ia32_Const(dbgi, irg, block); + add_irn_dep(res, be_abi_get_start_barrier(env.cg->birg->abi)); set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is)); - res = new_rd_ia32_CopyB(dbg, irg, block, new_dst, new_src, res, new_mem); + res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem); set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is)); /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */ @@ -1964,7 +1943,7 @@ static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) { be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in); } else { - res = new_rd_ia32_CopyB_i(dbg, irg, block, new_dst, new_src, new_mem); + res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem); set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is)); /* ok: now attach Proj's because movsd will destroy esi and edi */ @@ -1973,7 +1952,7 @@ static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) { be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); return res; } @@ -1983,14 +1962,13 @@ static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) { /** * Transforms a Mux node into CMov. * - * @param env The transformation environment * @return The transformed node. */ -static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) { - ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \ - get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode); +static ir_node *gen_Mux(ir_node *node) { + ir_node *new_op = new_rd_ia32_CMov(env.dbgi, env.irg, env.block, \ + get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -2003,22 +1981,21 @@ typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, /** * Transforms a Psi node into CMov. * - * @param env The transformation environment * @return The transformed node. */ -static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) { - ia32_code_gen_t *cg = env->cg; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *cmp_proj = get_Mux_sel(node); - ir_node *psi_true = get_Psi_val(node, 0); - ir_node *psi_default = get_Psi_default(node); - ir_node *new_psi_true = transform_node(env, psi_true); - ir_node *new_psi_default = transform_node(env, psi_default); - ir_node *noreg = ia32_new_NoReg_gp(cg); - ir_node *nomem = new_rd_NoMem(irg); +static ir_node *gen_Psi(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *psi_true = get_Psi_val(node, 0); + ir_node *new_psi_true = transform_node(psi_true); + ir_node *psi_default = get_Psi_default(node); + ir_node *new_psi_default = transform_node(psi_default); + ia32_code_gen_t *cg = env.cg; + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_node *cmp_proj = get_Mux_sel(node); + ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *nomem = new_rd_NoMem(irg); ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL; ir_node *new_cmp_a, *new_cmp_b; ir_mode *cmp_mode; @@ -2026,12 +2003,12 @@ static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) { assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b"); - cmp = get_Proj_pred(cmp_proj); - cmp_a = get_Cmp_left(cmp); - cmp_b = get_Cmp_right(cmp); - cmp_mode = get_irn_mode(cmp_a); - new_cmp_a = transform_node(env, cmp_a); - new_cmp_b = transform_node(env, cmp_b); + cmp = get_Proj_pred(cmp_proj); + cmp_a = get_Cmp_left(cmp); + cmp_b = get_Cmp_right(cmp); + cmp_mode = get_irn_mode(cmp_a); + new_cmp_a = transform_node(cmp_a); + new_cmp_b = transform_node(cmp_b); pnc = get_Proj_proj(cmp_proj); if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) { @@ -2052,37 +2029,37 @@ static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) { /* in case the compare operands are int, we move them into xmm register */ if (! mode_is_float(get_irn_mode(cmp_a))) { - new_cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_a, node, mode_E); - new_cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_b, node, mode_E); + new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm); + new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm); pnc |= 8; /* transform integer compare to fp compare */ } - new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem); + new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem); set_ia32_pncode(new_op, pnc); set_ia32_am_support(new_op, ia32_am_Source); SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node)); - and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, new_psi_true, new_op, nomem); + and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem); set_ia32_am_support(and1, ia32_am_None); set_ia32_commutative(and1); SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node)); - and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, new_psi_default, nomem); + and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem); set_ia32_am_support(and2, ia32_am_None); set_ia32_commutative(and2); SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node)); - new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem); + new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem); set_ia32_am_support(new_op, ia32_am_None); set_ia32_commutative(new_op); SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node)); } else { /* x87 FPU */ - new_op = new_rd_ia32_vfCMov(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default); + new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default); set_ia32_pncode(new_op, pnc); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); } } else { @@ -2117,18 +2094,18 @@ static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) { if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) { if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) { /* first case for SETcc: default is 0, set to 1 iff condition is true */ - new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a); + new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a); set_ia32_pncode(new_op, pnc); } else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) { /* second case for SETcc: default is 1, set to 0 iff condition is true: */ /* we invert condition and set default to 0 */ - new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a); + new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a); set_ia32_pncode(new_op, get_inversed_pnc(pnc)); } else { /* otherwise: use CMOVcc */ - new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, new_cmp_a, new_psi_true, new_psi_default); + new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default); set_ia32_pncode(new_op, pnc); } @@ -2137,20 +2114,20 @@ static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) { else { if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) { /* first case for SETcc: default is 0, set to 1 iff condition is true */ - new_op = gen_binop(env, node, cmp_a, cmp_b, set_func); + new_op = gen_binop(node, cmp_a, cmp_b, set_func); set_ia32_pncode(new_op, pnc); set_ia32_am_support(new_op, ia32_am_Source); } else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) { /* second case for SETcc: default is 1, set to 0 iff condition is true: */ /* we invert condition and set default to 0 */ - new_op = gen_binop(env, node, cmp_a, cmp_b, set_func); + new_op = gen_binop(node, cmp_a, cmp_b, set_func); set_ia32_pncode(new_op, get_inversed_pnc(pnc)); set_ia32_am_support(new_op, ia32_am_Source); } else { /* otherwise: use CMOVcc */ - new_op = cmov_func(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default); + new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default); set_ia32_pncode(new_op, pnc); SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node)); } @@ -2192,18 +2169,20 @@ static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) { /** * Create a conversion from x87 state register to general purpose. */ -static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) { - ia32_code_gen_t *cg = env->cg; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *op = get_Conv_op(node); - ir_node *new_op = transform_node(env, op); +static ir_node *gen_x87_fp_to_gp(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *op = get_Conv_op(node); + ir_node *new_op = transform_node(op); + ia32_code_gen_t *cg = env.cg; + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *trunc_mode = ia32_new_Fpu_truncate(cg); ir_node *fist, *load; /* do a fist */ - fist = new_rd_ia32_vfist(dbg, irg, block, get_irg_frame(irg), noreg, new_op, new_NoMem()); + fist = new_rd_ia32_vfist(dbgi, irg, block, + get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem()); set_ia32_use_frame(fist); set_ia32_am_support(fist, ia32_am_Dest); @@ -2213,7 +2192,7 @@ static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) { SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node)); /* do a Load */ - load = new_rd_ia32_Load(dbg, irg, block, get_irg_frame(irg), noreg, fist); + load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist); set_ia32_use_frame(load); set_ia32_am_support(load, ia32_am_Source); @@ -2228,35 +2207,33 @@ static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) { /** * Create a conversion from general purpose to x87 register */ -static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) { - ia32_code_gen_t *cg = env->cg; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *nomem = new_NoMem(); +static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { + ir_node *block = transform_node(get_nodes_block(node)); ir_node *op = get_Conv_op(node); - ir_node *new_op = transform_node(env, op); + ir_node *new_op = transform_node(op); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *nomem = new_NoMem(); ir_node *fild, *store; int src_bits; /* first convert to 32 bit if necessary */ src_bits = get_mode_size_bits(src_mode); if (src_bits == 8) { - new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem); + new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem); set_ia32_am_support(new_op, ia32_am_Source); set_ia32_ls_mode(new_op, src_mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); } else if (src_bits < 32) { - new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem); + new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem); set_ia32_am_support(new_op, ia32_am_Source); set_ia32_ls_mode(new_op, src_mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); } /* do a store */ - store = new_rd_ia32_Store(dbg, irg, block, get_irg_frame(irg), noreg, new_op, nomem); + store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem); set_ia32_use_frame(store); set_ia32_am_support(store, ia32_am_Dest); @@ -2265,15 +2242,15 @@ static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mo set_ia32_ls_mode(store, mode_Iu); /* do a fild */ - fild = new_rd_ia32_vfild(dbg, irg, block, get_irg_frame(irg), noreg, store); + fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store); set_ia32_use_frame(fild); set_ia32_am_support(fild, ia32_am_Source); set_ia32_op_type(fild, ia32_AddrModeS); set_ia32_am_flavour(fild, ia32_am_OB); - set_ia32_ls_mode(fild, mode); + set_ia32_ls_mode(fild, mode_Iu); - return new_r_Proj(irg, block, fild, mode_F, pn_ia32_vfild_res); + return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); } /** @@ -2282,77 +2259,84 @@ static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mo * @param env The transformation environment * @return The created ia32 Conv node */ -static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); +static ir_node *gen_Conv(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); ir_node *op = get_Conv_op(node); + ir_node *new_op = transform_node(op); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *src_mode = get_irn_mode(op); ir_mode *tgt_mode = get_irn_mode(node); int src_bits = get_mode_size_bits(src_mode); int tgt_bits = get_mode_size_bits(tgt_mode); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *res; - ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); ir_node *nomem = new_rd_NoMem(irg); - ir_node *new_op = transform_node(env, op); - DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) + ir_node *res; if (src_mode == tgt_mode) { - /* this should be optimized already, but who knows... */ - DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node)); - DB((mod, LEVEL_1, "killed Conv(mode, mode) ...")); - return new_op; + if (get_Conv_strict(node)) { + if (USE_SSE2(env.cg)) { + /* when we are in SSE mode, we can kill all strict no-op conversion */ + return new_op; + } + } else { + /* this should be optimized already, but who knows... */ + DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node)); + DB((dbg, LEVEL_1, "killed Conv(mode, mode) ...")); + return new_op; + } } if (mode_is_float(src_mode)) { /* we convert from float ... */ if (mode_is_float(tgt_mode)) { /* ... to float */ - if (USE_SSE2(env->cg)) { - DB((mod, LEVEL_1, "create Conv(float, float) ...")); - res = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, new_op, nomem); + if (USE_SSE2(env.cg)) { + DB((dbg, LEVEL_1, "create Conv(float, float) ...")); + res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem); set_ia32_ls_mode(res, tgt_mode); } else { // Matze: TODO what about strict convs? - DB((mod, LEVEL_1, "killed Conv(float, float) ...")); + DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node)); + DB((dbg, LEVEL_1, "killed Conv(float, float) ...")); return new_op; } } else { /* ... to int */ - DB((mod, LEVEL_1, "create Conv(float, int) ...")); - if (USE_SSE2(env->cg)) { - res = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, new_op, nomem); + DB((dbg, LEVEL_1, "create Conv(float, int) ...")); + if (USE_SSE2(env.cg)) { + res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem); set_ia32_ls_mode(res, src_mode); } else { - return gen_x87_fp_to_gp(env, node); + return gen_x87_fp_to_gp(node); } } } else { /* we convert from int ... */ if (mode_is_float(tgt_mode)) { - FP_USED(env->cg); + FP_USED(env.cg); /* ... to float */ - DB((mod, LEVEL_1, "create Conv(int, float) ...")); - if (USE_SSE2(env->cg)) { - res = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, new_op, nomem); + DB((dbg, LEVEL_1, "create Conv(int, float) ...")); + if (USE_SSE2(env.cg)) { + res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem); set_ia32_ls_mode(res, tgt_mode); if(src_bits == 32) { set_ia32_am_support(res, ia32_am_Source); } } else { - return gen_x87_gp_to_fp(env, node, src_mode); + return gen_x87_gp_to_fp(node, src_mode); } - } - else { + } else { + /* to int */ ir_mode *smaller_mode; - int smaller_bits; + int smaller_bits; if (src_bits == tgt_bits) { - DB((mod, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode)); + DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode)); return new_op; } - if(src_bits < tgt_bits) { + if (src_bits < tgt_bits) { smaller_mode = src_mode; smaller_bits = src_bits; } else { @@ -2360,40 +2344,520 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) { smaller_bits = tgt_bits; } - // The following is not correct, we can't change the mode, - // maybe others are using the load too - // better move this to a separate phase! -#if 0 - /* ... to int */ - if(is_Proj(new_op)) { - /* load operations do already sign/zero extend, so we have - * nothing left to do */ - ir_node *pred = get_Proj_pred(new_op); - if(is_ia32_Load(pred)) { - set_ia32_ls_mode(pred, smaller_mode); - return new_op; - } - } -#endif - - DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode)); + DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode)); if (smaller_bits == 8) { - res = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem); + res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem); set_ia32_ls_mode(res, smaller_mode); } else { - res = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem); + res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem); set_ia32_ls_mode(res, smaller_mode); } set_ia32_am_support(res, ia32_am_Source); } } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); return res; } +static +int check_immediate_constraint(tarval *tv, char immediate_constraint_type) +{ + long val; + + assert(tarval_is_long(tv)); + val = get_tarval_long(tv); + + switch (immediate_constraint_type) { + case 0: + return 1; + case 'I': + return val >= 0 && val <= 32; + case 'J': + return val >= 0 && val <= 63; + case 'K': + return val >= -128 && val <= 127; + case 'L': + return val == 0xff || val == 0xffff; + case 'M': + return val >= 0 && val <= 3; + case 'N': + return val >= 0 && val <= 255; + case 'O': + return val >= 0 && val <= 127; + default: + break; + } + panic("Invalid immediate constraint found"); + return 0; +} + +ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) +{ + int minus = 0; + tarval *offset = NULL; + int offset_sign = 0; + ir_entity *symconst_ent = NULL; + int symconst_sign = 0; + ir_mode *mode; + ir_node *cnst = NULL; + ir_node *symconst = NULL; + ir_node *res; + ir_graph *irg; + dbg_info *dbgi; + ir_node *block; + ia32_attr_t *attr; + + mode = get_irn_mode(node); + if(!mode_is_int(mode) && !mode_is_character(mode) && + !mode_is_reference(mode)) { + return NULL; + } + if(is_Minus(node)) { + minus = 1; + node = get_Minus_op(node); + } + + if(is_Const(node)) { + cnst = node; + symconst = NULL; + offset_sign = minus; + } else if(is_SymConst(node)) { + cnst = NULL; + symconst = node; + symconst_sign = minus; + } else if(is_Add(node)) { + ir_node *left = get_Add_left(node); + ir_node *right = get_Add_right(node); + if(is_Const(left) && is_SymConst(right)) { + cnst = left; + symconst = right; + symconst_sign = minus; + offset_sign = minus; + } else if(is_SymConst(left) && is_Const(right)) { + cnst = right; + symconst = left; + symconst_sign = minus; + offset_sign = minus; + } + } else if(is_Sub(node)) { + ir_node *left = get_Add_left(node); + ir_node *right = get_Add_right(node); + if(is_Const(left) && is_SymConst(right)) { + cnst = left; + symconst = right; + symconst_sign = !minus; + offset_sign = minus; + } else if(is_SymConst(left) && is_Const(right)) { + cnst = right; + symconst = left; + symconst_sign = minus; + offset_sign = !minus; + } + } else { + return NULL; + } + + if(cnst != NULL) { + offset = get_Const_tarval(cnst); + if(!tarval_is_long(offset)) { + ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a " + "long?\n", cnst); + return NULL; + } + + if(!check_immediate_constraint(offset, immediate_constraint_type)) + return NULL; + } + if(symconst != NULL) { + if(immediate_constraint_type != 0) { + /* we need full 32bits for symconsts */ + return NULL; + } + + if(get_SymConst_kind(symconst) != symconst_addr_ent) + return NULL; + symconst_ent = get_SymConst_entity(symconst); + } + + irg = env.irg; + dbgi = get_irn_dbg_info(node); + block = get_irg_start_block(irg); + res = new_rd_ia32_Immediate(dbgi, irg, block); + arch_set_irn_register(env.cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]); + + /* make sure we don't schedule stuff before the barrier */ + add_irn_dep(res, get_irg_frame(irg)); + + /* misuse some fields for now... */ + attr = get_ia32_attr(res); + attr->am_sc = symconst_ent; + attr->data.am_sc_sign = symconst_sign; + if(offset_sign && offset != NULL) { + offset = tarval_neg(offset); + } + attr->cnst_val.tv = offset; + attr->data.imm_tp = ia32_ImmConst; + + return res; +} + +typedef struct constraint_t constraint_t; +struct constraint_t { + int is_in; + int n_outs; + const arch_register_req_t **out_reqs; + + const arch_register_req_t *req; + unsigned immediate_possible; + char immediate_type; +}; + +void parse_asm_constraint(ir_node *node, int pos, constraint_t *constraint, + const char *c) +{ + int immediate_possible = 0; + char immediate_type = 0; + unsigned limited = 0; + const arch_register_class_t *cls = NULL; + ir_graph *irg; + struct obstack *obst; + arch_register_req_t *req; + unsigned *limited_ptr; + int p; + int same_as = -1; + + /* TODO: replace all the asserts with nice error messages */ + + printf("Constraint: %s\n", c); + + while(*c != 0) { + switch(*c) { + case ' ': + case '\t': + case '\n': + break; + + case 'a': + assert(cls == NULL || + (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + limited |= 1 << REG_EAX; + break; + case 'b': + assert(cls == NULL || + (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + limited |= 1 << REG_EBX; + break; + case 'c': + assert(cls == NULL || + (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + limited |= 1 << REG_ECX; + break; + case 'd': + assert(cls == NULL || + (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + limited |= 1 << REG_EDX; + break; + case 'D': + assert(cls == NULL || + (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + limited |= 1 << REG_EDI; + break; + case 'S': + assert(cls == NULL || + (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + limited |= 1 << REG_ESI; + break; + case 'Q': + case 'q': /* q means lower part of the regs only, this makes no + * difference to Q for us (we only assigne whole registers) */ + assert(cls == NULL || + (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX | + 1 << REG_EDX; + break; + case 'A': + assert(cls == NULL || + (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + limited |= 1 << REG_EAX | 1 << REG_EDX; + break; + case 'l': + assert(cls == NULL || + (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX | + 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI | + 1 << REG_EBP; + break; + + case 'R': + case 'r': + case 'p': + assert(cls == NULL); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + break; + + case 'f': + case 't': + case 'u': + assert(cls == NULL); + cls = &ia32_reg_classes[CLASS_ia32_vfp]; + break; + + case 'Y': + case 'x': + assert(cls == NULL); + /* TODO: check that sse2 is supported */ + cls = &ia32_reg_classes[CLASS_ia32_xmm]; + break; + + case 'I': + case 'J': + case 'K': + case 'L': + case 'M': + case 'N': + case 'O': + assert(!immediate_possible); + immediate_possible = 1; + immediate_type = *c; + break; + case 'n': + case 'i': + assert(!immediate_possible); + immediate_possible = 1; + break; + + case 'g': + assert(!immediate_possible && cls == NULL); + immediate_possible = 1; + cls = &ia32_reg_classes[CLASS_ia32_gp]; + break; + + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + assert(constraint->is_in && "can only specify same constraint " + "on input"); + + sscanf(c, "%d%n", &same_as, &p); + if(same_as >= 0) { + c += p; + continue; + } + break; + + case 'E': /* no float consts yet */ + case 'F': /* no float consts yet */ + case 's': /* makes no sense on x86 */ + case 'X': /* we can't support that in firm */ + case 'm': + case 'o': + case 'V': + case '<': /* no autodecrement on x86 */ + case '>': /* no autoincrement on x86 */ + case 'C': /* sse constant not supported yet */ + case 'G': /* 80387 constant not supported yet */ + case 'y': /* we don't support mmx registers yet */ + case 'Z': /* not available in 32 bit mode */ + case 'e': /* not available in 32 bit mode */ + assert(0 && "asm constraint not supported"); + break; + default: + assert(0 && "unknown asm constraint found"); + break; + } + ++c; + } + + if(same_as >= 0) { + const arch_register_req_t *other_constr; + + assert(cls == NULL && "same as and register constraint not supported"); + assert(!immediate_possible && "same as and immediate constraint not " + "supported"); + assert(same_as < constraint->n_outs && "wrong constraint number in " + "same_as constraint"); + + other_constr = constraint->out_reqs[same_as]; + + req = obstack_alloc(obst, sizeof(req[0])); + req->cls = other_constr->cls; + req->type = arch_register_req_type_should_be_same; + req->limited = NULL; + req->other_same = pos; + req->other_different = -1; + + /* switch constraints. This is because in firm we have same_as + * constraints on the output constraints while in the gcc asm syntax + * they are specified on the input constraints */ + constraint->req = other_constr; + constraint->out_reqs[same_as] = req; + constraint->immediate_possible = 0; + return; + } + + if(immediate_possible && cls == NULL) { + cls = &ia32_reg_classes[CLASS_ia32_gp]; + } + assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]); + assert(cls != NULL); + + if(immediate_possible) { + assert(constraint->is_in + && "imeediates make no sense for output constraints"); + } + /* todo: check types (no float input on 'r' constrainted in and such... */ + + irg = env.irg; + obst = get_irg_obstack(irg); + + if(limited != 0) { + req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned)); + limited_ptr = (unsigned*) (req+1); + } else { + req = obstack_alloc(obst, sizeof(req[0])); + } + memset(req, 0, sizeof(req[0])); + + if(limited != 0) { + req->type = arch_register_req_type_limited; + *limited_ptr = limited; + req->limited = limited_ptr; + } else { + req->type = arch_register_req_type_normal; + } + req->cls = cls; + + constraint->req = req; + constraint->immediate_possible = immediate_possible; + constraint->immediate_type = immediate_type; +} + +static +void parse_clobber(ir_node *node, int pos, constraint_t *constraint, + const char *c) +{ + panic("Clobbers not supported yet"); +} + +ir_node *gen_ASM(ir_node *node) +{ + int i, arity; + ir_graph *irg = env.irg; + ir_node *block = transform_node(get_nodes_block(node)); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node **in; + ir_node *res; + int out_arity; + int n_outs; + int n_clobbers; + ia32_attr_t *attr; + const arch_register_req_t **out_reqs; + const arch_register_req_t **in_reqs; + struct obstack *obst; + constraint_t parsed_constraint; + + /* assembler could contain float statements */ + FP_USED(env.cg); + + /* transform inputs */ + arity = get_irn_arity(node); + in = alloca(arity * sizeof(in[0])); + memset(in, 0, arity * sizeof(in[0])); + + n_outs = get_ASM_n_output_constraints(node); + n_clobbers = get_ASM_n_clobbers(node); + out_arity = n_outs + n_clobbers; + + /* construct register constraints */ + obst = get_irg_obstack(irg); + out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0])); + parsed_constraint.out_reqs = out_reqs; + parsed_constraint.n_outs = n_outs; + parsed_constraint.is_in = 0; + for(i = 0; i < out_arity; ++i) { + const char *c; + + if(i < n_outs) { + const ir_asm_constraint *constraint; + constraint = & get_ASM_output_constraints(node) [i]; + c = get_id_str(constraint->constraint); + parse_asm_constraint(node, i, &parsed_constraint, c); + } else { + ident *glob_id = get_ASM_clobbers(node) [i - n_outs]; + c = get_id_str(glob_id); + parse_clobber(node, i, &parsed_constraint, c); + } + out_reqs[i] = parsed_constraint.req; + } + + in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0])); + parsed_constraint.is_in = 1; + for(i = 0; i < arity; ++i) { + const ir_asm_constraint *constraint; + ident *constr_id; + const char *c; + + constraint = & get_ASM_input_constraints(node) [i]; + constr_id = constraint->constraint; + c = get_id_str(constr_id); + parse_asm_constraint(node, i, &parsed_constraint, c); + in_reqs[i] = parsed_constraint.req; + + if(parsed_constraint.immediate_possible) { + ir_node *pred = get_irn_n(node, i); + char imm_type = parsed_constraint.immediate_type; + ir_node *immediate = try_create_Immediate(pred, imm_type); + + if(immediate != NULL) { + in[i] = immediate; + } + } + } + + /* transform inputs */ + for(i = 0; i < arity; ++i) { + ir_node *pred; + ir_node *transformed; + + if(in[i] != NULL) + continue; + + pred = get_irn_n(node, i); + transformed = transform_node(pred); + in[i] = transformed; + } + + res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity); + + attr = get_ia32_attr(res); + attr->cnst_val.asm_text = get_ASM_text(node); + attr->data.imm_tp = ia32_ImmAsm; + set_ia32_out_req_all(res, out_reqs); + set_ia32_in_req_all(res, in_reqs); + + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); + + return res; +} /******************************************** * _ _ @@ -2405,33 +2869,33 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) { * ********************************************/ -static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) { - ir_node *new_op = NULL; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *nomem = new_rd_NoMem(env->irg); - ir_node *ptr = get_irn_n(node, 0); - ir_node *new_ptr = transform_node(env, ptr); - ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node); +static ir_node *gen_be_StackParam(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr); + ir_node *new_ptr = transform_node(ptr); + ir_node *new_op = NULL; + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *nomem = new_rd_NoMem(env.irg); + ir_entity *ent = arch_get_frame_entity(env.cg->arch_env, node); ir_mode *load_mode = get_irn_mode(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); ir_mode *proj_mode; long pn_res; if (mode_is_float(load_mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) { - new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, nomem); - pn_res = pn_ia32_xLoad_res; + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { + new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem); + pn_res = pn_ia32_xLoad_res; + proj_mode = mode_xmm; } else { - new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, nomem); - pn_res = pn_ia32_vfld_res; + new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem); + pn_res = pn_ia32_vfld_res; + proj_mode = mode_vfp; } - - proj_mode = mode_E; } else { - new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, nomem); + new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem); proj_mode = mode_Iu; pn_res = pn_ia32_Load_res; } @@ -2445,30 +2909,30 @@ static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) { set_ia32_ls_mode(new_op, load_mode); set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); - return new_rd_Proj(dbg, irg, block, new_op, proj_mode, pn_res); + return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res); } /** * Transforms a FrameAddr into an ia32 Add. */ -static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *op = get_irn_n(node, 0); - ir_node *new_op = transform_node(env, op); - ir_node *res; - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - - res = new_rd_ia32_Lea(dbg, irg, block, new_op, noreg); - set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node)); +static ir_node *gen_be_FrameAddr(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *op = get_irn_n(node, be_pos_FrameAddr_ptr); + ir_node *new_op = transform_node(op); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *res; + + res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg); + set_ia32_frame_ent(res, arch_get_frame_entity(env.cg->arch_env, node)); set_ia32_am_support(res, ia32_am_Full); set_ia32_use_frame(res); set_ia32_am_flavour(res, ia32_am_OB); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node)); return res; } @@ -2476,33 +2940,33 @@ static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) { /** * Transforms a FrameLoad into an ia32 Load. */ -static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) { +static ir_node *gen_be_FrameLoad(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem); + ir_node *new_mem = transform_node(mem); + ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr); + ir_node *new_ptr = transform_node(ptr); ir_node *new_op = NULL; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *mem = get_irn_n(node, 0); - ir_node *ptr = get_irn_n(node, 1); - ir_node *new_mem = transform_node(env, mem); - ir_node *new_ptr = transform_node(env, ptr); - ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_entity *ent = arch_get_frame_entity(env.cg->arch_env, node); ir_mode *mode = get_type_mode(get_entity_type(ent)); ir_node *projs[pn_Load_max]; ia32_collect_Projs(node, projs, pn_Load_max); if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) { - new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, new_mem); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { + new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem); } else { - new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem); + new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem); } } else { - new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, new_mem); + new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem); } set_ia32_frame_ent(new_op, ent); @@ -2513,7 +2977,7 @@ static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) { set_ia32_am_flavour(new_op, ia32_am_B); set_ia32_ls_mode(new_op, mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -2522,35 +2986,32 @@ static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) { /** * Transforms a FrameStore into an ia32 Store. */ -static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) { +static ir_node *gen_be_FrameStore(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem); + ir_node *new_mem = transform_node(mem); + ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr); + ir_node *new_ptr = transform_node(ptr); + ir_node *val = get_irn_n(node, be_pos_FrameStore_val); + ir_node *new_val = transform_node(val); ir_node *new_op = NULL; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *mem = get_irn_n(node, 0); - ir_node *ptr = get_irn_n(node, 1); - ir_node *val = get_irn_n(node, 2); - ir_node *new_mem = transform_node(env, mem); - ir_node *new_ptr = transform_node(env, ptr); - ir_node *new_val = transform_node(env, val); - ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_entity *ent = arch_get_frame_entity(env.cg->arch_env, node); ir_mode *mode = get_irn_mode(val); if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) { - new_op = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem); - } - else { - new_op = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem); + FP_USED(env.cg); + if (USE_SSE2(env.cg)) { + new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem); + } else { + new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem); } - } - else if (get_mode_size_bits(mode) == 8) { - new_op = new_rd_ia32_Store8Bit(dbg, irg, block, new_ptr, noreg, new_val, new_mem); - } - else { - new_op = new_rd_ia32_Store(dbg, irg, block, new_ptr, noreg, new_val, new_mem); + } else if (get_mode_size_bits(mode) == 8) { + new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem); + } else { + new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem); } set_ia32_frame_ent(new_op, ent); @@ -2561,7 +3022,7 @@ static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) { set_ia32_am_flavour(new_op, ia32_am_B); set_ia32_ls_mode(new_op, mode); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -2569,35 +3030,36 @@ static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) { /** * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return. */ -static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg; - ir_node *block; +static ir_node *gen_be_Return(ir_node *node) { + ir_graph *irg = env.irg; ir_node *ret_val = get_irn_n(node, be_pos_Return_val); ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem); ir_entity *ent = get_irg_entity(irg); ir_type *tp = get_entity_type(ent); + dbg_info *dbgi; + ir_node *block; ir_type *res_type; ir_mode *mode; - ir_node *frame, *sse_store, *fld, *mproj, *barrier; - ir_node *new_barrier, *new_ret_val, *new_ret_mem; - ir_node **in; - int pn_ret_val, pn_ret_mem, arity, i; + ir_node *frame, *sse_store, *fld, *mproj, *barrier; + ir_node *new_barrier, *new_ret_val, *new_ret_mem; + ir_node *noreg; + ir_node **in; + int pn_ret_val, pn_ret_mem, arity, i; assert(ret_val != NULL); - if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) { - return duplicate_node(env, node); + if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env.cg)) { + return duplicate_node(node); } res_type = get_method_res_type(tp, 0); - if (!is_Primitive_type(res_type)) { - return duplicate_node(env, node); + if (! is_Primitive_type(res_type)) { + return duplicate_node(node); } mode = get_type_mode(res_type); - if (!mode_is_float(mode)) { - return duplicate_node(env, node); + if (! mode_is_float(mode)) { + return duplicate_node(node); } assert(get_method_n_ress(tp) == 1); @@ -2609,20 +3071,22 @@ static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) { barrier = get_Proj_pred(ret_val); /* get result input of the Barrier */ - ret_val = get_irn_n(barrier, pn_ret_val); - new_ret_val = transform_node(env, ret_val); + ret_val = get_irn_n(barrier, pn_ret_val); + new_ret_val = transform_node(ret_val); /* get memory input of the Barrier */ - ret_mem = get_irn_n(barrier, pn_ret_mem); - new_ret_mem = transform_node(env, ret_mem); + ret_mem = get_irn_n(barrier, pn_ret_mem); + new_ret_mem = transform_node(ret_mem); frame = get_irg_frame(irg); - dbg = get_irn_dbg_info(barrier); - block = transform_node(env, get_nodes_block(barrier)); + dbgi = get_irn_dbg_info(barrier); + block = transform_node(get_nodes_block(barrier)); + + noreg = ia32_new_NoReg_gp(env.cg); /* store xmm0 onto stack */ - sse_store = new_rd_ia32_xStoreSimple(dbg, irg, block, frame, new_ret_val, new_ret_mem); + sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem); set_ia32_ls_mode(sse_store, mode); set_ia32_op_type(sse_store, ia32_AddrModeD); set_ia32_use_frame(sse_store); @@ -2630,7 +3094,7 @@ static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) { set_ia32_am_support(sse_store, ia32_am_Dest); /* load into st0 */ - fld = new_rd_ia32_SetST0(dbg, irg, block, frame, sse_store); + fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store); set_ia32_ls_mode(fld, mode); set_ia32_op_type(fld, ia32_AddrModeS); set_ia32_use_frame(fld); @@ -2638,58 +3102,59 @@ static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) { set_ia32_am_support(fld, ia32_am_Source); mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M); - fld = new_r_Proj(irg, block, fld, mode_E, pn_ia32_SetST0_res); - arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]); + fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res); + arch_set_irn_register(env.cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]); /* create a new barrier */ arity = get_irn_arity(barrier); in = alloca(arity * sizeof(in[0])); - for(i = 0; i < arity; ++i) { + for (i = 0; i < arity; ++i) { ir_node *new_in; - if(i == pn_ret_val) { + + if (i == pn_ret_val) { new_in = fld; - } else if(i == pn_ret_mem) { + } else if (i == pn_ret_mem) { new_in = mproj; } else { ir_node *in = get_irn_n(barrier, i); - new_in = transform_node(env, in); + new_in = transform_node(in); } in[i] = new_in; } - new_barrier = new_ir_node(dbg, irg, block, + new_barrier = new_ir_node(dbgi, irg, block, get_irn_op(barrier), get_irn_mode(barrier), arity, in); copy_node_attr(barrier, new_barrier); - duplicate_deps(env, barrier, new_barrier); + duplicate_deps(barrier, new_barrier); set_new_node(barrier, new_barrier); mark_irn_visited(barrier); /* transform normally */ - return duplicate_node(env, node); + return duplicate_node(node); } /** * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes. */ -static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) { - ir_node *new_op; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *sz = get_irn_n(node, be_pos_AddSP_size); - ir_node *new_sz = transform_node(env, sz); - ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); - ir_node *new_sp = transform_node(env, sp); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *nomem = new_NoMem(); +static ir_node *gen_be_AddSP(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *sz = get_irn_n(node, be_pos_AddSP_size); + ir_node *new_sz = transform_node(sz); + ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); + ir_node *new_sp = transform_node(sp); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *nomem = new_NoMem(); + ir_node *new_op; /* ia32 stack grows in reverse direction, make a SubSP */ - new_op = new_rd_ia32_SubSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem); + new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem); set_ia32_am_support(new_op, ia32_am_Source); - fold_immediate(env, new_op, 2, 3); + fold_immediate(new_op, 2, 3); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -2697,24 +3162,24 @@ static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) { /** * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes. */ -static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) { - ir_node *new_op; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *sz = get_irn_n(node, be_pos_SubSP_size); - ir_node *new_sz = transform_node(env, sz); - ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); - ir_node *new_sp = transform_node(env, sp); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *nomem = new_NoMem(); +static ir_node *gen_be_SubSP(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *sz = get_irn_n(node, be_pos_SubSP_size); + ir_node *new_sz = transform_node(sz); + ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); + ir_node *new_sp = transform_node(sp); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *nomem = new_NoMem(); + ir_node *new_op; /* ia32 stack grows in reverse direction, make an AddSP */ - new_op = new_rd_ia32_AddSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem); + new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem); set_ia32_am_support(new_op, ia32_am_Source); - fold_immediate(env, new_op, 2, 3); + fold_immediate(new_op, 2, 3); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -2724,16 +3189,16 @@ static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) { * as this is not done during register allocation because Unknown * is an "ignore" node. */ -static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) { +static ir_node *gen_Unknown(ir_node *node) { ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - if (USE_SSE2(env->cg)) - return ia32_new_Unknown_xmm(env->cg); + if (USE_SSE2(env.cg)) + return ia32_new_Unknown_xmm(env.cg); else - return ia32_new_Unknown_vfp(env->cg); - } else if (mode_is_int(mode) || mode_is_reference(mode)) { - return ia32_new_Unknown_gp(env->cg); + return ia32_new_Unknown_vfp(env.cg); + } else if (mode_needs_gp_reg(mode)) { + return ia32_new_Unknown_gp(env.cg); } else { assert(0 && "unsupported Unknown-Mode"); } @@ -2744,39 +3209,41 @@ static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) { /** * Change some phi modes */ -static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *phi; - int i, arity; +static ir_node *gen_Phi(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_node *phi; + int i, arity; - if(mode_is_int(mode) || mode_is_reference(mode)) { - // we shouldn't have any 64bit stuff around anymore + if(mode_needs_gp_reg(mode)) { + /* we shouldn't have any 64bit stuff around anymore */ assert(get_mode_size_bits(mode) <= 32); - // all integer operations are on 32bit registers now + /* all integer operations are on 32bit registers now */ mode = mode_Iu; } else if(mode_is_float(mode)) { assert(mode == mode_D || mode == mode_F); - // all float operations are on mode_E registers - mode = mode_E; + if (USE_SSE2(env.cg)) { + mode = mode_xmm; + } else { + mode = mode_vfp; + } } /* phi nodes allow loops, so we use the old arguments for now * and fix this later */ - phi = new_ir_node(dbg, irg, block, op_Phi, mode, get_irn_arity(node), - get_irn_in(node) + 1); + phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1); copy_node_attr(node, phi); - duplicate_deps(env, node, phi); + duplicate_deps(node, phi); set_new_node(node, phi); /* put the preds in the worklist */ arity = get_irn_arity(node); - for(i = 0; i < arity; ++i) { + for (i = 0; i < arity; ++i) { ir_node *pred = get_irn_n(node, i); - pdeq_putr(env->worklist, pred); + pdeq_putr(env.worklist, pred); } return phi; @@ -2803,29 +3270,29 @@ typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *bloc /** * Transforms a lowered Load into a "real" one. */ -static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_mode *mode = get_ia32_ls_mode(node); - ir_node *new_op; - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *ptr = get_irn_n(node, 0); - ir_node *mem = get_irn_n(node, 1); - ir_node *new_ptr = transform_node(env, ptr); - ir_node *new_mem = transform_node(env, mem); +static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *ptr = get_irn_n(node, 0); + ir_node *new_ptr = transform_node(ptr); + ir_node *mem = get_irn_n(node, 1); + ir_node *new_mem = transform_node(mem); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_ia32_ls_mode(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *new_op; /* Could be that we have SSE2 unit, but due to 64Bit Div/Conv lowering we have x87 nodes, so we need to enforce simulation. */ if (mode_is_float(mode)) { - FP_USED(env->cg); + FP_USED(env.cg); if (fp_unit == fp_x87) - FORCE_x87(env->cg); + FORCE_x87(env.cg); } - new_op = func(dbg, irg, block, new_ptr, noreg, new_mem); + new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem); set_ia32_am_support(new_op, ia32_am_Source); set_ia32_op_type(new_op, ia32_AddrModeS); @@ -2833,15 +3300,15 @@ static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, const set_ia32_am_offs_int(new_op, 0); set_ia32_am_scale(new_op, 1); set_ia32_am_sc(new_op, get_ia32_am_sc(node)); - if(is_ia32_am_sc_sign(node)) + if (is_ia32_am_sc_sign(node)) set_ia32_am_sc_sign(new_op); set_ia32_ls_mode(new_op, get_ia32_ls_mode(node)); - if(is_ia32_use_frame(node)) { + if (is_ia32_use_frame(node)) { set_ia32_frame_ent(new_op, get_ia32_frame_ent(node)); set_ia32_use_frame(new_op); } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -2849,33 +3316,33 @@ static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, const /** * Transforms a lowered Store into a "real" one. */ -static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_mode *mode = get_ia32_ls_mode(node); - ir_node *new_op; - long am_offs; +static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *ptr = get_irn_n(node, 0); + ir_node *new_ptr = transform_node(ptr); + ir_node *val = get_irn_n(node, 1); + ir_node *new_val = transform_node(val); + ir_node *mem = get_irn_n(node, 2); + ir_node *new_mem = transform_node(mem); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_mode *mode = get_ia32_ls_mode(node); + ir_node *new_op; + long am_offs; ia32_am_flavour_t am_flav = ia32_B; - ir_node *ptr = get_irn_n(node, 0); - ir_node *val = get_irn_n(node, 1); - ir_node *mem = get_irn_n(node, 2); - ir_node *new_ptr = transform_node(env, ptr); - ir_node *new_val = transform_node(env, val); - ir_node *new_mem = transform_node(env, mem); /* Could be that we have SSE2 unit, but due to 64Bit Div/Conv lowering we have x87 nodes, so we need to enforce simulation. */ if (mode_is_float(mode)) { - FP_USED(env->cg); + FP_USED(env.cg); if (fp_unit == fp_x87) - FORCE_x87(env->cg); + FORCE_x87(env.cg); } - new_op = func(dbg, irg, block, new_ptr, noreg, new_val, new_mem); + new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem); if ((am_offs = get_ia32_am_offs_int(node)) != 0) { am_flav |= ia32_O; @@ -2889,7 +3356,7 @@ static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, cons set_ia32_frame_ent(new_op, get_ia32_frame_ent(node)); set_ia32_use_frame(new_op); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); return new_op; } @@ -2902,42 +3369,42 @@ static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, cons * @return the created ia32 XXX node */ #define GEN_LOWERED_OP(op) \ - static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\ + static ir_node *gen_ia32_l_##op(ir_node *node) {\ ir_mode *mode = get_irn_mode(node); \ if (mode_is_float(mode)) \ - FP_USED(env->cg); \ - return gen_binop(env, node, get_binop_left(node), \ + FP_USED(env.cg); \ + return gen_binop(node, get_binop_left(node), \ get_binop_right(node), new_rd_ia32_##op); \ } #define GEN_LOWERED_x87_OP(op) \ - static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\ + static ir_node *gen_ia32_l_##op(ir_node *node) {\ ir_node *new_op; \ - FORCE_x87(env->cg); \ - new_op = gen_binop_float(env, node, get_binop_left(node), \ + FORCE_x87(env.cg); \ + new_op = gen_binop_float(node, get_binop_left(node), \ get_binop_right(node), new_rd_ia32_##op); \ return new_op; \ } #define GEN_LOWERED_UNOP(op) \ - static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\ - return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \ + static ir_node *gen_ia32_l_##op(ir_node *node) {\ + return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \ } #define GEN_LOWERED_SHIFT_OP(op) \ - static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\ - return gen_shift_binop(env, node, get_binop_left(node), \ + static ir_node *gen_ia32_l_##op(ir_node *node) {\ + return gen_shift_binop(node, get_binop_left(node), \ get_binop_right(node), new_rd_ia32_##op); \ } #define GEN_LOWERED_LOAD(op, fp_unit) \ - static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\ - return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \ + static ir_node *gen_ia32_l_##op(ir_node *node) {\ + return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \ } #define GEN_LOWERED_STORE(op, fp_unit) \ - static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\ - return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \ + static ir_node *gen_ia32_l_##op(ir_node *node) {\ + return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \ } GEN_LOWERED_OP(Adc) @@ -2954,28 +3421,30 @@ GEN_LOWERED_UNOP(Neg) GEN_LOWERED_LOAD(vfild, fp_x87) GEN_LOWERED_LOAD(Load, fp_none) -GEN_LOWERED_STORE(vfist, fp_x87) +/*GEN_LOWERED_STORE(vfist, fp_x87) + *TODO + */ GEN_LOWERED_STORE(Store, fp_none) -static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) { - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *left = get_binop_left(node); - ir_node *right = get_binop_right(node); - ir_node *new_left = transform_node(env, left); - ir_node *new_right = transform_node(env, right); - ir_node *vfdiv; - - vfdiv = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem()); +static ir_node *gen_ia32_l_vfdiv(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *left = get_binop_left(node); + ir_node *new_left = transform_node(left); + ir_node *right = get_binop_right(node); + ir_node *new_right = transform_node(right); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *vfdiv; + + vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem()); clear_ia32_commutative(vfdiv); set_ia32_am_support(vfdiv, ia32_am_Source); - fold_immediate(env, vfdiv, 2, 3); + fold_immediate(vfdiv, 2, 3); - SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env.cg, node)); - FORCE_x87(env->cg); + FORCE_x87(env.cg); return vfdiv; } @@ -2986,30 +3455,30 @@ static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) { * @param env The transformation environment * @return the created ia32 Mul node */ -static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) { - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *left = get_binop_left(node); - ir_node *right = get_binop_right(node); - ir_node *new_left = transform_node(env, left); - ir_node *new_right = transform_node(env, right); - ir_node *in[2]; +static ir_node *gen_ia32_l_Mul(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *left = get_binop_left(node); + ir_node *new_left = transform_node(left); + ir_node *right = get_binop_right(node); + ir_node *new_right = transform_node(right); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *in[2]; /* l_Mul is already a mode_T node, so we create the Mul in the normal way */ /* and then skip the result Proj, because all needed Projs are already there. */ - ir_node *muls = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem()); + ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem()); clear_ia32_commutative(muls); set_ia32_am_support(muls, ia32_am_Source); - fold_immediate(env, muls, 2, 3); + fold_immediate(muls, 2, 3); /* check if EAX and EDX proj exist, add missing one */ - in[0] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EAX); - in[1] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EDX); + in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX); + in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX); be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in); - SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env.cg, node)); return muls; } @@ -3025,28 +3494,26 @@ GEN_LOWERED_SHIFT_OP(Sar) * op3 - shift count * Only op3 can be an immediate. */ -static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node, - ir_node *op1, ir_node *op2, - ir_node *count) { - ir_node *new_op = NULL; - ir_graph *irg = env->irg; - ir_mode *mode = get_irn_mode(node); - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *nomem = new_NoMem(); - ir_node *imm_op; - ir_node *new_op1 = transform_node(env, op1); - ir_node *new_op2 = transform_node(env, op2); - ir_node *new_count = transform_node(env, count); - tarval *tv; - DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) - - assert(! mode_is_float(mode) && "Shift/Rotate with float not supported"); +static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1, + ir_node *op2, ir_node *count) +{ + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *new_op1 = transform_node(op1); + ir_node *new_op2 = transform_node(op2); + ir_node *new_count = transform_node(count); + ir_node *new_op = NULL; + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); + ir_node *nomem = new_NoMem(); + ir_node *imm_op; + tarval *tv; + + assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported"); /* Check if immediate optimization is on and */ /* if it's an operation with immediate. */ - imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL; + imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL; /* Limit imm_op within range imm8 */ if (imm_op) { @@ -3064,24 +3531,24 @@ static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *nod /* integer operations */ if (imm_op) { /* This is ShiftD with const */ - DB((mod, LEVEL_1, "ShiftD with immediate ...")); + DB((dbg, LEVEL_1, "ShiftD with immediate ...")); if (is_ia32_l_ShlD(node)) - new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, + new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg, new_op1, new_op2, noreg, nomem); else - new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, + new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg, new_op1, new_op2, noreg, nomem); copy_ia32_Immop_attr(new_op, imm_op); } else { /* This is a normal ShiftD */ - DB((mod, LEVEL_1, "ShiftD binop ...")); + DB((dbg, LEVEL_1, "ShiftD binop ...")); if (is_ia32_l_ShlD(node)) - new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, + new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_count, nomem); else - new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, + new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_count, nomem); } @@ -3089,48 +3556,50 @@ static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *nod // Matze: node has unsupported format (6inputs) //set_ia32_am_support(new_op, ia32_am_Dest); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node)); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node)); set_ia32_emit_cl(new_op); return new_op; } -static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) { - return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0), +static ir_node *gen_ia32_l_ShlD(ir_node *node) { + return gen_lowered_64bit_shifts(node, get_irn_n(node, 0), get_irn_n(node, 1), get_irn_n(node, 2)); } -static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) { - return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0), +static ir_node *gen_ia32_l_ShrD(ir_node *node) { + return gen_lowered_64bit_shifts(node, get_irn_n(node, 0), get_irn_n(node, 1), get_irn_n(node, 2)); } /** * In case SSE Unit is used, the node is transformed into a vfst + xLoad. */ -static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) { - ia32_code_gen_t *cg = env->cg; - ir_node *res = NULL; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *ptr = get_irn_n(node, 0); - ir_node *val = get_irn_n(node, 1); - ir_node *new_val = transform_node(env, val); - ir_node *mem = get_irn_n(node, 2); - ir_node *noreg, *new_ptr, *new_mem; +static ir_node *gen_ia32_l_X87toSSE(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *val = get_irn_n(node, 1); + ir_node *new_val = transform_node(val); + ia32_code_gen_t *cg = env.cg; + ir_node *res = NULL; + ir_graph *irg = env.irg; + dbg_info *dbgi; + ir_node *noreg, *new_ptr, *new_mem; + ir_node *ptr, *mem; if (USE_SSE2(cg)) { return new_val; } - noreg = ia32_new_NoReg_gp(cg); - new_mem = transform_node(env, mem); - new_ptr = transform_node(env, ptr); + mem = get_irn_n(node, 2); + new_mem = transform_node(mem); + ptr = get_irn_n(node, 0); + new_ptr = transform_node(ptr); + noreg = ia32_new_NoReg_gp(cg); + dbgi = get_irn_dbg_info(node); /* Store x87 -> MEM */ - res = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem); + res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem); set_ia32_frame_ent(res, get_ia32_frame_ent(node)); set_ia32_use_frame(res); set_ia32_ls_mode(res, get_ia32_ls_mode(node)); @@ -3139,14 +3608,14 @@ static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) { set_ia32_op_type(res, ia32_AddrModeD); /* Load MEM -> SSE */ - res = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, res); + res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res); set_ia32_frame_ent(res, get_ia32_frame_ent(node)); set_ia32_use_frame(res); set_ia32_ls_mode(res, get_ia32_ls_mode(node)); set_ia32_am_support(res, ia32_am_Source); set_ia32_am_flavour(res, ia32_B); set_ia32_op_type(res, ia32_AddrModeS); - res = new_rd_Proj(dbg, irg, block, res, mode_E, pn_ia32_xLoad_res); + res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res); return res; } @@ -3154,30 +3623,31 @@ static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) { /** * In case SSE Unit is used, the node is transformed into a xStore + vfld. */ -static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) { - ia32_code_gen_t *cg = env->cg; - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *res = NULL; - ir_node *ptr = get_irn_n(node, 0); - ir_node *val = get_irn_n(node, 1); - ir_node *mem = get_irn_n(node, 2); - ir_entity *fent = get_ia32_frame_ent(node); - ir_mode *lsmode = get_ia32_ls_mode(node); - ir_node *new_val = transform_node(env, val); - ir_node *noreg, *new_ptr, *new_mem; - int offs = 0; - - if (!USE_SSE2(cg)) { +static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *val = get_irn_n(node, 1); + ir_node *new_val = transform_node(val); + ia32_code_gen_t *cg = env.cg; + ir_graph *irg = env.irg; + ir_node *res = NULL; + ir_entity *fent = get_ia32_frame_ent(node); + ir_mode *lsmode = get_ia32_ls_mode(node); + int offs = 0; + ir_node *noreg, *new_ptr, *new_mem; + ir_node *ptr, *mem; + dbg_info *dbgi; + + if (! USE_SSE2(cg)) { /* SSE unit is not used -> skip this node. */ return new_val; } - noreg = ia32_new_NoReg_gp(cg); - new_val = transform_node(env, val); - new_ptr = transform_node(env, ptr); - new_mem = transform_node(env, mem); + ptr = get_irn_n(node, 0); + new_ptr = transform_node(ptr); + mem = get_irn_n(node, 2); + new_mem = transform_node(mem); + noreg = ia32_new_NoReg_gp(cg); + dbgi = get_irn_dbg_info(node); /* Store SSE -> MEM */ if (is_ia32_xLoad(skip_Proj(new_val))) { @@ -3188,7 +3658,7 @@ static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) { ptr = get_irn_n(ld, 0); offs = get_ia32_am_offs_int(ld); } else { - res = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem); + res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem); set_ia32_frame_ent(res, fent); set_ia32_use_frame(res); set_ia32_ls_mode(res, lsmode); @@ -3199,7 +3669,7 @@ static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) { } /* Load MEM -> x87 */ - res = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem); + res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem); set_ia32_frame_ent(res, fent); set_ia32_use_frame(res); set_ia32_ls_mode(res, lsmode); @@ -3207,7 +3677,7 @@ static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) { set_ia32_am_support(res, ia32_am_Source); set_ia32_am_flavour(res, ia32_B); set_ia32_op_type(res, ia32_AddrModeS); - res = new_rd_Proj(dbg, irg, block, res, lsmode, pn_ia32_vfld_res); + res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res); return res; } @@ -3225,31 +3695,31 @@ static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) { /** * the BAD transformer. */ -static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) { +static ir_node *bad_transform(ir_node *node) { panic("No transform function for %+F available.\n", node); return NULL; } -static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) { +static ir_node *gen_End(ir_node *node) { /* end has to be duplicated manually because we need a dynamic in array */ - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - int i, arity; - ir_node *new_end; + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = transform_node(get_nodes_block(node)); + int i, arity; + ir_node *new_end; - new_end = new_ir_node(dbg, irg, block, op_End, mode_X, -1, NULL); + new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL); copy_node_attr(node, new_end); - duplicate_deps(env, node, new_end); + duplicate_deps(node, new_end); set_irg_end(irg, new_end); set_new_node(new_end, new_end); /* transform preds */ arity = get_irn_arity(node); - for(i = 0; i < arity; ++i) { - ir_node *in = get_irn_n(node, i); - ir_node *new_in = transform_node(env, in); + for (i = 0; i < arity; ++i) { + ir_node *in = get_irn_n(node, i); + ir_node *new_in = transform_node(in); add_End_keepalive(new_end, new_in); } @@ -3257,24 +3727,24 @@ static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) { return new_end; } -static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *start_block = env->old_anchors[anchor_start_block]; - ir_node *block; - int i, arity; +static ir_node *gen_Block(ir_node *node) { + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *start_block = env.old_anchors[anchor_start_block]; + ir_node *block; + int i, arity; /* * We replace the ProjX from the start node with a jump, * so the startblock has no preds anymore now */ - if(node == start_block) { - return new_rd_Block(dbg, irg, 0, NULL); + if (node == start_block) { + return new_rd_Block(dbgi, irg, 0, NULL); } /* we use the old blocks for now, because jumps allow cycles in the graph * we have to fix this later */ - block = new_ir_node(dbg, irg, NULL, get_irn_op(node), get_irn_mode(node), + block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node), get_irn_arity(node), get_irn_in(node) + 1); copy_node_attr(node, block); @@ -3285,80 +3755,80 @@ static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) { /* put the preds in the worklist */ arity = get_irn_arity(node); - for(i = 0; i < arity; ++i) { + for (i = 0; i < arity; ++i) { ir_node *in = get_irn_n(node, i); - pdeq_putr(env->worklist, in); + pdeq_putr(env.worklist, in); } return block; } -static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - ir_node *block = transform_node(env, get_nodes_block(node)); - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *pred = get_Proj_pred(node); - ir_node *new_pred = transform_node(env, pred); - long proj = get_Proj_proj(node); - - if(proj == pn_be_AddSP_res) { - ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack); - arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]); +static ir_node *gen_Proj_be_AddSP(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = transform_node(pred); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + long proj = get_Proj_proj(node); + + if (proj == pn_be_AddSP_res) { + ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack); + arch_set_irn_register(env.cg->arch_env, res, &ia32_gp_regs[REG_ESP]); return res; - } else if(proj == pn_be_AddSP_M) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_AddSP_M); + } else if (proj == pn_be_AddSP_M) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M); } assert(0); return new_rd_Unknown(irg, get_irn_mode(node)); } -static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - ir_node *block = transform_node(env, get_nodes_block(node)); - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *pred = get_Proj_pred(node); - ir_node *new_pred = transform_node(env, pred); - long proj = get_Proj_proj(node); - - if(proj == pn_be_SubSP_res) { - ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack); - arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]); +static ir_node *gen_Proj_be_SubSP(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = transform_node(pred); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + long proj = get_Proj_proj(node); + + if (proj == pn_be_SubSP_res) { + ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack); + arch_set_irn_register(env.cg->arch_env, res, &ia32_gp_regs[REG_ESP]); return res; - } else if(proj == pn_be_SubSP_M) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_SubSP_M); + } else if (proj == pn_be_SubSP_M) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M); } assert(0); return new_rd_Unknown(irg, get_irn_mode(node)); } -static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - ir_node *block = transform_node(env, get_nodes_block(node)); - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *pred = get_Proj_pred(node); - ir_node *new_pred = transform_node(env, pred); - long proj = get_Proj_proj(node); +static ir_node *gen_Proj_Load(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = transform_node(pred); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + long proj = get_Proj_proj(node); /* renumber the proj */ - if(is_ia32_Load(new_pred)) { - if(proj == pn_Load_res) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Load_res); - } else if(proj == pn_Load_M) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Load_M); + if (is_ia32_Load(new_pred)) { + if (proj == pn_Load_res) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res); + } else if (proj == pn_Load_M) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M); } - } else if(is_ia32_xLoad(new_pred)) { - if(proj == pn_Load_res) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_xLoad_res); - } else if(proj == pn_Load_M) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_xLoad_M); + } else if (is_ia32_xLoad(new_pred)) { + if (proj == pn_Load_res) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res); + } else if (proj == pn_Load_M) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M); } - } else if(is_ia32_vfld(new_pred)) { - if(proj == pn_Load_res) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfld_res); - } else if(proj == pn_Load_M) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfld_M); + } else if (is_ia32_vfld(new_pred)) { + if (proj == pn_Load_res) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res); + } else if (proj == pn_Load_M) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M); } } @@ -3366,47 +3836,46 @@ static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) { return new_rd_Unknown(irg, get_irn_mode(node)); } -static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_mode *mode = get_irn_mode(node); - - ir_node *pred = get_Proj_pred(node); - ir_node *new_pred = transform_node(env, pred); - long proj = get_Proj_proj(node); +static ir_node *gen_Proj_DivMod(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = transform_node(pred); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + long proj = get_Proj_proj(node); assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)); - switch(get_irn_opcode(pred)) { + switch (get_irn_opcode(pred)) { case iro_Div: - switch(proj) { + switch (proj) { case pn_Div_M: - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Div_res: - return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); default: break; } break; case iro_Mod: - switch(proj) { + switch (proj) { case pn_Mod_M: - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Mod_res: - return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); default: break; } break; case iro_DivMod: - switch(proj) { + switch (proj) { case pn_DivMod_M: - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); case pn_DivMod_res_div: - return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); case pn_DivMod_res_mod: - return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); default: break; } @@ -3419,25 +3888,21 @@ static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) { return new_rd_Unknown(irg, mode); } -static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node) -{ - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_mode *mode = get_irn_mode(node); - - ir_node *pred = get_Proj_pred(node); - ir_node *new_pred = transform_node(env, pred); - long proj = get_Proj_proj(node); +static ir_node *gen_Proj_CopyB(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = transform_node(pred); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + long proj = get_Proj_proj(node); switch(proj) { case pn_CopyB_M_regular: - if(is_ia32_CopyB_i(new_pred)) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, - pn_ia32_CopyB_i_M); - } else if(is_ia32_CopyB(new_pred)) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, - pn_ia32_CopyB_M); + if (is_ia32_CopyB_i(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M); + } else if (is_ia32_CopyB(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M); } break; default: @@ -3448,22 +3913,20 @@ static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node) return new_rd_Unknown(irg, mode); } -static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node) -{ - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_mode *mode = get_irn_mode(node); - - ir_node *pred = get_Proj_pred(node); - ir_node *new_pred = transform_node(env, pred); - long proj = get_Proj_proj(node); +static ir_node *gen_Proj_l_vfdiv(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = transform_node(pred); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + long proj = get_Proj_proj(node); - switch(proj) { + switch (proj) { case pn_ia32_l_vfdiv_M: - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M); case pn_ia32_l_vfdiv_res: - return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfdiv_res); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res); default: assert(0); } @@ -3471,34 +3934,28 @@ static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node) return new_rd_Unknown(irg, mode); } -static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node) -{ - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_mode *mode = get_irn_mode(node); - - ir_node *pred = get_Proj_pred(node); - ir_node *new_pred = transform_node(env, pred); - long proj = get_Proj_proj(node); +static ir_node *gen_Proj_Quot(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = transform_node(pred); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + long proj = get_Proj_proj(node); switch(proj) { case pn_Quot_M: - if(is_ia32_xDiv(new_pred)) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, - pn_ia32_xDiv_M); - } else if(is_ia32_vfdiv(new_pred)) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_M, - pn_ia32_vfdiv_M); + if (is_ia32_xDiv(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M); + } else if (is_ia32_vfdiv(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M); } break; case pn_Quot_res: - if(is_ia32_xDiv(new_pred)) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_E, - pn_ia32_xDiv_res); - } else if(is_ia32_vfdiv(new_pred)) { - return new_rd_Proj(dbg, irg, block, new_pred, mode_E, - pn_ia32_vfdiv_res); + if (is_ia32_xDiv(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res); + } else if (is_ia32_vfdiv(new_pred)) { + return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res); } break; default: @@ -3509,26 +3966,25 @@ static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node) return new_rd_Unknown(irg, mode); } -static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - //dbg_info *dbg = get_irn_dbg_info(node); - dbg_info *dbg = NULL; - ir_node *block = transform_node(env, get_nodes_block(node)); - - ir_node *res = new_rd_ia32_LdTls(dbg, irg, block, mode_Iu); +static ir_node *gen_Proj_tls(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_graph *irg = env.irg; + dbg_info *dbgi = NULL; + ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu); return res; } -static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - long proj = get_Proj_proj(node); - ir_mode *mode = get_irn_mode(node); - ir_node *block = transform_node(env, get_nodes_block(node)); - ir_node *sse_load; - ir_node *call = get_Proj_pred(node); - ir_node *new_call = transform_node(env, call); +static ir_node *gen_Proj_be_Call(ir_node *node) { + ir_node *block = transform_node(get_nodes_block(node)); + ir_node *call = get_Proj_pred(node); + ir_node *new_call = transform_node(call); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + long proj = get_Proj_proj(node); + ir_mode *mode = get_irn_mode(node); + ir_node *sse_load; + const arch_register_class_t *cls; /* The following is kinda tricky: If we're using SSE, then we have to * move the result value of the call in floating point registers to an @@ -3536,39 +3992,38 @@ static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) { * after the call, we have to make sure to correctly make the * MemProj and the result Proj use these 2 nodes */ - if(proj == pn_be_Call_M_regular) { + if (proj == pn_be_Call_M_regular) { // get new node for result, are we doing the sse load/store hack? ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res); ir_node *call_res_new; ir_node *call_res_pred = NULL; - if(call_res != NULL) { - call_res_new = transform_node(env, call_res); + if (call_res != NULL) { + call_res_new = transform_node(call_res); call_res_pred = get_Proj_pred(call_res_new); } - if(call_res_pred == NULL || be_is_Call(call_res_pred)) { - return new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular); + if (call_res_pred == NULL || be_is_Call(call_res_pred)) { + return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular); } else { assert(is_ia32_xLoad(call_res_pred)); - return new_rd_Proj(dbg, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M); + return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M); } } - if(proj == pn_be_Call_first_res && mode_is_float(mode) - && USE_SSE2(env->cg)) { + if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env.cg)) { ir_node *fstp; ir_node *frame = get_irg_frame(irg); - ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *noreg = ia32_new_NoReg_gp(env.cg); ir_node *p; ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular); ir_node *keepin[1]; const arch_register_class_t *cls; /* in case there is no memory output: create one to serialize the copy FPU -> SSE */ - call_mem = new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular); + call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular); /* store st(0) onto stack */ - fstp = new_rd_ia32_GetST0(dbg, irg, block, frame, noreg, call_mem); + fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem); set_ia32_ls_mode(fstp, mode); set_ia32_op_type(fstp, ia32_AddrModeD); @@ -3577,15 +4032,14 @@ static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) { set_ia32_am_support(fstp, ia32_am_Dest); /* load into SSE register */ - sse_load = new_rd_ia32_xLoad(dbg, irg, block, frame, noreg, fstp); + sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp); set_ia32_ls_mode(sse_load, mode); set_ia32_op_type(sse_load, ia32_AddrModeS); set_ia32_use_frame(sse_load); set_ia32_am_flavour(sse_load, ia32_am_B); set_ia32_am_support(sse_load, ia32_am_Source); - //mproj = new_rd_Proj(dbg, irg, block, sse_load, mode_M, pn_ia32_xLoad_M); - sse_load = new_rd_Proj(dbg, irg, block, sse_load, mode_E, pn_ia32_xLoad_res); + sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res); /* now: create new Keep whith all former ins and one additional in - the result Proj */ @@ -3598,69 +4052,80 @@ static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) { assert(be_is_Keep(p) && "Keep expected."); /* keep the result */ - cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1); + cls = arch_get_irn_reg_class(env.cg->arch_env, sse_load, -1); keepin[0] = sse_load; be_new_Keep(cls, irg, block, 1, keepin); return sse_load; } - /* transform call modes to the mode_Iu or mode_E */ - if(mode_is_float(mode)) { - mode = mode_E; - } else if(mode != mode_M) { - mode = mode_Iu; + /* transform call modes */ + if (mode_is_data(mode)) { + cls = arch_get_irn_reg_class(env.cg->arch_env, node, -1); + mode = cls->mode; } - return new_rd_Proj(dbg, irg, block, new_call, mode, proj); + return new_rd_Proj(dbgi, irg, block, new_call, mode, proj); } -static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_node *pred = get_Proj_pred(node); - long proj = get_Proj_proj(node); +static ir_node *gen_Proj(ir_node *node) { + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *pred = get_Proj_pred(node); + long proj = get_Proj_proj(node); - if(is_Store(pred) || be_is_FrameStore(pred)) { - if(proj == pn_Store_M) { - return transform_node(env, pred); + if (is_Store(pred) || be_is_FrameStore(pred)) { + if (proj == pn_Store_M) { + return transform_node(pred); } else { assert(0); return new_r_Bad(irg); } - } else if(is_Load(pred) || be_is_FrameLoad(pred)) { - return gen_Proj_Load(env, node); - } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) { - return gen_Proj_DivMod(env, node); - } else if(is_CopyB(pred)) { - return gen_Proj_CopyB(env, node); - } else if(is_Quot(pred)) { - return gen_Proj_Quot(env, node); - } else if(is_ia32_l_vfdiv(pred)) { - return gen_Proj_l_vfdiv(env, node); - } else if(be_is_SubSP(pred)) { - return gen_Proj_be_SubSP(env, node); - } else if(be_is_AddSP(pred)) { - return gen_Proj_be_AddSP(env, node); - } else if(be_is_Call(pred)) { - return gen_Proj_be_Call(env, node); - } else if(get_irn_op(pred) == op_Start) { - if(proj == pn_Start_X_initial_exec) { + } else if (is_Load(pred) || be_is_FrameLoad(pred)) { + return gen_Proj_Load(node); + } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) { + return gen_Proj_DivMod(node); + } else if (is_CopyB(pred)) { + return gen_Proj_CopyB(node); + } else if (is_Quot(pred)) { + return gen_Proj_Quot(node); + } else if (is_ia32_l_vfdiv(pred)) { + return gen_Proj_l_vfdiv(node); + } else if (be_is_SubSP(pred)) { + return gen_Proj_be_SubSP(node); + } else if (be_is_AddSP(pred)) { + return gen_Proj_be_AddSP(node); + } else if (be_is_Call(pred)) { + return gen_Proj_be_Call(node); + } else if (get_irn_op(pred) == op_Start) { + if (proj == pn_Start_X_initial_exec) { ir_node *block = get_nodes_block(pred); ir_node *jump; - block = transform_node(env, block); - // we exchange the ProjX with a jump - jump = new_rd_Jmp(dbg, irg, block); + /* we exchange the ProjX with a jump */ + block = transform_node(block); + jump = new_rd_Jmp(dbgi, irg, block); ir_fprintf(stderr, "created jump: %+F\n", jump); return jump; } - if(node == env->old_anchors[anchor_tls]) { - return gen_Proj_tls(env, node); + if (node == env.old_anchors[anchor_tls]) { + return gen_Proj_tls(node); + } + } else { + ir_node *new_pred = transform_node(pred); + ir_node *block = transform_node(get_nodes_block(node)); + ir_mode *mode = get_irn_mode(node); + if (mode_needs_gp_reg(mode)) { + ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu, + get_Proj_proj(node)); +#ifdef DEBUG_libfirm + new_proj->node_nr = node->node_nr; +#endif + return new_proj; } } - return duplicate_node(env, node); + return duplicate_node(node); } /** @@ -3702,6 +4167,7 @@ static void register_transformers(void) { GEN(Store); GEN(Cond); + GEN(ASM); GEN(CopyB); //GEN(Mux); BAD(Mux); @@ -3732,7 +4198,7 @@ static void register_transformers(void) { GEN(ia32_l_vfsub); GEN(ia32_l_vfild); GEN(ia32_l_Load); - GEN(ia32_l_vfist); + /* GEN(ia32_l_vfist); TODO */ GEN(ia32_l_Store); GEN(ia32_l_X87toSSE); GEN(ia32_l_SSEtoX87); @@ -3782,78 +4248,83 @@ static void register_transformers(void) { #undef BAD } -static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node, - ir_node *new_node) +static void duplicate_deps(ir_node *old_node, ir_node *new_node) { int i; int deps = get_irn_deps(old_node); - for(i = 0; i < deps; ++i) { - ir_node *dep = get_irn_dep(old_node, i); - ir_node *new_dep = transform_node(env, dep); + for (i = 0; i < deps; ++i) { + ir_node *dep = get_irn_dep(old_node, i); + ir_node *new_dep = transform_node(dep); add_irn_dep(new_node, new_dep); } } -static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node) +static ir_node *duplicate_node(ir_node *node) { - ir_graph *irg = env->irg; - dbg_info *dbg = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_op *op = get_irn_op(node); - ir_node *block; - ir_node *new_node; - int i, arity; - - block = transform_node(env, get_nodes_block(node)); + ir_node *block = transform_node(get_nodes_block(node)); + ir_graph *irg = env.irg; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_op *op = get_irn_op(node); + ir_node *new_node; + int i, arity; arity = get_irn_arity(node); - if(op->opar == oparity_dynamic) { - new_node = new_ir_node(dbg, irg, block, op, mode, -1, NULL); - for(i = 0; i < arity; ++i) { + if (op->opar == oparity_dynamic) { + new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL); + for (i = 0; i < arity; ++i) { ir_node *in = get_irn_n(node, i); - in = transform_node(env, in); + in = transform_node(in); add_irn_n(new_node, in); } } else { ir_node **ins = alloca(arity * sizeof(ins[0])); - for(i = 0; i < arity; ++i) { + for (i = 0; i < arity; ++i) { ir_node *in = get_irn_n(node, i); - ins[i] = transform_node(env, in); + ins[i] = transform_node(in); } - new_node = new_ir_node(dbg, irg, block, op, mode, arity, ins); + new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins); } copy_node_attr(node, new_node); - duplicate_deps(env, node, new_node); + duplicate_deps(node, new_node); + +#ifdef DEBUG_libfirm + new_node->node_nr = node->node_nr; +#endif return new_node; } -static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node) -{ +/** + * Calls transformation function for given node and marks it visited. + */ +static ir_node *transform_node(ir_node *node) { ir_node *new_node; - ir_op *op = get_irn_op(node); + ir_op *op; - if(irn_visited(node)) { - assert(get_new_node(node) != NULL); - return get_new_node(node); + if (irn_visited(node)) { + new_node = get_new_node(node); + assert(new_node != NULL); + return new_node; } mark_irn_visited(node); DEBUG_ONLY(set_new_node(node, NULL)); + op = get_irn_op(node); if (op->ops.generic) { transform_func *transform = (transform_func *)op->ops.generic; - new_node = (*transform)(env, node); + new_node = transform(node); assert(new_node != NULL); } else { - new_node = duplicate_node(env, node); + new_node = duplicate_node(node); } - //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node); + DB((dbg, LEVEL_4, "%+F -> %+F\n", node, new_node)); set_new_node(node, new_node); mark_irn_visited(new_node); @@ -3861,126 +4332,131 @@ static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node) return new_node; } -static void fix_loops(ia32_transform_env_t *env, ir_node *node) -{ +/** + * Rewire nodes which are potential loops (like Phis) to avoid endless loops. + */ +static void fix_loops(ir_node *node) { int i, arity; - if(irn_visited(node)) + if (irn_visited(node)) return; + mark_irn_visited(node); - assert(node_is_in_irgs_storage(env->irg, node)); + assert(node_is_in_irgs_storage(env.irg, node)); - if(!is_Block(node)) { - ir_node *block = get_nodes_block(node); - ir_node *new_block = (ir_node*) get_irn_link(block); + if (! is_Block(node)) { + ir_node *block = get_nodes_block(node); + ir_node *new_block = (ir_node *)get_irn_link(block); - if(new_block != NULL) { + if (new_block != NULL) { set_nodes_block(node, new_block); block = new_block; } - fix_loops(env, block); + fix_loops(block); } arity = get_irn_arity(node); - for(i = 0; i < arity; ++i) { + for (i = 0; i < arity; ++i) { ir_node *in = get_irn_n(node, i); - ir_node *new = (ir_node*) get_irn_link(in); + ir_node *nw = (ir_node *)get_irn_link(in); - if(new != NULL && new != in) { - set_irn_n(node, i, new); - in = new; + if (nw != NULL && nw != in) { + set_irn_n(node, i, nw); + in = nw; } - fix_loops(env, in); + fix_loops(in); } arity = get_irn_deps(node); - for(i = 0; i < arity; ++i) { + for (i = 0; i < arity; ++i) { ir_node *in = get_irn_dep(node, i); - ir_node *new = (ir_node*) get_irn_link(in); + ir_node *nw = (ir_node *)get_irn_link(in); - if(new != NULL && new != in) { - set_irn_dep(node, i, new); - in = new; + if (nw != NULL && nw != in) { + set_irn_dep(node, i, nw); + in = nw; } - fix_loops(env, in); + fix_loops(in); } } -static void pre_transform_node(ir_node **place, ia32_transform_env_t *env) +static void pre_transform_node(ir_node **place) { - if(*place == NULL) + if (*place == NULL) return; - *place = transform_node(env, *place); + *place = transform_node(*place); } -static void transform_nodes(ia32_code_gen_t *cg) -{ - int i; +/** + * Transforms all nodes. Deletes the old obstack and creates a new one. + */ +static void transform_nodes(ia32_code_gen_t *cg) { + int i; ir_graph *irg = cg->irg; - ir_node *old_end; - ia32_transform_env_t env; + ir_node *old_end; hook_dead_node_elim(irg, 1); inc_irg_visited(irg); - env.irg = irg; - env.cg = cg; - env.visited = get_irg_visited(irg); - env.worklist = new_pdeq(); + env.irg = irg; + env.cg = cg; + env.visited = get_irg_visited(irg); + env.worklist = new_pdeq(); env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0])); - DEBUG_ONLY(env.mod = cg->mod); old_end = get_irg_end(irg); /* put all anchor nodes in the worklist */ - for(i = 0; i < anchor_max; ++i) { + for (i = 0; i < anchor_max; ++i) { ir_node *anchor = irg->anchors[i]; - if(anchor == NULL) + + if (anchor == NULL) continue; pdeq_putr(env.worklist, anchor); - // remember anchor + /* remember anchor */ env.old_anchors[i] = anchor; - // and set it to NULL to make sure we don't accidently use it + /* and set it to NULL to make sure we don't accidently use it */ irg->anchors[i] = NULL; } - // pre transform some anchors (so they are available in the other transform - // functions) - set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad])); - set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem])); - set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block])); - set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start])); - set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame])); - - pre_transform_node(&cg->unknown_gp, &env); - pre_transform_node(&cg->unknown_vfp, &env); - pre_transform_node(&cg->unknown_xmm, &env); - pre_transform_node(&cg->noreg_gp, &env); - pre_transform_node(&cg->noreg_vfp, &env); - pre_transform_node(&cg->noreg_xmm, &env); + /* pre transform some anchors (so they are available in the other transform + * functions) */ + set_irg_bad(irg, transform_node(env.old_anchors[anchor_bad])); + set_irg_no_mem(irg, transform_node(env.old_anchors[anchor_no_mem])); + set_irg_start_block(irg, transform_node(env.old_anchors[anchor_start_block])); + set_irg_start(irg, transform_node(env.old_anchors[anchor_start])); + set_irg_frame(irg, transform_node(env.old_anchors[anchor_frame])); + + pre_transform_node(&cg->unknown_gp); + pre_transform_node(&cg->unknown_vfp); + pre_transform_node(&cg->unknown_xmm); + pre_transform_node(&cg->noreg_gp); + pre_transform_node(&cg->noreg_vfp); + pre_transform_node(&cg->noreg_xmm); /* process worklist (this should transform all nodes in the graph) */ - while(!pdeq_empty(env.worklist)) { + while (! pdeq_empty(env.worklist)) { ir_node *node = pdeq_getl(env.worklist); - transform_node(&env, node); + transform_node(node); } /* fix loops and set new anchors*/ inc_irg_visited(irg); - for(i = 0; i < anchor_max; ++i) { + for (i = 0; i < anchor_max; ++i) { ir_node *anchor = env.old_anchors[i]; - if(anchor == NULL) + + if (anchor == NULL) continue; anchor = get_irn_link(anchor); - fix_loops(&env, anchor); + fix_loops(anchor); assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor); irg->anchors[i] = anchor; } @@ -4066,7 +4542,7 @@ static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg ir_node *cmp = get_Proj_pred(in); ir_node *cmp_a = get_Cmp_left(cmp); ir_node *cmp_b = get_Cmp_right(cmp); - dbg_info *dbg = get_irn_dbg_info(cmp); + dbg_info *dbgi = get_irn_dbg_info(cmp); ir_graph *irg = get_irn_irg(cmp); ir_node *block = get_nodes_block(cmp); ir_node *noreg = ia32_new_NoReg_gp(cg); @@ -4081,25 +4557,22 @@ static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg ir_mode *m = get_irn_mode(cmp_a); /* SSE FPU */ if (! mode_is_float(m)) { - cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode); - cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode); - } - else if (m == mode_F) { + cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode); + cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode); + } else if (m == mode_F) { /* we convert cmp values always to double, to get correct bitmask with cmpsd */ - cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a); - cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b); + cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a); + cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b); } - new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem); + new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem); set_ia32_pncode(new_op, pnc); SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp)); - } - else { + } else { /* x87 FPU */ assert(0); } - } - else { + } else { /* integer Psi */ construct_binop_func *set_func = NULL; @@ -4110,21 +4583,19 @@ static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg if (USE_SSE2(cg)) { /* SSE FPU */ set_func = new_rd_ia32_xCmpSet; - } - else { + } else { /* x87 FPU */ set_func = new_rd_ia32_vfCmpSet; } pnc &= 7; /* fp compare -> int compare */ - } - else { + } else { /* 2nd case: compare operand are integer too */ set_func = new_rd_ia32_CmpSet; } - new_op = set_func(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem); - if(!mode_is_signed(mode)) + new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem); + if (! mode_is_signed(mode)) pnc |= ia32_pn_Cmp_Unsigned; set_ia32_pncode(new_op, pnc); @@ -4133,8 +4604,7 @@ static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg /* the the new compare as in */ set_irn_n(cond, i, new_op); - } - else { + } else { /* another complex condition */ transform_psi_cond(in, mode, cg); } @@ -4143,8 +4613,8 @@ static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg /** * The Psi selector can be a tree of compares combined with "And"s and "Or"s. - * We create a Set node, respectively a xCmp in case the Psi is a float, for each - * compare, which causes the compare result to be stores in a register. The + * We create a Set node, respectively a xCmp in case the Psi is a float, for + * each compare, which causes the compare result to be stored in a register. The * "And"s and "Or"s are transformed later, we just have to set their mode right. */ void ia32_transform_psi_cond_tree(ir_node *node, void *env) { @@ -4160,11 +4630,13 @@ void ia32_transform_psi_cond_tree(ir_node *node, void *env) { psi_sel = get_Psi_cond(node, 0); /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */ - if (is_Proj(psi_sel)) + if (is_Proj(psi_sel)) { + assert(is_Cmp(get_Proj_pred(psi_sel))); return; + } //mode = get_irn_mode(node); - // TODO this is probably wrong... + // TODO probably wrong... mode = mode_Iu; transform_psi_cond(psi_sel, mode, cg); @@ -4173,17 +4645,24 @@ void ia32_transform_psi_cond_tree(ir_node *node, void *env) { block = get_nodes_block(node); /* we need to compare the evaluated condition tree with 0 */ - mode = get_irn_mode(node); + mode = get_irn_mode(node); if (mode_is_float(mode)) { - psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode); /* BEWARE: new_r_Const_long works for floating point as well */ - new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0)); + ir_node *zero = new_r_Const_long(irg, block, mode, 0); + + psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode); + new_cmp = new_r_Cmp(irg, block, psi_sel, zero); new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne); - } - else { - new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode_Iu, 0)); + } else { + ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0); + new_cmp = new_r_Cmp(irg, block, psi_sel, zero); new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt); } set_Psi_cond(node, 0, new_cmp); } + +void ia32_init_transform(void) +{ + FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform"); +}