X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=8319bbeb1384b4bb9c008ed22274f47f64d18b72;hb=e3b765fcef0e337f4fe2e17d57d2fbaf1912ec79;hp=72478f51b06ca0035e3927041ac7f80a4b8424f8;hpb=ca21c59ea00ff05918de26952e91ac39f1589e01;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 72478f51b..8319bbeb1 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -38,33 +38,31 @@ #include "irprog_t.h" #include "iredges_t.h" #include "irgmod.h" -#include "irvrfy.h" #include "ircons.h" #include "irgwalk.h" #include "irprintf.h" #include "debug.h" #include "irdom.h" +#include "iropt.h" #include "error.h" #include "array_t.h" -#include "height.h" +#include "heights.h" -#include "../benode.h" -#include "../besched.h" -#include "../beabi.h" -#include "../beutil.h" -#include "../beirg.h" -#include "../betranshlp.h" -#include "../be_t.h" +#include "benode.h" +#include "besched.h" +#include "beabi.h" +#include "beutil.h" +#include "beirg.h" +#include "betranshlp.h" +#include "be_t.h" #include "bearch_ia32_t.h" #include "ia32_common_transform.h" #include "ia32_nodes_attr.h" #include "ia32_transform.h" #include "ia32_new_nodes.h" -#include "ia32_map_regs.h" #include "ia32_dbg_stat.h" #include "ia32_optimize.h" -#include "ia32_util.h" #include "ia32_address_mode.h" #include "ia32_architecture.h" @@ -73,27 +71,14 @@ /* define this to construct SSE constants instead of load them */ #undef CONSTRUCT_SSE_CONST - -#define SFP_SIGN "0x80000000" -#define DFP_SIGN "0x8000000000000000" -#define SFP_ABS "0x7FFFFFFF" -#define DFP_ABS "0x7FFFFFFFFFFFFFFF" -#define DFP_INTMAX "9223372036854775807" -#define ULL_BIAS "18446744073709551616" - -#define ENT_SFP_SIGN ".LC_ia32_sfp_sign" -#define ENT_DFP_SIGN ".LC_ia32_dfp_sign" -#define ENT_SFP_ABS ".LC_ia32_sfp_abs" -#define ENT_DFP_ABS ".LC_ia32_dfp_abs" -#define ENT_ULL_BIAS ".LC_ia32_ull_bias" - -#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode) +#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode) #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode) DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) +static ir_node *old_initial_fpcw = NULL; static ir_node *initial_fpcw = NULL; -int no_pic_adjust; +int ia32_no_pic_adjust; typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, @@ -155,7 +140,7 @@ static bool is_Const_Minus_1(ir_node *node) */ static bool is_simple_x87_Const(ir_node *node) { - tarval *tv = get_Const_tarval(node); + ir_tarval *tv = get_Const_tarval(node); if (tarval_is_null(tv) || tarval_is_one(tv)) return true; @@ -168,8 +153,8 @@ static bool is_simple_x87_Const(ir_node *node) */ static bool is_simple_sse_Const(ir_node *node) { - tarval *tv = get_Const_tarval(node); - ir_mode *mode = get_tarval_mode(tv); + ir_tarval *tv = get_Const_tarval(node); + ir_mode *mode = get_tarval_mode(tv); if (mode == mode_F) return true; @@ -201,8 +186,11 @@ static bool is_simple_sse_Const(ir_node *node) */ static ir_node *get_symconst_base(void) { - if (env_cg->birg->main_env->options->pic) { - return arch_code_generator_get_pic_base(env_cg); + ir_graph *irg = current_ir_graph; + + if (be_get_irg_options(irg)->pic) { + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + return arch_env->impl->get_pic_base(irg); } return noreg_GP; @@ -213,21 +201,23 @@ static ir_node *get_symconst_base(void) */ static ir_node *gen_Const(ir_node *node) { - ir_node *old_block = get_nodes_block(node); - ir_node *block = be_transform_node(old_block); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); + ir_node *old_block = get_nodes_block(node); + ir_node *block = be_transform_node(old_block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_tarval *tv = get_Const_tarval(node); assert(is_Const(node)); if (mode_is_float(mode)) { - ir_node *res = NULL; - ir_node *load; - ir_node *base; - ir_entity *floatent; + ir_graph *irg = get_irn_irg(node); + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + ia32_isa_t *isa = (ia32_isa_t*) arch_env; + ir_node *res = NULL; + ir_node *load; + ir_entity *floatent; if (ia32_cg_config.use_sse2) { - tarval *tv = get_Const_tarval(node); if (tarval_is_null(tv)) { load = new_bd_ia32_xZero(dbgi, block); set_ia32_ls_mode(load, mode); @@ -258,6 +248,7 @@ static ir_node *gen_Const(ir_node *node) set_ia32_ls_mode(load, mode); res = load; } else { + ir_node *base; #ifdef CONSTRUCT_SSE_CONST if (mode == mode_D) { unsigned val = get_tarval_sub_bits(tv, 0) | @@ -283,22 +274,22 @@ static ir_node *gen_Const(ir_node *node) } } #endif /* CONSTRUCT_SSE_CONST */ - floatent = create_float_const_entity(node); + floatent = ia32_create_float_const_entity(isa, tv, NULL); base = get_symconst_base(); load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem, mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); res = new_r_Proj(load, mode_xmm, pn_ia32_xLoad_res); } } else { - if (is_Const_null(node)) { + if (tarval_is_null(tv)) { load = new_bd_ia32_vfldz(dbgi, block); res = load; set_ia32_ls_mode(load, mode); - } else if (is_Const_one(node)) { + } else if (tarval_is_one(tv)) { load = new_bd_ia32_vfld1(dbgi, block); res = load; set_ia32_ls_mode(load, mode); @@ -306,7 +297,7 @@ static ir_node *gen_Const(ir_node *node) ir_mode *ls_mode; ir_node *base; - floatent = create_float_const_entity(node); + floatent = ia32_create_float_const_entity(isa, tv, NULL); /* create_float_const_ent is smart and sometimes creates smaller entities */ ls_mode = get_type_mode(get_entity_type(floatent)); @@ -315,7 +306,7 @@ static ir_node *gen_Const(ir_node *node) ls_mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); res = new_r_Proj(load, mode_vfp, pn_ia32_vfld_res); } } @@ -323,12 +314,9 @@ static ir_node *gen_Const(ir_node *node) end: #endif /* CONSTRUCT_SSE_CONST */ SET_IA32_ORIG_NODE(load, node); - - be_dep_on_frame(load); return res; } else { /* non-float mode */ ir_node *cnst; - tarval *tv = get_Const_tarval(node); long val; tv = tarval_convert_to(tv, mode_Iu); @@ -342,7 +330,6 @@ end: cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val); SET_IA32_ORIG_NODE(cnst, node); - be_dep_on_frame(cnst); return cnst; } } @@ -360,9 +347,9 @@ static ir_node *gen_SymConst(ir_node *node) if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) - cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E); + cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_D); else - cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E); + cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, ia32_mode_E); set_ia32_am_sc(cnst, get_SymConst_entity(node)); set_ia32_use_frame(cnst); } else { @@ -372,73 +359,33 @@ static ir_node *gen_SymConst(ir_node *node) panic("backend only support symconst_addr_ent (at %+F)", node); } entity = get_SymConst_entity(node); - cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0); + if (get_entity_owner(entity) == get_tls_type()) { + ir_node *tls_base = new_bd_ia32_LdTls(NULL, block); + ir_node *lea = new_bd_ia32_Lea(dbgi, block, tls_base, noreg_GP); + set_ia32_am_sc(lea, entity); + cnst = lea; + } else { + cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0); + } } SET_IA32_ORIG_NODE(cnst, node); - be_dep_on_frame(cnst); return cnst; } -/** - * Create a float type for the given mode and cache it. - * - * @param mode the mode for the float type (might be integer mode for SSE2 types) - * @param align alignment - */ -static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) +static ir_type *make_array_type(ir_type *tp) { - ir_type *tp; - - assert(align <= 16); - - if (mode == mode_Iu) { - static ir_type *int_Iu[16] = {NULL, }; - - if (int_Iu[align] == NULL) { - int_Iu[align] = tp = new_type_primitive(mode); - /* set the specified alignment */ - set_type_alignment_bytes(tp, align); - } - return int_Iu[align]; - } else if (mode == mode_Lu) { - static ir_type *int_Lu[16] = {NULL, }; - - if (int_Lu[align] == NULL) { - int_Lu[align] = tp = new_type_primitive(mode); - /* set the specified alignment */ - set_type_alignment_bytes(tp, align); - } - return int_Lu[align]; - } else if (mode == mode_F) { - static ir_type *float_F[16] = {NULL, }; - - if (float_F[align] == NULL) { - float_F[align] = tp = new_type_primitive(mode); - /* set the specified alignment */ - set_type_alignment_bytes(tp, align); - } - return float_F[align]; - } else if (mode == mode_D) { - static ir_type *float_D[16] = {NULL, }; - - if (float_D[align] == NULL) { - float_D[align] = tp = new_type_primitive(mode); - /* set the specified alignment */ - set_type_alignment_bytes(tp, align); - } - return float_D[align]; - } else { - static ir_type *float_E[16] = {NULL, }; - - if (float_E[align] == NULL) { - float_E[align] = tp = new_type_primitive(mode); - /* set the specified alignment */ - set_type_alignment_bytes(tp, align); - } - return float_E[align]; - } + unsigned alignment = get_type_alignment_bytes(tp); + unsigned size = get_type_size_bytes(tp); + ir_type *res = new_type_array(1, tp); + set_type_alignment_bytes(res, alignment); + set_array_bounds_int(res, 0, 0, 2); + if (alignment > size) + size = alignment; + set_type_size_bytes(res, 2 * size); + set_type_state(res, layout_fixed); + return res; } /** @@ -449,33 +396,27 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) static ir_type *ia32_create_float_array(ir_type *tp) { ir_mode *mode = get_type_mode(tp); - unsigned align = get_type_alignment_bytes(tp); ir_type *arr; - assert(align <= 16); - if (mode == mode_F) { - static ir_type *float_F[16] = {NULL, }; + static ir_type *float_F; - if (float_F[align] != NULL) - return float_F[align]; - arr = float_F[align] = new_type_array(1, tp); + arr = float_F; + if (arr == NULL) + arr = float_F = make_array_type(tp); } else if (mode == mode_D) { - static ir_type *float_D[16] = {NULL, }; + static ir_type *float_D; - if (float_D[align] != NULL) - return float_D[align]; - arr = float_D[align] = new_type_array(1, tp); + arr = float_D; + if (arr == NULL) + arr = float_D = make_array_type(tp); } else { - static ir_type *float_E[16] = {NULL, }; + static ir_type *float_E; - if (float_E[align] != NULL) - return float_E[align]; - arr = float_E[align] = new_type_array(1, tp); + arr = float_E; + if (arr == NULL) + arr = float_E = make_array_type(tp); } - set_type_alignment_bytes(arr, align); - set_type_size_bytes(arr, 2 * get_type_size_bytes(tp)); - set_type_state(arr, layout_fixed); return arr; } @@ -483,58 +424,56 @@ static ir_type *ia32_create_float_array(ir_type *tp) ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) { static const struct { - const char *ent_name; + const char *name; const char *cnst_str; - char mode; - unsigned char align; + char mode; } names [ia32_known_const_max] = { - { ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */ - { ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */ - { ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */ - { ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */ - { ENT_ULL_BIAS, ULL_BIAS, 2, 4 } /* ia32_ULLBIAS */ + { "C_sfp_sign", "0x80000000", 0 }, + { "C_dfp_sign", "0x8000000000000000", 1 }, + { "C_sfp_abs", "0x7FFFFFFF", 0 }, + { "C_dfp_abs", "0x7FFFFFFFFFFFFFFF", 1 }, + { "C_ull_bias", "0x10000000000000000", 2 } }; static ir_entity *ent_cache[ia32_known_const_max]; - const char *ent_name, *cnst_str; - ir_type *tp; - ir_entity *ent; - tarval *tv; - ir_mode *mode; - - ent_name = names[kct].ent_name; - if (! ent_cache[kct]) { - cnst_str = names[kct].cnst_str; + ir_entity *ent = ent_cache[kct]; + if (ent == NULL) { + ir_graph *irg = current_ir_graph; + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + ia32_isa_t *isa = (ia32_isa_t*) arch_env; + const char *cnst_str = names[kct].cnst_str; + ident *name = new_id_from_str(names[kct].name); + ir_mode *mode; + ir_tarval *tv; switch (names[kct].mode) { case 0: mode = mode_Iu; break; case 1: mode = mode_Lu; break; - default: mode = mode_F; break; + case 2: mode = mode_F; break; + default: panic("internal compiler error (ia32_gen_fp_known_const)"); } - tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode); - tp = ia32_create_float_type(mode, names[kct].align); + tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode); - if (kct == ia32_ULLBIAS) - tp = ia32_create_float_array(tp); - ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp); + if (kct == ia32_ULLBIAS) { + ir_type *type = ia32_get_prim_type(mode_F); + ir_type *atype = ia32_create_float_array(type); + ir_initializer_t *initializer; - set_entity_ld_ident(ent, get_entity_ident(ent)); - add_entity_linkage(ent, IR_LINKAGE_CONSTANT); - set_entity_visibility(ent, ir_visibility_local); + ent = new_entity(get_glob_type(), name, atype); - if (kct == ia32_ULLBIAS) { - ir_initializer_t *initializer = create_initializer_compound(2); + set_entity_ld_ident(ent, name); + set_entity_visibility(ent, ir_visibility_private); + add_entity_linkage(ent, IR_LINKAGE_CONSTANT); + initializer = create_initializer_compound(2); set_initializer_compound_value(initializer, 0, create_initializer_tarval(get_mode_null(mode))); set_initializer_compound_value(initializer, 1, create_initializer_tarval(tv)); - set_entity_initializer(ent, initializer); } else { - set_entity_initializer(ent, create_initializer_tarval(tv)); + ent = ia32_create_float_const_entity(isa, tv, name); } - /* cache the entry */ ent_cache[kct] = ent; } @@ -589,10 +528,10 @@ static int ia32_use_source_address_mode(ir_node *block, ir_node *node, return 0; /* don't do AM if other node inputs depend on the load (via mem-proj) */ - if (other != NULL && prevents_AM(block, load, other)) + if (other != NULL && ia32_prevents_AM(block, load, other)) return 0; - if (other2 != NULL && prevents_AM(block, load, other2)) + if (other2 != NULL && ia32_prevents_AM(block, load, other2)) return 0; return 1; @@ -616,7 +555,7 @@ static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem) { /* construct load address */ memset(addr, 0, sizeof(addr[0])); - ia32_create_address_mode(addr, ptr, 0); + ia32_create_address_mode(addr, ptr, ia32_create_am_normal); addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP; addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP; @@ -634,11 +573,16 @@ static void build_address(ia32_address_mode_t *am, ir_node *node, /* floating point immediates */ if (is_Const(node)) { - ir_entity *entity = create_float_const_entity(node); + ir_graph *irg = get_irn_irg(node); + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + ia32_isa_t *isa = (ia32_isa_t*) arch_env; + ir_tarval *tv = get_Const_tarval(node); + ir_entity *entity = ia32_create_float_const_entity(isa, tv, NULL); addr->base = get_symconst_base(); addr->index = noreg_GP; addr->mem = nomem; addr->symconst_ent = entity; + addr->tls_segment = false; addr->use_frame = 1; am->ls_mode = get_type_mode(get_entity_type(entity)); am->pinned = op_pin_state_floats; @@ -667,6 +611,7 @@ static void set_address(ir_node *node, const ia32_address_t *addr) set_ia32_am_scale(node, addr->scale); set_ia32_am_sc(node, addr->symconst_ent); set_ia32_am_offs_int(node, addr->offset); + set_ia32_am_tls_segment(node, addr->tls_segment); if (addr->symconst_sign) set_ia32_am_sc_sign(node); if (addr->use_frame) @@ -709,8 +654,8 @@ static int is_downconv(const ir_node *node) return 0; /* we only want to skip the conv when we're the only user - * (not optimal but for now...) - */ + * (because this test is used in the context of address-mode selection + * and we don't want to use address mode for multiple users) */ if (get_irn_n_edges(node) > 1) return 0; @@ -722,7 +667,7 @@ static int is_downconv(const ir_node *node) get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode); } -/* Skip all Down-Conv's on a given node and return the resulting node. */ +/** Skip all Down-Conv's on a given node and return the resulting node. */ ir_node *ia32_skip_downconv(ir_node *node) { while (is_downconv(node)) @@ -731,6 +676,37 @@ ir_node *ia32_skip_downconv(ir_node *node) return node; } +static bool is_sameconv(ir_node *node) +{ + ir_mode *src_mode; + ir_mode *dest_mode; + + if (!is_Conv(node)) + return 0; + + /* we only want to skip the conv when we're the only user + * (because this test is used in the context of address-mode selection + * and we don't want to use address mode for multiple users) */ + if (get_irn_n_edges(node) > 1) + return 0; + + src_mode = get_irn_mode(get_Conv_op(node)); + dest_mode = get_irn_mode(node); + return + ia32_mode_needs_gp_reg(src_mode) && + ia32_mode_needs_gp_reg(dest_mode) && + get_mode_size_bits(dest_mode) == get_mode_size_bits(src_mode); +} + +/** Skip all signedness convs */ +static ir_node *ia32_skip_sameconv(ir_node *node) +{ + while (is_sameconv(node)) + node = get_Conv_op(node); + + return node; +} + static ir_node *create_upconv(ir_node *node, ir_node *orig_node) { ir_mode *mode = get_irn_mode(node); @@ -798,21 +774,26 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, if (op1 != NULL) { op1 = ia32_skip_downconv(op1); } + } else { + op2 = ia32_skip_sameconv(op2); + if (op1 != NULL) { + op1 = ia32_skip_sameconv(op1); + } } /* match immediates. firm nodes are normalized: constants are always on the * op2 input */ new_op2 = NULL; if (!(flags & match_try_am) && use_immediate) { - new_op2 = try_create_Immediate(op2, 0); + new_op2 = ia32_try_create_Immediate(op2, 0); } if (new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) { - build_address(am, op2, 0); + build_address(am, op2, ia32_create_am_normal); new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); if (mode_is_float(mode)) { - new_op2 = ia32_new_NoReg_vfp(env_cg); + new_op2 = ia32_new_NoReg_vfp(current_ir_graph); } else { new_op2 = noreg_GP; } @@ -821,10 +802,10 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, use_am && ia32_use_source_address_mode(block, op1, op2, other_op, flags)) { ir_node *noreg; - build_address(am, op1, 0); + build_address(am, op1, ia32_create_am_normal); if (mode_is_float(mode)) { - noreg = ia32_new_NoReg_vfp(env_cg); + noreg = ia32_new_NoReg_vfp(current_ir_graph); } else { noreg = noreg_GP; } @@ -834,11 +815,10 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } else { new_op1 = be_transform_node(op2); new_op2 = noreg; - am->ins_permuted = 1; + am->ins_permuted = true; } am->op_type = ia32_AddrModeS; } else { - ir_mode *mode; am->op_type = ia32_Normal; if (flags & match_try_am) { @@ -948,12 +928,12 @@ enum { n_ia32_l_binop_right, /**< ia32 right input */ n_ia32_l_binop_eflags /**< ia32 eflags input */ }; -COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left) -COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right) -COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags) -COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_minuend, n_Sbb_minuend) -COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend) -COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags) +COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Adc_left, n_Adc_left) +COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Adc_right, n_Adc_right) +COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Adc_eflags, n_Adc_eflags) +COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Sbb_minuend, n_Sbb_minuend) +COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend) +COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Sbb_eflags, n_Sbb_eflags) /** * Construct a binary operation which also consumes the eflags. @@ -996,14 +976,10 @@ static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, static ir_node *get_fpcw(void) { - ir_node *fpcw; if (initial_fpcw != NULL) return initial_fpcw; - fpcw = be_abi_get_ignore_irn(env_cg->birg->abi, - &ia32_fp_cw_regs[REG_FPCW]); - initial_fpcw = be_transform_node(fpcw); - + initial_fpcw = be_transform_node(old_initial_fpcw); return initial_fpcw; } @@ -1029,8 +1005,12 @@ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, match_flags_t flags = match_commutative; /* happens for div nodes... */ - if (mode == mode_T) - mode = get_divop_resmod(node); + if (mode == mode_T) { + if (is_Div(node)) + mode = get_Div_resmode(node); + else + panic("can't determine mode"); + } /* cannot use address mode with long double on x87 */ if (get_mode_size_bits(mode) <= 64) @@ -1069,15 +1049,19 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, { dbg_info *dbgi; ir_node *block, *new_block, *new_op1, *new_op2, *new_node; + ir_mode *mode = get_irn_mode(node); - assert(! mode_is_float(get_irn_mode(node))); + assert(! mode_is_float(mode)); assert(flags & match_immediate); assert((flags & ~(match_mode_neutral | match_immediate)) == 0); + if (get_mode_modulo_shift(mode) != 32) + panic("modulo shift!=32 not supported by ia32 backend"); + if (flags & match_mode_neutral) { op1 = ia32_skip_downconv(op1); new_op1 = be_transform_node(op1); - } else if (get_mode_size_bits(get_irn_mode(node)) != 32) { + } else if (get_mode_size_bits(mode) != 32) { new_op1 = create_upconv(op1, node); } else { new_op1 = be_transform_node(op1); @@ -1103,8 +1087,12 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, /* lowered shift instruction may have a dependency operand, handle it here */ if (get_irn_arity(node) == 3) { /* we have a dependency */ - ir_node *new_dep = be_transform_node(get_irn_n(node, 2)); - add_irn_dep(new_node, new_dep); + ir_node* dep = get_irn_n(node, 2); + if (get_irn_n_edges(dep) > 1) { + /* ... which has at least one user other than 'node' */ + ir_node *new_dep = be_transform_node(dep); + add_irn_dep(new_node, new_dep); + } } return new_node; @@ -1140,10 +1128,12 @@ static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, return new_node; } -static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, +static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, ia32_address_t *addr) { - ir_node *base, *index, *res; + ir_node *base; + ir_node *idx; + ir_node *res; base = addr->base; if (base == NULL) { @@ -1152,14 +1142,26 @@ static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, base = be_transform_node(base); } - index = addr->index; - if (index == NULL) { - index = noreg_GP; + idx = addr->index; + if (idx == NULL) { + idx = noreg_GP; } else { - index = be_transform_node(index); + idx = be_transform_node(idx); } - res = new_bd_ia32_Lea(dbgi, block, base, index); + /* segment overrides are ineffective for Leas :-( so we have to patch + * around... */ + if (addr->tls_segment) { + ir_node *tls_base = new_bd_ia32_LdTls(NULL, block); + assert(addr->symconst_ent != NULL); + if (base == noreg_GP) + base = tls_base; + else + base = new_bd_ia32_Lea(dbgi, block, tls_base, base); + addr->tls_segment = false; + } + + res = new_bd_ia32_Lea(dbgi, block, base, idx); set_address(res, addr); return res; @@ -1175,6 +1177,118 @@ static int am_has_immediates(const ia32_address_t *addr) || addr->frame_entity || addr->use_frame; } +typedef ir_node* (*new_shiftd_func)(dbg_info *dbgi, ir_node *block, + ir_node *high, ir_node *low, + ir_node *count); + +/** + * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs: + * op1 - target to be shifted + * op2 - contains bits to be shifted into target + * op3 - shift count + * Only op3 can be an immediate. + */ +static ir_node *gen_64bit_shifts(dbg_info *dbgi, ir_node *block, + ir_node *high, ir_node *low, ir_node *count, + new_shiftd_func func) +{ + ir_node *new_block = be_transform_node(block); + ir_node *new_high = be_transform_node(high); + ir_node *new_low = be_transform_node(low); + ir_node *new_count; + ir_node *new_node; + + /* the shift amount can be any mode that is bigger than 5 bits, since all + * other bits are ignored anyway */ + while (is_Conv(count) && + get_irn_n_edges(count) == 1 && + mode_is_int(get_irn_mode(count))) { + assert(get_mode_size_bits(get_irn_mode(count)) >= 5); + count = get_Conv_op(count); + } + new_count = create_immediate_or_transform(count, 0); + + new_node = func(dbgi, new_block, new_high, new_low, new_count); + return new_node; +} + +/** + * test wether 2 values result in 'x' and '32-x' when interpreted as a shift + * value. + */ +static bool is_complementary_shifts(ir_node *value1, ir_node *value2) +{ + if (is_Const(value1) && is_Const(value2)) { + ir_tarval *tv1 = get_Const_tarval(value1); + ir_tarval *tv2 = get_Const_tarval(value2); + if (tarval_is_long(tv1) && tarval_is_long(tv2)) { + long v1 = get_tarval_long(tv1); + long v2 = get_tarval_long(tv2); + return v1 <= v2 && v2 == 32-v1; + } + } + return false; +} + +static ir_node *match_64bit_shift(ir_node *node) +{ + ir_node *op1 = get_binop_left(node); + ir_node *op2 = get_binop_right(node); + assert(is_Or(node) || is_Add(node)); + + if (is_Shr(op1)) { + ir_node *tmp = op1; + op1 = op2; + op2 = tmp; + } + + /* match ShlD operation */ + if (is_Shl(op1) && is_Shr(op2)) { + ir_node *shl_right = get_Shl_right(op1); + ir_node *shl_left = get_Shl_left(op1); + ir_node *shr_right = get_Shr_right(op2); + ir_node *shr_left = get_Shr_left(op2); + /* constant ShlD operation */ + if (is_complementary_shifts(shl_right, shr_right)) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + return gen_64bit_shifts(dbgi, block, shl_left, shr_left, shl_right, + new_bd_ia32_ShlD); + } + /* constant ShrD operation */ + if (is_complementary_shifts(shr_right, shl_right)) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + return gen_64bit_shifts(dbgi, block, shr_left, shl_left, shr_right, + new_bd_ia32_ShrD); + } + /* lower_dw produces the following for ShlD: + * Or(Shr(Shr(high,1),Not(c)),Shl(low,c)) */ + if (is_Shr(shr_left) && is_Not(shr_right) + && is_Const_1(get_Shr_right(shr_left)) + && get_Not_op(shr_right) == shl_right) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *val_h = get_Shr_left(shr_left); + return gen_64bit_shifts(dbgi, block, shl_left, val_h, shl_right, + new_bd_ia32_ShlD); + } + /* lower_dw produces the following for ShrD: + * Or(Shl(Shl(high,1),Not(c)), Shr(low,c)) */ + if (is_Shl(shl_left) && is_Not(shl_right) + && is_Const_1(get_Shl_right(shl_left)) + && get_Not_op(shl_right) == shr_right) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *val_h = get_Shl_left(shl_left); + return gen_64bit_shifts(dbgi, block, shr_left, val_h, shr_right, + new_bd_ia32_ShrD); + } + } + + return NULL; +} + /** * Creates an ia32 Add. * @@ -1190,6 +1304,10 @@ static ir_node *gen_Add(ir_node *node) ia32_address_t addr; ia32_address_mode_t am; + new_node = match_64bit_shift(node); + if (new_node != NULL) + return new_node; + if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) return gen_binop(node, op1, op2, new_bd_ia32_xAdd, @@ -1222,7 +1340,6 @@ static ir_node *gen_Add(ir_node *node) if (addr.base == NULL && addr.index == NULL) { new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent, addr.symconst_sign, 0, addr.offset); - be_dep_on_frame(new_node); SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -1337,8 +1454,8 @@ static ir_node *gen_And(ir_node *node) /* is it a zero extension? */ if (is_Const(op2)) { - tarval *tv = get_Const_tarval(op2); - long v = get_tarval_long(tv); + ir_tarval *tv = get_Const_tarval(op2); + long v = get_tarval_long(tv); if (v == 0xFF || v == 0xFFFF) { dbg_info *dbgi = get_irn_dbg_info(node); @@ -1361,8 +1478,6 @@ static ir_node *gen_And(ir_node *node) match_commutative | match_mode_neutral | match_am | match_immediate); } - - /** * Creates an ia32 Or. * @@ -1372,6 +1487,11 @@ static ir_node *gen_Or(ir_node *node) { ir_node *op1 = get_Or_left(node); ir_node *op2 = get_Or_right(node); + ir_node *res; + + res = match_64bit_shift(node); + if (res != NULL) + return res; assert (! mode_is_float(get_irn_mode(node))); return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative @@ -1457,8 +1577,13 @@ static ir_node *transform_AM_mem(ir_node *const block, ins[n++] = be_transform_node(pred); } - ins[n++] = am_mem; + if (n==1 && ins[0] == am_mem) { + return am_mem; + /* creating a new Sync and relying on CSE may fail, + * if am_mem is a ProjM, which does not yet verify. */ + } + ins[n++] = am_mem; return new_r_Sync(block, n, ins); } else { ir_node *ins[2]; @@ -1485,7 +1610,6 @@ static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block, (void)orig; if (ia32_cg_config.use_short_sex_eax) { ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block); - be_dep_on_frame(pval); res = new_bd_ia32_Cltd(dbgi, block, val, pval); } else { ir_node *imm31 = ia32_create_Immediate(NULL, 0, 31); @@ -1496,14 +1620,15 @@ static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block, } /** - * Generates an ia32 DivMod with additional infrastructure for the + * Generates an ia32 Div with additional infrastructure for the * register allocator if needed. */ static ir_node *create_Div(ir_node *node) { - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + int throws_exception = ir_throws_exception(node); ir_node *mem; ir_node *new_mem; ir_node *op1; @@ -1528,12 +1653,6 @@ static ir_node *create_Div(ir_node *node) mem = get_Mod_mem(node); mode = get_Mod_resmode(node); break; - case iro_DivMod: - op1 = get_DivMod_left(node); - op2 = get_DivMod_right(node); - mem = get_DivMod_mem(node); - mode = get_DivMod_resmode(node); - break; default: panic("invalid divmod node %+F", node); } @@ -1551,12 +1670,12 @@ static ir_node *create_Div(ir_node *node) addr->index, new_mem, am.new_op2, am.new_op1, sign_extension); } else { sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0, 0); - be_dep_on_frame(sign_extension); new_node = new_bd_ia32_Div(dbgi, new_block, addr->base, addr->index, new_mem, am.new_op2, am.new_op1, sign_extension); } + ir_set_throws_exception(new_node, throws_exception); set_irn_pinned(new_node, get_irn_pinned(node)); @@ -1581,36 +1700,20 @@ static ir_node *gen_Mod(ir_node *node) */ static ir_node *gen_Div(ir_node *node) { - return create_Div(node); -} - -/** - * Generates an ia32 DivMod. - */ -static ir_node *gen_DivMod(ir_node *node) -{ - return create_Div(node); -} - - - -/** - * Creates an ia32 floating Div. - * - * @return The created ia32 xDiv node - */ -static ir_node *gen_Quot(ir_node *node) -{ - ir_node *op1 = get_Quot_left(node); - ir_node *op2 = get_Quot_right(node); + ir_mode *mode = get_Div_resmode(node); + if (mode_is_float(mode)) { + ir_node *op1 = get_Div_left(node); + ir_node *op2 = get_Div_right(node); - if (ia32_cg_config.use_sse2) { - return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am); - } else { - return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv); + if (ia32_cg_config.use_sse2) { + return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am); + } else { + return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv); + } } -} + return create_Div(node); +} /** * Creates an ia32 Shl. @@ -1652,8 +1755,8 @@ static ir_node *gen_Shrs(ir_node *node) ir_node *right = get_Shrs_right(node); if (is_Const(right)) { - tarval *tv = get_Const_tarval(right); - long val = get_tarval_long(tv); + ir_tarval *tv = get_Const_tarval(right); + long val = get_tarval_long(tv); if (val == 31) { /* this is a sign extension */ dbg_info *dbgi = get_irn_dbg_info(node); @@ -1669,8 +1772,8 @@ static ir_node *gen_Shrs(ir_node *node) ir_node *shl_left = get_Shl_left(left); ir_node *shl_right = get_Shl_right(left); if (is_Const(shl_right)) { - tarval *tv1 = get_Const_tarval(right); - tarval *tv2 = get_Const_tarval(shl_right); + ir_tarval *tv1 = get_Const_tarval(right); + ir_tarval *tv2 = get_Const_tarval(shl_right); if (tv1 == tv2 && tarval_is_long(tv1)) { long val = get_tarval_long(tv1); if (val == 16 || val == 24) { @@ -1736,39 +1839,14 @@ static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) */ static ir_node *gen_Rotl(ir_node *node) { - ir_node *rotate = NULL; ir_node *op1 = get_Rotl_left(node); ir_node *op2 = get_Rotl_right(node); - /* Firm has only RotL, so we are looking for a right (op2) - operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e", - that means we can create a RotR instead of an Add and a RotL */ - - if (is_Add(op2)) { - ir_node *add = op2; - ir_node *left = get_Add_left(add); - ir_node *right = get_Add_right(add); - if (is_Const(right)) { - tarval *tv = get_Const_tarval(right); - ir_mode *mode = get_irn_mode(node); - long bits = get_mode_size_bits(mode); - - if (is_Minus(left) && - tarval_is_long(tv) && - get_tarval_long(tv) == bits && - bits == 32) - { - DB((dbg, LEVEL_1, "RotL into RotR ... ")); - rotate = gen_Ror(node, op1, get_Minus_op(left)); - } - } - } - - if (rotate == NULL) { - rotate = gen_Rol(node, op1, op2); + if (is_Minus(op2)) { + return gen_Ror(node, op1, get_Minus_op(op2)); } - return rotate; + return gen_Rol(node, op1, op2); } @@ -1794,7 +1872,7 @@ static ir_node *gen_Minus(ir_node *node) /* TODO: non-optimal... if we have many xXors, then we should * rather create a load for the const and use that instead of * several AM nodes... */ - ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg); + ir_node *noreg_xmm = ia32_new_NoReg_xmm(current_ir_graph); new_node = new_bd_ia32_xXor(dbgi, block, get_symconst_base(), noreg_GP, nomem, new_op, noreg_xmm); @@ -1832,64 +1910,42 @@ static ir_node *gen_Not(ir_node *node) return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral); } - - -/** - * Transforms an Abs node. - * - * @return The created ia32 Abs node - */ -static ir_node *gen_Abs(ir_node *node) +static ir_node *create_float_abs(dbg_info *dbgi, ir_node *block, ir_node *op, + bool negate, ir_node *node) { - ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); - ir_node *op = get_Abs_op(node); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *new_op; + ir_mode *mode = get_irn_mode(op); + ir_node *new_op = be_transform_node(op); ir_node *new_node; int size; ir_entity *ent; - if (mode_is_float(mode)) { - new_op = be_transform_node(op); - - if (ia32_cg_config.use_sse2) { - ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg); - new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(), - noreg_GP, nomem, new_op, noreg_fp); - - size = get_mode_size_bits(mode); - ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS); - - set_ia32_am_sc(new_node, ent); + assert(mode_is_float(mode)); - SET_IA32_ORIG_NODE(new_node, node); + if (ia32_cg_config.use_sse2) { + ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph); + new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(), + noreg_GP, nomem, new_op, noreg_fp); - set_ia32_op_type(new_node, ia32_AddrModeS); - set_ia32_ls_mode(new_node, mode); - } else { - new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op); - SET_IA32_ORIG_NODE(new_node, node); - } - } else { - ir_node *xor, *sign_extension; + size = get_mode_size_bits(mode); + ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS); - if (get_mode_size_bits(mode) == 32) { - new_op = be_transform_node(op); - } else { - new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node); - } + set_ia32_am_sc(new_node, ent); - sign_extension = create_sex_32_64(dbgi, new_block, new_op, node); + SET_IA32_ORIG_NODE(new_node, node); - xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, - nomem, new_op, sign_extension); - SET_IA32_ORIG_NODE(xor, node); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode); - new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, - nomem, xor, sign_extension); + /* TODO, implement -Abs case */ + assert(!negate); + } else { + new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op); SET_IA32_ORIG_NODE(new_node, node); + if (negate) { + new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node); + SET_IA32_ORIG_NODE(new_node, node); + } } return new_node; @@ -1909,85 +1965,147 @@ static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) return new_bd_ia32_Bt(dbgi, new_block, op1, op2); } -/** - * Transform a node returning a "flag" result. - * - * @param node the node to transform - * @param pnc_out the compare mode to use - */ -static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) +static ia32_condition_code_t relation_to_condition_code(ir_relation relation, + ir_mode *mode) { - ir_node *flags; - ir_node *new_op; - ir_node *new_block; - dbg_info *dbgi; - - /* we have a Cmp as input */ - if (is_Proj(node)) { - ir_node *pred = get_Proj_pred(node); - if (is_Cmp(pred)) { - pn_Cmp pnc = get_Proj_proj(node); - if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) { - ir_node *l = get_Cmp_left(pred); - ir_node *r = get_Cmp_right(pred); - if (is_And(l)) { - ir_node *la = get_And_left(l); - ir_node *ra = get_And_right(l); - if (is_Shl(la)) { - ir_node *c = get_Shl_left(la); - if (is_Const_1(c) && (is_Const_0(r) || r == la)) { - /* (1 << n) & ra) */ - ir_node *n = get_Shl_right(la); - flags = gen_bt(pred, ra, n); - /* we must generate a Jc/Jnc jump */ - pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge; - if (r == la) - pnc ^= pn_Cmp_Leg; - *pnc_out = ia32_pn_Cmp_unsigned | pnc; - return flags; - } - } - if (is_Shl(ra)) { - ir_node *c = get_Shl_left(ra); - if (is_Const_1(c) && (is_Const_0(r) || r == ra)) { - /* la & (1 << n)) */ - ir_node *n = get_Shl_right(ra); - flags = gen_bt(pred, la, n); - /* we must generate a Jc/Jnc jump */ - pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge; - if (r == ra) - pnc ^= pn_Cmp_Leg; - *pnc_out = ia32_pn_Cmp_unsigned | pnc; - return flags; - } - } - } - } - /* add ia32 compare flags */ - { - ir_node *l = get_Cmp_left(pred); - ir_mode *mode = get_irn_mode(l); - if (mode_is_float(mode)) - pnc |= ia32_pn_Cmp_float; - else if (! mode_is_signed(mode)) - pnc |= ia32_pn_Cmp_unsigned; + if (mode_is_float(mode)) { + switch (relation) { + case ir_relation_equal: return ia32_cc_float_equal; + case ir_relation_less: return ia32_cc_float_below; + case ir_relation_less_equal: return ia32_cc_float_below_equal; + case ir_relation_greater: return ia32_cc_float_above; + case ir_relation_greater_equal: return ia32_cc_float_above_equal; + case ir_relation_less_greater: return ia32_cc_not_equal; + case ir_relation_less_equal_greater: return ia32_cc_not_parity; + case ir_relation_unordered: return ia32_cc_parity; + case ir_relation_unordered_equal: return ia32_cc_equal; + case ir_relation_unordered_less: return ia32_cc_float_unordered_below; + case ir_relation_unordered_less_equal: + return ia32_cc_float_unordered_below_equal; + case ir_relation_unordered_greater: + return ia32_cc_float_unordered_above; + case ir_relation_unordered_greater_equal: + return ia32_cc_float_unordered_above_equal; + case ir_relation_unordered_less_greater: + return ia32_cc_float_not_equal; + case ir_relation_false: + case ir_relation_true: + /* should we introduce a jump always/jump never? */ + break; + } + panic("Unexpected float pnc"); + } else if (mode_is_signed(mode)) { + switch (relation) { + case ir_relation_unordered_equal: + case ir_relation_equal: return ia32_cc_equal; + case ir_relation_unordered_less: + case ir_relation_less: return ia32_cc_less; + case ir_relation_unordered_less_equal: + case ir_relation_less_equal: return ia32_cc_less_equal; + case ir_relation_unordered_greater: + case ir_relation_greater: return ia32_cc_greater; + case ir_relation_unordered_greater_equal: + case ir_relation_greater_equal: return ia32_cc_greater_equal; + case ir_relation_unordered_less_greater: + case ir_relation_less_greater: return ia32_cc_not_equal; + case ir_relation_less_equal_greater: + case ir_relation_unordered: + case ir_relation_false: + case ir_relation_true: + /* introduce jump always/jump never? */ + break; + } + panic("Unexpected pnc"); + } else { + switch (relation) { + case ir_relation_unordered_equal: + case ir_relation_equal: return ia32_cc_equal; + case ir_relation_unordered_less: + case ir_relation_less: return ia32_cc_below; + case ir_relation_unordered_less_equal: + case ir_relation_less_equal: return ia32_cc_below_equal; + case ir_relation_unordered_greater: + case ir_relation_greater: return ia32_cc_above; + case ir_relation_unordered_greater_equal: + case ir_relation_greater_equal: return ia32_cc_above_equal; + case ir_relation_unordered_less_greater: + case ir_relation_less_greater: return ia32_cc_not_equal; + case ir_relation_less_equal_greater: + case ir_relation_unordered: + case ir_relation_false: + case ir_relation_true: + /* introduce jump always/jump never? */ + break; + } + panic("Unexpected pnc"); + } +} + +static ir_node *get_flags_node_cmp(ir_node *cmp, ia32_condition_code_t *cc_out) +{ + /* must have a Cmp as input */ + ir_relation relation = get_Cmp_relation(cmp); + ir_relation possible; + ir_node *l = get_Cmp_left(cmp); + ir_node *r = get_Cmp_right(cmp); + ir_mode *mode = get_irn_mode(l); + ir_node *flags; + + /* check for bit-test */ + if (ia32_cg_config.use_bt && (relation == ir_relation_equal + || (mode_is_signed(mode) && relation == ir_relation_less_greater) + || (!mode_is_signed(mode) && ((relation & ir_relation_greater_equal) == ir_relation_greater))) + && is_And(l)) { + ir_node *la = get_And_left(l); + ir_node *ra = get_And_right(l); + if (is_Shl(ra)) { + ir_node *tmp = la; + la = ra; + ra = tmp; + } + if (is_Shl(la)) { + ir_node *c = get_Shl_left(la); + if (is_Const_1(c) && is_Const_0(r)) { + /* (1 << n) & ra) */ + ir_node *n = get_Shl_right(la); + flags = gen_bt(cmp, ra, n); + /* the bit is copied into the CF flag */ + if (relation & ir_relation_equal) + *cc_out = ia32_cc_above_equal; /* test for CF=0 */ + else + *cc_out = ia32_cc_below; /* test for CF=1 */ + return flags; } - *pnc_out = pnc; - flags = be_transform_node(pred); - return flags; } } - /* a mode_b value, we have to compare it against 0 */ - dbgi = get_irn_dbg_info(node); - new_block = be_transform_node(get_nodes_block(node)); - new_op = be_transform_node(node); - flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, - new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0); - *pnc_out = pn_Cmp_Lg; + /* the middle-end tries to eliminate impossible relations, so a ptr != 0 + * test becomes ptr > 0. But for x86 an equal comparison is preferable to + * a >0 (we can sometimes eliminate the cmp in favor of flags produced by + * a predecessor node). So add the < bit */ + possible = ir_get_possible_cmp_relations(l, r); + if (((relation & ir_relation_less) && !(possible & ir_relation_greater)) + || ((relation & ir_relation_greater) && !(possible & ir_relation_less))) + relation |= ir_relation_less_greater; + + /* just do a normal transformation of the Cmp */ + *cc_out = relation_to_condition_code(relation, mode); + flags = be_transform_node(cmp); return flags; } +/** + * Transform a node returning a "flag" result. + * + * @param node the node to transform + * @param cc_out the compare mode to use + */ +static ir_node *get_flags_node(ir_node *node, ia32_condition_code_t *cc_out) +{ + assert(is_Cmp(node)); + return get_flags_node_cmp(node, cc_out); +} + /** * Transforms a Load. * @@ -1996,23 +2114,23 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) static ir_node *gen_Load(ir_node *node) { ir_node *old_block = get_nodes_block(node); - ir_node *block = be_transform_node(old_block); - ir_node *ptr = get_Load_ptr(node); - ir_node *mem = get_Load_mem(node); - ir_node *new_mem = be_transform_node(mem); + ir_node *block = be_transform_node(old_block); + ir_node *ptr = get_Load_ptr(node); + ir_node *mem = get_Load_mem(node); + ir_node *new_mem = be_transform_node(mem); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_Load_mode(node); + int throws_exception = ir_throws_exception(node); ir_node *base; - ir_node *index; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_Load_mode(node); - ir_mode *res_mode; + ir_node *idx; ir_node *new_node; ia32_address_t addr; /* construct load address */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, ptr, 0); - base = addr.base; - index = addr.index; + ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); + base = addr.base; + idx = addr.index; if (base == NULL) { base = noreg_GP; @@ -2020,34 +2138,32 @@ static ir_node *gen_Load(ir_node *node) base = be_transform_node(base); } - if (index == NULL) { - index = noreg_GP; + if (idx == NULL) { + idx = noreg_GP; } else { - index = be_transform_node(index); + idx = be_transform_node(idx); } if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) { - new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem, + new_node = new_bd_ia32_xLoad(dbgi, block, base, idx, new_mem, mode); - res_mode = mode_xmm; } else { - new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem, + new_node = new_bd_ia32_vfld(dbgi, block, base, idx, new_mem, mode); - res_mode = mode_vfp; } } else { assert(mode != mode_b); /* create a conv node with address mode for smaller modes */ if (get_mode_size_bits(mode) < 32) { - new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index, + new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, idx, new_mem, noreg_GP, mode); } else { - new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem); + new_node = new_bd_ia32_Load(dbgi, block, base, idx, new_mem); } - res_mode = mode_Iu; } + ir_set_throws_exception(new_node, throws_exception); set_irn_pinned(new_node, get_irn_pinned(node)); set_ia32_op_type(new_node, ia32_AddrModeS); @@ -2055,15 +2171,14 @@ static ir_node *gen_Load(ir_node *node) set_address(new_node, &addr); if (get_irn_pinned(node) == op_pin_state_floats) { - assert(pn_ia32_xLoad_res == pn_ia32_vfld_res - && pn_ia32_vfld_res == pn_ia32_Load_res - && pn_ia32_Load_res == pn_ia32_res); - arch_irn_add_flags(new_node, arch_irn_flags_rematerializable); + assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res + && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res + && (int)pn_ia32_Load_res == (int)pn_ia32_res); + arch_add_irn_flags(new_node, arch_irn_flags_rematerializable); } SET_IA32_ORIG_NODE(new_node, node); - be_dep_on_frame(new_node); return new_node; } @@ -2092,14 +2207,14 @@ static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem, /* don't do AM if other node inputs depend on the load (via mem-proj) */ if (other != NULL && get_nodes_block(other) == block && - heights_reachable_in_block(heights, other, load)) { + heights_reachable_in_block(ia32_heights, other, load)) { return 0; } - if (prevents_AM(block, load, mem)) + if (ia32_prevents_AM(block, load, mem)) return 0; /* Store should be attached to the load via mem */ - assert(heights_reachable_in_block(heights, mem, load)); + assert(heights_reachable_in_block(ia32_heights, mem, load)); return 1; } @@ -2158,7 +2273,8 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node); mem_proj = be_transform_node(am.mem_proj); - be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node); + be_set_transformed_node(am.mem_proj, new_node); + be_set_transformed_node(mem_proj, new_node); return new_node; } @@ -2193,32 +2309,26 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node); mem_proj = be_transform_node(am.mem_proj); - be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node); + be_set_transformed_node(am.mem_proj, new_node); + be_set_transformed_node(mem_proj, new_node); return new_node; } -static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc) -{ - ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu; - return get_negated_pnc(pnc, mode); -} - static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) { - ir_mode *mode = get_irn_mode(node); - ir_node *mux_true = get_Mux_true(node); - ir_node *mux_false = get_Mux_false(node); - ir_node *cond; - ir_node *new_mem; - dbg_info *dbgi; - ir_node *block; - ir_node *new_block; - ir_node *flags; - ir_node *new_node; - bool negated; - pn_Cmp pnc; - ia32_address_t addr; + ir_mode *mode = get_irn_mode(node); + ir_node *mux_true = get_Mux_true(node); + ir_node *mux_false = get_Mux_false(node); + ir_node *cond; + dbg_info *dbgi; + ir_node *block; + ir_node *new_block; + ir_node *flags; + ir_node *new_node; + bool negated; + ia32_condition_code_t cc; + ia32_address_t addr; if (get_mode_size_bits(mode) != 8) return NULL; @@ -2232,21 +2342,20 @@ static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) } cond = get_Mux_sel(node); - flags = get_flags_node(cond, &pnc); + flags = get_flags_node(cond, &cc); /* we can't handle the float special cases with SetM */ - if (pnc & ia32_pn_Cmp_float) + if (cc & ia32_cc_additional_float_cases) return NULL; if (negated) - pnc = ia32_get_negated_pnc(pnc); + cc = ia32_negate_condition_code(cc); build_address_ptr(&addr, ptr, mem); dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); new_block = be_transform_node(block); - new_mem = be_transform_node(mem); new_node = new_bd_ia32_SetccMem(dbgi, new_block, addr.base, - addr.index, addr.mem, flags, pnc); + addr.index, addr.mem, flags, cc); set_address(new_node, &addr); set_ia32_op_type(new_node, ia32_AddrModeD); set_ia32_ls_mode(new_node, mode); @@ -2439,80 +2548,90 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) { ir_mode *mode = get_irn_mode(cns); unsigned size = get_mode_size_bytes(mode); - tarval *tv = get_Const_tarval(cns); + ir_tarval *tv = get_Const_tarval(cns); ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); ir_node *ptr = get_Store_ptr(node); ir_node *mem = get_Store_mem(node); dbg_info *dbgi = get_irn_dbg_info(node); int ofs = 0; - size_t i = 0; + int i = 0; + int throws_exception = ir_throws_exception(node); ir_node *ins[4]; ia32_address_t addr; - assert(size % 4 == 0); - assert(size <= 16); - build_address_ptr(&addr, ptr, mem); do { - unsigned val = - get_tarval_sub_bits(tv, ofs) | - (get_tarval_sub_bits(tv, ofs + 1) << 8) | - (get_tarval_sub_bits(tv, ofs + 2) << 16) | - (get_tarval_sub_bits(tv, ofs + 3) << 24); + unsigned val; + unsigned delta; + ir_mode *mode; + if (size >= 4) { + val= get_tarval_sub_bits(tv, ofs) | + (get_tarval_sub_bits(tv, ofs + 1) << 8) | + (get_tarval_sub_bits(tv, ofs + 2) << 16) | + (get_tarval_sub_bits(tv, ofs + 3) << 24); + delta = 4; + mode = mode_Iu; + } else if (size >= 2) { + val= get_tarval_sub_bits(tv, ofs) | + (get_tarval_sub_bits(tv, ofs + 1) << 8); + delta = 2; + mode = mode_Hu; + } else { + panic("invalid size of Store float to mem (%+F)", node); + } ir_node *imm = ia32_create_Immediate(NULL, 0, val); ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base, addr.index, addr.mem, imm); + ir_node *new_mem = new_r_Proj(new_node, mode_M, pn_ia32_Store_M); + ir_set_throws_exception(new_node, throws_exception); set_irn_pinned(new_node, get_irn_pinned(node)); set_ia32_op_type(new_node, ia32_AddrModeD); - set_ia32_ls_mode(new_node, mode_Iu); + set_ia32_ls_mode(new_node, mode); set_address(new_node, &addr); SET_IA32_ORIG_NODE(new_node, node); assert(i < 4); - ins[i++] = new_node; + ins[i++] = new_mem; - size -= 4; - ofs += 4; - addr.offset += 4; + size -= delta; + ofs += delta; + addr.offset += delta; } while (size != 0); if (i > 1) { return new_rd_Sync(dbgi, new_block, i, ins); } else { - return ins[0]; + return get_Proj_pred(ins[0]); } } /** * Generate a vfist or vfisttp instruction. */ -static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, - ir_node *mem, ir_node *val, ir_node **fist) +static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, + ir_node *index, ir_node *mem, ir_node *val) { - ir_node *new_node; - if (ia32_cg_config.use_fisttp) { /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied if other users exists */ ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val); - ir_node *value = new_r_Proj(vfisttp, mode_E, pn_ia32_vfisttp_res); + ir_node *value = new_r_Proj(vfisttp, ia32_mode_E, pn_ia32_vfisttp_res); be_new_Keep(block, 1, &value); - new_node = new_r_Proj(vfisttp, mode_M, pn_ia32_vfisttp_M); - *fist = vfisttp; + return vfisttp; } else { - ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); + ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph); /* do a fist */ - new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode); - *fist = new_node; + ir_node *vfist = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode); + return vfist; } - return new_node; } + /** * Transforms a general (no special case) Store. * @@ -2527,7 +2646,9 @@ static ir_node *gen_general_Store(ir_node *node) ir_node *ptr = get_Store_ptr(node); ir_node *mem = get_Store_mem(node); dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_val, *new_node, *store; + int throws_exception = ir_throws_exception(node); + ir_node *new_val; + ir_node *new_node; ia32_address_t addr; /* check for destination address mode */ @@ -2537,7 +2658,7 @@ static ir_node *gen_general_Store(ir_node *node) /* construct store address */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, ptr, 0); + ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); if (addr.base == NULL) { addr.base = noreg_GP; @@ -2569,12 +2690,12 @@ static ir_node *gen_general_Store(ir_node *node) new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, mode); } - store = new_node; } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) { val = get_Conv_op(val); /* TODO: is this optimisation still necessary at all (middleend)? */ - /* We can skip ALL float->float up-Convs (and strict-up-Convs) before stores. */ + /* We can skip ALL float->float up-Convs (and strict-up-Convs) before + * stores. */ while (is_Conv(val)) { ir_node *op = get_Conv_op(val); if (!mode_is_float(get_irn_mode(op))) @@ -2584,7 +2705,7 @@ static ir_node *gen_general_Store(ir_node *node) val = op; } new_val = be_transform_node(val); - new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, &store); + new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val); } else { new_val = create_immediate_or_transform(val, 0); assert(mode != mode_b); @@ -2596,15 +2717,15 @@ static ir_node *gen_general_Store(ir_node *node) new_node = new_bd_ia32_Store(dbgi, new_block, addr.base, addr.index, addr.mem, new_val); } - store = new_node; } + ir_set_throws_exception(new_node, throws_exception); - set_irn_pinned(store, get_irn_pinned(node)); - set_ia32_op_type(store, ia32_AddrModeD); - set_ia32_ls_mode(store, mode); + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeD); + set_ia32_ls_mode(new_node, mode); - set_address(store, &addr); - SET_IA32_ORIG_NODE(store, node); + set_address(new_node, &addr); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -2616,8 +2737,8 @@ static ir_node *gen_general_Store(ir_node *node) */ static ir_node *gen_Store(ir_node *node) { - ir_node *val = get_Store_value(node); - ir_mode *mode = get_irn_mode(val); + ir_node *val = get_Store_value(node); + ir_mode *mode = get_irn_mode(val); if (mode_is_float(mode) && is_Const(val)) { /* We can transform every floating const store @@ -2637,46 +2758,31 @@ static ir_node *gen_Store(ir_node *node) */ static ir_node *create_Switch(ir_node *node) { - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *sel = get_Cond_selector(node); - ir_node *new_sel = be_transform_node(sel); - long switch_min = LONG_MAX; - long switch_max = LONG_MIN; - long default_pn = get_Cond_default_proj(node); - ir_node *new_node; - const ir_edge_t *edge; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *sel = get_Cond_selector(node); + ir_node *new_sel = be_transform_node(sel); + long default_pn = get_Cond_default_proj(node); + ir_node *new_node; + ir_entity *entity; assert(get_mode_size_bits(get_irn_mode(sel)) == 32); - /* determine the smallest switch case value */ - foreach_out_edge(node, edge) { - ir_node *proj = get_edge_src_irn(edge); - long pn = get_Proj_proj(proj); - if (pn == default_pn) - continue; + entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type()); + set_entity_visibility(entity, ir_visibility_private); + add_entity_linkage(entity, IR_LINKAGE_CONSTANT); - if (pn < switch_min) - switch_min = pn; - if (pn > switch_max) - switch_max = pn; - } - - if ((unsigned long) (switch_max - switch_min) > 128000) { - panic("Size of switch %+F bigger than 128000", node); - } - - if (switch_min != 0) { - /* if smallest switch case is not 0 we need an additional sub */ - new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg_GP); - add_ia32_am_offs_int(new_sel, -switch_min); - set_ia32_op_type(new_sel, ia32_AddrModeS); - - SET_IA32_ORIG_NODE(new_sel, node); - } - - new_node = new_bd_ia32_SwitchJmp(dbgi, block, new_sel, default_pn); + /* TODO: we could perform some more matching here to also use the base + * register of the address mode */ + new_node + = new_bd_ia32_SwitchJmp(dbgi, block, noreg_GP, new_sel, default_pn); + set_ia32_am_scale(new_node, 2); + set_ia32_am_sc(new_node, entity); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode_Iu); SET_IA32_ORIG_NODE(new_node, node); + // FIXME This seems wrong. GCC uses PIC for switch on OS X. + get_ia32_attr(new_node)->data.am_sc_no_pic_adjust = true; return new_node; } @@ -2686,23 +2792,23 @@ static ir_node *create_Switch(ir_node *node) */ static ir_node *gen_Cond(ir_node *node) { - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *sel = get_Cond_selector(node); - ir_mode *sel_mode = get_irn_mode(sel); - ir_node *flags = NULL; - ir_node *new_node; - pn_Cmp pnc; + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *sel = get_Cond_selector(node); + ir_mode *sel_mode = get_irn_mode(sel); + ir_node *flags = NULL; + ir_node *new_node; + ia32_condition_code_t cc; if (sel_mode != mode_b) { return create_Switch(node); } /* we get flags from a Cmp */ - flags = get_flags_node(sel, &pnc); + flags = get_flags_node(sel, &cc); - new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, pnc); + new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, cc); SET_IA32_ORIG_NODE(new_node, node); return new_node; @@ -2785,25 +2891,6 @@ static ir_node *create_Ucomi(ir_node *node) return new_node; } -/** - * helper function: checks whether all Cmp projs are Lg or Eq which is needed - * to fold an and into a test node - */ -static bool can_fold_test_and(ir_node *node) -{ - const ir_edge_t *edge; - - /** we can only have eq and lg projs */ - foreach_out_edge(node, edge) { - ir_node *proj = get_edge_src_irn(edge); - pn_Cmp pnc = get_Proj_proj(proj); - if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) - return false; - } - - return true; -} - /** * returns true if it is assured, that the upper bits of a node are "clean" * which means for a 16 or 8 bit value, that the upper bits in the register @@ -2874,7 +2961,8 @@ static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode) return shifted == 0 || shifted == -1; } else { unsigned long shifted = (unsigned long)attr->offset; - shifted >>= get_mode_size_bits(mode); + shifted >>= get_mode_size_bits(mode)-1; + shifted >>= 1; return shifted == 0; } } @@ -2898,7 +2986,6 @@ static ir_node *gen_Cmp(ir_node *node) ir_node *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - int cmp_unsigned; if (mode_is_float(cmp_mode)) { if (ia32_cg_config.use_sse2) { @@ -2911,11 +2998,9 @@ static ir_node *gen_Cmp(ir_node *node) assert(ia32_mode_needs_gp_reg(cmp_mode)); /* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */ - cmp_unsigned = !mode_is_signed(cmp_mode); if (is_Const_0(right) && is_And(left) && - get_irn_n_edges(left) == 1 && - can_fold_test_and(node)) { + get_irn_n_edges(left) == 1) { /* Test(and_left, and_right) */ ir_node *and_left = get_And_left(left); ir_node *and_right = get_And_right(left); @@ -2939,11 +3024,10 @@ static ir_node *gen_Cmp(ir_node *node) if (get_mode_size_bits(cmp_mode) == 8) { new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base, - addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted, - cmp_unsigned); + addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted); } else { new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned); + addr->mem, am.new_op1, am.new_op2, am.ins_permuted); } } else { /* Cmp(left, right) */ @@ -2960,11 +3044,10 @@ static ir_node *gen_Cmp(ir_node *node) if (get_mode_size_bits(cmp_mode) == 8) { new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, - am.new_op2, am.ins_permuted, - cmp_unsigned); + am.new_op2, am.ins_permuted); } else { new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned); + addr->mem, am.new_op1, am.new_op2, am.ins_permuted); } } set_am_attributes(new_node, &am); @@ -2978,7 +3061,7 @@ static ir_node *gen_Cmp(ir_node *node) } static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, - pn_Cmp pnc) + ia32_condition_code_t cc) { dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); @@ -2998,11 +3081,11 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, match_commutative | match_am | match_16bit_am | match_mode_neutral); if (am.ins_permuted) - pnc = ia32_get_negated_pnc(pnc); + cc = ia32_negate_condition_code(cc); new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, new_flags, - pnc); + cc); set_am_attributes(new_node, &am); SET_IA32_ORIG_NODE(new_node, node); @@ -3016,13 +3099,13 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, * Creates a ia32 Setcc instruction. */ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, - ir_node *flags, pn_Cmp pnc, + ir_node *flags, ia32_condition_code_t cc, ir_node *orig_node) { ir_mode *mode = get_irn_mode(orig_node); ir_node *new_node; - new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, pnc); + new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, cc); SET_IA32_ORIG_NODE(new_node, orig_node); /* we might need to conv the result up */ @@ -3044,7 +3127,7 @@ static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b) ir_node *new_node; ir_node *sub; ir_node *sbb; - ir_node *not; + ir_node *notn; ir_node *eflags; ir_node *block; @@ -3057,19 +3140,19 @@ static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b) if (is_Proj(new_node)) { sub = get_Proj_pred(new_node); - assert(is_ia32_Sub(sub)); } else { sub = new_node; set_irn_mode(sub, mode_T); new_node = new_rd_Proj(NULL, sub, mode, pn_ia32_res); } + assert(is_ia32_Sub(sub)); eflags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags); - dbgi = get_irn_dbg_info(psi); - sbb = new_bd_ia32_Sbb0(dbgi, block, eflags); - not = new_bd_ia32_Not(dbgi, block, sbb); + dbgi = get_irn_dbg_info(psi); + sbb = new_bd_ia32_Sbb0(dbgi, block, eflags); + notn = new_bd_ia32_Not(dbgi, block, sbb); - new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, not); + new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, notn); set_ia32_commutative(new_node); return new_node; } @@ -3088,8 +3171,8 @@ static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **ne ir_mode *mode = *new_mode; ir_type *tp; ir_initializer_t *initializer; - tarval *tv0 = get_Const_tarval(c0); - tarval *tv1 = get_Const_tarval(c1); + ir_tarval *tv0 = get_Const_tarval(c0); + ir_tarval *tv1 = get_Const_tarval(c1); if (mode == NULL) { /* detect the best mode for the constants */ @@ -3113,13 +3196,13 @@ static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **ne } - tp = ia32_create_float_type(mode, 4); + tp = ia32_get_prim_type(mode); tp = ia32_create_float_array(tp); - ent = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp); + ent = new_entity(get_glob_type(), id_unique("C%u"), tp); set_entity_ld_ident(ent, get_entity_ident(ent)); - set_entity_visibility(ent, ir_visibility_local); + set_entity_visibility(ent, ir_visibility_private); add_entity_linkage(ent, IR_LINKAGE_CONSTANT); initializer = create_initializer_compound(2); @@ -3150,9 +3233,8 @@ enum setcc_transform_insn { }; typedef struct setcc_transform { - unsigned num_steps; - unsigned permutate_cmp_ins; - pn_Cmp pnc; + unsigned num_steps; + ia32_condition_code_t cc; struct { enum setcc_transform_insn transform; long val; @@ -3165,30 +3247,30 @@ typedef struct setcc_transform { * Find a transformation that creates 0 and 1 from * tv_t and tv_f. */ -static void find_const_transform(pn_Cmp pnc, tarval *t, tarval *f, +static void find_const_transform(ia32_condition_code_t cc, + ir_tarval *t, ir_tarval *f, setcc_transform_t *res) { unsigned step = 0; res->num_steps = 0; - res->permutate_cmp_ins = 0; if (tarval_is_null(t)) { - tarval *tmp = t; + ir_tarval *tmp = t; t = f; f = tmp; - pnc = ia32_get_negated_pnc(pnc); - } else if (tarval_cmp(t, f) == pn_Cmp_Lt) { + cc = ia32_negate_condition_code(cc); + } else if (tarval_cmp(t, f) == ir_relation_less) { // now, t is the bigger one - tarval *tmp = t; + ir_tarval *tmp = t; t = f; f = tmp; - pnc = ia32_get_negated_pnc(pnc); + cc = ia32_negate_condition_code(cc); } - res->pnc = pnc; + res->cc = cc; if (! tarval_is_null(f)) { - tarval *t_sub = tarval_sub(t, f, NULL); + ir_tarval *t_sub = tarval_sub(t, f, NULL); t = t_sub; res->steps[step].transform = SETCC_TR_ADD; @@ -3268,11 +3350,11 @@ static void find_const_transform(pn_Cmp pnc, tarval *t, tarval *f, ++step; res->steps[step].transform = SETCC_TR_NEG; } else { - int v = get_tarval_lowest_bit(t); - assert(v >= 0); + int val = get_tarval_lowest_bit(t); + assert(val >= 0); res->steps[step].transform = SETCC_TR_SHL; - res->steps[step].scale = v; + res->steps[step].scale = val; } } ++step; @@ -3290,28 +3372,39 @@ static void find_const_transform(pn_Cmp pnc, tarval *t, tarval *f, */ static ir_node *gen_Mux(ir_node *node) { - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *mux_true = get_Mux_true(node); - ir_node *mux_false = get_Mux_false(node); - ir_node *cond = get_Mux_sel(node); - ir_mode *mode = get_irn_mode(node); - ir_node *flags; - ir_node *new_node; - pn_Cmp pnc; - - assert(get_irn_mode(cond) == mode_b); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *mux_true = get_Mux_true(node); + ir_node *mux_false = get_Mux_false(node); + ir_node *sel = get_Mux_sel(node); + ir_mode *mode = get_irn_mode(node); + ir_node *flags; + ir_node *new_node; + int is_abs; + ia32_condition_code_t cc; + + assert(get_irn_mode(sel) == mode_b); + + is_abs = ir_mux_is_abs(sel, mux_false, mux_true); + if (is_abs != 0) { + if (ia32_mode_needs_gp_reg(mode)) { + ir_fprintf(stderr, "Optimisation warning: Integer abs %+F not transformed\n", + node); + } else { + ir_node *op = ir_get_abs_op(sel, mux_false, mux_true); + return create_float_abs(dbgi, block, op, is_abs < 0, node); + } + } /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */ if (mode_is_float(mode)) { - ir_node *cmp = get_Proj_pred(cond); - ir_node *cmp_left = get_Cmp_left(cmp); - ir_node *cmp_right = get_Cmp_right(cmp); - pn_Cmp pnc = get_Proj_proj(cond); + ir_node *cmp_left = get_Cmp_left(sel); + ir_node *cmp_right = get_Cmp_right(sel); + ir_relation relation = get_Cmp_relation(sel); if (ia32_cg_config.use_sse2) { - if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) { + if (relation == ir_relation_less || relation == ir_relation_less_equal) { if (cmp_left == mux_true && cmp_right == mux_false) { /* Mux(a <= b, a, b) => MIN */ return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin, @@ -3321,7 +3414,7 @@ static ir_node *gen_Mux(ir_node *node) return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax, match_commutative | match_am | match_two_users); } - } else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) { + } else if (relation == ir_relation_greater || relation == ir_relation_greater_equal) { if (cmp_left == mux_true && cmp_right == mux_false) { /* Mux(a >= b, a, b) => MAX */ return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax, @@ -3340,8 +3433,8 @@ static ir_node *gen_Mux(ir_node *node) ir_mode *new_mode; unsigned scale; - flags = get_flags_node(cond, &pnc); - new_node = create_set_32bit(dbgi, new_block, flags, pnc, node); + flags = get_flags_node(sel, &cc); + new_node = create_set_32bit(dbgi, new_block, flags, cc, node); if (ia32_cg_config.use_sse2) { /* cannot load from different mode on SSE */ @@ -3353,31 +3446,15 @@ static ir_node *gen_Mux(ir_node *node) am.addr.symconst_ent = ia32_create_const_array(mux_false, mux_true, &new_mode); - switch (get_mode_size_bytes(new_mode)) { - case 4: + if (new_mode == mode_F) { scale = 2; - break; - case 8: + } else if (new_mode == mode_D) { scale = 3; - break; - case 10: - /* use 2 * 5 */ - scale = 1; - new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); - set_ia32_am_scale(new_node, 2); - break; - case 12: - /* use 4 * 3 */ - scale = 2; - new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); - set_ia32_am_scale(new_node, 1); - break; - case 16: + } else if (new_mode == ia32_mode_E) { /* arg, shift 16 NOT supported */ scale = 3; - new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, new_node); - break; - default: + new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); + } else { panic("Unsupported constant size"); } @@ -3388,6 +3465,7 @@ static ir_node *gen_Mux(ir_node *node) am.addr.offset = 0; am.addr.scale = scale; am.addr.use_frame = 0; + am.addr.tls_segment = false; am.addr.frame_entity = NULL; am.addr.symconst_sign = 0; am.mem_proj = am.addr.mem; @@ -3396,7 +3474,7 @@ static ir_node *gen_Mux(ir_node *node) am.new_op2 = NULL; am.pinned = op_pin_state_floats; am.commutative = 1; - am.ins_permuted = 0; + am.ins_permuted = false; if (ia32_cg_config.use_sse2) load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode); @@ -3411,57 +3489,51 @@ static ir_node *gen_Mux(ir_node *node) } else { assert(ia32_mode_needs_gp_reg(mode)); - if (is_Proj(cond)) { - ir_node *cmp = get_Proj_pred(cond); - if (is_Cmp(cmp)) { - ir_node *cmp_left = get_Cmp_left(cmp); - ir_node *cmp_right = get_Cmp_right(cmp); - pn_Cmp pnc = get_Proj_proj(cond); - - /* check for unsigned Doz first */ - if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) && - is_Const_0(mux_false) && is_Sub(mux_true) && - get_Sub_left(mux_true) == cmp_left && get_Sub_right(mux_true) == cmp_right) { - /* Mux(a >=u b, a - b, 0) unsigned Doz */ - return create_doz(node, cmp_left, cmp_right); - } else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) && - is_Const_0(mux_true) && is_Sub(mux_false) && - get_Sub_left(mux_false) == cmp_left && get_Sub_right(mux_false) == cmp_right) { - /* Mux(a <=u b, 0, a - b) unsigned Doz */ + if (is_Cmp(sel)) { + ir_node *cmp_left = get_Cmp_left(sel); + ir_node *cmp_right = get_Cmp_right(sel); + ir_relation relation = get_Cmp_relation(sel); + ir_node *val_true = mux_true; + ir_node *val_false = mux_false; + + if (is_Const(val_true) && is_Const_null(val_true)) { + ir_node *tmp = val_false; + val_false = val_true; + val_true = tmp; + relation = get_negated_relation(relation); + } + if (is_Const_0(val_false) && is_Sub(val_true)) { + if ((relation & ir_relation_greater) + && get_Sub_left(val_true) == cmp_left + && get_Sub_right(val_true) == cmp_right) { return create_doz(node, cmp_left, cmp_right); } + if ((relation & ir_relation_less) + && get_Sub_left(val_true) == cmp_right + && get_Sub_right(val_true) == cmp_left) { + return create_doz(node, cmp_right, cmp_left); + } } } - flags = get_flags_node(cond, &pnc); + flags = get_flags_node(sel, &cc); if (is_Const(mux_true) && is_Const(mux_false)) { /* both are const, good */ - tarval *tv_true = get_Const_tarval(mux_true); - tarval *tv_false = get_Const_tarval(mux_false); + ir_tarval *tv_true = get_Const_tarval(mux_true); + ir_tarval *tv_false = get_Const_tarval(mux_false); setcc_transform_t res; int step; - /* check if flags is a cmp node and we are the only user, - i.e no other user yet */ - int permutate_allowed = 0; - if (is_ia32_Cmp(flags) && get_irn_n_edges(flags) == 0) { - /* yes, we can permutate its inputs */ - permutate_allowed = 1; - } - find_const_transform(pnc, tv_true, tv_false, &res); + find_const_transform(cc, tv_true, tv_false, &res); new_node = node; - if (res.permutate_cmp_ins) { - ia32_attr_t *attr = get_ia32_attr(flags); - attr->data.ins_permuted ^= 1; - } for (step = (int)res.num_steps - 1; step >= 0; --step) { ir_node *imm; switch (res.steps[step].transform) { case SETCC_TR_ADD: - imm = ia32_immediate_from_long(res.steps[step].val); - new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm); + new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, noreg_GP); + add_ia32_am_offs_int(new_node, res.steps[step].val); break; case SETCC_TR_ADDxx: new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); @@ -3491,7 +3563,7 @@ static ir_node *gen_Mux(ir_node *node) new_node = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm); break; case SETCC_TR_SET: - new_node = create_set_32bit(dbgi, new_block, flags, res.pnc, new_node); + new_node = create_set_32bit(dbgi, new_block, flags, res.cc, node); break; case SETCC_TR_SBB: new_node = new_bd_ia32_Sbb0(dbgi, new_block, flags); @@ -3501,13 +3573,12 @@ static ir_node *gen_Mux(ir_node *node) } } } else { - new_node = create_CMov(node, cond, flags, pnc); + new_node = create_CMov(node, sel, flags, cc); } return new_node; } } - /** * Create a conversion from x87 state register to general purpose. */ @@ -3519,13 +3590,17 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); + ir_node *frame = get_irg_frame(irg); ir_node *fist, *load, *mem; - mem = gen_vfist(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist); + fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_op); set_irn_pinned(fist, op_pin_state_floats); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); + assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M); + mem = new_r_Proj(fist, mode_M, pn_ia32_vfist_M); + assert(get_mode_size_bits(mode) <= 32); /* exception we can only store signed 32 bit integers, so for unsigned we store a 64bit (signed) integer and load the lower bits */ @@ -3564,6 +3639,7 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) ir_graph *irg = get_Block_irg(block); dbg_info *dbgi = get_irn_dbg_info(node); ir_node *frame = get_irg_frame(irg); + ir_node *store_mem; ir_node *store, *load; ir_node *new_node; @@ -3572,12 +3648,14 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) set_ia32_op_type(store, ia32_AddrModeD); SET_IA32_ORIG_NODE(store, node); - load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store, tgt_mode); + store_mem = new_r_Proj(store, mode_M, pn_ia32_vfst_M); + + load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode); set_ia32_use_frame(load); set_ia32_op_type(load, ia32_AddrModeS); SET_IA32_ORIG_NODE(load, node); - new_node = new_r_Proj(load, mode_E, pn_ia32_vfld_res); + new_node = new_r_Proj(load, ia32_mode_E, pn_ia32_vfld_res); return new_node; } @@ -3606,6 +3684,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) ir_mode *store_mode; ir_node *fild; ir_node *store; + ir_node *store_mem; ir_node *new_node; /* fild can use source AM if the operand is a signed 16bit or 32bit integer */ @@ -3651,6 +3730,8 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) set_ia32_op_type(store, ia32_AddrModeD); set_ia32_ls_mode(store, mode_Iu); + store_mem = new_r_Proj(store, mode_M, pn_ia32_Store_M); + /* exception for 32bit unsigned, do a 64bit spill+load */ if (!mode_is_signed(mode)) { ir_node *in[2]; @@ -3659,23 +3740,24 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, zero_const); + ir_node *zero_store_mem = new_r_Proj(zero_store, mode_M, pn_ia32_Store_M); set_ia32_use_frame(zero_store); set_ia32_op_type(zero_store, ia32_AddrModeD); add_ia32_am_offs_int(zero_store, 4); set_ia32_ls_mode(zero_store, mode_Iu); - in[0] = zero_store; - in[1] = store; + in[0] = zero_store_mem; + in[1] = store_mem; - store = new_rd_Sync(dbgi, block, 2, in); + store_mem = new_rd_Sync(dbgi, block, 2, in); store_mode = mode_Ls; } else { store_mode = mode_Is; } /* do a fild */ - fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store); + fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem); set_ia32_use_frame(fild); set_ia32_op_type(fild, ia32_AddrModeS); @@ -3771,7 +3853,7 @@ static ir_node *gen_Conv(ir_node *node) } } else { /* this should be optimized already, but who knows... */ - DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node)); + DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node);) DB((dbg, LEVEL_1, "killed Conv(mode, mode) ...")); return be_transform_node(op); } @@ -3792,8 +3874,7 @@ static ir_node *gen_Conv(ir_node *node) /* if fp_no_float_fold is not set then we assume that we * don't have any float operations in a non * mode_float_arithmetic mode and can skip strict upconvs */ - if (src_bits < tgt_bits - && !(get_irg_fp_model(current_ir_graph) & fp_no_float_fold)) { + if (src_bits < tgt_bits) { DB((dbg, LEVEL_1, "killed Conv(float, float) ...")); return new_op; } else { @@ -3828,7 +3909,7 @@ static ir_node *gen_Conv(ir_node *node) set_ia32_ls_mode(res, tgt_mode); } else { unsigned int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0); - unsigned float_mantissa = tarval_ieee754_get_mantissa_size(tgt_mode); + unsigned float_mantissa = get_mode_mantissa_size(tgt_mode); res = gen_x87_gp_to_fp(node, src_mode); /* we need a strict-Conv, if the int mode has more bits than the @@ -3863,7 +3944,7 @@ static ir_node *gen_Conv(ir_node *node) static ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type) { - ir_node *new_node = try_create_Immediate(node, immediate_constraint_type); + ir_node *new_node = ia32_try_create_Immediate(node, immediate_constraint_type); if (new_node == NULL) { new_node = be_transform_node(node); } @@ -3895,19 +3976,27 @@ static ir_node *gen_be_FrameAddr(ir_node *node) */ static ir_node *gen_be_Return(ir_node *node) { - ir_graph *irg = current_ir_graph; - ir_node *ret_val = get_irn_n(node, be_pos_Return_val); - ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem); - ir_entity *ent = get_irg_entity(irg); - ir_type *tp = get_entity_type(ent); - dbg_info *dbgi; - ir_node *block; + ir_graph *irg = current_ir_graph; + ir_node *ret_val = get_irn_n(node, n_be_Return_val); + ir_node *ret_mem = get_irn_n(node, n_be_Return_mem); + ir_node *new_ret_val = be_transform_node(ret_val); + ir_node *new_ret_mem = be_transform_node(ret_mem); + ir_entity *ent = get_irg_entity(irg); + ir_type *tp = get_entity_type(ent); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = be_transform_node(get_nodes_block(node)); ir_type *res_type; ir_mode *mode; - ir_node *frame, *sse_store, *fld, *mproj, *barrier; - ir_node *new_barrier, *new_ret_val, *new_ret_mem; - ir_node **in; - int pn_ret_val, pn_ret_mem, arity, i; + ir_node *frame; + ir_node *sse_store; + ir_node *store_mem; + ir_node *fld; + ir_node *mproj; + int i; + int arity; + unsigned pop; + ir_node **in; + ir_node *new_node; assert(ret_val != NULL); if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) { @@ -3927,66 +4016,42 @@ static ir_node *gen_be_Return(ir_node *node) assert(get_method_n_ress(tp) == 1); - pn_ret_val = get_Proj_proj(ret_val); - pn_ret_mem = get_Proj_proj(ret_mem); - - /* get the Barrier */ - barrier = get_Proj_pred(ret_val); - - /* get result input of the Barrier */ - ret_val = get_irn_n(barrier, pn_ret_val); - new_ret_val = be_transform_node(ret_val); - - /* get memory input of the Barrier */ - ret_mem = get_irn_n(barrier, pn_ret_mem); - new_ret_mem = be_transform_node(ret_mem); - frame = get_irg_frame(irg); - dbgi = get_irn_dbg_info(barrier); - block = be_transform_node(get_nodes_block(barrier)); - /* store xmm0 onto stack */ sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg_GP, new_ret_mem, new_ret_val); set_ia32_ls_mode(sse_store, mode); set_ia32_op_type(sse_store, ia32_AddrModeD); set_ia32_use_frame(sse_store); + store_mem = new_r_Proj(sse_store, mode_M, pn_ia32_xStoreSimple_M); /* load into x87 register */ - fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, sse_store, mode); + fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, mode); set_ia32_op_type(fld, ia32_AddrModeS); set_ia32_use_frame(fld); mproj = new_r_Proj(fld, mode_M, pn_ia32_vfld_M); fld = new_r_Proj(fld, mode_vfp, pn_ia32_vfld_res); - /* create a new barrier */ - arity = get_irn_arity(barrier); + /* create a new return */ + arity = get_irn_arity(node); in = ALLOCAN(ir_node*, arity); + pop = be_Return_get_pop(node); for (i = 0; i < arity; ++i) { - ir_node *new_in; - - if (i == pn_ret_val) { - new_in = fld; - } else if (i == pn_ret_mem) { - new_in = mproj; + ir_node *op = get_irn_n(node, i); + if (op == ret_val) { + in[i] = fld; + } else if (op == ret_mem) { + in[i] = mproj; } else { - ir_node *in = get_irn_n(barrier, i); - new_in = be_transform_node(in); + in[i] = be_transform_node(op); } - in[i] = new_in; } + new_node = be_new_Return(dbgi, irg, block, arity, pop, arity, in); + copy_node_attr(irg, node, new_node); - new_barrier = new_ir_node(dbgi, irg, block, - get_irn_op(barrier), get_irn_mode(barrier), - arity, in); - copy_node_attr(barrier, new_barrier); - be_duplicate_deps(barrier, new_barrier); - be_set_transformed_node(barrier, new_barrier); - - /* transform normally */ - return be_duplicate_node(node); + return new_node; } /** @@ -3994,11 +4059,15 @@ static ir_node *gen_be_Return(ir_node *node) */ static ir_node *gen_be_AddSP(ir_node *node) { - ir_node *sz = get_irn_n(node, be_pos_AddSP_size); - ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); + ir_node *sz = get_irn_n(node, n_be_AddSP_size); + ir_node *sp = get_irn_n(node, n_be_AddSP_old_sp); - return gen_binop(node, sp, sz, new_bd_ia32_SubSP, - match_am | match_immediate); + ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_SubSP, + match_am | match_immediate); + assert(is_ia32_SubSP(new_node)); + arch_set_irn_register_out(new_node, pn_ia32_SubSP_stack, + &ia32_registers[REG_ESP]); + return new_node; } /** @@ -4006,11 +4075,15 @@ static ir_node *gen_be_AddSP(ir_node *node) */ static ir_node *gen_be_SubSP(ir_node *node) { - ir_node *sz = get_irn_n(node, be_pos_SubSP_size); - ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); + ir_node *sz = get_irn_n(node, n_be_SubSP_size); + ir_node *sp = get_irn_n(node, n_be_SubSP_old_sp); - return gen_binop(node, sp, sz, new_bd_ia32_AddSP, - match_am | match_immediate); + ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_AddSP, + match_am | match_immediate); + assert(is_ia32_AddSP(new_node)); + arch_set_irn_register_out(new_node, pn_ia32_AddSP_stack, + &ia32_registers[REG_ESP]); + return new_node; } /** @@ -4047,10 +4120,10 @@ static ir_node *gen_Phi(ir_node *node) * and fix this later */ phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1); - copy_node_attr(node, phi); + copy_node_attr(irg, node, phi); be_duplicate_deps(node, phi); - arch_set_out_register_req(phi, 0, req); + arch_set_irn_register_req_out(phi, 0, req); be_enqueue_preds(node); @@ -4097,65 +4170,6 @@ static ir_node *gen_IJmp(ir_node *node) return new_node; } -/** - * Transform a Bound node. - */ -static ir_node *gen_Bound(ir_node *node) -{ - ir_node *new_node; - ir_node *lower = get_Bound_lower(node); - dbg_info *dbgi = get_irn_dbg_info(node); - - if (is_Const_0(lower)) { - /* typical case for Java */ - ir_node *sub, *res, *flags, *block; - - res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node), - new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate); - - block = get_nodes_block(res); - if (! is_Proj(res)) { - sub = res; - set_irn_mode(sub, mode_T); - res = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_res); - } else { - sub = get_Proj_pred(res); - } - flags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags); - new_node = new_bd_ia32_Jcc(dbgi, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned); - SET_IA32_ORIG_NODE(new_node, node); - } else { - panic("generic Bound not supported in ia32 Backend"); - } - return new_node; -} - - -static ir_node *gen_ia32_l_ShlDep(ir_node *node) -{ - ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val); - ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count); - - return gen_shift_binop(node, left, right, new_bd_ia32_Shl, - match_immediate | match_mode_neutral); -} - -static ir_node *gen_ia32_l_ShrDep(ir_node *node) -{ - ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val); - ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count); - return gen_shift_binop(node, left, right, new_bd_ia32_Shr, - match_immediate); -} - -static ir_node *gen_ia32_l_SarDep(ir_node *node) -{ - ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val); - ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count); - return gen_shift_binop(node, left, right, new_bd_ia32_Sar, - match_immediate); -} - static ir_node *gen_ia32_l_Add(ir_node *node) { ir_node *left = get_irn_n(node, n_ia32_l_Add_left); @@ -4165,7 +4179,7 @@ static ir_node *gen_ia32_l_Add(ir_node *node) match_mode_neutral); if (is_Proj(lowered)) { - lowered = get_Proj_pred(lowered); + lowered = get_Proj_pred(lowered); } else { assert(is_ia32_Add(lowered)); set_irn_mode(lowered, mode_T); @@ -4217,7 +4231,7 @@ static ir_node *gen_ia32_l_Sub(ir_node *node) match_am | match_immediate | match_mode_neutral); if (is_Proj(lowered)) { - lowered = get_Proj_pred(lowered); + lowered = get_Proj_pred(lowered); } else { assert(is_ia32_Sub(lowered)); set_irn_mode(lowered, mode_T); @@ -4232,62 +4246,6 @@ static ir_node *gen_ia32_l_Sbb(ir_node *node) match_am | match_immediate | match_mode_neutral); } -/** - * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs: - * op1 - target to be shifted - * op2 - contains bits to be shifted into target - * op3 - shift count - * Only op3 can be an immediate. - */ -static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high, - ir_node *low, ir_node *count) -{ - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_high = be_transform_node(high); - ir_node *new_low = be_transform_node(low); - ir_node *new_count; - ir_node *new_node; - - /* the shift amount can be any mode that is bigger than 5 bits, since all - * other bits are ignored anyway */ - while (is_Conv(count) && - get_irn_n_edges(count) == 1 && - mode_is_int(get_irn_mode(count))) { - assert(get_mode_size_bits(get_irn_mode(count)) >= 5); - count = get_Conv_op(count); - } - new_count = create_immediate_or_transform(count, 0); - - if (is_ia32_l_ShlD(node)) { - new_node = new_bd_ia32_ShlD(dbgi, new_block, new_high, new_low, - new_count); - } else { - new_node = new_bd_ia32_ShrD(dbgi, new_block, new_high, new_low, - new_count); - } - SET_IA32_ORIG_NODE(new_node, node); - - return new_node; -} - -static ir_node *gen_ia32_l_ShlD(ir_node *node) -{ - ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high); - ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low); - ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count); - return gen_lowered_64bit_shifts(node, high, low, count); -} - -static ir_node *gen_ia32_l_ShrD(ir_node *node) -{ - ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high); - ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low); - ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count); - return gen_lowered_64bit_shifts(node, high, low, count); -} - static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) { ir_node *src_block = get_nodes_block(node); @@ -4301,7 +4259,10 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) ir_node *new_val_high = be_transform_node(val_high); ir_node *in[2]; ir_node *sync, *fild, *res; - ir_node *store_low, *store_high; + ir_node *store_low; + ir_node *store_high; + ir_node *mem_low; + ir_node *mem_high; if (ia32_cg_config.use_sse2) { panic("ia32_l_LLtoFloat not implemented for SSE2"); @@ -4315,6 +4276,9 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) SET_IA32_ORIG_NODE(store_low, node); SET_IA32_ORIG_NODE(store_high, node); + mem_low = new_r_Proj(store_low, mode_M, pn_ia32_Store_M); + mem_high = new_r_Proj(store_high, mode_M, pn_ia32_Store_M); + set_ia32_use_frame(store_low); set_ia32_use_frame(store_high); set_ia32_op_type(store_low, ia32_AddrModeD); @@ -4323,8 +4287,8 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) set_ia32_ls_mode(store_high, mode_Is); add_ia32_am_offs_int(store_high, 4); - in[0] = store_low; - in[1] = store_high; + in[0] = mem_low; + in[1] = mem_high; sync = new_rd_Sync(dbgi, block, 2, in); /* do a fild */ @@ -4350,6 +4314,7 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) am.addr.offset = 0; am.addr.scale = 2; am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS); + am.addr.tls_segment = false; am.addr.use_frame = 0; am.addr.frame_entity = NULL; am.addr.symconst_sign = 0; @@ -4357,10 +4322,10 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) am.mem_proj = nomem; am.op_type = ia32_AddrModeS; am.new_op1 = res; - am.new_op2 = ia32_new_NoReg_vfp(env_cg); + am.new_op2 = ia32_new_NoReg_vfp(current_ir_graph); am.pinned = op_pin_state_floats; am.commutative = 1; - am.ins_permuted = 0; + am.ins_permuted = false; fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, am.new_op1, am.new_op2, get_fpcw()); @@ -4381,24 +4346,16 @@ static ir_node *gen_ia32_l_FloattoLL(ir_node *node) ir_node *frame = get_irg_frame(irg); ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val); ir_node *new_val = be_transform_node(val); - ir_node *fist, *mem; + ir_node *fist; - mem = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val, &fist); + fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val); SET_IA32_ORIG_NODE(fist, node); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); set_ia32_ls_mode(fist, mode_Ls); - return mem; -} - -/** - * the BAD transformer. - */ -static ir_node *bad_transform(ir_node *node) -{ - panic("No transform function for %+F available.", node); - return NULL; + assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M); + return new_r_Proj(fist, mode_M, pn_ia32_vfist_M); } static ir_node *gen_Proj_l_FloattoLL(ir_node *node) @@ -4448,7 +4405,7 @@ static ir_node *gen_Proj_be_AddSP(ir_node *node) if (proj == pn_be_AddSP_sp) { ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_SubSP_stack); - arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); + arch_set_irn_register(res, &ia32_registers[REG_ESP]); return res; } else if (proj == pn_be_AddSP_res) { return new_rd_Proj(dbgi, new_pred, mode_Iu, @@ -4473,7 +4430,7 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node) if (proj == pn_be_SubSP_sp) { ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_AddSP_stack); - arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); + arch_set_irn_register(res, &ia32_registers[REG_ESP]); return res; } else if (proj == pn_be_SubSP_M) { return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_AddSP_M); @@ -4488,10 +4445,9 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node) static ir_node *gen_Proj_Load(ir_node *node) { ir_node *new_pred; - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *pred = get_Proj_pred(node); - dbg_info *dbgi = get_irn_dbg_info(node); - long proj = get_Proj_proj(node); + ir_node *pred = get_Proj_pred(node); + dbg_info *dbgi = get_irn_dbg_info(node); + long proj = get_Proj_proj(node); /* loads might be part of source address mode matches, so we don't * transform the ProjMs yet (with the exception of loads whose result is @@ -4512,57 +4468,58 @@ static ir_node *gen_Proj_Load(ir_node *node) /* renumber the proj */ new_pred = be_transform_node(pred); if (is_ia32_Load(new_pred)) { - switch (proj) { + switch ((pn_Load)proj) { case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Load_res); case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Load_M); - case pn_Load_X_regular: - return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_regular); } } else if (is_ia32_Conv_I2I(new_pred) || is_ia32_Conv_I2I8Bit(new_pred)) { set_irn_mode(new_pred, mode_T); - if (proj == pn_Load_res) { + switch ((pn_Load)proj) { + case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_res); - } else if (proj == pn_Load_M) { + case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_mem); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_regular); } } else if (is_ia32_xLoad(new_pred)) { - switch (proj) { + switch ((pn_Load)proj) { case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xLoad_res); case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xLoad_M); - case pn_Load_X_regular: - return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_regular); } } else if (is_ia32_vfld(new_pred)) { - switch (proj) { + switch ((pn_Load)proj) { case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res); case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M); - case pn_Load_X_regular: - return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_regular); } } else { /* can happen for ProJMs when source address mode happened for the @@ -4577,132 +4534,185 @@ static ir_node *gen_Proj_Load(ir_node *node) return new_rd_Proj(dbgi, new_pred, mode_M, 1); } - panic("No idea how to transform proj"); + panic("No idea how to transform Proj(Load) %+F", node); +} + +static ir_node *gen_Proj_Store(ir_node *node) +{ + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + dbg_info *dbgi = get_irn_dbg_info(node); + long pn = get_Proj_proj(node); + + if (is_ia32_Store(new_pred) || is_ia32_Store8Bit(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Store_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_regular); + } + } else if (is_ia32_vfist(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfist_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_regular); + } + } else if (is_ia32_vfisttp(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfisttp_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_regular); + } + } else if (is_ia32_vfst(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfst_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_regular); + } + } else if (is_ia32_xStore(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xStore_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_regular); + } + } else if (is_Sync(new_pred)) { + /* hack for the case that gen_float_const_Store produced a Sync */ + if (pn == pn_Store_M) { + return new_pred; + } + panic("exception control flow for gen_float_const_Store not implemented yet"); + } else if (get_ia32_op_type(new_pred) == ia32_AddrModeD) { + /* destination address mode */ + if (pn == pn_Store_M) { + return new_pred; + } + panic("exception control flow for destination AM not implemented yet"); + } + + panic("No idea how to transform Proj(Store) %+F", node); } /** - * Transform and renumber the Projs from a DivMod like instruction. + * Transform and renumber the Projs from a Div or Mod instruction. */ -static ir_node *gen_Proj_DivMod(ir_node *node) +static ir_node *gen_Proj_Div(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); dbg_info *dbgi = get_irn_dbg_info(node); - long proj = get_Proj_proj(node); + long proj = get_Proj_proj(node); - assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)); + assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M); + assert((long)pn_ia32_Div_div_res == (long)pn_ia32_IDiv_div_res); - switch (get_irn_opcode(pred)) { - case iro_Div: - switch (proj) { - case pn_Div_M: - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); - case pn_Div_res: - return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res); - case pn_Div_X_regular: - return new_rd_Jmp(dbgi, block); - case pn_Div_X_except: - set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); - default: - break; - } - break; - case iro_Mod: - switch (proj) { - case pn_Mod_M: + switch ((pn_Div)proj) { + case pn_Div_M: + if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) { return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); - case pn_Mod_res: - return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res); - case pn_Mod_X_except: - set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); - default: - break; + } else if (is_ia32_xDiv(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M); + } else if (is_ia32_vfdiv(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfdiv_M); + } else { + panic("Div transformed to unexpected thing %+F", new_pred); } - break; - case iro_DivMod: - switch (proj) { - case pn_DivMod_M: - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); - case pn_DivMod_res_div: + case pn_Div_res: + if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) { return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res); - case pn_DivMod_res_mod: - return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res); - case pn_DivMod_X_regular: - return new_rd_Jmp(dbgi, block); - case pn_DivMod_X_except: - set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); - default: - break; + } else if (is_ia32_xDiv(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res); + } else if (is_ia32_vfdiv(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfdiv_res); + } else { + panic("Div transformed to unexpected thing %+F", new_pred); } - break; - default: - break; + case pn_Div_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except); + case pn_Div_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular); } - panic("No idea how to transform proj->DivMod"); + panic("No idea how to transform proj->Div"); } /** - * Transform and renumber the Projs from a CopyB. + * Transform and renumber the Projs from a Div or Mod instruction. */ -static ir_node *gen_Proj_CopyB(ir_node *node) +static ir_node *gen_Proj_Mod(ir_node *node) { ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); - switch (proj) { - case pn_CopyB_M_regular: - if (is_ia32_CopyB_i(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M); - } else if (is_ia32_CopyB(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M); - } - break; - default: - break; - } + assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)); + assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M); + assert((long)pn_ia32_Div_mod_res == (long)pn_ia32_IDiv_mod_res); - panic("No idea how to transform proj->CopyB"); + switch ((pn_Mod)proj) { + case pn_Mod_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); + case pn_Mod_res: + return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res); + case pn_Mod_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except); + case pn_Mod_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular); + } + panic("No idea how to transform proj->Mod"); } /** - * Transform and renumber the Projs from a Quot. + * Transform and renumber the Projs from a CopyB. */ -static ir_node *gen_Proj_Quot(ir_node *node) +static ir_node *gen_Proj_CopyB(ir_node *node) { ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); - switch (proj) { - case pn_Quot_M: - if (is_ia32_xDiv(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M); - } else if (is_ia32_vfdiv(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfdiv_M); + switch ((pn_CopyB)proj) { + case pn_CopyB_M: + if (is_ia32_CopyB_i(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M); + } else if (is_ia32_CopyB(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M); } break; - case pn_Quot_res: - if (is_ia32_xDiv(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res); - } else if (is_ia32_vfdiv(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfdiv_res); + case pn_CopyB_X_regular: + if (is_ia32_CopyB_i(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_regular); + } else if (is_ia32_CopyB(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_regular); } break; - case pn_Quot_X_regular: - case pn_Quot_X_except: - default: + case pn_CopyB_X_except: + if (is_ia32_CopyB_i(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_except); + } else if (is_ia32_CopyB(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_except); + } break; } - panic("No idea how to transform proj->Quot"); + panic("No idea how to transform proj->CopyB"); } static ir_node *gen_be_Call(ir_node *node) @@ -4710,10 +4720,10 @@ static ir_node *gen_be_Call(ir_node *node) dbg_info *const dbgi = get_irn_dbg_info(node); ir_node *const src_block = get_nodes_block(node); ir_node *const block = be_transform_node(src_block); - ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem); - ir_node *const src_sp = get_irn_n(node, be_pos_Call_sp); + ir_node *const src_mem = get_irn_n(node, n_be_Call_mem); + ir_node *const src_sp = get_irn_n(node, n_be_Call_sp); ir_node *const sp = be_transform_node(src_sp); - ir_node *const src_ptr = get_irn_n(node, be_pos_Call_ptr); + ir_node *const src_ptr = get_irn_n(node, n_be_Call_ptr); ia32_address_mode_t am; ia32_address_t *const addr = &am.addr; ir_node * mem; @@ -4726,6 +4736,7 @@ static ir_node *gen_be_Call(ir_node *node) unsigned const pop = be_Call_get_pop(node); ir_type *const call_tp = be_Call_get_type(node); int old_no_pic_adjust; + int throws_exception = ir_throws_exception(node); /* Run the x87 simulator if the call returns a float value */ if (get_method_n_ress(call_tp) > 0) { @@ -4733,7 +4744,9 @@ static ir_node *gen_be_Call(ir_node *node) ir_mode *const res_mode = get_type_mode(res_type); if (res_mode != NULL && mode_is_float(res_mode)) { - env_cg->do_x87_sim = 1; + ir_graph *irg = current_ir_graph; + ia32_irg_data_t *irg_data = ia32_get_irg_data(irg); + irg_data->do_x87_sim = 1; } } @@ -4741,27 +4754,28 @@ static ir_node *gen_be_Call(ir_node *node) assert(be_Call_get_entity(node) == NULL); /* special case for PIC trampoline calls */ - old_no_pic_adjust = no_pic_adjust; - no_pic_adjust = env_cg->birg->main_env->options->pic; + old_no_pic_adjust = ia32_no_pic_adjust; + ia32_no_pic_adjust = be_get_irg_options(current_ir_graph)->pic; match_arguments(&am, src_block, NULL, src_ptr, src_mem, match_am | match_immediate); - no_pic_adjust = old_no_pic_adjust; + ia32_no_pic_adjust = old_no_pic_adjust; i = get_irn_arity(node) - 1; fpcw = be_transform_node(get_irn_n(node, i--)); - for (; i >= be_pos_Call_first_arg; --i) { - arch_register_req_t const *const req = arch_get_register_req(node, i); + for (; i >= n_be_Call_first_arg; --i) { + arch_register_req_t const *const req + = arch_get_irn_register_req_in(node, i); ir_node *const reg_parm = be_transform_node(get_irn_n(node, i)); assert(req->type == arch_register_req_type_limited); assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]); switch (*req->limited) { - case 1 << REG_EAX: assert(eax == noreg_GP); eax = reg_parm; break; - case 1 << REG_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break; - case 1 << REG_EDX: assert(edx == noreg_GP); edx = reg_parm; break; + case 1 << REG_GP_EAX: assert(eax == noreg_GP); eax = reg_parm; break; + case 1 << REG_GP_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break; + case 1 << REG_GP_EDX: assert(edx == noreg_GP); edx = reg_parm; break; default: panic("Invalid GP register for register parameter"); } } @@ -4769,6 +4783,7 @@ static ir_node *gen_be_Call(ir_node *node) mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem); call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem, am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp); + ir_set_throws_exception(call, throws_exception); set_am_attributes(call, &am); call = fix_mem_proj(call, &am); @@ -4815,10 +4830,11 @@ static ir_node *gen_debugbreak(ir_node *node) */ static ir_node *gen_return_address(ir_node *node) { - ir_node *param = get_Builtin_param(node, 0); - ir_node *frame = get_Builtin_param(node, 1); - dbg_info *dbgi = get_irn_dbg_info(node); - tarval *tv = get_Const_tarval(param); + ir_node *param = get_Builtin_param(node, 0); + ir_node *frame = get_Builtin_param(node, 1); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_tarval *tv = get_Const_tarval(param); + ir_graph *irg = get_irn_irg(node); unsigned long value = get_tarval_long(tv); ir_node *block = be_transform_node(get_nodes_block(node)); @@ -4840,13 +4856,13 @@ static ir_node *gen_return_address(ir_node *node) set_ia32_am_offs_int(load, 0); set_ia32_use_frame(load); - set_ia32_frame_ent(load, ia32_get_return_address_entity()); + set_ia32_frame_ent(load, ia32_get_return_address_entity(irg)); if (get_irn_pinned(node) == op_pin_state_floats) { - assert(pn_ia32_xLoad_res == pn_ia32_vfld_res - && pn_ia32_vfld_res == pn_ia32_Load_res - && pn_ia32_Load_res == pn_ia32_res); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res + && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res + && (int)pn_ia32_Load_res == (int)pn_ia32_res); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); } SET_IA32_ORIG_NODE(load, node); @@ -4858,10 +4874,11 @@ static ir_node *gen_return_address(ir_node *node) */ static ir_node *gen_frame_address(ir_node *node) { - ir_node *param = get_Builtin_param(node, 0); - ir_node *frame = get_Builtin_param(node, 1); - dbg_info *dbgi = get_irn_dbg_info(node); - tarval *tv = get_Const_tarval(param); + ir_node *param = get_Builtin_param(node, 0); + ir_node *frame = get_Builtin_param(node, 1); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_tarval *tv = get_Const_tarval(param); + ir_graph *irg = get_irn_irg(node); unsigned long value = get_tarval_long(tv); ir_node *block = be_transform_node(get_nodes_block(node)); @@ -4882,7 +4899,7 @@ static ir_node *gen_frame_address(ir_node *node) set_ia32_op_type(load, ia32_AddrModeS); set_ia32_ls_mode(load, mode_Iu); - ent = ia32_get_frame_address_entity(); + ent = ia32_get_frame_address_entity(irg); if (ent != NULL) { set_ia32_am_offs_int(load, 0); set_ia32_use_frame(load); @@ -4893,10 +4910,10 @@ static ir_node *gen_frame_address(ir_node *node) } if (get_irn_pinned(node) == op_pin_state_floats) { - assert(pn_ia32_xLoad_res == pn_ia32_vfld_res - && pn_ia32_vfld_res == pn_ia32_Load_res - && pn_ia32_Load_res == pn_ia32_res); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res + && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res + && (int)pn_ia32_Load_res == (int)pn_ia32_res); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); } SET_IA32_ORIG_NODE(load, node); @@ -4909,10 +4926,10 @@ static ir_node *gen_frame_address(ir_node *node) static ir_node *gen_prefetch(ir_node *node) { dbg_info *dbgi; - ir_node *ptr, *block, *mem, *base, *index; + ir_node *ptr, *block, *mem, *base, *idx; ir_node *param, *new_node; long rw, locality; - tarval *tv; + ir_tarval *tv; ia32_address_t addr; if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) { @@ -4927,9 +4944,9 @@ static ir_node *gen_prefetch(ir_node *node) /* construct load address */ memset(&addr, 0, sizeof(addr)); ptr = get_Builtin_param(node, 0); - ia32_create_address_mode(&addr, ptr, 0); - base = addr.base; - index = addr.index; + ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); + base = addr.base; + idx = addr.index; if (base == NULL) { base = noreg_GP; @@ -4937,10 +4954,10 @@ static ir_node *gen_prefetch(ir_node *node) base = be_transform_node(base); } - if (index == NULL) { - index = noreg_GP; + if (idx == NULL) { + idx = noreg_GP; } else { - index = be_transform_node(index); + idx = be_transform_node(idx); } dbgi = get_irn_dbg_info(node); @@ -4949,7 +4966,7 @@ static ir_node *gen_prefetch(ir_node *node) if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) { /* we have 3DNow!, this was already checked above */ - new_node = new_bd_ia32_PrefetchW(dbgi, block, base, index, mem); + new_node = new_bd_ia32_PrefetchW(dbgi, block, base, idx, mem); } else if (ia32_cg_config.use_sse_prefetch) { /* note: rw == 1 is IGNORED in that case */ param = get_Builtin_param(node, 2); @@ -4959,22 +4976,22 @@ static ir_node *gen_prefetch(ir_node *node) /* SSE style prefetch */ switch (locality) { case 0: - new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, index, mem); + new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, idx, mem); break; case 1: - new_node = new_bd_ia32_Prefetch2(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch2(dbgi, block, base, idx, mem); break; case 2: - new_node = new_bd_ia32_Prefetch1(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch1(dbgi, block, base, idx, mem); break; default: - new_node = new_bd_ia32_Prefetch0(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch0(dbgi, block, base, idx, mem); break; } } else { assert(ia32_cg_config.use_3dnow_prefetch); /* 3DNow! style prefetch */ - new_node = new_bd_ia32_Prefetch(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch(dbgi, block, base, idx, mem); } set_irn_pinned(new_node, get_irn_pinned(node)); @@ -4984,7 +5001,6 @@ static ir_node *gen_prefetch(ir_node *node) SET_IA32_ORIG_NODE(new_node, node); - be_dep_on_frame(new_node); return new_r_Proj(new_node, mode_M, pn_ia32_Prefetch_M); } @@ -5022,7 +5038,7 @@ static ir_node *gen_ffs(ir_node *node) ir_node *real = skip_Proj(bsf); dbg_info *dbgi = get_irn_dbg_info(real); ir_node *block = get_nodes_block(real); - ir_node *flag, *set, *conv, *neg, *or; + ir_node *flag, *set, *conv, *neg, *orn, *add; /* bsf x */ if (get_irn_mode(real) != mode_T) { @@ -5033,7 +5049,7 @@ static ir_node *gen_ffs(ir_node *node) flag = new_r_Proj(real, mode_b, pn_ia32_flags); /* sete */ - set = new_bd_ia32_Setcc(dbgi, block, flag, pn_Cmp_Eq); + set = new_bd_ia32_Setcc(dbgi, block, flag, ia32_cc_equal); SET_IA32_ORIG_NODE(set, node); /* conv to 32bit */ @@ -5044,11 +5060,13 @@ static ir_node *gen_ffs(ir_node *node) neg = new_bd_ia32_Neg(dbgi, block, conv); /* or */ - or = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg); - set_ia32_commutative(or); + orn = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg); + set_ia32_commutative(orn); /* add 1 */ - return new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP, nomem, or, ia32_create_Immediate(NULL, 0, 1)); + add = new_bd_ia32_Lea(dbgi, block, orn, noreg_GP); + add_ia32_am_offs_int(add, 1); + return add; } /** @@ -5078,32 +5096,33 @@ static ir_node *gen_ctz(ir_node *node) */ static ir_node *gen_parity(ir_node *node) { - ir_node *param = get_Builtin_param(node, 0); dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *param = get_Builtin_param(node, 0); + ir_node *new_param = be_transform_node(param); + ir_node *new_node; - ir_node *block = get_nodes_block(node); - - ir_node *new_block = be_transform_node(block); - ir_node *imm, *cmp, *new_node; - - ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; - - - /* cmp param, 0 */ - match_arguments(&am, block, NULL, param, NULL, match_am); - imm = ia32_create_Immediate(NULL, 0, 0); - cmp = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index, - addr->mem, imm, am.new_op2, am.ins_permuted, 0); - set_am_attributes(cmp, &am); - set_ia32_ls_mode(cmp, mode_Iu); + /* the x86 parity bit is stupid: it only looks at the lowest byte, + * so we have to do complicated xoring first. + * (we should also better lower this before the backend so we still have a + * chance for CSE, constant folding and other goodies for some of these + * operations) + */ + ir_node *count = ia32_create_Immediate(NULL, 0, 16); + ir_node *shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count); + ir_node *xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem, + shr, new_param); + ir_node *xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xor); + ir_node *flags; - SET_IA32_ORIG_NODE(cmp, node); + set_ia32_commutative(xor); - cmp = fix_mem_proj(cmp, &am); + set_irn_mode(xor2, mode_T); + flags = new_r_Proj(xor2, mode_Iu, pn_ia32_XorHighLow_flags); /* setp */ - new_node = new_bd_ia32_Setcc(dbgi, new_block, cmp, ia32_pn_Cmp_parity); + new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, ia32_cc_not_parity); SET_IA32_ORIG_NODE(new_node, node); /* conv to 32bit */ @@ -5146,6 +5165,13 @@ static ir_node *gen_popcount(ir_node *node) new_param = be_transform_node(param); /* do the standard popcount algo */ + /* TODO: This is stupid, we should transform this before the backend, + * to get CSE, localopts, etc. for the operations + * TODO: This is also not the optimal algorithm (it is just the starting + * example in hackers delight, they optimize it more on the following page) + * But I'm too lazy to fix this now, as the code should get lowered before + * the backend anyway. + */ /* m1 = x & 0x55555555 */ imm = ia32_create_Immediate(NULL, 0, 0x55555555); @@ -5153,7 +5179,7 @@ static ir_node *gen_popcount(ir_node *node) /* s1 = x >> 1 */ simm = ia32_create_Immediate(NULL, 0, 1); - s1 = new_bd_ia32_Shl(dbgi, new_block, new_param, simm); + s1 = new_bd_ia32_Shr(dbgi, new_block, new_param, simm); /* m2 = s1 & 0x55555555 */ m2 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s1, imm); @@ -5167,7 +5193,7 @@ static ir_node *gen_popcount(ir_node *node) /* s2 = m3 >> 2 */ simm = ia32_create_Immediate(NULL, 0, 2); - s2 = new_bd_ia32_Shl(dbgi, new_block, m3, simm); + s2 = new_bd_ia32_Shr(dbgi, new_block, m3, simm); /* m5 = s2 & 0x33333333 */ m5 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, imm); @@ -5181,7 +5207,7 @@ static ir_node *gen_popcount(ir_node *node) /* s3 = m6 >> 4 */ simm = ia32_create_Immediate(NULL, 0, 4); - s3 = new_bd_ia32_Shl(dbgi, new_block, m6, simm); + s3 = new_bd_ia32_Shr(dbgi, new_block, m6, simm); /* m8 = s3 & 0x0F0F0F0F */ m8 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, imm); @@ -5195,7 +5221,7 @@ static ir_node *gen_popcount(ir_node *node) /* s4 = m9 >> 8 */ simm = ia32_create_Immediate(NULL, 0, 8); - s4 = new_bd_ia32_Shl(dbgi, new_block, m9, simm); + s4 = new_bd_ia32_Shr(dbgi, new_block, m9, simm); /* m11 = s4 & 0x00FF00FF */ m11 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s4, imm); @@ -5209,7 +5235,7 @@ static ir_node *gen_popcount(ir_node *node) /* s5 = m12 >> 16 */ simm = ia32_create_Immediate(NULL, 0, 16); - s5 = new_bd_ia32_Shl(dbgi, new_block, m12, simm); + s5 = new_bd_ia32_Shr(dbgi, new_block, m12, simm); /* res = m13 + s5 */ return new_bd_ia32_Lea(dbgi, new_block, m13, s5); @@ -5317,7 +5343,7 @@ static ir_node *gen_inner_trampoline(ir_node *node) /* construct store address */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, ptr, 0); + ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); if (addr.base == NULL) { addr.base = noreg_GP; @@ -5369,7 +5395,8 @@ static ir_node *gen_inner_trampoline(ir_node *node) if (is_SymConst(callee)) { rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, 0, -10); } else { - rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), ia32_create_Immediate(NULL, 0, -10)); + rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), noreg_GP); + add_ia32_am_offs_int(rel, -10); } rel = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, rel, trampoline); @@ -5473,7 +5500,7 @@ static ir_node *gen_Proj_Builtin(ir_node *proj) static ir_node *gen_be_IncSP(ir_node *node) { ir_node *res = be_duplicate_node(node); - arch_irn_add_flags(res, arch_irn_flags_modify_flags); + arch_add_irn_flags(res, arch_irn_flags_modify_flags); return res; } @@ -5490,23 +5517,27 @@ static ir_node *gen_Proj_be_Call(ir_node *node) ir_mode *mode = get_irn_mode(node); ir_node *res; - if (proj == pn_be_Call_M_regular) { + if (proj == pn_be_Call_M) { return new_rd_Proj(dbgi, new_call, mode_M, n_ia32_Call_mem); } /* transform call modes */ if (mode_is_data(mode)) { - const arch_register_class_t *cls = arch_get_irn_reg_class_out(node); + const arch_register_class_t *cls = arch_get_irn_reg_class(node); mode = cls->mode; } /* Map from be_Call to ia32_Call proj number */ if (proj == pn_be_Call_sp) { proj = pn_ia32_Call_stack; - } else if (proj == pn_be_Call_M_regular) { + } else if (proj == pn_be_Call_M) { proj = pn_ia32_Call_M; + } else if (proj == pn_be_Call_X_except) { + proj = pn_ia32_Call_X_except; + } else if (proj == pn_be_Call_X_regular) { + proj = pn_ia32_Call_X_regular; } else { - arch_register_req_t const *const req = arch_get_register_req_out(node); - int const n_outs = arch_irn_get_n_outs(new_call); + arch_register_req_t const *const req = arch_get_irn_register_req(node); + int const n_outs = arch_get_irn_n_outs(new_call); int i; assert(proj >= pn_be_Call_first_res); @@ -5514,7 +5545,7 @@ static ir_node *gen_Proj_be_Call(ir_node *node) for (i = 0; i < n_outs; ++i) { arch_register_req_t const *const new_req - = arch_get_out_register_req(new_call, i); + = arch_get_irn_register_req_out(new_call, i); if (!(new_req->type & arch_register_req_type_limited) || new_req->cls != req->cls || @@ -5531,13 +5562,13 @@ static ir_node *gen_Proj_be_Call(ir_node *node) /* TODO arch_set_irn_register() only operates on Projs, need variant with index */ switch (proj) { - case pn_ia32_Call_stack: - arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); - break; + case pn_ia32_Call_stack: + arch_set_irn_register(res, &ia32_registers[REG_ESP]); + break; - case pn_ia32_Call_fpcw: - arch_set_irn_register(res, &ia32_fp_cw_regs[REG_FPCW]); - break; + case pn_ia32_Call_fpcw: + arch_set_irn_register(res, &ia32_registers[REG_FPCW]); + break; } return res; @@ -5553,32 +5584,6 @@ static ir_node *gen_Proj_Cmp(ir_node *node) node); } -/** - * Transform the Projs from a Bound. - */ -static ir_node *gen_Proj_Bound(ir_node *node) -{ - ir_node *new_node, *block; - ir_node *pred = get_Proj_pred(node); - - switch (get_Proj_proj(node)) { - case pn_Bound_M: - return be_transform_node(get_Bound_mem(pred)); - case pn_Bound_X_regular: - new_node = be_transform_node(pred); - block = get_nodes_block(new_node); - return new_r_Proj(new_node, mode_X, pn_ia32_Jcc_true); - case pn_Bound_X_except: - new_node = be_transform_node(pred); - block = get_nodes_block(new_node); - return new_r_Proj(new_node, mode_X, pn_ia32_Jcc_false); - case pn_Bound_res: - return be_transform_node(get_Bound_index(pred)); - default: - panic("unsupported Proj from Bound"); - } -} - static ir_node *gen_Proj_ASM(ir_node *node) { ir_mode *mode = get_irn_mode(node); @@ -5587,11 +5592,11 @@ static ir_node *gen_Proj_ASM(ir_node *node) long pos = get_Proj_proj(node); if (mode == mode_M) { - pos = arch_irn_get_n_outs(new_pred)-1; + pos = arch_get_irn_n_outs(new_pred)-1; } else if (mode_is_int(mode) || mode_is_reference(mode)) { mode = mode_Iu; } else if (mode_is_float(mode)) { - mode = mode_E; + mode = ia32_mode_E; } else { panic("unexpected proj mode at ASM"); } @@ -5608,27 +5613,20 @@ static ir_node *gen_Proj(ir_node *node) long proj; switch (get_irn_opcode(pred)) { - case iro_Store: - proj = get_Proj_proj(node); - if (proj == pn_Store_M) { - return be_transform_node(pred); - } else { - panic("No idea how to transform proj->Store"); - } case iro_Load: return gen_Proj_Load(node); + case iro_Store: + return gen_Proj_Store(node); case iro_ASM: return gen_Proj_ASM(node); case iro_Builtin: return gen_Proj_Builtin(node); case iro_Div: + return gen_Proj_Div(node); case iro_Mod: - case iro_DivMod: - return gen_Proj_DivMod(node); + return gen_Proj_Mod(node); case iro_CopyB: return gen_Proj_CopyB(node); - case iro_Quot: - return gen_Proj_Quot(node); case beo_SubSP: return gen_Proj_be_SubSP(node); case beo_AddSP: @@ -5637,8 +5635,6 @@ static ir_node *gen_Proj(ir_node *node) return gen_Proj_be_Call(node); case iro_Cmp: return gen_Proj_Cmp(node); - case iro_Bound: - return gen_Proj_Bound(node); case iro_Start: proj = get_Proj_proj(node); switch (proj) { @@ -5651,9 +5647,6 @@ static ir_node *gen_Proj(ir_node *node) return jump; } - - case pn_Start_P_tls: - return gen_Proj_tls(node); } break; @@ -5684,97 +5677,62 @@ static ir_node *gen_Proj(ir_node *node) static void register_transformers(void) { /* first clear the generic function pointer for all ops */ - clear_irp_opcodes_generic_func(); - -#define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; } -#define BAD(a) op_##a->ops.generic = (op_func)bad_transform - - GEN(Add); - GEN(Sub); - GEN(Mul); - GEN(Mulh); - GEN(And); - GEN(Or); - GEN(Eor); - - GEN(Shl); - GEN(Shr); - GEN(Shrs); - GEN(Rotl); - - GEN(Quot); - - GEN(Div); - GEN(Mod); - GEN(DivMod); - - GEN(Minus); - GEN(Conv); - GEN(Abs); - GEN(Not); - - GEN(Load); - GEN(Store); - GEN(Cond); - - GEN(Cmp); - GEN(ASM); - GEN(CopyB); - GEN(Mux); - GEN(Proj); - GEN(Phi); - GEN(Jmp); - GEN(IJmp); - GEN(Bound); - - /* transform ops from intrinsic lowering */ - GEN(ia32_l_Add); - GEN(ia32_l_Adc); - GEN(ia32_l_Mul); - GEN(ia32_l_IMul); - GEN(ia32_l_ShlDep); - GEN(ia32_l_ShrDep); - GEN(ia32_l_SarDep); - GEN(ia32_l_ShlD); - GEN(ia32_l_ShrD); - GEN(ia32_l_Sub); - GEN(ia32_l_Sbb); - GEN(ia32_l_LLtoFloat); - GEN(ia32_l_FloattoLL); - - GEN(Const); - GEN(SymConst); - GEN(Unknown); - - /* we should never see these nodes */ - BAD(Raise); - BAD(Sel); - BAD(InstOf); - BAD(Cast); - BAD(Free); - BAD(Tuple); - BAD(Id); - //BAD(Bad); - BAD(Confirm); - BAD(Filter); - BAD(CallBegin); - BAD(EndReg); - BAD(EndExcept); - - /* handle builtins */ - GEN(Builtin); - - /* handle generic backend nodes */ - GEN(be_FrameAddr); - GEN(be_Call); - GEN(be_IncSP); - GEN(be_Return); - GEN(be_AddSP); - GEN(be_SubSP); - GEN(be_Copy); - -#undef GEN -#undef BAD + be_start_transform_setup(); + + be_set_transform_function(op_Add, gen_Add); + be_set_transform_function(op_And, gen_And); + be_set_transform_function(op_ASM, ia32_gen_ASM); + be_set_transform_function(op_be_AddSP, gen_be_AddSP); + be_set_transform_function(op_be_Call, gen_be_Call); + be_set_transform_function(op_be_Copy, gen_be_Copy); + be_set_transform_function(op_be_FrameAddr, gen_be_FrameAddr); + be_set_transform_function(op_be_IncSP, gen_be_IncSP); + be_set_transform_function(op_be_Return, gen_be_Return); + be_set_transform_function(op_be_SubSP, gen_be_SubSP); + be_set_transform_function(op_Builtin, gen_Builtin); + be_set_transform_function(op_Cmp, gen_Cmp); + be_set_transform_function(op_Cond, gen_Cond); + be_set_transform_function(op_Const, gen_Const); + be_set_transform_function(op_Conv, gen_Conv); + be_set_transform_function(op_CopyB, ia32_gen_CopyB); + be_set_transform_function(op_Div, gen_Div); + be_set_transform_function(op_Eor, gen_Eor); + be_set_transform_function(op_ia32_l_Adc, gen_ia32_l_Adc); + be_set_transform_function(op_ia32_l_Add, gen_ia32_l_Add); + be_set_transform_function(op_ia32_Leave, be_duplicate_node); + be_set_transform_function(op_ia32_l_FloattoLL, gen_ia32_l_FloattoLL); + be_set_transform_function(op_ia32_l_IMul, gen_ia32_l_IMul); + be_set_transform_function(op_ia32_l_LLtoFloat, gen_ia32_l_LLtoFloat); + be_set_transform_function(op_ia32_l_Mul, gen_ia32_l_Mul); + be_set_transform_function(op_ia32_l_Sbb, gen_ia32_l_Sbb); + be_set_transform_function(op_ia32_l_Sub, gen_ia32_l_Sub); + be_set_transform_function(op_ia32_GetEIP, be_duplicate_node); + be_set_transform_function(op_ia32_Minus64Bit, be_duplicate_node); + be_set_transform_function(op_ia32_NoReg_GP, be_duplicate_node); + be_set_transform_function(op_ia32_NoReg_VFP, be_duplicate_node); + be_set_transform_function(op_ia32_NoReg_XMM, be_duplicate_node); + be_set_transform_function(op_ia32_PopEbp, be_duplicate_node); + be_set_transform_function(op_ia32_Push, be_duplicate_node); + be_set_transform_function(op_IJmp, gen_IJmp); + be_set_transform_function(op_Jmp, gen_Jmp); + be_set_transform_function(op_Load, gen_Load); + be_set_transform_function(op_Minus, gen_Minus); + be_set_transform_function(op_Mod, gen_Mod); + be_set_transform_function(op_Mul, gen_Mul); + be_set_transform_function(op_Mulh, gen_Mulh); + be_set_transform_function(op_Mux, gen_Mux); + be_set_transform_function(op_Not, gen_Not); + be_set_transform_function(op_Or, gen_Or); + be_set_transform_function(op_Phi, gen_Phi); + be_set_transform_function(op_Proj, gen_Proj); + be_set_transform_function(op_Rotl, gen_Rotl); + be_set_transform_function(op_Shl, gen_Shl); + be_set_transform_function(op_Shr, gen_Shr); + be_set_transform_function(op_Shrs, gen_Shrs); + be_set_transform_function(op_Store, gen_Store); + be_set_transform_function(op_Sub, gen_Sub); + be_set_transform_function(op_SymConst, gen_SymConst); + be_set_transform_function(op_Unknown, ia32_gen_Unknown); } /** @@ -5782,104 +5740,17 @@ static void register_transformers(void) */ static void ia32_pretransform_node(void) { - ia32_code_gen_t *cg = env_cg; - - cg->unknown_gp = be_pre_transform_node(cg->unknown_gp); - cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp); - cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm); - cg->noreg_gp = be_pre_transform_node(cg->noreg_gp); - cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp); - cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm); - - nomem = get_irg_no_mem(current_ir_graph); - noreg_GP = ia32_new_NoReg_gp(cg); - - get_fpcw(); -} - -/** - * Walker, checks if all ia32 nodes producing more than one result have their - * Projs, otherwise creates new Projs and keeps them using a be_Keep node. - */ -static void add_missing_keep_walker(ir_node *node, void *data) -{ - int n_outs, i; - unsigned found_projs = 0; - const ir_edge_t *edge; - ir_mode *mode = get_irn_mode(node); - ir_node *last_keep; - (void) data; - if (mode != mode_T) - return; - if (!is_ia32_irn(node)) - return; - - n_outs = arch_irn_get_n_outs(node); - if (n_outs <= 0) - return; - if (is_ia32_SwitchJmp(node)) - return; - - assert(n_outs < (int) sizeof(unsigned) * 8); - foreach_out_edge(node, edge) { - ir_node *proj = get_edge_src_irn(edge); - int pn; - - /* The node could be kept */ - if (is_End(proj)) - continue; - - if (get_irn_mode(proj) == mode_M) - continue; - - pn = get_Proj_proj(proj); - assert(pn < n_outs); - found_projs |= 1 << pn; - } - + ir_graph *irg = current_ir_graph; + ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph); - /* are keeps missing? */ - last_keep = NULL; - for (i = 0; i < n_outs; ++i) { - ir_node *block; - ir_node *in[1]; - const arch_register_req_t *req; - const arch_register_class_t *cls; + irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp); + irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp); + irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm); + irg_data->get_eip = be_pre_transform_node(irg_data->get_eip); + irg_data->fpu_trunc_mode = be_pre_transform_node(irg_data->fpu_trunc_mode); - if (found_projs & (1 << i)) { - continue; - } - - req = arch_get_out_register_req(node, i); - cls = req->cls; - if (cls == NULL) { - continue; - } - if (cls == &ia32_reg_classes[CLASS_ia32_flags]) { - continue; - } - - block = get_nodes_block(node); - in[0] = new_r_Proj(node, arch_register_class_mode(cls), i); - if (last_keep != NULL) { - be_Keep_add_node(last_keep, cls, in[0]); - } else { - last_keep = be_new_Keep(block, 1, in); - if (sched_is_scheduled(node)) { - sched_add_after(node, last_keep); - } - } - } -} - -/** - * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs - * and keeps them. - */ -void ia32_add_missing_keeps(ia32_code_gen_t *cg) -{ - ir_graph *irg = be_get_birg_irg(cg->birg); - irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL); + nomem = get_irg_no_mem(irg); + noreg_GP = ia32_new_NoReg_gp(irg); } /** @@ -5889,9 +5760,9 @@ void ia32_add_missing_keeps(ia32_code_gen_t *cg) */ static void postprocess_fp_call_results(void) { - int i; + size_t i, n; - for (i = ARR_LEN(call_list) - 1; i >= 0; --i) { + for (i = 0, n = ARR_LEN(call_list); i < n; ++i) { ir_node *call = call_list[i]; ir_type *mtp = call_types[i]; int j; @@ -5900,14 +5771,14 @@ static void postprocess_fp_call_results(void) ir_type *res_tp = get_method_res_type(mtp, j); ir_node *res, *new_res; const ir_edge_t *edge, *next; - ir_mode *mode; + ir_mode *res_mode; if (! is_atomic_type(res_tp)) { /* no floating point return */ continue; } - mode = get_type_mode(res_tp); - if (! mode_is_float(mode)) { + res_mode = get_type_mode(res_tp); + if (! mode_is_float(res_mode)) { /* no floating point return */ continue; } @@ -5928,12 +5799,13 @@ static void postprocess_fp_call_results(void) dbg_info *db = get_irn_dbg_info(succ); ir_node *block = get_nodes_block(succ); ir_node *base = get_irn_n(succ, n_ia32_xStore_base); - ir_node *index = get_irn_n(succ, n_ia32_xStore_index); + ir_node *idx = get_irn_n(succ, n_ia32_xStore_index); ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem); ir_node *value = get_irn_n(succ, n_ia32_xStore_val); ir_mode *mode = get_ia32_ls_mode(succ); - ir_node *st = new_bd_ia32_vfst(db, block, base, index, mem, value, mode); + ir_node *st = new_bd_ia32_vfst(db, block, base, idx, mem, value, mode); + //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_vfst_M); set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ)); if (is_ia32_use_frame(succ)) set_ia32_use_frame(st); @@ -5941,55 +5813,67 @@ static void postprocess_fp_call_results(void) set_irn_pinned(st, get_irn_pinned(succ)); set_ia32_op_type(st, ia32_AddrModeD); + assert((long)pn_ia32_xStore_M == (long)pn_ia32_vfst_M); + assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_vfst_X_regular); + assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_vfst_X_except); + exchange(succ, st); - } else { - if (new_res == NULL) { - dbg_info *db = get_irn_dbg_info(call); - ir_node *block = get_nodes_block(call); - ir_node *frame = get_irg_frame(current_ir_graph); - ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M); - ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M); - ir_node *vfst, *xld, *new_mem; - - /* store st(0) on stack */ - vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, res, mode); - set_ia32_op_type(vfst, ia32_AddrModeD); - set_ia32_use_frame(vfst); - - /* load into SSE register */ - xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst, mode); - set_ia32_op_type(xld, ia32_AddrModeS); - set_ia32_use_frame(xld); - - new_res = new_r_Proj(xld, mode, pn_ia32_xLoad_res); - new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M); - - if (old_mem != NULL) { - edges_reroute(old_mem, new_mem, current_ir_graph); - kill_node(old_mem); - } + + continue; + } + + if (new_res == NULL) { + dbg_info *db = get_irn_dbg_info(call); + ir_node *block = get_nodes_block(call); + ir_node *frame = get_irg_frame(current_ir_graph); + ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M); + ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M); + ir_node *vfst, *xld, *new_mem; + ir_node *vfst_mem; + + /* store st(0) on stack */ + vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, + res, res_mode); + set_ia32_op_type(vfst, ia32_AddrModeD); + set_ia32_use_frame(vfst); + + vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_vfst_M); + + /* load into SSE register */ + xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst_mem, + res_mode); + set_ia32_op_type(xld, ia32_AddrModeS); + set_ia32_use_frame(xld); + + new_res = new_r_Proj(xld, res_mode, pn_ia32_xLoad_res); + new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M); + + if (old_mem != NULL) { + edges_reroute(old_mem, new_mem); + kill_node(old_mem); } - set_irn_n(succ, get_edge_src_pos(edge), new_res); } + set_irn_n(succ, get_edge_src_pos(edge), new_res); } } } } /* do the transformation */ -void ia32_transform_graph(ia32_code_gen_t *cg) +void ia32_transform_graph(ir_graph *irg) { int cse_last; register_transformers(); - env_cg = cg; - initial_fpcw = NULL; - no_pic_adjust = 0; + initial_fpcw = NULL; + ia32_no_pic_adjust = 0; + + old_initial_fpcw = be_get_initial_reg_value(irg, &ia32_registers[REG_FPCW]); be_timer_push(T_HEIGHTS); - heights = heights_new(cg->irg); + ia32_heights = heights_new(irg); be_timer_pop(T_HEIGHTS); - ia32_calculate_non_address_mode_nodes(cg->birg); + ia32_calculate_non_address_mode_nodes(irg); /* the transform phase is not safe for CSE (yet) because several nodes get * attributes set after their creation */ @@ -5998,7 +5882,7 @@ void ia32_transform_graph(ia32_code_gen_t *cg) call_list = NEW_ARR_F(ir_node *, 0); call_types = NEW_ARR_F(ir_type *, 0); - be_transform_graph(cg->birg, ia32_pretransform_node); + be_transform_graph(irg, ia32_pretransform_node); if (ia32_cg_config.use_sse2) postprocess_fp_call_results(); @@ -6008,8 +5892,8 @@ void ia32_transform_graph(ia32_code_gen_t *cg) set_opt_cse(cse_last); ia32_free_non_address_mode_nodes(); - heights_free(heights); - heights = NULL; + heights_free(ia32_heights); + ia32_heights = NULL; } void ia32_init_transform(void)