X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=6e986f7eef383caf1982d97a282a74f36df68a53;hb=e73a20bf2f7d542f4e6921b5d907c33d004c5f0a;hp=e649358a9baaa655e4bd487fd323edf2536631c6;hpb=c019db5bac0aaa9c93b6ce97be6822867f5970f4;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index e649358a9..6e986f7ee 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -22,7 +22,6 @@ * @brief This file implements the IR transformation from firm into * ia32-Firm. * @author Christian Wuerdig, Matthias Braun - * @version $Id$ */ #include "config.h" @@ -43,17 +42,18 @@ #include "irprintf.h" #include "debug.h" #include "irdom.h" +#include "iropt.h" #include "error.h" #include "array_t.h" #include "heights.h" -#include "../benode.h" -#include "../besched.h" -#include "../beabi.h" -#include "../beutil.h" -#include "../beirg.h" -#include "../betranshlp.h" -#include "../be_t.h" +#include "benode.h" +#include "besched.h" +#include "beabi.h" +#include "beutil.h" +#include "beirg.h" +#include "betranshlp.h" +#include "be_t.h" #include "bearch_ia32_t.h" #include "ia32_common_transform.h" @@ -62,7 +62,6 @@ #include "ia32_new_nodes.h" #include "ia32_dbg_stat.h" #include "ia32_optimize.h" -#include "ia32_util.h" #include "ia32_address_mode.h" #include "ia32_architecture.h" @@ -71,25 +70,12 @@ /* define this to construct SSE constants instead of load them */ #undef CONSTRUCT_SSE_CONST - -#define SFP_SIGN "0x80000000" -#define DFP_SIGN "0x8000000000000000" -#define SFP_ABS "0x7FFFFFFF" -#define DFP_ABS "0x7FFFFFFFFFFFFFFF" -#define DFP_INTMAX "9223372036854775807" -#define ULL_BIAS "18446744073709551616" - -#define ENT_SFP_SIGN "C_ia32_sfp_sign" -#define ENT_DFP_SIGN "C_ia32_dfp_sign" -#define ENT_SFP_ABS "C_ia32_sfp_abs" -#define ENT_DFP_ABS "C_ia32_dfp_abs" -#define ENT_ULL_BIAS "C_ia32_ull_bias" - #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode) #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode) DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) +static ir_node *old_initial_fpcw = NULL; static ir_node *initial_fpcw = NULL; int ia32_no_pic_adjust; @@ -201,7 +187,7 @@ static ir_node *get_symconst_base(void) { ir_graph *irg = current_ir_graph; - if (be_get_irg_options(irg)->pic) { + if (be_options.pic) { const arch_env_t *arch_env = be_get_irg_arch_env(irg); return arch_env->impl->get_pic_base(irg); } @@ -214,21 +200,23 @@ static ir_node *get_symconst_base(void) */ static ir_node *gen_Const(ir_node *node) { - ir_node *old_block = get_nodes_block(node); - ir_node *block = be_transform_node(old_block); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); + ir_node *old_block = get_nodes_block(node); + ir_node *block = be_transform_node(old_block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_tarval *tv = get_Const_tarval(node); assert(is_Const(node)); if (mode_is_float(mode)) { - ir_node *res = NULL; - ir_node *load; - ir_node *base; - ir_entity *floatent; + ir_graph *irg = get_irn_irg(node); + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + ia32_isa_t *isa = (ia32_isa_t*) arch_env; + ir_node *res = NULL; + ir_node *load; + ir_entity *floatent; if (ia32_cg_config.use_sse2) { - ir_tarval *tv = get_Const_tarval(node); if (tarval_is_null(tv)) { load = new_bd_ia32_xZero(dbgi, block); set_ia32_ls_mode(load, mode); @@ -259,6 +247,7 @@ static ir_node *gen_Const(ir_node *node) set_ia32_ls_mode(load, mode); res = load; } else { + ir_node *base; #ifdef CONSTRUCT_SSE_CONST if (mode == mode_D) { unsigned val = get_tarval_sub_bits(tv, 0) | @@ -284,22 +273,22 @@ static ir_node *gen_Const(ir_node *node) } } #endif /* CONSTRUCT_SSE_CONST */ - floatent = ia32_create_float_const_entity(node); + floatent = ia32_create_float_const_entity(isa, tv, NULL); base = get_symconst_base(); load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem, mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); res = new_r_Proj(load, mode_xmm, pn_ia32_xLoad_res); } } else { - if (is_Const_null(node)) { + if (tarval_is_null(tv)) { load = new_bd_ia32_vfldz(dbgi, block); res = load; set_ia32_ls_mode(load, mode); - } else if (is_Const_one(node)) { + } else if (tarval_is_one(tv)) { load = new_bd_ia32_vfld1(dbgi, block); res = load; set_ia32_ls_mode(load, mode); @@ -307,7 +296,7 @@ static ir_node *gen_Const(ir_node *node) ir_mode *ls_mode; ir_node *base; - floatent = ia32_create_float_const_entity(node); + floatent = ia32_create_float_const_entity(isa, tv, NULL); /* create_float_const_ent is smart and sometimes creates smaller entities */ ls_mode = get_type_mode(get_entity_type(floatent)); @@ -316,7 +305,7 @@ static ir_node *gen_Const(ir_node *node) ls_mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); res = new_r_Proj(load, mode_vfp, pn_ia32_vfld_res); } } @@ -326,9 +315,8 @@ end: SET_IA32_ORIG_NODE(load, node); return res; } else { /* non-float mode */ - ir_node *cnst; - ir_tarval *tv = get_Const_tarval(node); - long val; + ir_node *cnst; + long val; tv = tarval_convert_to(tv, mode_Iu); @@ -358,9 +346,9 @@ static ir_node *gen_SymConst(ir_node *node) if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) - cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E); + cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_D); else - cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E); + cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, ia32_mode_E); set_ia32_am_sc(cnst, get_SymConst_entity(node)); set_ia32_use_frame(cnst); } else { @@ -385,64 +373,18 @@ static ir_node *gen_SymConst(ir_node *node) return cnst; } -/** - * Create a float type for the given mode and cache it. - * - * @param mode the mode for the float type (might be integer mode for SSE2 types) - * @param align alignment - */ -static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) +static ir_type *make_array_type(ir_type *tp) { - ir_type *tp; - - assert(align <= 16); - - if (mode == mode_Iu) { - static ir_type *int_Iu[16] = {NULL, }; - - if (int_Iu[align] == NULL) { - int_Iu[align] = tp = new_type_primitive(mode); - /* set the specified alignment */ - set_type_alignment_bytes(tp, align); - } - return int_Iu[align]; - } else if (mode == mode_Lu) { - static ir_type *int_Lu[16] = {NULL, }; - - if (int_Lu[align] == NULL) { - int_Lu[align] = tp = new_type_primitive(mode); - /* set the specified alignment */ - set_type_alignment_bytes(tp, align); - } - return int_Lu[align]; - } else if (mode == mode_F) { - static ir_type *float_F[16] = {NULL, }; - - if (float_F[align] == NULL) { - float_F[align] = tp = new_type_primitive(mode); - /* set the specified alignment */ - set_type_alignment_bytes(tp, align); - } - return float_F[align]; - } else if (mode == mode_D) { - static ir_type *float_D[16] = {NULL, }; - - if (float_D[align] == NULL) { - float_D[align] = tp = new_type_primitive(mode); - /* set the specified alignment */ - set_type_alignment_bytes(tp, align); - } - return float_D[align]; - } else { - static ir_type *float_E[16] = {NULL, }; - - if (float_E[align] == NULL) { - float_E[align] = tp = new_type_primitive(mode); - /* set the specified alignment */ - set_type_alignment_bytes(tp, align); - } - return float_E[align]; - } + unsigned alignment = get_type_alignment_bytes(tp); + unsigned size = get_type_size_bytes(tp); + ir_type *res = new_type_array(1, tp); + set_type_alignment_bytes(res, alignment); + set_array_bounds_int(res, 0, 0, 2); + if (alignment > size) + size = alignment; + set_type_size_bytes(res, 2 * size); + set_type_state(res, layout_fixed); + return res; } /** @@ -453,33 +395,27 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) static ir_type *ia32_create_float_array(ir_type *tp) { ir_mode *mode = get_type_mode(tp); - unsigned align = get_type_alignment_bytes(tp); ir_type *arr; - assert(align <= 16); - if (mode == mode_F) { - static ir_type *float_F[16] = {NULL, }; + static ir_type *float_F; - if (float_F[align] != NULL) - return float_F[align]; - arr = float_F[align] = new_type_array(1, tp); + arr = float_F; + if (arr == NULL) + arr = float_F = make_array_type(tp); } else if (mode == mode_D) { - static ir_type *float_D[16] = {NULL, }; + static ir_type *float_D; - if (float_D[align] != NULL) - return float_D[align]; - arr = float_D[align] = new_type_array(1, tp); + arr = float_D; + if (arr == NULL) + arr = float_D = make_array_type(tp); } else { - static ir_type *float_E[16] = {NULL, }; + static ir_type *float_E; - if (float_E[align] != NULL) - return float_E[align]; - arr = float_E[align] = new_type_array(1, tp); + arr = float_E; + if (arr == NULL) + arr = float_E = make_array_type(tp); } - set_type_alignment_bytes(arr, align); - set_type_size_bytes(arr, 2 * get_type_size_bytes(tp)); - set_type_state(arr, layout_fixed); return arr; } @@ -487,58 +423,56 @@ static ir_type *ia32_create_float_array(ir_type *tp) ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) { static const struct { - const char *ent_name; + const char *name; const char *cnst_str; - char mode; - unsigned char align; + char mode; } names [ia32_known_const_max] = { - { ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */ - { ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */ - { ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */ - { ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */ - { ENT_ULL_BIAS, ULL_BIAS, 2, 4 } /* ia32_ULLBIAS */ + { "C_sfp_sign", "0x80000000", 0 }, + { "C_dfp_sign", "0x8000000000000000", 1 }, + { "C_sfp_abs", "0x7FFFFFFF", 0 }, + { "C_dfp_abs", "0x7FFFFFFFFFFFFFFF", 1 }, + { "C_ull_bias", "0x10000000000000000", 2 } }; static ir_entity *ent_cache[ia32_known_const_max]; - const char *ent_name, *cnst_str; - ir_type *tp; - ir_entity *ent; - ir_tarval *tv; - ir_mode *mode; - - ent_name = names[kct].ent_name; - if (! ent_cache[kct]) { - cnst_str = names[kct].cnst_str; + ir_entity *ent = ent_cache[kct]; + if (ent == NULL) { + ir_graph *irg = current_ir_graph; + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + ia32_isa_t *isa = (ia32_isa_t*) arch_env; + const char *cnst_str = names[kct].cnst_str; + ident *name = new_id_from_str(names[kct].name); + ir_mode *mode; + ir_tarval *tv; switch (names[kct].mode) { case 0: mode = mode_Iu; break; case 1: mode = mode_Lu; break; - default: mode = mode_F; break; + case 2: mode = mode_F; break; + default: panic("internal compiler error"); } - tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode); - tp = ia32_create_float_type(mode, names[kct].align); + tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode); - if (kct == ia32_ULLBIAS) - tp = ia32_create_float_array(tp); - ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp); + if (kct == ia32_ULLBIAS) { + ir_type *type = ia32_get_prim_type(mode_F); + ir_type *atype = ia32_create_float_array(type); + ir_initializer_t *initializer; - set_entity_ld_ident(ent, get_entity_ident(ent)); - add_entity_linkage(ent, IR_LINKAGE_CONSTANT); - set_entity_visibility(ent, ir_visibility_private); + ent = new_entity(get_glob_type(), name, atype); - if (kct == ia32_ULLBIAS) { - ir_initializer_t *initializer = create_initializer_compound(2); + set_entity_ld_ident(ent, name); + set_entity_visibility(ent, ir_visibility_private); + add_entity_linkage(ent, IR_LINKAGE_CONSTANT); + initializer = create_initializer_compound(2); set_initializer_compound_value(initializer, 0, create_initializer_tarval(get_mode_null(mode))); set_initializer_compound_value(initializer, 1, create_initializer_tarval(tv)); - set_entity_initializer(ent, initializer); } else { - set_entity_initializer(ent, create_initializer_tarval(tv)); + ent = ia32_create_float_const_entity(isa, tv, name); } - /* cache the entry */ ent_cache[kct] = ent; } @@ -553,15 +487,20 @@ ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) * input here, for unary operations use NULL). */ static int ia32_use_source_address_mode(ir_node *block, ir_node *node, - ir_node *other, ir_node *other2, match_flags_t flags) + ir_node *other, ir_node *other2, + match_flags_t flags) { ir_node *load; + ir_mode *mode; long pn; /* float constants are always available */ if (is_Const(node)) { - ir_mode *mode = get_irn_mode(node); + mode = get_irn_mode(node); if (mode_is_float(mode)) { + ir_tarval *tv = get_Const_tarval(node); + if (!tarval_ieee754_can_conv_lossless(tv, mode_D)) + return 0; if (ia32_cg_config.use_sse2) { if (is_simple_sse_Const(node)) return 0; @@ -573,6 +512,7 @@ static int ia32_use_source_address_mode(ir_node *block, ir_node *node, return 0; return 1; } + return 0; } if (!is_Proj(node)) @@ -583,6 +523,10 @@ static int ia32_use_source_address_mode(ir_node *block, ir_node *node, return 0; if (get_nodes_block(load) != block) return 0; + mode = get_irn_mode(node); + /* we can't fold mode_E AM */ + if (mode == ia32_mode_E) + return 0; /* we only use address mode if we're the only user of the load */ if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1)) return 0; @@ -638,7 +582,11 @@ static void build_address(ia32_address_mode_t *am, ir_node *node, /* floating point immediates */ if (is_Const(node)) { - ir_entity *entity = ia32_create_float_const_entity(node); + ir_graph *irg = get_irn_irg(node); + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + ia32_isa_t *isa = (ia32_isa_t*) arch_env; + ir_tarval *tv = get_Const_tarval(node); + ir_entity *entity = ia32_create_float_const_entity(isa, tv, NULL); addr->base = get_symconst_base(); addr->index = noreg_GP; addr->mem = nomem; @@ -714,12 +662,6 @@ static int is_downconv(const ir_node *node) if (!is_Conv(node)) return 0; - /* we only want to skip the conv when we're the only user - * (because this test is used in the context of address-mode selection - * and we don't want to use address mode for multiple users) */ - if (get_irn_n_edges(node) > 1) - return 0; - src_mode = get_irn_mode(get_Conv_op(node)); dest_mode = get_irn_mode(node); return @@ -731,8 +673,15 @@ static int is_downconv(const ir_node *node) /** Skip all Down-Conv's on a given node and return the resulting node. */ ir_node *ia32_skip_downconv(ir_node *node) { - while (is_downconv(node)) + while (is_downconv(node)) { + /* we only want to skip the conv when we're the only user + * (because this test is used in the context of address-mode selection + * and we don't want to use address mode for multiple users) */ + if (get_irn_n_edges(node) > 1) + break; + node = get_Conv_op(node); + } return node; } @@ -762,28 +711,44 @@ static bool is_sameconv(ir_node *node) /** Skip all signedness convs */ static ir_node *ia32_skip_sameconv(ir_node *node) { - while (is_sameconv(node)) + while (is_sameconv(node)) { node = get_Conv_op(node); + } return node; } -static ir_node *create_upconv(ir_node *node, ir_node *orig_node) +static ir_node *transform_sext(ir_node *node, ir_node *orig_node) { - ir_mode *mode = get_irn_mode(node); - ir_node *block; - ir_mode *tgt_mode; - dbg_info *dbgi; + ir_mode *mode = get_irn_mode(node); + ir_node *block = get_nodes_block(node); + dbg_info *dbgi = get_irn_dbg_info(node); + return create_I2I_Conv(mode, mode_Is, dbgi, block, node, orig_node); +} +static ir_node *transform_zext(ir_node *node, ir_node *orig_node) +{ + ir_mode *mode = get_irn_mode(node); + ir_node *block = get_nodes_block(node); + dbg_info *dbgi = get_irn_dbg_info(node); + /* normalize to an unsigned mode */ + switch (get_mode_size_bits(mode)) { + case 8: mode = mode_Bu; break; + case 16: mode = mode_Hu; break; + default: + panic("ia32: invalid mode in zest: %+F", node); + } + return create_I2I_Conv(mode, mode_Iu, dbgi, block, node, orig_node); +} + +static ir_node *transform_upconv(ir_node *node, ir_node *orig_node) +{ + ir_mode *mode = get_irn_mode(node); if (mode_is_signed(mode)) { - tgt_mode = mode_Is; + return transform_sext(node, orig_node); } else { - tgt_mode = mode_Iu; + return transform_zext(node, orig_node); } - block = get_nodes_block(node); - dbgi = get_irn_dbg_info(node); - - return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node); } /** @@ -880,7 +845,6 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } am->op_type = ia32_AddrModeS; } else { - ir_mode *mode; am->op_type = ia32_Normal; if (flags & match_try_am) { @@ -890,17 +854,29 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } mode = get_irn_mode(op2); - if (flags & match_upconv_32 && get_mode_size_bits(mode) != 32) { - new_op1 = (op1 == NULL ? NULL : create_upconv(op1, NULL)); - if (new_op2 == NULL) - new_op2 = create_upconv(op2, NULL); - am->ls_mode = mode_Iu; + if (get_mode_size_bits(mode) != 32 + && (flags & (match_mode_neutral | match_upconv | match_zero_ext))) { + if (flags & match_upconv) { + new_op1 = (op1 == NULL ? NULL : transform_upconv(op1, op1)); + if (new_op2 == NULL) + new_op2 = transform_upconv(op2, op2); + } else if (flags & match_zero_ext) { + new_op1 = (op1 == NULL ? NULL : transform_zext(op1, op1)); + if (new_op2 == NULL) + new_op2 = transform_zext(op2, op2); + } else { + new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); + if (new_op2 == NULL) + new_op2 = be_transform_node(op2); + assert(flags & match_mode_neutral); + } + mode = mode_Iu; } else { new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); if (new_op2 == NULL) new_op2 = be_transform_node(op2); - am->ls_mode = (flags & match_mode_neutral) ? mode_Iu : mode; } + am->ls_mode = mode; } if (addr->base == NULL) addr->base = noreg_GP; @@ -1038,17 +1014,45 @@ static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, static ir_node *get_fpcw(void) { - ir_node *fpcw; if (initial_fpcw != NULL) return initial_fpcw; - fpcw = be_abi_get_ignore_irn(current_ir_graph, - &ia32_registers[REG_FPCW]); - initial_fpcw = be_transform_node(fpcw); - + initial_fpcw = be_transform_node(old_initial_fpcw); return initial_fpcw; } +static ir_node *skip_float_upconv(ir_node *node) +{ + ir_mode *mode = get_irn_mode(node); + assert(mode_is_float(mode)); + + while (is_Conv(node)) { + ir_node *pred = get_Conv_op(node); + ir_mode *pred_mode = get_irn_mode(pred); + + /** + * suboptimal, but without this check the address mode matcher + * can incorrectly think that something has only 1 user + */ + if (get_irn_n_edges(node) > 1) + break; + + if (!mode_is_float(pred_mode) + || get_mode_size_bits(pred_mode) > get_mode_size_bits(mode)) + break; + node = pred; + mode = pred_mode; + } + return node; +} + +static void check_x87_floatmode(ir_mode *mode) +{ + if (mode != ia32_mode_E) { + panic("ia32: x87 only supports x86 extended float mode"); + } +} + /** * Construct a standard binary operation, set AM and immediate if required. * @@ -1060,27 +1064,22 @@ static ir_node *get_fpcw(void) static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, construct_binop_float_func *func) { - ir_mode *mode = get_irn_mode(node); dbg_info *dbgi; - ir_node *block, *new_block, *new_node; + ir_node *block; + ir_node *new_block; + ir_node *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; ia32_x87_attr_t *attr; /* All operations are considered commutative, because there are reverse * variants */ - match_flags_t flags = match_commutative; + match_flags_t flags = match_commutative | match_am; + ir_mode *mode + = is_Div(node) ? get_Div_resmode(node) : get_irn_mode(node); + check_x87_floatmode(mode); - /* happens for div nodes... */ - if (mode == mode_T) { - if (is_Div(node)) - mode = get_Div_resmode(node); - else - panic("can't determine mode"); - } - - /* cannot use address mode with long double on x87 */ - if (get_mode_size_bits(mode) <= 64) - flags |= match_am; + op1 = skip_float_upconv(op1); + op2 = skip_float_upconv(op2); block = get_nodes_block(node); match_arguments(&am, block, op1, op2, NULL, flags); @@ -1113,20 +1112,37 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, construct_shift_func *func, match_flags_t flags) { - dbg_info *dbgi; - ir_node *block, *new_block, *new_op1, *new_op2, *new_node; + ir_mode *mode = get_irn_mode(node); - assert(! mode_is_float(get_irn_mode(node))); + assert(! mode_is_float(mode)); assert(flags & match_immediate); - assert((flags & ~(match_mode_neutral | match_immediate)) == 0); + assert((flags & ~(match_mode_neutral | match_zero_ext | match_upconv | match_immediate)) == 0); + + if (get_mode_modulo_shift(mode) != 32) { + /* TODO: implement special cases for non-modulo shifts */ + panic("modulo shift!=32 not supported by ia32 backend"); + } + ir_node *new_op1; + ir_node *new_op2; if (flags & match_mode_neutral) { op1 = ia32_skip_downconv(op1); new_op1 = be_transform_node(op1); - } else if (get_mode_size_bits(get_irn_mode(node)) != 32) { - new_op1 = create_upconv(op1, node); } else { - new_op1 = be_transform_node(op1); + op1 = ia32_skip_sameconv(op1); + if (get_mode_size_bits(mode) != 32) { + if (flags & match_upconv) { + new_op1 = transform_upconv(op1, node); + } else if (flags & match_zero_ext) { + new_op1 = transform_zext(op1, node); + } else { + /* match_mode_neutral not handled here because it makes no + * sense for shift operations */ + panic("ia32 code selection failed for %+F", node); + } + } else { + new_op1 = be_transform_node(op1); + } } /* the shift amount can be any mode that is bigger than 5 bits, since all @@ -1140,10 +1156,10 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, } new_op2 = create_immediate_or_transform(op2, 0); - dbgi = get_irn_dbg_info(node); - block = get_nodes_block(node); - new_block = be_transform_node(block); - new_node = func(dbgi, new_block, new_op1, new_op2); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *new_node = func(dbgi, new_block, new_op1, new_op2); SET_IA32_ORIG_NODE(new_node, node); /* lowered shift instruction may have a dependency operand, handle it here */ @@ -1193,7 +1209,9 @@ static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, ia32_address_t *addr) { - ir_node *base, *index, *res; + ir_node *base; + ir_node *idx; + ir_node *res; base = addr->base; if (base == NULL) { @@ -1202,11 +1220,11 @@ static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, base = be_transform_node(base); } - index = addr->index; - if (index == NULL) { - index = noreg_GP; + idx = addr->index; + if (idx == NULL) { + idx = noreg_GP; } else { - index = be_transform_node(index); + idx = be_transform_node(idx); } /* segment overrides are ineffective for Leas :-( so we have to patch @@ -1221,7 +1239,7 @@ static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, addr->tls_segment = false; } - res = new_bd_ia32_Lea(dbgi, block, base, index); + res = new_bd_ia32_Lea(dbgi, block, base, idx); set_address(res, addr); return res; @@ -1237,6 +1255,118 @@ static int am_has_immediates(const ia32_address_t *addr) || addr->frame_entity || addr->use_frame; } +typedef ir_node* (*new_shiftd_func)(dbg_info *dbgi, ir_node *block, + ir_node *high, ir_node *low, + ir_node *count); + +/** + * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs: + * op1 - target to be shifted + * op2 - contains bits to be shifted into target + * op3 - shift count + * Only op3 can be an immediate. + */ +static ir_node *gen_64bit_shifts(dbg_info *dbgi, ir_node *block, + ir_node *high, ir_node *low, ir_node *count, + new_shiftd_func func) +{ + ir_node *new_block = be_transform_node(block); + ir_node *new_high = be_transform_node(high); + ir_node *new_low = be_transform_node(low); + ir_node *new_count; + ir_node *new_node; + + /* the shift amount can be any mode that is bigger than 5 bits, since all + * other bits are ignored anyway */ + while (is_Conv(count) && + get_irn_n_edges(count) == 1 && + mode_is_int(get_irn_mode(count))) { + assert(get_mode_size_bits(get_irn_mode(count)) >= 5); + count = get_Conv_op(count); + } + new_count = create_immediate_or_transform(count, 0); + + new_node = func(dbgi, new_block, new_high, new_low, new_count); + return new_node; +} + +/** + * test wether 2 values result in 'x' and '32-x' when interpreted as a shift + * value. + */ +static bool is_complementary_shifts(ir_node *value1, ir_node *value2) +{ + if (is_Const(value1) && is_Const(value2)) { + ir_tarval *tv1 = get_Const_tarval(value1); + ir_tarval *tv2 = get_Const_tarval(value2); + if (tarval_is_long(tv1) && tarval_is_long(tv2)) { + long v1 = get_tarval_long(tv1); + long v2 = get_tarval_long(tv2); + return v1 <= v2 && v2 == 32-v1; + } + } + return false; +} + +static ir_node *match_64bit_shift(ir_node *node) +{ + ir_node *op1 = get_binop_left(node); + ir_node *op2 = get_binop_right(node); + assert(is_Or(node) || is_Add(node)); + + if (is_Shr(op1)) { + ir_node *tmp = op1; + op1 = op2; + op2 = tmp; + } + + /* match ShlD operation */ + if (is_Shl(op1) && is_Shr(op2)) { + ir_node *shl_right = get_Shl_right(op1); + ir_node *shl_left = get_Shl_left(op1); + ir_node *shr_right = get_Shr_right(op2); + ir_node *shr_left = get_Shr_left(op2); + /* constant ShlD operation */ + if (is_complementary_shifts(shl_right, shr_right)) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + return gen_64bit_shifts(dbgi, block, shl_left, shr_left, shl_right, + new_bd_ia32_ShlD); + } + /* constant ShrD operation */ + if (is_complementary_shifts(shr_right, shl_right)) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + return gen_64bit_shifts(dbgi, block, shr_left, shl_left, shr_right, + new_bd_ia32_ShrD); + } + /* lower_dw produces the following for ShlD: + * Or(Shr(Shr(high,1),Not(c)),Shl(low,c)) */ + if (is_Shr(shr_left) && is_Not(shr_right) + && is_Const_1(get_Shr_right(shr_left)) + && get_Not_op(shr_right) == shl_right) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *val_h = get_Shr_left(shr_left); + return gen_64bit_shifts(dbgi, block, shl_left, val_h, shl_right, + new_bd_ia32_ShlD); + } + /* lower_dw produces the following for ShrD: + * Or(Shl(Shl(high,1),Not(c)), Shr(low,c)) */ + if (is_Shl(shl_left) && is_Not(shl_right) + && is_Const_1(get_Shl_right(shl_left)) + && get_Not_op(shl_right) == shr_right) { + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *val_h = get_Shl_left(shl_left); + return gen_64bit_shifts(dbgi, block, shr_left, val_h, shr_right, + new_bd_ia32_ShrD); + } + } + + return NULL; +} + /** * Creates an ia32 Add. * @@ -1252,6 +1382,10 @@ static ir_node *gen_Add(ir_node *node) ia32_address_t addr; ia32_address_mode_t am; + new_node = match_64bit_shift(node); + if (new_node != NULL) + return new_node; + if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) return gen_binop(node, op1, op2, new_bd_ia32_xAdd, @@ -1262,9 +1396,6 @@ static ir_node *gen_Add(ir_node *node) ia32_mark_non_am(node); - op2 = ia32_skip_downconv(op2); - op1 = ia32_skip_downconv(op1); - /** * Rules for an Add: * 0. Immediate Trees (example Add(Symconst, Const) -> Const) @@ -1422,8 +1553,6 @@ static ir_node *gen_And(ir_node *node) match_commutative | match_mode_neutral | match_am | match_immediate); } - - /** * Creates an ia32 Or. * @@ -1433,6 +1562,11 @@ static ir_node *gen_Or(ir_node *node) { ir_node *op1 = get_Or_left(node); ir_node *op2 = get_Or_right(node); + ir_node *res; + + res = match_64bit_shift(node); + if (res != NULL) + return res; assert (! mode_is_float(get_irn_mode(node))); return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative @@ -1566,9 +1700,10 @@ static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block, */ static ir_node *create_Div(ir_node *node) { - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + int throws_exception = ir_throws_exception(node); ir_node *mem; ir_node *new_mem; ir_node *op1; @@ -1597,7 +1732,7 @@ static ir_node *create_Div(ir_node *node) panic("invalid divmod node %+F", node); } - match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv_32); + match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv); /* Beware: We don't need a Sync, if the memory predecessor of the Div node is the memory of the consumed address. We can have only the second op as address @@ -1615,6 +1750,7 @@ static ir_node *create_Div(ir_node *node) addr->index, new_mem, am.new_op2, am.new_op1, sign_extension); } + ir_set_throws_exception(new_node, throws_exception); set_irn_pinned(new_node, get_irn_pinned(node)); @@ -1678,11 +1814,10 @@ static ir_node *gen_Shr(ir_node *node) ir_node *left = get_Shr_left(node); ir_node *right = get_Shr_right(node); - return gen_shift_binop(node, left, right, new_bd_ia32_Shr, match_immediate); + return gen_shift_binop(node, left, right, new_bd_ia32_Shr, + match_immediate | match_zero_ext); } - - /** * Creates an ia32 Sar. * @@ -1736,7 +1871,8 @@ static ir_node *gen_Shrs(ir_node *node) } } - return gen_shift_binop(node, left, right, new_bd_ia32_Sar, match_immediate); + return gen_shift_binop(node, left, right, new_bd_ia32_Sar, + match_immediate | match_upconv); } @@ -1823,6 +1959,7 @@ static ir_node *gen_Minus(ir_node *node) set_ia32_op_type(new_node, ia32_AddrModeS); set_ia32_ls_mode(new_node, mode); } else { + check_x87_floatmode(mode); new_node = new_bd_ia32_vfchs(dbgi, block, new_op); } } else { @@ -1849,68 +1986,43 @@ static ir_node *gen_Not(ir_node *node) return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral); } -static ir_node *create_abs(dbg_info *dbgi, ir_node *block, ir_node *op, - bool negate, ir_node *node) +static ir_node *create_float_abs(dbg_info *dbgi, ir_node *block, ir_node *op, + bool negate, ir_node *node) { ir_node *new_block = be_transform_node(block); ir_mode *mode = get_irn_mode(op); - ir_node *new_op; + ir_node *new_op = be_transform_node(op); ir_node *new_node; int size; ir_entity *ent; - if (mode_is_float(mode)) { - new_op = be_transform_node(op); + assert(mode_is_float(mode)); - if (ia32_cg_config.use_sse2) { - ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph); - new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(), - noreg_GP, nomem, new_op, noreg_fp); + if (ia32_cg_config.use_sse2) { + ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph); + new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(), + noreg_GP, nomem, new_op, noreg_fp); - size = get_mode_size_bits(mode); - ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS); + size = get_mode_size_bits(mode); + ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS); - set_ia32_am_sc(new_node, ent); + set_ia32_am_sc(new_node, ent); - SET_IA32_ORIG_NODE(new_node, node); + SET_IA32_ORIG_NODE(new_node, node); - set_ia32_op_type(new_node, ia32_AddrModeS); - set_ia32_ls_mode(new_node, mode); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode); - /* TODO, implement -Abs case */ - assert(!negate); - } else { - new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op); - SET_IA32_ORIG_NODE(new_node, node); - if (negate) { - new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node); - SET_IA32_ORIG_NODE(new_node, node); - } - } + /* TODO, implement -Abs case */ + assert(!negate); } else { - ir_node *xorn; - ir_node *sign_extension; - - if (get_mode_size_bits(mode) == 32) { - new_op = be_transform_node(op); - } else { - new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node); - } - - sign_extension = create_sex_32_64(dbgi, new_block, new_op, node); - - xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, - nomem, new_op, sign_extension); - SET_IA32_ORIG_NODE(xorn, node); - + check_x87_floatmode(mode); + new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op); + SET_IA32_ORIG_NODE(new_node, node); if (negate) { - new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, - nomem, sign_extension, xorn); - } else { - new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, - nomem, xorn, sign_extension); + new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node); + SET_IA32_ORIG_NODE(new_node, node); } - SET_IA32_ORIG_NODE(new_node, node); } return new_node; @@ -1931,7 +2043,8 @@ static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) } static ia32_condition_code_t relation_to_condition_code(ir_relation relation, - ir_mode *mode) + ir_mode *mode, + bool overflow_possible) { if (mode_is_float(mode)) { switch (relation) { @@ -1964,13 +2077,15 @@ static ia32_condition_code_t relation_to_condition_code(ir_relation relation, case ir_relation_unordered_equal: case ir_relation_equal: return ia32_cc_equal; case ir_relation_unordered_less: - case ir_relation_less: return ia32_cc_less; + case ir_relation_less: + return overflow_possible ? ia32_cc_less : ia32_cc_sign; case ir_relation_unordered_less_equal: case ir_relation_less_equal: return ia32_cc_less_equal; case ir_relation_unordered_greater: case ir_relation_greater: return ia32_cc_greater; case ir_relation_unordered_greater_equal: - case ir_relation_greater_equal: return ia32_cc_greater_equal; + case ir_relation_greater_equal: + return overflow_possible ? ia32_cc_greater_equal : ia32_cc_not_sign; case ir_relation_unordered_less_greater: case ir_relation_less_greater: return ia32_cc_not_equal; case ir_relation_less_equal_greater: @@ -2006,32 +2121,22 @@ static ia32_condition_code_t relation_to_condition_code(ir_relation relation, } } -static ir_node *get_flags_mode_b(ir_node *node, ia32_condition_code_t *cc_out) -{ - /* a mode_b value, we have to compare it against 0 */ - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_block = be_transform_node(get_nodes_block(node)); - ir_node *new_op = be_transform_node(node); - ir_node *flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, new_op, false); - *cc_out = ia32_cc_not_equal; - return flags; -} - -static ir_node *get_flags_node_cmp(ir_node *cmp, ia32_condition_code_t *cc_out) +static ir_node *get_flags_node(ir_node *cmp, ia32_condition_code_t *cc_out) { /* must have a Cmp as input */ ir_relation relation = get_Cmp_relation(cmp); - ir_relation possible; ir_node *l = get_Cmp_left(cmp); ir_node *r = get_Cmp_right(cmp); ir_mode *mode = get_irn_mode(l); + bool overflow_possible; ir_node *flags; /* check for bit-test */ - if (ia32_cg_config.use_bt && (relation == ir_relation_equal - || (mode_is_signed(mode) && relation == ir_relation_less_greater) - || (!mode_is_signed(mode) && ((relation & ir_relation_greater_equal) == ir_relation_greater))) - && is_And(l)) { + if (ia32_cg_config.use_bt + && (relation == ir_relation_equal + || (mode_is_signed(mode) && relation == ir_relation_less_greater) + || (!mode_is_signed(mode) && ((relation & ir_relation_greater_equal) == ir_relation_greater))) + && is_And(l)) { ir_node *la = get_And_left(l); ir_node *ra = get_And_right(l); if (is_Shl(ra)) { @@ -2044,7 +2149,7 @@ static ir_node *get_flags_node_cmp(ir_node *cmp, ia32_condition_code_t *cc_out) if (is_Const_1(c) && is_Const_0(r)) { /* (1 << n) & ra) */ ir_node *n = get_Shl_right(la); - flags = gen_bt(cmp, ra, n); + flags = gen_bt(cmp, ra, n); /* the bit is copied into the CF flag */ if (relation & ir_relation_equal) *cc_out = ia32_cc_above_equal; /* test for CF=0 */ @@ -2055,35 +2160,25 @@ static ir_node *get_flags_node_cmp(ir_node *cmp, ia32_condition_code_t *cc_out) } } - /* the middle-end tries to eliminate impossible relations, so a ptr != 0 + /* the middle-end tries to eliminate impossible relations, so a ptr <> 0 * test becomes ptr > 0. But for x86 an equal comparison is preferable to * a >0 (we can sometimes eliminate the cmp in favor of flags produced by - * a predecessor node). So add the < bit */ - possible = ir_get_possible_cmp_relations(l, r); - if (((relation & ir_relation_less) && !(possible & ir_relation_greater)) - || ((relation & ir_relation_greater) && !(possible & ir_relation_less))) - relation |= ir_relation_less_greater; + * a predecessor node). So add the < bit. + * (Note that we do not want to produce <=> (which can happen for + * unoptimized code), because no x86 flag can represent that */ + if (!(relation & ir_relation_equal) && relation & ir_relation_less_greater) + relation |= get_negated_relation(ir_get_possible_cmp_relations(l, r)) & ir_relation_less_greater; + + overflow_possible = true; + if (is_Const(r) && is_Const_null(r)) + overflow_possible = false; /* just do a normal transformation of the Cmp */ - *cc_out = relation_to_condition_code(relation, mode); + *cc_out = relation_to_condition_code(relation, mode, overflow_possible); flags = be_transform_node(cmp); return flags; } -/** - * Transform a node returning a "flag" result. - * - * @param node the node to transform - * @param cc_out the compare mode to use - */ -static ir_node *get_flags_node(ir_node *node, ia32_condition_code_t *cc_out) -{ - if (is_Cmp(node)) - return get_flags_node_cmp(node, cc_out); - assert(get_irn_mode(node) == mode_b); - return get_flags_mode_b(node, cc_out); -} - /** * Transforms a Load. * @@ -2098,16 +2193,17 @@ static ir_node *gen_Load(ir_node *node) ir_node *new_mem = be_transform_node(mem); dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_Load_mode(node); + int throws_exception = ir_throws_exception(node); ir_node *base; - ir_node *index; + ir_node *idx; ir_node *new_node; ia32_address_t addr; /* construct load address */ memset(&addr, 0, sizeof(addr)); ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); - base = addr.base; - index = addr.index; + base = addr.base; + idx = addr.index; if (base == NULL) { base = noreg_GP; @@ -2115,18 +2211,18 @@ static ir_node *gen_Load(ir_node *node) base = be_transform_node(base); } - if (index == NULL) { - index = noreg_GP; + if (idx == NULL) { + idx = noreg_GP; } else { - index = be_transform_node(index); + idx = be_transform_node(idx); } if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) { - new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem, + new_node = new_bd_ia32_xLoad(dbgi, block, base, idx, new_mem, mode); } else { - new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem, + new_node = new_bd_ia32_vfld(dbgi, block, base, idx, new_mem, mode); } } else { @@ -2134,12 +2230,13 @@ static ir_node *gen_Load(ir_node *node) /* create a conv node with address mode for smaller modes */ if (get_mode_size_bits(mode) < 32) { - new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index, + new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, idx, new_mem, noreg_GP, mode); } else { - new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem); + new_node = new_bd_ia32_Load(dbgi, block, base, idx, new_mem); } } + ir_set_throws_exception(new_node, throws_exception); set_irn_pinned(new_node, get_irn_pinned(node)); set_ia32_op_type(new_node, ia32_AddrModeS); @@ -2150,7 +2247,7 @@ static ir_node *gen_Load(ir_node *node) assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res && (int)pn_ia32_Load_res == (int)pn_ia32_res); - arch_irn_add_flags(new_node, arch_irn_flags_rematerializable); + arch_add_irn_flags(new_node, arch_irn_flags_rematerializable); } SET_IA32_ORIG_NODE(new_node, node); @@ -2532,72 +2629,82 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) dbg_info *dbgi = get_irn_dbg_info(node); int ofs = 0; int i = 0; + int throws_exception = ir_throws_exception(node); ir_node *ins[4]; ia32_address_t addr; - assert(size % 4 == 0); - assert(size <= 16); - build_address_ptr(&addr, ptr, mem); do { - unsigned val = - get_tarval_sub_bits(tv, ofs) | - (get_tarval_sub_bits(tv, ofs + 1) << 8) | - (get_tarval_sub_bits(tv, ofs + 2) << 16) | - (get_tarval_sub_bits(tv, ofs + 3) << 24); + unsigned val; + unsigned delta; + ir_mode *mode; + if (size >= 4) { + val= get_tarval_sub_bits(tv, ofs) | + (get_tarval_sub_bits(tv, ofs + 1) << 8) | + (get_tarval_sub_bits(tv, ofs + 2) << 16) | + (get_tarval_sub_bits(tv, ofs + 3) << 24); + delta = 4; + mode = mode_Iu; + } else if (size >= 2) { + val= get_tarval_sub_bits(tv, ofs) | + (get_tarval_sub_bits(tv, ofs + 1) << 8); + delta = 2; + mode = mode_Hu; + } else { + panic("invalid size of Store float to mem (%+F)", node); + } ir_node *imm = ia32_create_Immediate(NULL, 0, val); ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base, addr.index, addr.mem, imm); + ir_node *new_mem = new_r_Proj(new_node, mode_M, pn_ia32_Store_M); + ir_set_throws_exception(new_node, throws_exception); set_irn_pinned(new_node, get_irn_pinned(node)); set_ia32_op_type(new_node, ia32_AddrModeD); - set_ia32_ls_mode(new_node, mode_Iu); + set_ia32_ls_mode(new_node, mode); set_address(new_node, &addr); SET_IA32_ORIG_NODE(new_node, node); assert(i < 4); - ins[i++] = new_node; + ins[i++] = new_mem; - size -= 4; - ofs += 4; - addr.offset += 4; + size -= delta; + ofs += delta; + addr.offset += delta; } while (size != 0); if (i > 1) { return new_rd_Sync(dbgi, new_block, i, ins); } else { - return ins[0]; + return get_Proj_pred(ins[0]); } } /** * Generate a vfist or vfisttp instruction. */ -static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, - ir_node *mem, ir_node *val, ir_node **fist) +static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, + ir_node *index, ir_node *mem, ir_node *val) { - ir_node *new_node; - if (ia32_cg_config.use_fisttp) { /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied if other users exists */ ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val); - ir_node *value = new_r_Proj(vfisttp, mode_E, pn_ia32_vfisttp_res); + ir_node *value = new_r_Proj(vfisttp, ia32_mode_E, pn_ia32_vfisttp_res); be_new_Keep(block, 1, &value); - new_node = new_r_Proj(vfisttp, mode_M, pn_ia32_vfisttp_M); - *fist = vfisttp; + return vfisttp; } else { ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph); /* do a fist */ - new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode); - *fist = new_node; + ir_node *vfist = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode); + return vfist; } - return new_node; } + /** * Transforms a general (no special case) Store. * @@ -2612,7 +2719,9 @@ static ir_node *gen_general_Store(ir_node *node) ir_node *ptr = get_Store_ptr(node); ir_node *mem = get_Store_mem(node); dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_val, *new_node, *store; + int throws_exception = ir_throws_exception(node); + ir_node *new_val; + ir_node *new_node; ia32_address_t addr; /* check for destination address mode */ @@ -2638,14 +2747,6 @@ static ir_node *gen_general_Store(ir_node *node) addr.mem = be_transform_node(mem); if (mode_is_float(mode)) { - /* Convs (and strict-Convs) before stores are unnecessary if the mode - is the same. */ - while (is_Conv(val) && mode == get_irn_mode(val)) { - ir_node *op = get_Conv_op(val); - if (!mode_is_float(get_irn_mode(op))) - break; - val = op; - } new_val = be_transform_node(val); if (ia32_cg_config.use_sse2) { new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base, @@ -2654,42 +2755,35 @@ static ir_node *gen_general_Store(ir_node *node) new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, mode); } - store = new_node; } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) { - val = get_Conv_op(val); - - /* TODO: is this optimisation still necessary at all (middleend)? */ - /* We can skip ALL float->float up-Convs (and strict-up-Convs) before stores. */ - while (is_Conv(val)) { - ir_node *op = get_Conv_op(val); - if (!mode_is_float(get_irn_mode(op))) - break; - if (get_mode_size_bits(get_irn_mode(op)) > get_mode_size_bits(get_irn_mode(val))) - break; - val = op; - } + val = get_Conv_op(val); new_val = be_transform_node(val); - new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, &store); + new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val); } else { + unsigned dest_bits = get_mode_size_bits(mode); + while (is_downconv(val) + && get_mode_size_bits(get_irn_mode(val)) >= dest_bits) { + val = get_Conv_op(val); + } new_val = create_immediate_or_transform(val, 0); assert(mode != mode_b); - if (get_mode_size_bits(mode) == 8) { + if (dest_bits == 8) { new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base, addr.index, addr.mem, new_val); } else { new_node = new_bd_ia32_Store(dbgi, new_block, addr.base, addr.index, addr.mem, new_val); } - store = new_node; } + ir_set_throws_exception(new_node, throws_exception); - set_irn_pinned(store, get_irn_pinned(node)); - set_ia32_op_type(store, ia32_AddrModeD); - set_ia32_ls_mode(store, mode); + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeD); + set_ia32_ls_mode(new_node, mode); - set_address(store, &addr); - SET_IA32_ORIG_NODE(store, node); + set_address(new_node, &addr); + SET_IA32_ORIG_NODE(new_node, node); return new_node; } @@ -2701,8 +2795,8 @@ static ir_node *gen_general_Store(ir_node *node) */ static ir_node *gen_Store(ir_node *node) { - ir_node *val = get_Store_value(node); - ir_mode *mode = get_irn_mode(val); + ir_node *val = get_Store_value(node); + ir_mode *mode = get_irn_mode(val); if (mode_is_float(mode) && is_Const(val)) { /* We can transform every floating const store @@ -2720,48 +2814,39 @@ static ir_node *gen_Store(ir_node *node) * * @return the created ia32 SwitchJmp node */ -static ir_node *create_Switch(ir_node *node) -{ - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *sel = get_Cond_selector(node); - ir_node *new_sel = be_transform_node(sel); - long switch_min = LONG_MAX; - long switch_max = LONG_MIN; - long default_pn = get_Cond_default_proj(node); - ir_node *new_node; - const ir_edge_t *edge; - - assert(get_mode_size_bits(get_irn_mode(sel)) == 32); - - /* determine the smallest switch case value */ - foreach_out_edge(node, edge) { - ir_node *proj = get_edge_src_irn(edge); - long pn = get_Proj_proj(proj); - if (pn == default_pn) - continue; - - if (pn < switch_min) - switch_min = pn; - if (pn > switch_max) - switch_max = pn; - } - - if ((unsigned long) (switch_max - switch_min) > 128000) { - panic("Size of switch %+F bigger than 128000", node); - } - - if (switch_min != 0) { - /* if smallest switch case is not 0 we need an additional sub */ - new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg_GP); - add_ia32_am_offs_int(new_sel, -switch_min); - set_ia32_op_type(new_sel, ia32_AddrModeS); - - SET_IA32_ORIG_NODE(new_sel, node); - } - - new_node = new_bd_ia32_SwitchJmp(dbgi, block, new_sel, default_pn); +static ir_node *gen_Switch(ir_node *node) +{ + dbg_info *dbgi = get_irn_dbg_info(node); + ir_graph *irg = get_irn_irg(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *sel = get_Switch_selector(node); + ir_node *new_sel = be_transform_node(sel); + ir_mode *sel_mode = get_irn_mode(sel); + const ir_switch_table *table = get_Switch_table(node); + unsigned n_outs = get_Switch_n_outs(node); + ir_node *new_node; + ir_entity *entity; + + assert(get_mode_size_bits(sel_mode) <= 32); + assert(!mode_is_float(sel_mode)); + sel = ia32_skip_sameconv(sel); + if (get_mode_size_bits(sel_mode) < 32) + new_sel = transform_upconv(sel, node); + + entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type()); + set_entity_visibility(entity, ir_visibility_private); + add_entity_linkage(entity, IR_LINKAGE_CONSTANT); + + table = ir_switch_table_duplicate(irg, table); + + new_node = new_bd_ia32_SwitchJmp(dbgi, block, noreg_GP, new_sel, n_outs, table); + set_ia32_am_scale(new_node, 2); + set_ia32_am_sc(new_node, entity); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode_Iu); SET_IA32_ORIG_NODE(new_node, node); + // FIXME This seems wrong. GCC uses PIC for switch on OS X. + get_ia32_attr(new_node)->data.am_sc_no_pic_adjust = true; return new_node; } @@ -2775,15 +2860,10 @@ static ir_node *gen_Cond(ir_node *node) ir_node *new_block = be_transform_node(block); dbg_info *dbgi = get_irn_dbg_info(node); ir_node *sel = get_Cond_selector(node); - ir_mode *sel_mode = get_irn_mode(sel); ir_node *flags = NULL; ir_node *new_node; ia32_condition_code_t cc; - if (sel_mode != mode_b) { - return create_Switch(node); - } - /* we get flags from a Cmp */ flags = get_flags_node(sel, &cc); @@ -2816,8 +2896,10 @@ static ir_node *create_Fucom(ir_node *node) ir_node *left = get_Cmp_left(node); ir_node *new_left = be_transform_node(left); ir_node *right = get_Cmp_right(node); + ir_mode *cmp_mode = get_irn_mode(left); ir_node *new_right; ir_node *new_node; + check_x87_floatmode(cmp_mode); if (ia32_cg_config.use_fucomi) { new_right = be_transform_node(right); @@ -2826,15 +2908,14 @@ static ir_node *create_Fucom(ir_node *node) set_ia32_commutative(new_node); SET_IA32_ORIG_NODE(new_node, node); } else { - if (ia32_cg_config.use_ftst && is_Const_0(right)) { + if (is_Const_0(right)) { new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0); } else { new_right = be_transform_node(right); new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0); + set_ia32_commutative(new_node); } - set_ia32_commutative(new_node); - SET_IA32_ORIG_NODE(new_node, node); new_node = new_bd_ia32_Sahf(dbgi, new_block, new_node); @@ -2870,84 +2951,18 @@ static ir_node *create_Ucomi(ir_node *node) return new_node; } -/** - * returns true if it is assured, that the upper bits of a node are "clean" - * which means for a 16 or 8 bit value, that the upper bits in the register - * are 0 for unsigned and a copy of the last significant bit for signed - * numbers. - */ -static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode) +static bool ia32_mux_upper_bits_clean(const ir_node *node, ir_mode *mode) { - assert(ia32_mode_needs_gp_reg(mode)); - if (get_mode_size_bits(mode) >= 32) - return true; - - if (is_Proj(transformed_node)) - return upper_bits_clean(get_Proj_pred(transformed_node), mode); - - switch (get_ia32_irn_opcode(transformed_node)) { - case iro_ia32_Conv_I2I: - case iro_ia32_Conv_I2I8Bit: { - ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node); - if (mode_is_signed(smaller_mode) != mode_is_signed(mode)) - return false; - if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode)) - return false; - - return true; - } - - case iro_ia32_Shr: - if (mode_is_signed(mode)) { - return false; /* TODO handle signed modes */ - } else { - ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count); - if (is_ia32_Immediate(right) || is_ia32_Const(right)) { - const ia32_immediate_attr_t *attr - = get_ia32_immediate_attr_const(right); - if (attr->symconst == 0 && - (unsigned)attr->offset >= 32 - get_mode_size_bits(mode)) { - return true; - } - } - return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode); - } - - case iro_ia32_Sar: - /* TODO too conservative if shift amount is constant */ - return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Sar_val), mode); - - case iro_ia32_And: - if (!mode_is_signed(mode)) { - return - upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_right), mode) || - upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_left), mode); - } - /* TODO if one is known to be zero extended, then || is sufficient */ - /* FALLTHROUGH */ - case iro_ia32_Or: - case iro_ia32_Xor: - return - upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_right), mode) && - upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_left), mode); - - case iro_ia32_Const: - case iro_ia32_Immediate: { - const ia32_immediate_attr_t *attr = - get_ia32_immediate_attr_const(transformed_node); - if (mode_is_signed(mode)) { - long shifted = attr->offset >> (get_mode_size_bits(mode) - 1); - return shifted == 0 || shifted == -1; - } else { - unsigned long shifted = (unsigned long)attr->offset; - shifted >>= get_mode_size_bits(mode); - return shifted == 0; - } - } - - default: - return false; + ir_node *mux_true = get_Mux_true(node); + ir_node *mux_false = get_Mux_false(node); + ir_mode *mux_mode = get_irn_mode(node); + /* mux nodes which get transformed to the set instruction are not clean */ + if (is_Const(mux_true) && is_Const(mux_false) + && get_mode_size_bits(mux_mode) == 8) { + return false; } + return be_upper_bits_clean(mux_true, mode) + && be_upper_bits_clean(mux_false, mode); } /** @@ -2990,32 +3005,37 @@ static ir_node *gen_Cmp(ir_node *node) assert(get_irn_mode(and_left) == cmp_mode); match_arguments(&am, block, and_left, and_right, NULL, - match_commutative | - match_am | match_8bit_am | match_16bit_am | - match_am_and_immediates | match_immediate); + match_commutative | + match_am | match_8bit_am | match_16bit_am | + match_am_and_immediates | match_immediate); /* use 32bit compare mode if possible since the opcode is smaller */ - if (upper_bits_clean(am.new_op1, cmp_mode) && - upper_bits_clean(am.new_op2, cmp_mode)) { + if (am.op_type == ia32_Normal && + be_upper_bits_clean(and_left, cmp_mode) && + be_upper_bits_clean(and_right, cmp_mode)) { cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu; } if (get_mode_size_bits(cmp_mode) == 8) { new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base, - addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted); + addr->index, addr->mem, + am.new_op1, am.new_op2, + am.ins_permuted); } else { - new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, am.ins_permuted); + new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2, am.ins_permuted); } } else { /* Cmp(left, right) */ match_arguments(&am, block, left, right, NULL, - match_commutative | match_am | match_8bit_am | - match_16bit_am | match_am_and_immediates | - match_immediate); + match_commutative | + match_am | match_8bit_am | match_16bit_am | + match_am_and_immediates | match_immediate); /* use 32bit compare mode if possible since the opcode is smaller */ - if (upper_bits_clean(am.new_op1, cmp_mode) && - upper_bits_clean(am.new_op2, cmp_mode)) { + if (am.op_type == ia32_Normal && + be_upper_bits_clean(left, cmp_mode) && + be_upper_bits_clean(right, cmp_mode)) { cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu; } @@ -3025,7 +3045,8 @@ static ir_node *gen_Cmp(ir_node *node) am.new_op2, am.ins_permuted); } else { new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, am.ins_permuted); + addr->mem, am.new_op1, am.new_op2, + am.ins_permuted); } } set_am_attributes(new_node, &am); @@ -3128,9 +3149,11 @@ static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b) dbgi = get_irn_dbg_info(psi); sbb = new_bd_ia32_Sbb0(dbgi, block, eflags); + set_ia32_ls_mode(sbb, mode_Iu); notn = new_bd_ia32_Not(dbgi, block, sbb); new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, notn); + set_ia32_ls_mode(new_node, mode_Iu); set_ia32_commutative(new_node); return new_node; } @@ -3174,7 +3197,7 @@ static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **ne } - tp = ia32_create_float_type(mode, 4); + tp = ia32_get_prim_type(mode); tp = ia32_create_float_array(tp); ent = new_entity(get_glob_type(), id_unique("C%u"), tp); @@ -3207,7 +3230,6 @@ enum setcc_transform_insn { SETCC_TR_NOT, SETCC_TR_AND, SETCC_TR_SET, - SETCC_TR_SBB, }; typedef struct setcc_transform { @@ -3328,11 +3350,11 @@ static void find_const_transform(ia32_condition_code_t cc, ++step; res->steps[step].transform = SETCC_TR_NEG; } else { - int v = get_tarval_lowest_bit(t); - assert(v >= 0); + int val = get_tarval_lowest_bit(t); + assert(val >= 0); res->steps[step].transform = SETCC_TR_SHL; - res->steps[step].scale = v; + res->steps[step].scale = val; } } ++step; @@ -3364,9 +3386,15 @@ static ir_node *gen_Mux(ir_node *node) assert(get_irn_mode(sel) == mode_b); - is_abs = be_mux_is_abs(sel, mux_true, mux_false); + is_abs = ir_mux_is_abs(sel, mux_false, mux_true); if (is_abs != 0) { - return create_abs(dbgi, block, be_get_abs_op(sel), is_abs < 0, node); + if (ia32_mode_needs_gp_reg(mode)) { + ir_fprintf(stderr, "Optimisation warning: Integer abs %+F not transformed\n", + node); + } else { + ir_node *op = ir_get_abs_op(sel, mux_false, mux_true); + return create_float_abs(dbgi, block, op, is_abs < 0, node); + } } /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */ @@ -3418,31 +3446,15 @@ static ir_node *gen_Mux(ir_node *node) am.addr.symconst_ent = ia32_create_const_array(mux_false, mux_true, &new_mode); - switch (get_mode_size_bytes(new_mode)) { - case 4: + if (new_mode == mode_F) { scale = 2; - break; - case 8: + } else if (new_mode == mode_D) { scale = 3; - break; - case 10: - /* use 2 * 5 */ - scale = 1; - new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); - set_ia32_am_scale(new_node, 2); - break; - case 12: - /* use 4 * 3 */ - scale = 2; - new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); - set_ia32_am_scale(new_node, 1); - break; - case 16: + } else if (new_mode == ia32_mode_E) { /* arg, shift 16 NOT supported */ scale = 3; new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); - break; - default: + } else { panic("Unsupported constant size"); } @@ -3553,9 +3565,6 @@ static ir_node *gen_Mux(ir_node *node) case SETCC_TR_SET: new_node = create_set_32bit(dbgi, new_block, flags, res.cc, node); break; - case SETCC_TR_SBB: - new_node = new_bd_ia32_Sbb0(dbgi, new_block, flags); - break; default: panic("unknown setcc transform"); } @@ -3567,7 +3576,6 @@ static ir_node *gen_Mux(ir_node *node) } } - /** * Create a conversion from x87 state register to general purpose. */ @@ -3579,13 +3587,17 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); + ir_node *frame = get_irg_frame(irg); ir_node *fist, *load, *mem; - mem = gen_vfist(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist); + fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_op); set_irn_pinned(fist, op_pin_state_floats); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); + assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M); + mem = new_r_Proj(fist, mode_M, pn_ia32_vfist_M); + assert(get_mode_size_bits(mode) <= 32); /* exception we can only store signed 32 bit integers, so for unsigned we store a 64bit (signed) integer and load the lower bits */ @@ -3616,14 +3628,15 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) } /** - * Creates a x87 strict Conv by placing a Store and a Load + * Creates a x87 Conv by placing a Store and a Load */ -static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) +static ir_node *gen_x87_conv(ir_mode *tgt_mode, ir_node *node) { ir_node *block = get_nodes_block(node); ir_graph *irg = get_Block_irg(block); dbg_info *dbgi = get_irn_dbg_info(node); ir_node *frame = get_irg_frame(irg); + ir_node *store_mem; ir_node *store, *load; ir_node *new_node; @@ -3632,12 +3645,14 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) set_ia32_op_type(store, ia32_AddrModeD); SET_IA32_ORIG_NODE(store, node); - load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store, tgt_mode); + store_mem = new_r_Proj(store, mode_M, pn_ia32_vfst_M); + + load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode); set_ia32_use_frame(load); set_ia32_op_type(load, ia32_AddrModeS); SET_IA32_ORIG_NODE(load, node); - new_node = new_r_Proj(load, mode_E, pn_ia32_vfld_res); + new_node = new_r_Proj(load, ia32_mode_E, pn_ia32_vfld_res); return new_node; } @@ -3666,13 +3681,14 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) ir_mode *store_mode; ir_node *fild; ir_node *store; + ir_node *store_mem; ir_node *new_node; /* fild can use source AM if the operand is a signed 16bit or 32bit integer */ if (possible_int_mode_for_fp(src_mode)) { ia32_address_mode_t am; - match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am); + match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am | match_upconv); if (am.op_type == ia32_AddrModeS) { ia32_address_t *addr = &am.addr; @@ -3695,7 +3711,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) /* first convert to 32 bit signed if necessary */ if (get_mode_size_bits(src_mode) < 32) { - if (!upper_bits_clean(new_op, src_mode)) { + if (!be_upper_bits_clean(op, src_mode)) { new_op = create_Conv_I2I(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, src_mode); SET_IA32_ORIG_NODE(new_op, node); } @@ -3711,6 +3727,8 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) set_ia32_op_type(store, ia32_AddrModeD); set_ia32_ls_mode(store, mode_Iu); + store_mem = new_r_Proj(store, mode_M, pn_ia32_Store_M); + /* exception for 32bit unsigned, do a 64bit spill+load */ if (!mode_is_signed(mode)) { ir_node *in[2]; @@ -3719,23 +3737,24 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, zero_const); + ir_node *zero_store_mem = new_r_Proj(zero_store, mode_M, pn_ia32_Store_M); set_ia32_use_frame(zero_store); set_ia32_op_type(zero_store, ia32_AddrModeD); add_ia32_am_offs_int(zero_store, 4); set_ia32_ls_mode(zero_store, mode_Iu); - in[0] = zero_store; - in[1] = store; + in[0] = zero_store_mem; + in[1] = store_mem; - store = new_rd_Sync(dbgi, block, 2, in); + store_mem = new_rd_Sync(dbgi, block, 2, in); store_mode = mode_Ls; } else { store_mode = mode_Is; } /* do a fild */ - fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store); + fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem); set_ia32_use_frame(fild); set_ia32_op_type(fild, ia32_AddrModeS); @@ -3755,16 +3774,11 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, { ir_node *new_block = be_transform_node(block); ir_node *new_node; - ir_mode *smaller_mode; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; (void) node; - if (get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode)) { - smaller_mode = src_mode; - } else { - smaller_mode = tgt_mode; - } + assert(get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode)); #ifdef DEBUG_libfirm if (is_Const(op)) { @@ -3773,25 +3787,19 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, } #endif + if (be_upper_bits_clean(op, src_mode)) { + return be_transform_node(op); + } + match_arguments(&am, block, NULL, op, NULL, match_am | match_8bit_am | match_16bit_am); - if (upper_bits_clean(am.new_op2, smaller_mode)) { - /* unnecessary conv. in theory it shouldn't have been AM */ - assert(is_ia32_NoReg_GP(addr->base)); - assert(is_ia32_NoReg_GP(addr->index)); - assert(is_NoMem(addr->mem)); - assert(am.addr.offset == 0); - assert(am.addr.symconst_ent == NULL); - return am.new_op2; - } - new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index, - addr->mem, am.new_op2, smaller_mode); + addr->mem, am.new_op2, src_mode); set_am_attributes(new_node, &am); /* match_arguments assume that out-mode = in-mode, this isn't true here * so fix it */ - set_ia32_ls_mode(new_node, smaller_mode); + set_ia32_ls_mode(new_node, src_mode); SET_IA32_ORIG_NODE(new_node, node); new_node = fix_mem_proj(new_node, &am); return new_node; @@ -3824,17 +3832,10 @@ static ir_node *gen_Conv(ir_node *node) } if (src_mode == tgt_mode) { - if (get_Conv_strict(node)) { - if (ia32_cg_config.use_sse2) { - /* when we are in SSE mode, we can kill all strict no-op conversion */ - return be_transform_node(op); - } - } else { - /* this should be optimized already, but who knows... */ - DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node)); + /* this should be optimized already, but who knows... */ + DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node);) DB((dbg, LEVEL_1, "killed Conv(mode, mode) ...")); - return be_transform_node(op); - } + return be_transform_node(op); } if (mode_is_float(src_mode)) { @@ -3848,21 +3849,14 @@ static ir_node *gen_Conv(ir_node *node) nomem, new_op); set_ia32_ls_mode(res, tgt_mode); } else { - if (get_Conv_strict(node)) { - /* if fp_no_float_fold is not set then we assume that we - * don't have any float operations in a non - * mode_float_arithmetic mode and can skip strict upconvs */ - if (src_bits < tgt_bits) { - DB((dbg, LEVEL_1, "killed Conv(float, float) ...")); - return new_op; - } else { - res = gen_x87_strict_conv(tgt_mode, new_op); - SET_IA32_ORIG_NODE(get_Proj_pred(res), node); - return res; - } + if (src_bits < tgt_bits) { + DB((dbg, LEVEL_1, "killed Conv(float, float) ...")); + return new_op; + } else { + res = gen_x87_conv(tgt_mode, new_op); + SET_IA32_ORIG_NODE(get_Proj_pred(res), node); + return res; } - DB((dbg, LEVEL_1, "killed Conv(float, float) ...")); - return new_op; } } else { /* ... to int */ @@ -3887,13 +3881,13 @@ static ir_node *gen_Conv(ir_node *node) set_ia32_ls_mode(res, tgt_mode); } else { unsigned int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0); - unsigned float_mantissa = tarval_ieee754_get_mantissa_size(tgt_mode); + unsigned float_mantissa = get_mode_mantissa_size(tgt_mode); res = gen_x87_gp_to_fp(node, src_mode); - /* we need a strict-Conv, if the int mode has more bits than the + /* we need a float-conv, if the int mode has more bits than the * float mantissa */ if (float_mantissa < int_mantissa) { - res = gen_x87_strict_conv(tgt_mode, res); + res = gen_x87_conv(tgt_mode, res); SET_IA32_ORIG_NODE(get_Proj_pred(res), node); } return res; @@ -3905,7 +3899,7 @@ static ir_node *gen_Conv(ir_node *node) return be_transform_node(op); } else { /* to int */ - if (src_bits == tgt_bits) { + if (src_bits >= tgt_bits) { DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode)); return be_transform_node(op); @@ -3965,7 +3959,11 @@ static ir_node *gen_be_Return(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_type *res_type; ir_mode *mode; - ir_node *frame, *sse_store, *fld, *mproj; + ir_node *frame; + ir_node *sse_store; + ir_node *store_mem; + ir_node *fld; + ir_node *mproj; int i; int arity; unsigned pop; @@ -3998,9 +3996,10 @@ static ir_node *gen_be_Return(ir_node *node) set_ia32_ls_mode(sse_store, mode); set_ia32_op_type(sse_store, ia32_AddrModeD); set_ia32_use_frame(sse_store); + store_mem = new_r_Proj(sse_store, mode_M, pn_ia32_xStoreSimple_M); /* load into x87 register */ - fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, sse_store, mode); + fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, mode); set_ia32_op_type(fld, ia32_AddrModeS); set_ia32_use_frame(fld); @@ -4038,8 +4037,8 @@ static ir_node *gen_be_AddSP(ir_node *node) ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_SubSP, match_am | match_immediate); assert(is_ia32_SubSP(new_node)); - arch_irn_set_register(new_node, pn_ia32_SubSP_stack, - &ia32_registers[REG_ESP]); + arch_set_irn_register_out(new_node, pn_ia32_SubSP_stack, + &ia32_registers[REG_ESP]); return new_node; } @@ -4054,23 +4053,15 @@ static ir_node *gen_be_SubSP(ir_node *node) ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_AddSP, match_am | match_immediate); assert(is_ia32_AddSP(new_node)); - arch_irn_set_register(new_node, pn_ia32_AddSP_stack, - &ia32_registers[REG_ESP]); + arch_set_irn_register_out(new_node, pn_ia32_AddSP_stack, + &ia32_registers[REG_ESP]); return new_node; } -/** - * Change some phi modes - */ static ir_node *gen_Phi(ir_node *node) { + ir_mode *mode = get_irn_mode(node); const arch_register_req_t *req; - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *phi; - if (ia32_mode_needs_gp_reg(mode)) { /* we shouldn't have any 64bit stuff around anymore */ assert(get_mode_size_bits(mode) <= 32); @@ -4089,18 +4080,7 @@ static ir_node *gen_Phi(ir_node *node) req = arch_no_register_req; } - /* phi nodes allow loops, so we use the old arguments for now - * and fix this later */ - phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), - get_irn_in(node) + 1); - copy_node_attr(irg, node, phi); - be_duplicate_deps(node, phi); - - arch_set_out_register_req(phi, 0, req); - - be_enqueue_preds(node); - - return phi; + return be_transform_phi(node, req); } static ir_node *gen_Jmp(ir_node *node) @@ -4131,10 +4111,11 @@ static ir_node *gen_IJmp(ir_node *node) assert(get_irn_mode(op) == mode_P); - match_arguments(&am, block, NULL, op, NULL, match_am | match_immediate); + match_arguments(&am, block, NULL, op, NULL, + match_am | match_immediate | match_upconv); new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index, - addr->mem, am.new_op2); + addr->mem, am.new_op2); set_am_attributes(new_node, &am); SET_IA32_ORIG_NODE(new_node, node); @@ -4143,31 +4124,6 @@ static ir_node *gen_IJmp(ir_node *node) return new_node; } -static ir_node *gen_ia32_l_ShlDep(ir_node *node) -{ - ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val); - ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count); - - return gen_shift_binop(node, left, right, new_bd_ia32_Shl, - match_immediate | match_mode_neutral); -} - -static ir_node *gen_ia32_l_ShrDep(ir_node *node) -{ - ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val); - ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count); - return gen_shift_binop(node, left, right, new_bd_ia32_Shr, - match_immediate); -} - -static ir_node *gen_ia32_l_SarDep(ir_node *node) -{ - ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val); - ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count); - return gen_shift_binop(node, left, right, new_bd_ia32_Sar, - match_immediate); -} - static ir_node *gen_ia32_l_Add(ir_node *node) { ir_node *left = get_irn_n(node, n_ia32_l_Add_left); @@ -4244,62 +4200,6 @@ static ir_node *gen_ia32_l_Sbb(ir_node *node) match_am | match_immediate | match_mode_neutral); } -/** - * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs: - * op1 - target to be shifted - * op2 - contains bits to be shifted into target - * op3 - shift count - * Only op3 can be an immediate. - */ -static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high, - ir_node *low, ir_node *count) -{ - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_high = be_transform_node(high); - ir_node *new_low = be_transform_node(low); - ir_node *new_count; - ir_node *new_node; - - /* the shift amount can be any mode that is bigger than 5 bits, since all - * other bits are ignored anyway */ - while (is_Conv(count) && - get_irn_n_edges(count) == 1 && - mode_is_int(get_irn_mode(count))) { - assert(get_mode_size_bits(get_irn_mode(count)) >= 5); - count = get_Conv_op(count); - } - new_count = create_immediate_or_transform(count, 0); - - if (is_ia32_l_ShlD(node)) { - new_node = new_bd_ia32_ShlD(dbgi, new_block, new_high, new_low, - new_count); - } else { - new_node = new_bd_ia32_ShrD(dbgi, new_block, new_high, new_low, - new_count); - } - SET_IA32_ORIG_NODE(new_node, node); - - return new_node; -} - -static ir_node *gen_ia32_l_ShlD(ir_node *node) -{ - ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high); - ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low); - ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count); - return gen_lowered_64bit_shifts(node, high, low, count); -} - -static ir_node *gen_ia32_l_ShrD(ir_node *node) -{ - ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high); - ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low); - ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count); - return gen_lowered_64bit_shifts(node, high, low, count); -} - static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) { ir_node *src_block = get_nodes_block(node); @@ -4313,10 +4213,13 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) ir_node *new_val_high = be_transform_node(val_high); ir_node *in[2]; ir_node *sync, *fild, *res; - ir_node *store_low, *store_high; + ir_node *store_low; + ir_node *store_high; + ir_node *mem_low; + ir_node *mem_high; if (ia32_cg_config.use_sse2) { - panic("ia32_l_LLtoFloat not implemented for SSE2"); + panic("not implemented for SSE2"); } /* do a store */ @@ -4327,6 +4230,9 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) SET_IA32_ORIG_NODE(store_low, node); SET_IA32_ORIG_NODE(store_high, node); + mem_low = new_r_Proj(store_low, mode_M, pn_ia32_Store_M); + mem_high = new_r_Proj(store_high, mode_M, pn_ia32_Store_M); + set_ia32_use_frame(store_low); set_ia32_use_frame(store_high); set_ia32_op_type(store_low, ia32_AddrModeD); @@ -4335,8 +4241,8 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) set_ia32_ls_mode(store_high, mode_Is); add_ia32_am_offs_int(store_high, 4); - in[0] = store_low; - in[1] = store_high; + in[0] = mem_low; + in[1] = mem_high; sync = new_rd_Sync(dbgi, block, 2, in); /* do a fild */ @@ -4394,15 +4300,16 @@ static ir_node *gen_ia32_l_FloattoLL(ir_node *node) ir_node *frame = get_irg_frame(irg); ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val); ir_node *new_val = be_transform_node(val); - ir_node *fist, *mem; + ir_node *fist; - mem = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val, &fist); + fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val); SET_IA32_ORIG_NODE(fist, node); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); set_ia32_ls_mode(fist, mode_Ls); - return mem; + assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M); + return new_r_Proj(fist, mode_M, pn_ia32_vfist_M); } static ir_node *gen_Proj_l_FloattoLL(ir_node *node) @@ -4492,10 +4399,9 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node) static ir_node *gen_Proj_Load(ir_node *node) { ir_node *new_pred; - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *pred = get_Proj_pred(node); - dbg_info *dbgi = get_irn_dbg_info(node); - long proj = get_Proj_proj(node); + ir_node *pred = get_Proj_pred(node); + dbg_info *dbgi = get_irn_dbg_info(node); + long proj = get_Proj_proj(node); /* loads might be part of source address mode matches, so we don't * transform the ProjMs yet (with the exception of loads whose result is @@ -4516,57 +4422,58 @@ static ir_node *gen_Proj_Load(ir_node *node) /* renumber the proj */ new_pred = be_transform_node(pred); if (is_ia32_Load(new_pred)) { - switch (proj) { + switch ((pn_Load)proj) { case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Load_res); case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Load_M); - case pn_Load_X_regular: - return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_regular); } } else if (is_ia32_Conv_I2I(new_pred) || is_ia32_Conv_I2I8Bit(new_pred)) { set_irn_mode(new_pred, mode_T); - if (proj == pn_Load_res) { + switch ((pn_Load)proj) { + case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_res); - } else if (proj == pn_Load_M) { + case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_mem); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_regular); } } else if (is_ia32_xLoad(new_pred)) { - switch (proj) { + switch ((pn_Load)proj) { case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xLoad_res); case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xLoad_M); - case pn_Load_X_regular: - return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_regular); } } else if (is_ia32_vfld(new_pred)) { - switch (proj) { + switch ((pn_Load)proj) { case pn_Load_res: return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res); case pn_Load_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M); - case pn_Load_X_regular: - return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_except); + case pn_Load_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_regular); } } else { /* can happen for ProJMs when source address mode happened for the @@ -4581,7 +4488,76 @@ static ir_node *gen_Proj_Load(ir_node *node) return new_rd_Proj(dbgi, new_pred, mode_M, 1); } - panic("No idea how to transform proj"); + panic("No idea how to transform Proj(Load) %+F", node); +} + +static ir_node *gen_Proj_Store(ir_node *node) +{ + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + dbg_info *dbgi = get_irn_dbg_info(node); + long pn = get_Proj_proj(node); + + if (is_ia32_Store(new_pred) || is_ia32_Store8Bit(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Store_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_regular); + } + } else if (is_ia32_vfist(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfist_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_regular); + } + } else if (is_ia32_vfisttp(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfisttp_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_regular); + } + } else if (is_ia32_vfst(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfst_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_regular); + } + } else if (is_ia32_xStore(new_pred)) { + switch ((pn_Store)pn) { + case pn_Store_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xStore_M); + case pn_Store_X_except: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_except); + case pn_Store_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_regular); + } + } else if (is_Sync(new_pred)) { + /* hack for the case that gen_float_const_Store produced a Sync */ + if (pn == pn_Store_M) { + return new_pred; + } + panic("exception control flow not implemented yet"); + } else if (get_ia32_op_type(new_pred) == ia32_AddrModeD) { + /* destination address mode */ + if (pn == pn_Store_M) { + return new_pred; + } + panic("exception control flow for destination AM not implemented yet"); + } + + panic("No idea how to transform Proj(Store) %+F", node); } /** @@ -4589,16 +4565,15 @@ static ir_node *gen_Proj_Load(ir_node *node) */ static ir_node *gen_Proj_Div(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); dbg_info *dbgi = get_irn_dbg_info(node); - long proj = get_Proj_proj(node); + long proj = get_Proj_proj(node); - assert(pn_ia32_Div_M == pn_ia32_IDiv_M); - assert(pn_ia32_Div_div_res == pn_ia32_IDiv_div_res); + assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M); + assert((long)pn_ia32_Div_div_res == (long)pn_ia32_IDiv_div_res); - switch (proj) { + switch ((pn_Div)proj) { case pn_Div_M: if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) { return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); @@ -4619,13 +4594,11 @@ static ir_node *gen_Proj_Div(ir_node *node) } else { panic("Div transformed to unexpected thing %+F", new_pred); } - case pn_Div_X_regular: - return new_rd_Jmp(dbgi, block); case pn_Div_X_except: set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except); + case pn_Div_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular); } panic("No idea how to transform proj->Div"); @@ -4642,19 +4615,19 @@ static ir_node *gen_Proj_Mod(ir_node *node) long proj = get_Proj_proj(node); assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)); - assert(pn_ia32_Div_M == pn_ia32_IDiv_M); - assert(pn_ia32_Div_mod_res == pn_ia32_IDiv_mod_res); + assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M); + assert((long)pn_ia32_Div_mod_res == (long)pn_ia32_IDiv_mod_res); - switch (proj) { + switch ((pn_Mod)proj) { case pn_Mod_M: return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); case pn_Mod_res: return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res); case pn_Mod_X_except: set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); - default: - break; + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except); + case pn_Mod_X_regular: + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular); } panic("No idea how to transform proj->Mod"); } @@ -4669,7 +4642,7 @@ static ir_node *gen_Proj_CopyB(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); - switch (proj) { + switch ((pn_CopyB)proj) { case pn_CopyB_M: if (is_ia32_CopyB_i(new_pred)) { return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M); @@ -4677,7 +4650,19 @@ static ir_node *gen_Proj_CopyB(ir_node *node) return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M); } break; - default: + case pn_CopyB_X_regular: + if (is_ia32_CopyB_i(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_regular); + } else if (is_ia32_CopyB(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_regular); + } + break; + case pn_CopyB_X_except: + if (is_ia32_CopyB_i(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_except); + } else if (is_ia32_CopyB(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_except); + } break; } @@ -4705,6 +4690,7 @@ static ir_node *gen_be_Call(ir_node *node) unsigned const pop = be_Call_get_pop(node); ir_type *const call_tp = be_Call_get_type(node); int old_no_pic_adjust; + int throws_exception = ir_throws_exception(node); /* Run the x87 simulator if the call returns a float value */ if (get_method_n_ress(call_tp) > 0) { @@ -4723,17 +4709,18 @@ static ir_node *gen_be_Call(ir_node *node) /* special case for PIC trampoline calls */ old_no_pic_adjust = ia32_no_pic_adjust; - ia32_no_pic_adjust = be_get_irg_options(current_ir_graph)->pic; + ia32_no_pic_adjust = be_options.pic; match_arguments(&am, src_block, NULL, src_ptr, src_mem, - match_am | match_immediate); + match_am | match_immediate | match_upconv); ia32_no_pic_adjust = old_no_pic_adjust; i = get_irn_arity(node) - 1; fpcw = be_transform_node(get_irn_n(node, i--)); for (; i >= n_be_Call_first_arg; --i) { - arch_register_req_t const *const req = arch_get_register_req(node, i); + arch_register_req_t const *const req + = arch_get_irn_register_req_in(node, i); ir_node *const reg_parm = be_transform_node(get_irn_n(node, i)); assert(req->type == arch_register_req_type_limited); @@ -4750,6 +4737,7 @@ static ir_node *gen_be_Call(ir_node *node) mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem); call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem, am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp); + ir_set_throws_exception(call, throws_exception); set_am_attributes(call, &am); call = fix_mem_proj(call, &am); @@ -4828,7 +4816,7 @@ static ir_node *gen_return_address(ir_node *node) assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res && (int)pn_ia32_Load_res == (int)pn_ia32_res); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); } SET_IA32_ORIG_NODE(load, node); @@ -4879,7 +4867,7 @@ static ir_node *gen_frame_address(ir_node *node) assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res && (int)pn_ia32_Load_res == (int)pn_ia32_res); - arch_irn_add_flags(load, arch_irn_flags_rematerializable); + arch_add_irn_flags(load, arch_irn_flags_rematerializable); } SET_IA32_ORIG_NODE(load, node); @@ -4892,7 +4880,7 @@ static ir_node *gen_frame_address(ir_node *node) static ir_node *gen_prefetch(ir_node *node) { dbg_info *dbgi; - ir_node *ptr, *block, *mem, *base, *index; + ir_node *ptr, *block, *mem, *base, *idx; ir_node *param, *new_node; long rw, locality; ir_tarval *tv; @@ -4911,8 +4899,8 @@ static ir_node *gen_prefetch(ir_node *node) memset(&addr, 0, sizeof(addr)); ptr = get_Builtin_param(node, 0); ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); - base = addr.base; - index = addr.index; + base = addr.base; + idx = addr.index; if (base == NULL) { base = noreg_GP; @@ -4920,10 +4908,10 @@ static ir_node *gen_prefetch(ir_node *node) base = be_transform_node(base); } - if (index == NULL) { - index = noreg_GP; + if (idx == NULL) { + idx = noreg_GP; } else { - index = be_transform_node(index); + idx = be_transform_node(idx); } dbgi = get_irn_dbg_info(node); @@ -4932,7 +4920,7 @@ static ir_node *gen_prefetch(ir_node *node) if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) { /* we have 3DNow!, this was already checked above */ - new_node = new_bd_ia32_PrefetchW(dbgi, block, base, index, mem); + new_node = new_bd_ia32_PrefetchW(dbgi, block, base, idx, mem); } else if (ia32_cg_config.use_sse_prefetch) { /* note: rw == 1 is IGNORED in that case */ param = get_Builtin_param(node, 2); @@ -4942,22 +4930,22 @@ static ir_node *gen_prefetch(ir_node *node) /* SSE style prefetch */ switch (locality) { case 0: - new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, index, mem); + new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, idx, mem); break; case 1: - new_node = new_bd_ia32_Prefetch2(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch2(dbgi, block, base, idx, mem); break; case 2: - new_node = new_bd_ia32_Prefetch1(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch1(dbgi, block, base, idx, mem); break; default: - new_node = new_bd_ia32_Prefetch0(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch0(dbgi, block, base, idx, mem); break; } } else { assert(ia32_cg_config.use_3dnow_prefetch); /* 3DNow! style prefetch */ - new_node = new_bd_ia32_Prefetch(dbgi, block, base, index, mem); + new_node = new_bd_ia32_Prefetch(dbgi, block, base, idx, mem); } set_irn_pinned(new_node, get_irn_pinned(node)); @@ -5027,6 +5015,7 @@ static ir_node *gen_ffs(ir_node *node) /* or */ orn = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg); + set_ia32_ls_mode(orn, mode_Iu); set_ia32_commutative(orn); /* add 1 */ @@ -5076,12 +5065,15 @@ static ir_node *gen_parity(ir_node *node) * operations) */ ir_node *count = ia32_create_Immediate(NULL, 0, 16); - ir_node *shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count); - ir_node *xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem, - shr, new_param); - ir_node *xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xor); + ir_node *shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count); + ir_node *xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem, + shr, new_param); + ir_node *xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xorn); ir_node *flags; + set_ia32_ls_mode(xorn, mode_Iu); + set_ia32_commutative(xorn); + set_irn_mode(xor2, mode_T); flags = new_r_Proj(xor2, mode_Iu, pn_ia32_XorHighLow_flags); @@ -5116,7 +5108,7 @@ static ir_node *gen_popcount(ir_node *node) ia32_address_t *addr = &am.addr; ir_node *cnt; - match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am); + match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am | match_upconv); cnt = new_bd_ia32_Popcnt(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2); set_am_attributes(cnt, &am); @@ -5217,27 +5209,23 @@ static ir_node *gen_bswap(ir_node *node) ir_node *new_block = be_transform_node(block); ir_mode *mode = get_irn_mode(param); unsigned size = get_mode_size_bits(mode); - ir_node *m1, *m2, *m3, *m4, *s1, *s2, *s3, *s4; switch (size) { case 32: - if (ia32_cg_config.use_i486) { + if (ia32_cg_config.use_bswap) { /* swap available */ return new_bd_ia32_Bswap(dbgi, new_block, param); + } else { + ir_node *i8 = ia32_create_Immediate(NULL, 0, 8); + ir_node *rol1 = new_bd_ia32_Rol(dbgi, new_block, param, i8); + ir_node *i16 = ia32_create_Immediate(NULL, 0, 16); + ir_node *rol2 = new_bd_ia32_Rol(dbgi, new_block, rol1, i16); + ir_node *rol3 = new_bd_ia32_Rol(dbgi, new_block, rol2, i8); + set_ia32_ls_mode(rol1, mode_Hu); + set_ia32_ls_mode(rol2, mode_Iu); + set_ia32_ls_mode(rol3, mode_Hu); + return rol3; } - s1 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24)); - s2 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8)); - - m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, ia32_create_Immediate(NULL, 0, 0xFF00)); - m2 = new_bd_ia32_Lea(dbgi, new_block, s1, m1); - - s3 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8)); - - m3 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, ia32_create_Immediate(NULL, 0, 0xFF0000)); - m4 = new_bd_ia32_Lea(dbgi, new_block, m2, m3); - - s4 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24)); - return new_bd_ia32_Lea(dbgi, new_block, m4, s4); case 16: /* swap16 always available */ @@ -5414,7 +5402,7 @@ static ir_node *gen_Builtin(ir_node *node) case ir_bk_inner_trampoline: return gen_inner_trampoline(node); } - panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind)); + panic("Builtin %s not implemented", get_builtin_kind_name(kind)); } /** @@ -5435,7 +5423,7 @@ static ir_node *gen_Proj_Builtin(ir_node *proj) case ir_bk_parity: case ir_bk_popcount: case ir_bk_bswap: - assert(get_Proj_proj(proj) == pn_Builtin_1_result); + assert(get_Proj_proj(proj) == pn_Builtin_max+1); return new_node; case ir_bk_trap: case ir_bk_debugbreak: @@ -5444,27 +5432,27 @@ static ir_node *gen_Proj_Builtin(ir_node *proj) assert(get_Proj_proj(proj) == pn_Builtin_M); return new_node; case ir_bk_inport: - if (get_Proj_proj(proj) == pn_Builtin_1_result) { + if (get_Proj_proj(proj) == pn_Builtin_max+1) { return new_r_Proj(new_node, get_irn_mode(proj), pn_ia32_Inport_res); } else { assert(get_Proj_proj(proj) == pn_Builtin_M); return new_r_Proj(new_node, mode_M, pn_ia32_Inport_M); } case ir_bk_inner_trampoline: - if (get_Proj_proj(proj) == pn_Builtin_1_result) { + if (get_Proj_proj(proj) == pn_Builtin_max+1) { return get_Tuple_pred(new_node, 1); } else { assert(get_Proj_proj(proj) == pn_Builtin_M); return get_Tuple_pred(new_node, 0); } } - panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind)); + panic("Builtin %s not implemented", get_builtin_kind_name(kind)); } static ir_node *gen_be_IncSP(ir_node *node) { ir_node *res = be_duplicate_node(node); - arch_irn_add_flags(res, arch_irn_flags_modify_flags); + arch_add_irn_flags(res, arch_irn_flags_modify_flags); return res; } @@ -5481,23 +5469,27 @@ static ir_node *gen_Proj_be_Call(ir_node *node) ir_mode *mode = get_irn_mode(node); ir_node *res; - if (proj == pn_be_Call_M_regular) { + if (proj == pn_be_Call_M) { return new_rd_Proj(dbgi, new_call, mode_M, n_ia32_Call_mem); } /* transform call modes */ if (mode_is_data(mode)) { - const arch_register_class_t *cls = arch_get_irn_reg_class_out(node); + const arch_register_class_t *cls = arch_get_irn_reg_class(node); mode = cls->mode; } /* Map from be_Call to ia32_Call proj number */ if (proj == pn_be_Call_sp) { proj = pn_ia32_Call_stack; - } else if (proj == pn_be_Call_M_regular) { + } else if (proj == pn_be_Call_M) { proj = pn_ia32_Call_M; + } else if (proj == pn_be_Call_X_except) { + proj = pn_ia32_Call_X_except; + } else if (proj == pn_be_Call_X_regular) { + proj = pn_ia32_Call_X_regular; } else { - arch_register_req_t const *const req = arch_get_register_req_out(node); - int const n_outs = arch_irn_get_n_outs(new_call); + arch_register_req_t const *const req = arch_get_irn_register_req(node); + int const n_outs = arch_get_irn_n_outs(new_call); int i; assert(proj >= pn_be_Call_first_res); @@ -5505,7 +5497,7 @@ static ir_node *gen_Proj_be_Call(ir_node *node) for (i = 0; i < n_outs; ++i) { arch_register_req_t const *const new_req - = arch_get_out_register_req(new_call, i); + = arch_get_irn_register_req_out(new_call, i); if (!(new_req->type & arch_register_req_type_limited) || new_req->cls != req->cls || @@ -5522,28 +5514,18 @@ static ir_node *gen_Proj_be_Call(ir_node *node) /* TODO arch_set_irn_register() only operates on Projs, need variant with index */ switch (proj) { - case pn_ia32_Call_stack: - arch_set_irn_register(res, &ia32_registers[REG_ESP]); - break; + case pn_ia32_Call_stack: + arch_set_irn_register(res, &ia32_registers[REG_ESP]); + break; - case pn_ia32_Call_fpcw: - arch_set_irn_register(res, &ia32_registers[REG_FPCW]); - break; + case pn_ia32_Call_fpcw: + arch_set_irn_register(res, &ia32_registers[REG_FPCW]); + break; } return res; } -/** - * Transform the Projs from a Cmp. - */ -static ir_node *gen_Proj_Cmp(ir_node *node) -{ - /* this probably means not all mode_b nodes were lowered... */ - panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)", - node); -} - static ir_node *gen_Proj_ASM(ir_node *node) { ir_mode *mode = get_irn_mode(node); @@ -5552,11 +5534,11 @@ static ir_node *gen_Proj_ASM(ir_node *node) long pos = get_Proj_proj(node); if (mode == mode_M) { - pos = arch_irn_get_n_outs(new_pred)-1; + pos = arch_get_irn_n_outs(new_pred)-1; } else if (mode_is_int(mode) || mode_is_reference(mode)) { mode = mode_Iu; } else if (mode_is_float(mode)) { - mode = mode_E; + mode = ia32_mode_E; } else { panic("unexpected proj mode at ASM"); } @@ -5573,15 +5555,10 @@ static ir_node *gen_Proj(ir_node *node) long proj; switch (get_irn_opcode(pred)) { - case iro_Store: - proj = get_Proj_proj(node); - if (proj == pn_Store_M) { - return be_transform_node(pred); - } else { - panic("No idea how to transform proj->Store"); - } case iro_Load: return gen_Proj_Load(node); + case iro_Store: + return gen_Proj_Store(node); case iro_ASM: return gen_Proj_ASM(node); case iro_Builtin: @@ -5598,8 +5575,6 @@ static ir_node *gen_Proj(ir_node *node) return gen_Proj_be_AddSP(node); case beo_Call: return gen_Proj_be_Call(node); - case iro_Cmp: - return gen_Proj_Cmp(node); case iro_Start: proj = get_Proj_proj(node); switch (proj) { @@ -5669,12 +5644,7 @@ static void register_transformers(void) be_set_transform_function(op_ia32_l_IMul, gen_ia32_l_IMul); be_set_transform_function(op_ia32_l_LLtoFloat, gen_ia32_l_LLtoFloat); be_set_transform_function(op_ia32_l_Mul, gen_ia32_l_Mul); - be_set_transform_function(op_ia32_l_SarDep, gen_ia32_l_SarDep); be_set_transform_function(op_ia32_l_Sbb, gen_ia32_l_Sbb); - be_set_transform_function(op_ia32_l_ShlDep, gen_ia32_l_ShlDep); - be_set_transform_function(op_ia32_l_ShlD, gen_ia32_l_ShlD); - be_set_transform_function(op_ia32_l_ShrDep, gen_ia32_l_ShrDep); - be_set_transform_function(op_ia32_l_ShrD, gen_ia32_l_ShrD); be_set_transform_function(op_ia32_l_Sub, gen_ia32_l_Sub); be_set_transform_function(op_ia32_GetEIP, be_duplicate_node); be_set_transform_function(op_ia32_Minus64Bit, be_duplicate_node); @@ -5701,8 +5671,11 @@ static void register_transformers(void) be_set_transform_function(op_Shrs, gen_Shrs); be_set_transform_function(op_Store, gen_Store); be_set_transform_function(op_Sub, gen_Sub); + be_set_transform_function(op_Switch, gen_Switch); be_set_transform_function(op_SymConst, gen_SymConst); be_set_transform_function(op_Unknown, ia32_gen_Unknown); + + be_set_upper_bits_clean_function(op_Mux, ia32_mux_upper_bits_clean); } /** @@ -5721,8 +5694,6 @@ static void ia32_pretransform_node(void) nomem = get_irg_no_mem(irg); noreg_GP = ia32_new_NoReg_gp(irg); - - get_fpcw(); } /** @@ -5742,15 +5713,14 @@ static void postprocess_fp_call_results(void) for (j = get_method_n_ress(mtp) - 1; j >= 0; --j) { ir_type *res_tp = get_method_res_type(mtp, j); ir_node *res, *new_res; - const ir_edge_t *edge, *next; - ir_mode *mode; + ir_mode *res_mode; if (! is_atomic_type(res_tp)) { /* no floating point return */ continue; } - mode = get_type_mode(res_tp); - if (! mode_is_float(mode)) { + res_mode = get_type_mode(res_tp); + if (! mode_is_float(res_mode)) { /* no floating point return */ continue; } @@ -5759,7 +5729,7 @@ static void postprocess_fp_call_results(void) new_res = NULL; /* now patch the users */ - foreach_out_edge_safe(res, edge, next) { + foreach_out_edge_safe(res, edge) { ir_node *succ = get_edge_src_irn(edge); /* ignore Keeps */ @@ -5771,12 +5741,13 @@ static void postprocess_fp_call_results(void) dbg_info *db = get_irn_dbg_info(succ); ir_node *block = get_nodes_block(succ); ir_node *base = get_irn_n(succ, n_ia32_xStore_base); - ir_node *index = get_irn_n(succ, n_ia32_xStore_index); + ir_node *idx = get_irn_n(succ, n_ia32_xStore_index); ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem); ir_node *value = get_irn_n(succ, n_ia32_xStore_val); ir_mode *mode = get_ia32_ls_mode(succ); - ir_node *st = new_bd_ia32_vfst(db, block, base, index, mem, value, mode); + ir_node *st = new_bd_ia32_vfst(db, block, base, idx, mem, value, mode); + //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_vfst_M); set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ)); if (is_ia32_use_frame(succ)) set_ia32_use_frame(st); @@ -5784,36 +5755,47 @@ static void postprocess_fp_call_results(void) set_irn_pinned(st, get_irn_pinned(succ)); set_ia32_op_type(st, ia32_AddrModeD); + assert((long)pn_ia32_xStore_M == (long)pn_ia32_vfst_M); + assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_vfst_X_regular); + assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_vfst_X_except); + exchange(succ, st); - } else { - if (new_res == NULL) { - dbg_info *db = get_irn_dbg_info(call); - ir_node *block = get_nodes_block(call); - ir_node *frame = get_irg_frame(current_ir_graph); - ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M); - ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M); - ir_node *vfst, *xld, *new_mem; - - /* store st(0) on stack */ - vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, res, mode); - set_ia32_op_type(vfst, ia32_AddrModeD); - set_ia32_use_frame(vfst); - - /* load into SSE register */ - xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst, mode); - set_ia32_op_type(xld, ia32_AddrModeS); - set_ia32_use_frame(xld); - - new_res = new_r_Proj(xld, mode, pn_ia32_xLoad_res); - new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M); - - if (old_mem != NULL) { - edges_reroute(old_mem, new_mem); - kill_node(old_mem); - } + + continue; + } + + if (new_res == NULL) { + dbg_info *db = get_irn_dbg_info(call); + ir_node *block = get_nodes_block(call); + ir_node *frame = get_irg_frame(current_ir_graph); + ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M); + ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M); + ir_node *vfst, *xld, *new_mem; + ir_node *vfst_mem; + + /* store st(0) on stack */ + vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, + res, res_mode); + set_ia32_op_type(vfst, ia32_AddrModeD); + set_ia32_use_frame(vfst); + + vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_vfst_M); + + /* load into SSE register */ + xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst_mem, + res_mode); + set_ia32_op_type(xld, ia32_AddrModeS); + set_ia32_use_frame(xld); + + new_res = new_r_Proj(xld, res_mode, pn_ia32_xLoad_res); + new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M); + + if (old_mem != NULL) { + edges_reroute(old_mem, new_mem); + kill_node(old_mem); } - set_irn_n(succ, get_edge_src_pos(edge), new_res); } + set_irn_n(succ, get_edge_src_pos(edge), new_res); } } } @@ -5828,6 +5810,8 @@ void ia32_transform_graph(ir_graph *irg) initial_fpcw = NULL; ia32_no_pic_adjust = 0; + old_initial_fpcw = be_get_initial_reg_value(irg, &ia32_registers[REG_FPCW]); + be_timer_push(T_HEIGHTS); ia32_heights = heights_new(irg); be_timer_pop(T_HEIGHTS);