X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=52ee5ea92aa03baa35037262efc7d31d2521c501;hb=cbfbedae75798a9830fb0ef090189345ede85dc8;hp=df81ef0e0ff02e21bb280c83e6b54865c4843756;hpb=50a823bf08de13bc862566d96ea6e1c3b2f3000a;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index df81ef0e0..52ee5ea92 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -150,6 +150,24 @@ static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_gr return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res); } +/** +* SSE convert of an float node into a double node. +*/ +static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block, + ir_node *in, ir_node *old_node) +{ + ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *nomem = new_rd_NoMem(irg); + + ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem); + set_ia32_src_mode(conv, mode_F); + set_ia32_tgt_mode(conv, mode_D); + set_ia32_am_support(conv, ia32_am_Source); + SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node)); + + return new_rd_Proj(dbg, irg, block, conv, mode_D, pn_ia32_Conv_FP2FP_res); +} + /* Generates an entity for a known FP const (used for FP Neg + Abs) */ static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) { static const struct { @@ -1401,7 +1419,7 @@ static ir_node *gen_Store(ia32_transform_env_t *env) { ir_node *ptr = get_Store_ptr(node); ir_node *sptr = ptr; ir_node *mem = get_Store_mem(node); - ir_mode *mode = get_irn_link(node); + ir_mode *mode = get_irn_mode(val); ir_node *sval = val; int is_imm = 0; ir_node *new_op; @@ -1629,9 +1647,9 @@ static ir_node *gen_CopyB(ia32_transform_env_t *env) { int rem; ir_node *in[3], *tmp; - /* If we have to copy more than 16 bytes, we use REP MOVSx and */ + /* If we have to copy more than 32 bytes, we use REP MOVSx and */ /* then we need the size explicitly in ECX. */ - if (size >= 16 * 4) { + if (size >= 32 * 4) { rem = size & 0x3; /* size % 4 */ size >>= 2; @@ -1998,6 +2016,7 @@ static ir_node *gen_Conv(ia32_transform_env_t *env) { int src_bits = get_mode_size_bits(src_mode); int tgt_bits = get_mode_size_bits(tgt_mode); int pn = -1; + int kill = 0; ir_node *block = env->block; ir_node *new_op = NULL; ir_node *noreg = ia32_new_NoReg_gp(env->cg); @@ -2021,7 +2040,13 @@ static ir_node *gen_Conv(ia32_transform_env_t *env) { } else { DB((mod, LEVEL_1, "killed Conv(float, float) ...")); - edges_reroute(env->irn, op, irg); + /* + remark: we create a intermediate conv here, so modes will be spread correctly + these convs will be killed later + */ + new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem); + pn = pn_ia32_Conv_FP2FP_res; + kill = 1; } } else { @@ -2071,7 +2096,13 @@ static ir_node *gen_Conv(ia32_transform_env_t *env) { /* ... to int */ if (get_mode_size_bits(src_mode) == tgt_bits) { DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode)); - edges_reroute(env->irn, op, irg); + /* + remark: we create a intermediate conv here, so modes will be spread correctly + these convs will be killed later + */ + new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem); + pn = pn_ia32_Conv_I2I_res; + kill = 1; } else { DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode)); @@ -2095,6 +2126,9 @@ static ir_node *gen_Conv(ia32_transform_env_t *env) { set_ia32_am_support(new_op, ia32_am_Source); new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn); + + if (kill) + nodeset_insert(env->cg->kill_conv, new_op); } return new_op; @@ -2151,7 +2185,7 @@ static ir_node *gen_be_StackParam(ia32_transform_env_t *env) { ir_node *noreg = ia32_new_NoReg_gp(env->cg); ir_node *mem = new_rd_NoMem(env->irg); ir_node *ptr = get_irn_n(node, 0); - entity *ent = be_get_frame_entity(node); + entity *ent = arch_get_frame_entity(env->cg->arch_env, node); ir_mode *mode = env->mode; /* choose the block where to place the load */ @@ -2175,6 +2209,7 @@ static ir_node *gen_be_StackParam(ia32_transform_env_t *env) { set_ia32_op_type(new_op, ia32_AddrModeS); set_ia32_am_flavour(new_op, ia32_B); set_ia32_ls_mode(new_op, mode); + set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable); SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); @@ -2192,7 +2227,7 @@ static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) { ir_node *nomem = new_rd_NoMem(env->irg); new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem); - set_ia32_frame_ent(new_op, be_get_frame_entity(node)); + set_ia32_frame_ent(new_op, arch_get_frame_entity(env->cg->arch_env, node)); set_ia32_am_support(new_op, ia32_am_Full); set_ia32_use_frame(new_op); set_ia32_immop_type(new_op, ia32_ImmConst); @@ -2212,7 +2247,7 @@ static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) { ir_node *noreg = ia32_new_NoReg_gp(env->cg); ir_node *mem = get_irn_n(node, 0); ir_node *ptr = get_irn_n(node, 1); - entity *ent = be_get_frame_entity(node); + entity *ent = arch_get_frame_entity(env->cg->arch_env, node); ir_mode *mode = get_type_mode(get_entity_type(ent)); if (mode_is_float(mode)) { @@ -2249,7 +2284,7 @@ static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) { ir_node *mem = get_irn_n(node, 0); ir_node *ptr = get_irn_n(node, 1); ir_node *val = get_irn_n(node, 2); - entity *ent = be_get_frame_entity(node); + entity *ent = arch_get_frame_entity(env->cg->arch_env, node); ir_mode *mode = get_irn_mode(val); if (mode_is_float(mode)) { @@ -2383,6 +2418,53 @@ static ir_node *gen_be_Return(ia32_transform_env_t *env) { return NULL; } +/** + * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes. + */ +static ir_node *gen_be_AddSP(ia32_transform_env_t *env) { + ir_node *new_op; + const ir_edge_t *edge; + ir_node *sz = get_irn_n(env->irn, be_pos_AddSP_size); + ir_node *sp = get_irn_n(env->irn, be_pos_AddSP_old_sp); + + new_op = new_rd_ia32_AddSP(env->dbg, env->irg, env->block, sp, sz); + + if (is_ia32_Const(sz)) { + set_ia32_Immop_attr(new_op, sz); + set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg)); + } + else if (is_ia32_Load(sz) && get_ia32_am_flavour(sz) == ia32_O) { + set_ia32_immop_type(new_op, ia32_ImmSymConst); + set_ia32_op_type(new_op, ia32_AddrModeS); + set_ia32_am_sc(new_op, get_ia32_am_sc(sz)); + add_ia32_am_offs(new_op, get_ia32_am_offs(sz)); + set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg)); + } + + /* fix proj nums */ + foreach_out_edge(env->irn, edge) { + ir_node *proj = get_edge_src_irn(edge); + + assert(is_Proj(proj)); + + if (get_Proj_proj(proj) == pn_be_AddSP_res) { + /* the node is not yet exchanged: we need to set the register manually */ + ia32_attr_t *attr = get_ia32_attr(new_op); + attr->slots[pn_ia32_AddSP_stack] = &ia32_gp_regs[REG_ESP]; + set_Proj_proj(proj, pn_ia32_AddSP_stack); + } + else if (get_Proj_proj(proj) == pn_be_AddSP_M) { + set_Proj_proj(proj, pn_ia32_AddSP_M); + } + else { + assert(0); + } + } + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + return new_op; +} /** * This function just sets the register for the Unknown node @@ -2883,6 +2965,7 @@ void ia32_register_transformers(void) { GEN(be_FrameLoad); GEN(be_FrameStore); GEN(be_StackParam); + GEN(be_AddSP); /* set the register for all Unknown nodes */ GEN(Unknown); @@ -2931,12 +3014,12 @@ void ia32_transform_node(ir_node *node, void *env) { ia32_transform_env_t tenv; transform_func *transform = (transform_func *)op->ops.generic; - tenv.block = get_nodes_block(node); - tenv.dbg = get_irn_dbg_info(node); - tenv.irg = current_ir_graph; - tenv.irn = node; - tenv.mode = get_irn_mode(node); - tenv.cg = cg; + tenv.block = get_nodes_block(node); + tenv.dbg = get_irn_dbg_info(node); + tenv.irg = current_ir_graph; + tenv.irn = node; + tenv.mode = get_irn_mode(node); + tenv.cg = cg; DEBUG_ONLY(tenv.mod = cg->mod;) asm_node = (*transform)(&tenv); @@ -2987,11 +3070,16 @@ static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg /* Psi is float, we need a floating point compare */ if (USE_SSE2(cg)) { + ir_mode *m = get_irn_mode(cmp_a); /* SSE FPU */ - if (! mode_is_float(get_irn_mode(cmp_a))) { + if (! mode_is_float(m)) { cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode); cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode); - pnc |= 8; + } + else if (m == mode_F) { + /* we convert cmp values always to double, to get correct bitmask with cmpsd */ + cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a); + cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b); } new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);