X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=52ee5ea92aa03baa35037262efc7d31d2521c501;hb=cbfbedae75798a9830fb0ef090189345ede85dc8;hp=1e52279a48601f1e01b6f1b060ad93c9ea7998c2;hpb=e9aed9e92b065a67f4991396417d99366db435aa;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 1e52279a4..52ee5ea92 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -25,6 +25,8 @@ #include "irprintf.h" #include "debug.h" #include "irdom.h" +#include "type.h" +#include "entity.h" #include "archop.h" /* we need this for Min and Max nodes */ #include "../benode_t.h" @@ -148,6 +150,24 @@ static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_gr return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res); } +/** +* SSE convert of an float node into a double node. +*/ +static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block, + ir_node *in, ir_node *old_node) +{ + ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *nomem = new_rd_NoMem(irg); + + ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem); + set_ia32_src_mode(conv, mode_F); + set_ia32_tgt_mode(conv, mode_D); + set_ia32_am_support(conv, ia32_am_Source); + SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node)); + + return new_rd_Proj(dbg, irg, block, conv, mode_D, pn_ia32_Conv_FP2FP_res); +} + /* Generates an entity for a known FP const (used for FP Neg + Abs) */ static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) { static const struct { @@ -236,26 +256,31 @@ static ir_node *get_expr_op(ir_node *op1, ir_node *op2) { * @return The constructed ia32 node. */ static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) { - ir_node *new_op = NULL; - ir_mode *mode = env->mode; - dbg_info *dbg = env->dbg; - ir_graph *irg = env->irg; - ir_node *block = env->block; - ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg); - ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg); - ir_node *nomem = new_NoMem(); - ir_node *expr_op, *imm_op; + ir_node *new_op = NULL; + ir_mode *mode = env->mode; + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg); + ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg); + ir_node *nomem = new_NoMem(); + int is_mul = 0; + ir_node *expr_op, *imm_op; DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;) /* Check if immediate optimization is on and */ /* if it's an operation with immediate. */ - /* MulS and Mulh don't support immediates */ + /* Mul/MulS/Mulh don't support immediates */ if (! (env->cg->opt & IA32_OPT_IMMOPS) || + func == new_rd_ia32_Mul || func == new_rd_ia32_Mulh || func == new_rd_ia32_MulS) { expr_op = op1; imm_op = NULL; + /* immediate operations are requested, but we are here: it a mul */ + if (env->cg->opt & IA32_OPT_IMMOPS) + is_mul = 1; } else if (is_op_commutative(get_irn_op(env->irn))) { imm_op = get_immediate_op(op1, op2); @@ -307,6 +332,10 @@ static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, /* set AM support */ set_ia32_am_support(new_op, ia32_am_Full); } + + /* Muls can only have AM source */ + if (is_mul) + set_ia32_am_support(new_op, ia32_am_Source); } SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); @@ -1196,12 +1225,13 @@ ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) { size = get_mode_size_bits(env->mode); name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN); - set_ia32_sc(new_op, name); + set_ia32_am_sc(new_op, name); SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(new_op, env->mode); - set_ia32_immop_type(new_op, ia32_ImmSymConst); + set_ia32_op_type(new_op, ia32_AddrModeS); + set_ia32_ls_mode(new_op, env->mode); new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res); } @@ -1268,12 +1298,13 @@ static ir_node *gen_Abs(ia32_transform_env_t *env) { size = get_mode_size_bits(mode); name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS); - set_ia32_sc(res, name); + set_ia32_am_sc(res, name); SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); set_ia32_res_mode(res, mode); - set_ia32_immop_type(res, ia32_ImmSymConst); + set_ia32_op_type(res, ia32_AddrModeS); + set_ia32_ls_mode(res, env->mode); res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res); } @@ -1388,7 +1419,7 @@ static ir_node *gen_Store(ia32_transform_env_t *env) { ir_node *ptr = get_Store_ptr(node); ir_node *sptr = ptr; ir_node *mem = get_Store_mem(node); - ir_mode *mode = get_irn_link(node); + ir_mode *mode = get_irn_mode(val); ir_node *sval = val; int is_imm = 0; ir_node *new_op; @@ -1602,21 +1633,23 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) { * @return The transformed node. */ static ir_node *gen_CopyB(ia32_transform_env_t *env) { - ir_node *res = NULL; - dbg_info *dbg = env->dbg; - ir_graph *irg = env->irg; - ir_mode *mode = env->mode; - ir_node *block = env->block; - ir_node *node = env->irn; - ir_node *src = get_CopyB_src(node); - ir_node *dst = get_CopyB_dst(node); - ir_node *mem = get_CopyB_mem(node); - int size = get_type_size_bytes(get_CopyB_type(node)); - int rem; - - /* If we have to copy more than 16 bytes, we use REP MOVSx and */ + ir_node *res = NULL; + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *node = env->irn; + ir_node *src = get_CopyB_src(node); + ir_node *dst = get_CopyB_dst(node); + ir_node *mem = get_CopyB_mem(node); + int size = get_type_size_bytes(get_CopyB_type(node)); + ir_mode *dst_mode = get_irn_mode(dst); + ir_mode *src_mode = get_irn_mode(src); + int rem; + ir_node *in[3], *tmp; + + /* If we have to copy more than 32 bytes, we use REP MOVSx and */ /* then we need the size explicitly in ECX. */ - if (size >= 16 * 4) { + if (size >= 32 * 4) { rem = size & 0x3; /* size % 4 */ size >>= 2; @@ -1624,13 +1657,30 @@ static ir_node *gen_CopyB(ia32_transform_env_t *env) { set_ia32_op_type(res, ia32_Const); set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is)); - res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode); + res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem); set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is)); + + /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */ + in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST); + in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC); + in[2] = new_r_Proj(irg, block, res, mode_Is, pn_ia32_CopyB_CNT); + be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in); + + tmp = ia32_get_proj_for_mode(node, mode_M); + set_Proj_proj(tmp, pn_ia32_CopyB_M); } else { - res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode); + res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem); set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is)); set_ia32_immop_type(res, ia32_ImmConst); + + /* ok: now attach Proj's because movsd will destroy esi and edi */ + in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST); + in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC); + be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in); + + tmp = ia32_get_proj_for_mode(node, mode_M); + set_Proj_proj(tmp, pn_ia32_CopyB_i_M); } SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn)); @@ -1966,6 +2016,7 @@ static ir_node *gen_Conv(ia32_transform_env_t *env) { int src_bits = get_mode_size_bits(src_mode); int tgt_bits = get_mode_size_bits(tgt_mode); int pn = -1; + int kill = 0; ir_node *block = env->block; ir_node *new_op = NULL; ir_node *noreg = ia32_new_NoReg_gp(env->cg); @@ -1989,7 +2040,13 @@ static ir_node *gen_Conv(ia32_transform_env_t *env) { } else { DB((mod, LEVEL_1, "killed Conv(float, float) ...")); - edges_reroute(env->irn, op, irg); + /* + remark: we create a intermediate conv here, so modes will be spread correctly + these convs will be killed later + */ + new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem); + pn = pn_ia32_Conv_FP2FP_res; + kill = 1; } } else { @@ -2039,7 +2096,13 @@ static ir_node *gen_Conv(ia32_transform_env_t *env) { /* ... to int */ if (get_mode_size_bits(src_mode) == tgt_bits) { DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode)); - edges_reroute(env->irn, op, irg); + /* + remark: we create a intermediate conv here, so modes will be spread correctly + these convs will be killed later + */ + new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem); + pn = pn_ia32_Conv_I2I_res; + kill = 1; } else { DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode)); @@ -2063,6 +2126,9 @@ static ir_node *gen_Conv(ia32_transform_env_t *env) { set_ia32_am_support(new_op, ia32_am_Source); new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn); + + if (kill) + nodeset_insert(env->cg->kill_conv, new_op); } return new_op; @@ -2119,7 +2185,7 @@ static ir_node *gen_be_StackParam(ia32_transform_env_t *env) { ir_node *noreg = ia32_new_NoReg_gp(env->cg); ir_node *mem = new_rd_NoMem(env->irg); ir_node *ptr = get_irn_n(node, 0); - entity *ent = be_get_frame_entity(node); + entity *ent = arch_get_frame_entity(env->cg->arch_env, node); ir_mode *mode = env->mode; /* choose the block where to place the load */ @@ -2143,6 +2209,7 @@ static ir_node *gen_be_StackParam(ia32_transform_env_t *env) { set_ia32_op_type(new_op, ia32_AddrModeS); set_ia32_am_flavour(new_op, ia32_B); set_ia32_ls_mode(new_op, mode); + set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable); SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); @@ -2160,7 +2227,7 @@ static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) { ir_node *nomem = new_rd_NoMem(env->irg); new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem); - set_ia32_frame_ent(new_op, be_get_frame_entity(node)); + set_ia32_frame_ent(new_op, arch_get_frame_entity(env->cg->arch_env, node)); set_ia32_am_support(new_op, ia32_am_Full); set_ia32_use_frame(new_op); set_ia32_immop_type(new_op, ia32_ImmConst); @@ -2180,7 +2247,7 @@ static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) { ir_node *noreg = ia32_new_NoReg_gp(env->cg); ir_node *mem = get_irn_n(node, 0); ir_node *ptr = get_irn_n(node, 1); - entity *ent = be_get_frame_entity(node); + entity *ent = arch_get_frame_entity(env->cg->arch_env, node); ir_mode *mode = get_type_mode(get_entity_type(ent)); if (mode_is_float(mode)) { @@ -2217,7 +2284,7 @@ static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) { ir_node *mem = get_irn_n(node, 0); ir_node *ptr = get_irn_n(node, 1); ir_node *val = get_irn_n(node, 2); - entity *ent = be_get_frame_entity(node); + entity *ent = arch_get_frame_entity(env->cg->arch_env, node); ir_mode *mode = get_irn_mode(val); if (mode_is_float(mode)) { @@ -2247,6 +2314,158 @@ static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) { return new_op; } +/** + * In case SSE is used we need to copy the result from FPU TOS. + */ +static ir_node *gen_be_Call(ia32_transform_env_t *env) { + ir_node *call_res = get_proj_for_pn(env->irn, pn_be_Call_first_res); + ir_node *call_mem = get_proj_for_pn(env->irn, pn_be_Call_M_regular); + ir_mode *mode; + + if (! call_res || ! USE_SSE2(env->cg)) + return NULL; + + mode = get_irn_mode(call_res); + + /* in case there is no memory output: create one to serialize the copy FPU -> SSE */ + if (! call_mem) + call_mem = new_r_Proj(env->irg, env->block, env->irn, mode_M, pn_be_Call_M_regular); + + if (mode_is_float(mode)) { + /* store st(0) onto stack */ + ir_node *frame = get_irg_frame(env->irg); + ir_node *fstp = new_rd_ia32_GetST0(env->dbg, env->irg, env->block, frame, call_mem); + ir_node *mproj = new_r_Proj(env->irg, env->block, fstp, mode_M, pn_ia32_GetST0_M); + entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0); + ir_node *sse_load; + + set_ia32_ls_mode(fstp, mode); + set_ia32_op_type(fstp, ia32_AddrModeD); + set_ia32_use_frame(fstp); + set_ia32_frame_ent(fstp, ent); + set_ia32_am_flavour(fstp, ia32_B); + set_ia32_am_support(fstp, ia32_am_Dest); + + /* load into SSE register */ + sse_load = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, frame, ia32_new_NoReg_gp(env->cg), mproj); + set_ia32_ls_mode(sse_load, mode); + set_ia32_op_type(sse_load, ia32_AddrModeS); + set_ia32_use_frame(sse_load); + set_ia32_frame_ent(sse_load, ent); + set_ia32_am_flavour(sse_load, ia32_B); + set_ia32_am_support(sse_load, ia32_am_Source); + sse_load = new_r_Proj(env->irg, env->block, sse_load, mode, pn_ia32_xLoad_res); + + /* reroute all users of the result proj to the sse load */ + edges_reroute(call_res, sse_load, env->irg); + } + + return NULL; +} + +/** + * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return. + */ +static ir_node *gen_be_Return(ia32_transform_env_t *env) { + ir_node *ret_val = get_irn_n(env->irn, be_pos_Return_val); + ir_node *ret_mem = get_irn_n(env->irn, be_pos_Return_mem); + entity *ent = get_irg_entity(get_irn_irg(ret_val)); + ir_type *tp = get_entity_type(ent); + + if (be_Return_get_n_rets(env->irn) < 1 || ! ret_val || ! USE_SSE2(env->cg)) + return NULL; + + + if (get_method_n_ress(tp) == 1) { + ir_type *res_type = get_method_res_type(tp, 0); + ir_mode *mode; + + if(is_Primitive_type(res_type)) { + mode = get_type_mode(res_type); + if(mode_is_float(mode)) { + ir_node *frame = get_irg_frame(env->irg); + entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0); + ir_node *sse_store, *fld, *mproj; + + /* store xmm0 onto stack */ + sse_store = new_rd_ia32_xStoreSimple(env->dbg, env->irg, env->block, frame, ret_val, ret_mem); + set_ia32_ls_mode(sse_store, mode); + set_ia32_op_type(sse_store, ia32_AddrModeD); + set_ia32_use_frame(sse_store); + set_ia32_frame_ent(sse_store, ent); + set_ia32_am_flavour(sse_store, ia32_B); + set_ia32_am_support(sse_store, ia32_am_Dest); + sse_store = new_r_Proj(env->irg, env->block, sse_store, mode_M, pn_ia32_xStore_M); + + /* load into st0 */ + fld = new_rd_ia32_SetST0(env->dbg, env->irg, env->block, frame, sse_store); + set_ia32_ls_mode(fld, mode); + set_ia32_op_type(fld, ia32_AddrModeS); + set_ia32_use_frame(fld); + set_ia32_frame_ent(fld, ent); + set_ia32_am_flavour(fld, ia32_B); + set_ia32_am_support(fld, ia32_am_Source); + mproj = new_r_Proj(env->irg, env->block, fld, mode_M, pn_ia32_SetST0_M); + fld = new_r_Proj(env->irg, env->block, fld, mode, pn_ia32_SetST0_res); + + /* set new return value */ + set_irn_n(env->irn, be_pos_Return_val, fld); + set_irn_n(env->irn, be_pos_Return_mem, mproj); + } + } + } + + return NULL; +} + +/** + * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes. + */ +static ir_node *gen_be_AddSP(ia32_transform_env_t *env) { + ir_node *new_op; + const ir_edge_t *edge; + ir_node *sz = get_irn_n(env->irn, be_pos_AddSP_size); + ir_node *sp = get_irn_n(env->irn, be_pos_AddSP_old_sp); + + new_op = new_rd_ia32_AddSP(env->dbg, env->irg, env->block, sp, sz); + + if (is_ia32_Const(sz)) { + set_ia32_Immop_attr(new_op, sz); + set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg)); + } + else if (is_ia32_Load(sz) && get_ia32_am_flavour(sz) == ia32_O) { + set_ia32_immop_type(new_op, ia32_ImmSymConst); + set_ia32_op_type(new_op, ia32_AddrModeS); + set_ia32_am_sc(new_op, get_ia32_am_sc(sz)); + add_ia32_am_offs(new_op, get_ia32_am_offs(sz)); + set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg)); + } + + /* fix proj nums */ + foreach_out_edge(env->irn, edge) { + ir_node *proj = get_edge_src_irn(edge); + + assert(is_Proj(proj)); + + if (get_Proj_proj(proj) == pn_be_AddSP_res) { + /* the node is not yet exchanged: we need to set the register manually */ + ia32_attr_t *attr = get_ia32_attr(new_op); + attr->slots[pn_ia32_AddSP_stack] = &ia32_gp_regs[REG_ESP]; + set_Proj_proj(proj, pn_ia32_AddSP_stack); + } + else if (get_Proj_proj(proj) == pn_be_AddSP_M) { + set_Proj_proj(proj, pn_ia32_AddSP_M); + } + else { + assert(0); + } + } + + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn)); + + return new_op; +} + /** * This function just sets the register for the Unknown node * as this is not done during register allocation because Unknown @@ -2724,6 +2943,7 @@ void ia32_register_transformers(void) { IGN(SymConst); IGN(Sync); + /* we should never see these nodes */ BAD(Raise); BAD(Sel); BAD(InstOf); @@ -2738,10 +2958,14 @@ void ia32_register_transformers(void) { BAD(EndReg); BAD(EndExcept); + /* handle generic backend nodes */ GEN(be_FrameAddr); + GEN(be_Call); + GEN(be_Return); GEN(be_FrameLoad); GEN(be_FrameStore); GEN(be_StackParam); + GEN(be_AddSP); /* set the register for all Unknown nodes */ GEN(Unknown); @@ -2790,12 +3014,12 @@ void ia32_transform_node(ir_node *node, void *env) { ia32_transform_env_t tenv; transform_func *transform = (transform_func *)op->ops.generic; - tenv.block = get_nodes_block(node); - tenv.dbg = get_irn_dbg_info(node); - tenv.irg = current_ir_graph; - tenv.irn = node; - tenv.mode = get_irn_mode(node); - tenv.cg = cg; + tenv.block = get_nodes_block(node); + tenv.dbg = get_irn_dbg_info(node); + tenv.irg = current_ir_graph; + tenv.irn = node; + tenv.mode = get_irn_mode(node); + tenv.cg = cg; DEBUG_ONLY(tenv.mod = cg->mod;) asm_node = (*transform)(&tenv); @@ -2846,11 +3070,16 @@ static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg /* Psi is float, we need a floating point compare */ if (USE_SSE2(cg)) { + ir_mode *m = get_irn_mode(cmp_a); /* SSE FPU */ - if (! mode_is_float(get_irn_mode(cmp_a))) { + if (! mode_is_float(m)) { cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode); cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode); - pnc |= 8; + } + else if (m == mode_F) { + /* we convert cmp values always to double, to get correct bitmask with cmpsd */ + cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a); + cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b); } new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);