X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=4df706bccf753fd5d97f35a56241a7b415d2c964;hb=14b4e9b3f48cd53db6c3179283ce8354d5127ce1;hp=bedcf493bf31355815da206ea6d108e10017e9a1;hpb=41eca21e7add2e4f30f14c46600a23839852b3fc;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index bedcf493b..4df706bcc 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -48,11 +48,11 @@ #include "array_t.h" #include "height.h" -#include "../benode_t.h" +#include "../benode.h" #include "../besched.h" #include "../beabi.h" #include "../beutil.h" -#include "../beirg_t.h" +#include "../beirg.h" #include "../betranshlp.h" #include "../be_t.h" @@ -93,6 +93,7 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) static ir_node *initial_fpcw = NULL; +int no_pic_adjust; typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, @@ -194,6 +195,19 @@ static bool is_simple_sse_Const(ir_node *node) return false; } +/** + * return NoREG or pic_base in case of PIC. + * This is necessary as base address for newly created symbols + */ +static ir_node *get_symconst_base(void) +{ + if (env_cg->birg->main_env->options->pic) { + return arch_code_generator_get_pic_base(env_cg); + } + + return noreg_GP; +} + /** * Transforms a Const. */ @@ -209,6 +223,7 @@ static ir_node *gen_Const(ir_node *node) if (mode_is_float(mode)) { ir_node *res = NULL; ir_node *load; + ir_node *base; ir_entity *floatent; if (ia32_cg_config.use_sse2) { @@ -238,7 +253,7 @@ static ir_node *gen_Const(ir_node *node) (get_tarval_sub_bits(tv, 1) << 8) | (get_tarval_sub_bits(tv, 2) << 16) | (get_tarval_sub_bits(tv, 3) << 24); - ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val); + ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val); load = new_bd_ia32_xMovd(dbgi, block, cnst); set_ia32_ls_mode(load, mode); res = load; @@ -258,7 +273,7 @@ static ir_node *gen_Const(ir_node *node) (get_tarval_sub_bits(tv, 5) << 8) | (get_tarval_sub_bits(tv, 6) << 16) | (get_tarval_sub_bits(tv, 7) << 24); - cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val); + cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val); load = new_bd_ia32_xMovd(dbgi, block, cnst); set_ia32_ls_mode(load, mode); psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32); @@ -270,11 +285,13 @@ static ir_node *gen_Const(ir_node *node) #endif /* CONSTRUCT_SSE_CONST */ floatent = create_float_const_entity(node); - load = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode); + base = get_symconst_base(); + load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem, + mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); arch_irn_add_flags(load, arch_irn_flags_rematerializable); - res = new_r_Proj(current_ir_graph, block, load, mode_xmm, pn_ia32_xLoad_res); + res = new_r_Proj(block, load, mode_xmm, pn_ia32_xLoad_res); } } else { if (is_Const_null(node)) { @@ -287,18 +304,19 @@ static ir_node *gen_Const(ir_node *node) set_ia32_ls_mode(load, mode); } else { ir_mode *ls_mode; + ir_node *base; floatent = create_float_const_entity(node); /* create_float_const_ent is smart and sometimes creates smaller entities */ ls_mode = get_type_mode(get_entity_type(floatent)); - - load = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, + base = get_symconst_base(); + load = new_bd_ia32_vfld(dbgi, block, base, noreg_GP, nomem, ls_mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); arch_irn_add_flags(load, arch_irn_flags_rematerializable); - res = new_r_Proj(current_ir_graph, block, load, mode_vfp, pn_ia32_vfld_res); + res = new_r_Proj(block, load, mode_vfp, pn_ia32_vfld_res); } } #ifdef CONSTRUCT_SSE_CONST @@ -321,7 +339,7 @@ end: } val = get_tarval_long(tv); - cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val); + cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val); SET_IA32_ORIG_NODE(cnst, node); be_dep_on_frame(cnst); @@ -354,7 +372,7 @@ static ir_node *gen_SymConst(ir_node *node) panic("backend only support symconst_addr_ent (at %+F)", node); } entity = get_SymConst_entity(node); - cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0); + cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0); } SET_IA32_ORIG_NODE(cnst, node); @@ -369,8 +387,8 @@ static ir_node *gen_SymConst(ir_node *node) * @param mode the mode for the float type (might be integer mode for SSE2 types) * @param align alignment */ -static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { - char buf[32]; +static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) +{ ir_type *tp; assert(align <= 16); @@ -379,8 +397,7 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { static ir_type *int_Iu[16] = {NULL, }; if (int_Iu[align] == NULL) { - snprintf(buf, sizeof(buf), "int_Iu_%u", align); - int_Iu[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + int_Iu[align] = tp = new_type_primitive(mode); /* set the specified alignment */ set_type_alignment_bytes(tp, align); } @@ -389,8 +406,7 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { static ir_type *int_Lu[16] = {NULL, }; if (int_Lu[align] == NULL) { - snprintf(buf, sizeof(buf), "int_Lu_%u", align); - int_Lu[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + int_Lu[align] = tp = new_type_primitive(mode); /* set the specified alignment */ set_type_alignment_bytes(tp, align); } @@ -399,8 +415,7 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { static ir_type *float_F[16] = {NULL, }; if (float_F[align] == NULL) { - snprintf(buf, sizeof(buf), "float_F_%u", align); - float_F[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + float_F[align] = tp = new_type_primitive(mode); /* set the specified alignment */ set_type_alignment_bytes(tp, align); } @@ -409,8 +424,7 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { static ir_type *float_D[16] = {NULL, }; if (float_D[align] == NULL) { - snprintf(buf, sizeof(buf), "float_D_%u", align); - float_D[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + float_D[align] = tp = new_type_primitive(mode); /* set the specified alignment */ set_type_alignment_bytes(tp, align); } @@ -419,8 +433,7 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { static ir_type *float_E[16] = {NULL, }; if (float_E[align] == NULL) { - snprintf(buf, sizeof(buf), "float_E_%u", align); - float_E[align] = tp = new_type_primitive(new_id_from_str(buf), mode); + float_E[align] = tp = new_type_primitive(mode); /* set the specified alignment */ set_type_alignment_bytes(tp, align); } @@ -433,8 +446,8 @@ static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) { * * @param tp the atomic type */ -static ir_type *ia32_create_float_array(ir_type *tp) { - char buf[32]; +static ir_type *ia32_create_float_array(ir_type *tp) +{ ir_mode *mode = get_type_mode(tp); unsigned align = get_type_alignment_bytes(tp); ir_type *arr; @@ -446,22 +459,19 @@ static ir_type *ia32_create_float_array(ir_type *tp) { if (float_F[align] != NULL) return float_F[align]; - snprintf(buf, sizeof(buf), "arr_float_F_%u", align); - arr = float_F[align] = new_type_array(new_id_from_str(buf), 1, tp); + arr = float_F[align] = new_type_array(1, tp); } else if (mode == mode_D) { static ir_type *float_D[16] = {NULL, }; if (float_D[align] != NULL) return float_D[align]; - snprintf(buf, sizeof(buf), "arr_float_D_%u", align); - arr = float_D[align] = new_type_array(new_id_from_str(buf), 1, tp); + arr = float_D[align] = new_type_array(1, tp); } else { static ir_type *float_E[16] = {NULL, }; if (float_E[align] != NULL) return float_E[align]; - snprintf(buf, sizeof(buf), "arr_float_E_%u", align); - arr = float_E[align] = new_type_array(new_id_from_str(buf), 1, tp); + arr = float_E[align] = new_type_array(1, tp); } set_type_alignment_bytes(arr, align); set_type_size_bytes(arr, 2 * get_type_size_bytes(tp)); @@ -509,9 +519,8 @@ ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp); set_entity_ld_ident(ent, get_entity_ident(ent)); - set_entity_visibility(ent, visibility_local); - set_entity_variability(ent, variability_constant); - set_entity_allocation(ent, allocation_static); + add_entity_linkage(ent, IR_LINKAGE_CONSTANT); + set_entity_visibility(ent, ir_visibility_local); if (kct == ia32_ULLBIAS) { ir_initializer_t *initializer = create_initializer_compound(2); @@ -623,9 +632,10 @@ static void build_address(ia32_address_mode_t *am, ir_node *node, ir_node *mem; ir_node *new_mem; + /* floating point immediates */ if (is_Const(node)) { ir_entity *entity = create_float_const_entity(node); - addr->base = noreg_GP; + addr->base = get_symconst_base(); addr->index = noreg_GP; addr->mem = nomem; addr->symconst_ent = entity; @@ -828,6 +838,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } am->op_type = ia32_AddrModeS; } else { + ir_mode *mode; am->op_type = ia32_Normal; if (flags & match_try_am) { @@ -836,11 +847,18 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, return; } - new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); - if (new_op2 == NULL) - new_op2 = be_transform_node(op2); - am->ls_mode = - (flags & match_mode_neutral ? mode_Iu : get_irn_mode(op2)); + mode = get_irn_mode(op2); + if (flags & match_upconv_32 && get_mode_size_bits(mode) != 32) { + new_op1 = (op1 == NULL ? NULL : create_upconv(op1, NULL)); + if (new_op2 == NULL) + new_op2 = create_upconv(op2, NULL); + am->ls_mode = mode_Iu; + } else { + new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); + if (new_op2 == NULL) + new_op2 = be_transform_node(op2); + am->ls_mode = (flags & match_mode_neutral) ? mode_Iu : mode; + } } if (addr->base == NULL) addr->base = noreg_GP; @@ -880,7 +898,7 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) if (mode != mode_T) { set_irn_mode(node, mode_T); - return new_rd_Proj(NULL, current_ir_graph, get_nodes_block(node), node, mode, pn_ia32_res); + return new_rd_Proj(NULL, get_nodes_block(node), node, mode, pn_ia32_res); } else { return node; } @@ -1000,7 +1018,7 @@ static ir_node *get_fpcw(void) static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, construct_binop_float_func *func) { - ir_mode *mode = get_irn_mode(node); + ir_mode *mode = get_irn_mode(node); dbg_info *dbgi; ir_node *block, *new_block, *new_node; ia32_address_mode_t am; @@ -1010,6 +1028,10 @@ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, * variants */ match_flags_t flags = match_commutative; + /* happens for div nodes... */ + if (mode == mode_T) + mode = get_divop_resmod(node); + /* cannot use address mode with long double on x87 */ if (get_mode_size_bits(mode) <= 64) flags |= match_am; @@ -1199,7 +1221,7 @@ static ir_node *gen_Add(ir_node *node) /* a constant? */ if (addr.base == NULL && addr.index == NULL) { new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent, - addr.symconst_sign, addr.offset); + addr.symconst_sign, 0, addr.offset); be_dep_on_frame(new_node); SET_IA32_ORIG_NODE(new_node, node); return new_node; @@ -1290,14 +1312,16 @@ static ir_node *gen_Mulh(ir_node *node) ir_node *new_node; ir_node *proj_res_high; + if (get_mode_size_bits(mode) != 32) { + panic("Mulh without 32bit size not supported in ia32 backend (%+F)", node); + } + if (mode_is_signed(mode)) { new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am); - proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node, - mode_Iu, pn_ia32_IMul1OP_res_high); + proj_res_high = new_rd_Proj(dbgi, new_block, new_node, mode_Iu, pn_ia32_IMul1OP_res_high); } else { new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am); - proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node, - mode_Iu, pn_ia32_Mul_res_high); + proj_res_high = new_rd_Proj(dbgi, new_block, new_node, mode_Iu, pn_ia32_Mul_res_high); } return proj_res_high; } @@ -1401,7 +1425,7 @@ static ir_node *gen_Sub(ir_node *node) | match_am | match_immediate); } -static ir_node *transform_AM_mem(ir_graph *const irg, ir_node *const block, +static ir_node *transform_AM_mem(ir_node *const block, ir_node *const src_val, ir_node *const src_mem, ir_node *const am_mem) @@ -1437,13 +1461,13 @@ static ir_node *transform_AM_mem(ir_graph *const irg, ir_node *const block, ins[n++] = am_mem; - return new_r_Sync(irg, block, n, ins); + return new_r_Sync(block, n, ins); } else { ir_node *ins[2]; ins[0] = be_transform_node(src_mem); ins[1] = am_mem; - return new_r_Sync(irg, block, 2, ins); + return new_r_Sync(block, 2, ins); } } @@ -1516,19 +1540,19 @@ static ir_node *create_Div(ir_node *node) panic("invalid divmod node %+F", node); } - match_arguments(&am, block, op1, op2, NULL, match_am); + match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv_32); /* Beware: We don't need a Sync, if the memory predecessor of the Div node is the memory of the consumed address. We can have only the second op as address in Div nodes, so check only op2. */ - new_mem = transform_AM_mem(current_ir_graph, block, op2, mem, addr->mem); + new_mem = transform_AM_mem(block, op2, mem, addr->mem); if (mode_is_signed(mode)) { sign_extension = create_sex_32_64(dbgi, new_block, am.new_op1, node); new_node = new_bd_ia32_IDiv(dbgi, new_block, addr->base, addr->index, new_mem, am.new_op2, am.new_op1, sign_extension); } else { - sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0); + sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0, 0); be_dep_on_frame(sign_extension); new_node = new_bd_ia32_Div(dbgi, new_block, addr->base, @@ -1774,8 +1798,8 @@ static ir_node *gen_Minus(ir_node *node) * several AM nodes... */ ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg); - new_node = new_bd_ia32_xXor(dbgi, block, noreg_GP, noreg_GP, - nomem, new_op, noreg_xmm); + new_node = new_bd_ia32_xXor(dbgi, block, get_symconst_base(), + noreg_GP, nomem, new_op, noreg_xmm); size = get_mode_size_bits(mode); ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN); @@ -1802,7 +1826,7 @@ static ir_node *gen_Minus(ir_node *node) */ static ir_node *gen_Not(ir_node *node) { - ir_node *op = get_Not_op(node); + ir_node *op = get_Not_op(node); assert(get_irn_mode(node) != mode_b); /* should be lowered already */ assert (! mode_is_float(get_irn_mode(node))); @@ -1834,8 +1858,8 @@ static ir_node *gen_Abs(ir_node *node) if (ia32_cg_config.use_sse2) { ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg); - new_node = new_bd_ia32_xAnd(dbgi, new_block, noreg_GP, noreg_GP, - nomem, new_op, noreg_fp); + new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(), + noreg_GP, nomem, new_op, noreg_fp); size = get_mode_size_bits(mode); ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS); @@ -1941,8 +1965,17 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) } } } - flags = be_transform_node(pred); + /* add ia32 compare flags */ + { + ir_node *l = get_Cmp_left(pred); + ir_mode *mode = get_irn_mode(l); + if (mode_is_float(mode)) + pnc |= ia32_pn_Cmp_float; + else if (! mode_is_signed(mode)) + pnc |= ia32_pn_Cmp_unsigned; + } *pnc_out = pnc; + flags = be_transform_node(pred); return flags; } } @@ -2113,7 +2146,7 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, dbgi = get_irn_dbg_info(node); block = be_transform_node(src_block); - new_mem = transform_AM_mem(current_ir_graph, block, am.am_node, mem, addr->mem); + new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem); if (get_mode_size_bits(mode) == 8) { new_node = func8bit(dbgi, block, addr->base, addr->index, new_mem, new_op); @@ -2153,7 +2186,7 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, dbgi = get_irn_dbg_info(node); block = be_transform_node(src_block); - new_mem = transform_AM_mem(current_ir_graph, block, am.am_node, mem, addr->mem); + new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem); new_node = func(dbgi, block, addr->base, addr->index, new_mem); set_address(new_node, addr); set_ia32_op_type(new_node, ia32_AddrModeD); @@ -2167,43 +2200,55 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, return new_node; } +static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc) +{ + ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu; + return get_negated_pnc(pnc, mode); +} + static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) { - ir_mode *mode = get_irn_mode(node); - ir_node *mux_true = get_Mux_true(node); - ir_node *mux_false = get_Mux_false(node); - ir_node *cond; - ir_node *new_mem; - dbg_info *dbgi; - ir_node *block; - ir_node *new_block; - ir_node *flags; - ir_node *new_node; - int negated; - pn_Cmp pnc; - ia32_address_t addr; + ir_mode *mode = get_irn_mode(node); + ir_node *mux_true = get_Mux_true(node); + ir_node *mux_false = get_Mux_false(node); + ir_node *cond; + ir_node *new_mem; + dbg_info *dbgi; + ir_node *block; + ir_node *new_block; + ir_node *flags; + ir_node *new_node; + bool negated; + pn_Cmp pnc; + ia32_address_t addr; if (get_mode_size_bits(mode) != 8) return NULL; if (is_Const_1(mux_true) && is_Const_0(mux_false)) { - negated = 0; + negated = false; } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) { - negated = 1; + negated = true; } else { return NULL; } + cond = get_Mux_sel(node); + flags = get_flags_node(cond, &pnc); + /* we can't handle the float special cases with SetM */ + if (pnc & ia32_pn_Cmp_float) + return NULL; + if (negated) + pnc = ia32_get_negated_pnc(pnc); + build_address_ptr(&addr, ptr, mem); dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); new_block = be_transform_node(block); - cond = get_Mux_sel(node); - flags = get_flags_node(cond, &pnc); new_mem = be_transform_node(mem); - new_node = new_bd_ia32_SetMem(dbgi, new_block, addr.base, - addr.index, addr.mem, flags, pnc, negated); + new_node = new_bd_ia32_SetccMem(dbgi, new_block, addr.base, + addr.index, addr.mem, flags, pnc); set_address(new_node, &addr); set_ia32_op_type(new_node, ia32_AddrModeD); set_ia32_ls_mode(new_node, mode); @@ -2329,6 +2374,7 @@ static ir_node *try_create_dest_am(ir_node *node) case iro_Mux: new_node = try_create_SetMem(val, ptr, mem); break; + case iro_Minus: op1 = get_Minus_op(val); new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NegMem); @@ -2437,7 +2483,7 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) } while (size != 0); if (i > 1) { - return new_rd_Sync(dbgi, current_ir_graph, new_block, i, ins); + return new_rd_Sync(dbgi, new_block, i, ins); } else { return ins[0]; } @@ -2446,7 +2492,7 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) /** * Generate a vfist or vfisttp instruction. */ -static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, +static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node **fist) { ir_node *new_node; @@ -2454,12 +2500,11 @@ static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node if (ia32_cg_config.use_fisttp) { /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied if other users exists */ - const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp]; ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val); - ir_node *value = new_r_Proj(irg, block, vfisttp, mode_E, pn_ia32_vfisttp_res); - be_new_Keep(reg_class, irg, block, 1, &value); + ir_node *value = new_r_Proj(block, vfisttp, mode_E, pn_ia32_vfisttp_res); + be_new_Keep(block, 1, &value); - new_node = new_r_Proj(irg, block, vfisttp, mode_M, pn_ia32_vfisttp_M); + new_node = new_r_Proj(block, vfisttp, mode_M, pn_ia32_vfisttp_M); *fist = vfisttp; } else { ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); @@ -2541,7 +2586,7 @@ static ir_node *gen_general_Store(ir_node *node) val = op; } new_val = be_transform_node(val); - new_node = gen_vfist(dbgi, current_ir_graph, new_block, addr.base, addr.index, addr.mem, new_val, &store); + new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, &store); } else { new_val = create_immediate_or_transform(val, 0); assert(mode != mode_b); @@ -2619,8 +2664,8 @@ static ir_node *create_Switch(ir_node *node) switch_max = pn; } - if ((unsigned long) (switch_max - switch_min) > 256000) { - panic("Size of switch %+F bigger than 256000", node); + if ((unsigned long) (switch_max - switch_min) > 128000) { + panic("Size of switch %+F bigger than 128000", node); } if (switch_min != 0) { @@ -2954,9 +2999,12 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, match_arguments(&am, block, val_false, val_true, flags, match_commutative | match_am | match_16bit_am | match_mode_neutral); - new_node = new_bd_ia32_CMov(dbgi, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, new_flags, - am.ins_permuted, pnc); + if (am.ins_permuted) + pnc = ia32_get_negated_pnc(pnc); + + new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index, + addr->mem, am.new_op1, am.new_op2, new_flags, + pnc); set_am_attributes(new_node, &am); SET_IA32_ORIG_NODE(new_node, node); @@ -2970,13 +3018,13 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, * Creates a ia32 Setcc instruction. */ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, - ir_node *flags, pn_Cmp pnc, ir_node *orig_node, - int ins_permuted) + ir_node *flags, pn_Cmp pnc, + ir_node *orig_node) { ir_mode *mode = get_irn_mode(orig_node); ir_node *new_node; - new_node = new_bd_ia32_Set(dbgi, new_block, flags, pnc, ins_permuted); + new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, pnc); SET_IA32_ORIG_NODE(new_node, orig_node); /* we might need to conv the result up */ @@ -2992,11 +3040,15 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, /** * Create instruction for an unsigned Difference or Zero. */ -static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) +static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b) { - ir_graph *irg = current_ir_graph; - ir_mode *mode = get_irn_mode(psi); - ir_node *new_node, *sub, *sbb, *eflags, *block; + ir_mode *mode = get_irn_mode(psi); + ir_node *new_node; + ir_node *sub; + ir_node *sbb; + ir_node *not; + ir_node *eflags; + ir_node *block; dbg_info *dbgi; @@ -3011,14 +3063,15 @@ static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) } else { sub = new_node; set_irn_mode(sub, mode_T); - new_node = new_rd_Proj(NULL, irg, block, sub, mode, pn_ia32_res); + new_node = new_rd_Proj(NULL, block, sub, mode, pn_ia32_res); } - eflags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags); + eflags = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_Sub_flags); dbgi = get_irn_dbg_info(psi); sbb = new_bd_ia32_Sbb0(dbgi, block, eflags); + not = new_bd_ia32_Not(dbgi, block, sbb); - new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, sbb); + new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, not); set_ia32_commutative(new_node); return new_node; } @@ -3031,7 +3084,8 @@ static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) * @param new_mode IN/OUT for the mode of the constants, if NULL * smallest possible mode will be used */ -static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **new_mode) { +static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **new_mode) +{ ir_entity *ent; ir_mode *mode = *new_mode; ir_type *tp; @@ -3067,9 +3121,8 @@ static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **ne ent = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp); set_entity_ld_ident(ent, get_entity_ident(ent)); - set_entity_visibility(ent, visibility_local); - set_entity_variability(ent, variability_constant); - set_entity_allocation(ent, allocation_static); + set_entity_visibility(ent, ir_visibility_local); + add_entity_linkage(ent, IR_LINKAGE_CONSTANT); initializer = create_initializer_compound(2); @@ -3082,6 +3135,156 @@ static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **ne return ent; } +/** + * Possible transformations for creating a Setcc. + */ +enum setcc_transform_insn { + SETCC_TR_ADD, + SETCC_TR_ADDxx, + SETCC_TR_LEA, + SETCC_TR_LEAxx, + SETCC_TR_SHL, + SETCC_TR_NEG, + SETCC_TR_NOT, + SETCC_TR_AND, + SETCC_TR_SET, + SETCC_TR_SBB, +}; + +typedef struct setcc_transform { + unsigned num_steps; + unsigned permutate_cmp_ins; + pn_Cmp pnc; + struct { + enum setcc_transform_insn transform; + long val; + int scale; + } steps[4]; +} setcc_transform_t; + +/** + * Setcc can only handle 0 and 1 result. + * Find a transformation that creates 0 and 1 from + * tv_t and tv_f. + */ +static void find_const_transform(pn_Cmp pnc, tarval *t, tarval *f, + setcc_transform_t *res) +{ + unsigned step = 0; + + res->num_steps = 0; + res->permutate_cmp_ins = 0; + + if (tarval_is_null(t)) { + tarval *tmp = t; + t = f; + f = tmp; + pnc = ia32_get_negated_pnc(pnc); + } else if (tarval_cmp(t, f) == pn_Cmp_Lt) { + // now, t is the bigger one + tarval *tmp = t; + t = f; + f = tmp; + pnc = ia32_get_negated_pnc(pnc); + } + res->pnc = pnc; + + if (! tarval_is_null(f)) { + tarval *t_sub = tarval_sub(t, f, NULL); + + t = t_sub; + res->steps[step].transform = SETCC_TR_ADD; + + if (t == tarval_bad) + panic("constant subtract failed"); + if (! tarval_is_long(f)) + panic("tarval is not long"); + + res->steps[step].val = get_tarval_long(f); + ++step; + f = tarval_sub(f, f, NULL); + assert(tarval_is_null(f)); + } + + if (tarval_is_one(t)) { + res->steps[step].transform = SETCC_TR_SET; + res->num_steps = ++step; + return; + } + + if (tarval_is_minus_one(t)) { + res->steps[step].transform = SETCC_TR_NEG; + ++step; + res->steps[step].transform = SETCC_TR_SET; + res->num_steps = ++step; + return; + } + if (tarval_is_long(t)) { + long v = get_tarval_long(t); + + res->steps[step].val = 0; + switch (v) { + case 9: + if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD) + --step; + res->steps[step].transform = SETCC_TR_LEAxx; + res->steps[step].scale = 3; /* (a << 3) + a */ + break; + case 8: + if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD) + --step; + res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA; + res->steps[step].scale = 3; /* (a << 3) */ + break; + case 5: + if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD) + --step; + res->steps[step].transform = SETCC_TR_LEAxx; + res->steps[step].scale = 2; /* (a << 2) + a */ + break; + case 4: + if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD) + --step; + res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA; + res->steps[step].scale = 2; /* (a << 2) */ + break; + case 3: + if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD) + --step; + res->steps[step].transform = SETCC_TR_LEAxx; + res->steps[step].scale = 1; /* (a << 1) + a */ + break; + case 2: + if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD) + --step; + res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA; + res->steps[step].scale = 1; /* (a << 1) */ + break; + case 1: + res->num_steps = step; + return; + default: + if (! tarval_is_single_bit(t)) { + res->steps[step].transform = SETCC_TR_AND; + res->steps[step].val = v; + ++step; + res->steps[step].transform = SETCC_TR_NEG; + } else { + int v = get_tarval_lowest_bit(t); + assert(v >= 0); + + res->steps[step].transform = SETCC_TR_SHL; + res->steps[step].scale = v; + } + } + ++step; + res->steps[step].transform = SETCC_TR_SET; + res->num_steps = ++step; + return; + } + panic("tarval is not long"); +} + /** * Transforms a Mux node into some code sequence. * @@ -3132,6 +3335,7 @@ static ir_node *gen_Mux(ir_node *node) } } } + if (is_Const(mux_true) && is_Const(mux_false)) { ia32_address_mode_t am; ir_node *load; @@ -3139,7 +3343,7 @@ static ir_node *gen_Mux(ir_node *node) unsigned scale; flags = get_flags_node(cond, &pnc); - new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0); + new_node = create_set_32bit(dbgi, new_block, flags, pnc, node); if (ia32_cg_config.use_sse2) { /* cannot load from different mode on SSE */ @@ -3180,7 +3384,7 @@ static ir_node *gen_Mux(ir_node *node) } am.ls_mode = new_mode; - am.addr.base = noreg_GP; + am.addr.base = get_symconst_base(); am.addr.index = new_node; am.addr.mem = nomem; am.addr.offset = 0; @@ -3202,7 +3406,7 @@ static ir_node *gen_Mux(ir_node *node) load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode); set_am_attributes(load, &am); - return new_rd_Proj(NULL, current_ir_graph, block, load, mode_vfp, pn_ia32_res); + return new_rd_Proj(NULL, block, load, mode_vfp, pn_ia32_res); } panic("cannot transform floating point Mux"); @@ -3221,12 +3425,12 @@ static ir_node *gen_Mux(ir_node *node) is_Const_0(mux_false) && is_Sub(mux_true) && get_Sub_left(mux_true) == cmp_left && get_Sub_right(mux_true) == cmp_right) { /* Mux(a >=u b, a - b, 0) unsigned Doz */ - return create_Doz(node, cmp_left, cmp_right); + return create_doz(node, cmp_left, cmp_right); } else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) && is_Const_0(mux_true) && is_Sub(mux_false) && get_Sub_left(mux_false) == cmp_left && get_Sub_right(mux_false) == cmp_right) { /* Mux(a <=u b, 0, a - b) unsigned Doz */ - return create_Doz(node, cmp_left, cmp_right); + return create_doz(node, cmp_left, cmp_right); } } } @@ -3235,16 +3439,70 @@ static ir_node *gen_Mux(ir_node *node) if (is_Const(mux_true) && is_Const(mux_false)) { /* both are const, good */ - if (is_Const_1(mux_true) && is_Const_0(mux_false)) { - new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0); - } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) { - new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/1); - } else { - /* Not that simple. */ - goto need_cmov; + tarval *tv_true = get_Const_tarval(mux_true); + tarval *tv_false = get_Const_tarval(mux_false); + setcc_transform_t res; + int step; + + /* check if flags is a cmp node and we are the only user, + i.e no other user yet */ + int permutate_allowed = 0; + if (is_ia32_Cmp(flags) && get_irn_n_edges(flags) == 0) { + /* yes, we can permutate its inputs */ + permutate_allowed = 1; + } + find_const_transform(pnc, tv_true, tv_false, &res); + new_node = node; + if (res.permutate_cmp_ins) { + ia32_attr_t *attr = get_ia32_attr(flags); + attr->data.ins_permuted ^= 1; + } + for (step = (int)res.num_steps - 1; step >= 0; --step) { + ir_node *imm; + + switch (res.steps[step].transform) { + case SETCC_TR_ADD: + imm = ia32_immediate_from_long(res.steps[step].val); + new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm); + break; + case SETCC_TR_ADDxx: + new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); + break; + case SETCC_TR_LEA: + new_node = new_bd_ia32_Lea(dbgi, new_block, noreg_GP, new_node); + set_ia32_am_scale(new_node, res.steps[step].scale); + set_ia32_am_offs_int(new_node, res.steps[step].val); + break; + case SETCC_TR_LEAxx: + new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); + set_ia32_am_scale(new_node, res.steps[step].scale); + set_ia32_am_offs_int(new_node, res.steps[step].val); + break; + case SETCC_TR_SHL: + imm = ia32_immediate_from_long(res.steps[step].scale); + new_node = new_bd_ia32_Shl(dbgi, new_block, new_node, imm); + break; + case SETCC_TR_NEG: + new_node = new_bd_ia32_Neg(dbgi, new_block, new_node); + break; + case SETCC_TR_NOT: + new_node = new_bd_ia32_Not(dbgi, new_block, new_node); + break; + case SETCC_TR_AND: + imm = ia32_immediate_from_long(res.steps[step].val); + new_node = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm); + break; + case SETCC_TR_SET: + new_node = create_set_32bit(dbgi, new_block, flags, res.pnc, new_node); + break; + case SETCC_TR_SBB: + new_node = new_bd_ia32_Sbb0(dbgi, new_block, flags); + break; + default: + panic("unknown setcc transform"); + } } } else { -need_cmov: new_node = create_CMov(node, cond, flags, pnc); } return new_node; @@ -3265,7 +3523,7 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) ir_mode *mode = get_irn_mode(node); ir_node *fist, *load, *mem; - mem = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist); + mem = gen_vfist(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist); set_irn_pinned(fist, op_pin_state_floats); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); @@ -3296,7 +3554,7 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) } SET_IA32_ORIG_NODE(load, node); - return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res); + return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res); } /** @@ -3305,7 +3563,7 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) { ir_node *block = get_nodes_block(node); - ir_graph *irg = current_ir_graph; + ir_graph *irg = get_Block_irg(block); dbg_info *dbgi = get_irn_dbg_info(node); ir_node *frame = get_irg_frame(irg); ir_node *store, *load; @@ -3321,7 +3579,7 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) set_ia32_op_type(load, ia32_AddrModeS); SET_IA32_ORIG_NODE(load, node); - new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res); + new_node = new_r_Proj(block, load, mode_E, pn_ia32_vfld_res); return new_node; } @@ -3342,7 +3600,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { ir_node *src_block = get_nodes_block(node); ir_node *block = be_transform_node(src_block); - ir_graph *irg = current_ir_graph; + ir_graph *irg = get_Block_irg(block); dbg_info *dbgi = get_irn_dbg_info(node); ir_node *op = get_Conv_op(node); ir_node *new_op = NULL; @@ -3361,7 +3619,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) ia32_address_t *addr = &am.addr; fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem); - new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); + new_node = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res); set_am_attributes(fild, &am); SET_IA32_ORIG_NODE(fild, node); @@ -3412,7 +3670,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) in[0] = zero_store; in[1] = store; - store = new_rd_Sync(dbgi, irg, block, 2, in); + store = new_rd_Sync(dbgi, block, 2, in); store_mode = mode_Ls; } else { store_mode = mode_Is; @@ -3425,7 +3683,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) set_ia32_op_type(fild, ia32_AddrModeS); set_ia32_ls_mode(fild, store_mode); - new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); + new_node = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res); return new_node; } @@ -3502,10 +3760,9 @@ static ir_node *gen_Conv(ir_node *node) assert(!mode_is_int(src_mode) || src_bits <= 32); assert(!mode_is_int(tgt_mode) || tgt_bits <= 32); + /* modeB -> X should already be lowered by the lower_mode_b pass */ if (src_mode == mode_b) { - assert(mode_is_int(tgt_mode) || mode_is_reference(tgt_mode)); - /* nothing to do, we already model bools as 0/1 ints */ - return be_transform_node(op); + panic("ConvB not lowered %+F", node); } if (src_mode == tgt_mode) { @@ -3526,16 +3783,6 @@ static ir_node *gen_Conv(ir_node *node) new_op = be_transform_node(op); /* we convert from float ... */ if (mode_is_float(tgt_mode)) { -#if 0 - /* Matze: I'm a bit unsure what the following is for? seems wrong - * to me... */ - if (src_mode == mode_E && tgt_mode == mode_D - && !get_Conv_strict(node)) { - DB((dbg, LEVEL_1, "killed Conv(mode, mode) ...")); - return new_op; - } -#endif - /* ... to float */ if (ia32_cg_config.use_sse2) { DB((dbg, LEVEL_1, "create Conv(float, float) ...")); @@ -3713,8 +3960,8 @@ static ir_node *gen_be_Return(ir_node *node) set_ia32_op_type(fld, ia32_AddrModeS); set_ia32_use_frame(fld); - mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M); - fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res); + mproj = new_r_Proj(block, fld, mode_M, pn_ia32_vfld_M); + fld = new_r_Proj(block, fld, mode_vfp, pn_ia32_vfld_res); /* create a new barrier */ arity = get_irn_arity(barrier); @@ -3773,6 +4020,7 @@ static ir_node *gen_be_SubSP(ir_node *node) */ static ir_node *gen_Phi(ir_node *node) { + const arch_register_req_t *req; ir_node *block = be_transform_node(get_nodes_block(node)); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); @@ -3784,12 +4032,17 @@ static ir_node *gen_Phi(ir_node *node) assert(get_mode_size_bits(mode) <= 32); /* all integer operations are on 32bit registers now */ mode = mode_Iu; + req = ia32_reg_classes[CLASS_ia32_gp].class_req; } else if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) { mode = mode_xmm; + req = ia32_reg_classes[CLASS_ia32_xmm].class_req; } else { mode = mode_vfp; + req = ia32_reg_classes[CLASS_ia32_vfp].class_req; } + } else { + req = arch_no_register_req; } /* phi nodes allow loops, so we use the old arguments for now @@ -3799,11 +4052,26 @@ static ir_node *gen_Phi(ir_node *node) copy_node_attr(node, phi); be_duplicate_deps(node, phi); + arch_set_out_register_req(phi, 0, req); + be_enqueue_preds(node); return phi; } +static ir_node *gen_Jmp(ir_node *node) +{ + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_node; + + new_node = new_bd_ia32_Jmp(dbgi, new_block); + SET_IA32_ORIG_NODE(new_node, node); + + return new_node; +} + /** * Transform IJmp */ @@ -3843,7 +4111,6 @@ static ir_node *gen_Bound(ir_node *node) if (is_Const_0(lower)) { /* typical case for Java */ ir_node *sub, *res, *flags, *block; - ir_graph *irg = current_ir_graph; res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node), new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate); @@ -3852,11 +4119,11 @@ static ir_node *gen_Bound(ir_node *node) if (! is_Proj(res)) { sub = res; set_irn_mode(sub, mode_T); - res = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_res); + res = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_res); } else { sub = get_Proj_pred(res); } - flags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags); + flags = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_Sub_flags); new_node = new_bd_ia32_Jcc(dbgi, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned); SET_IA32_ORIG_NODE(new_node, node); } else { @@ -4060,7 +4327,7 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) in[0] = store_low; in[1] = store_high; - sync = new_rd_Sync(dbgi, irg, block, 2, in); + sync = new_rd_Sync(dbgi, block, 2, in); /* do a fild */ fild = new_bd_ia32_vfild(dbgi, block, frame, noreg_GP, sync); @@ -4071,7 +4338,7 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) SET_IA32_ORIG_NODE(fild, node); - res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); + res = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res); if (! mode_is_signed(get_irn_mode(val_high))) { ia32_address_mode_t am; @@ -4079,7 +4346,7 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) ir_node *count = ia32_create_Immediate(NULL, 0, 31); ir_node *fadd; - am.addr.base = noreg_GP; + am.addr.base = get_symconst_base(); am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count); am.addr.mem = nomem; am.addr.offset = 0; @@ -4102,7 +4369,7 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) set_am_attributes(fadd, &am); set_irn_mode(fadd, mode_T); - res = new_rd_Proj(NULL, irg, block, fadd, mode_vfp, pn_ia32_res); + res = new_rd_Proj(NULL, block, fadd, mode_vfp, pn_ia32_res); } return res; } @@ -4111,14 +4378,14 @@ static ir_node *gen_ia32_l_FloattoLL(ir_node *node) { ir_node *src_block = get_nodes_block(node); ir_node *block = be_transform_node(src_block); - ir_graph *irg = current_ir_graph; + ir_graph *irg = get_Block_irg(block); dbg_info *dbgi = get_irn_dbg_info(node); ir_node *frame = get_irg_frame(irg); ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val); ir_node *new_val = be_transform_node(val); ir_node *fist, *mem; - mem = gen_vfist(dbgi, irg, block, frame, noreg_GP, nomem, new_val, &fist); + mem = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val, &fist); SET_IA32_ORIG_NODE(fist, node); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); @@ -4138,8 +4405,8 @@ static ir_node *bad_transform(ir_node *node) static ir_node *gen_Proj_l_FloattoLL(ir_node *node) { - ir_graph *irg = current_ir_graph; ir_node *block = be_transform_node(get_nodes_block(node)); + ir_graph *irg = get_Block_irg(block); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); ir_node *frame = get_irg_frame(irg); @@ -4165,7 +4432,7 @@ static ir_node *gen_Proj_l_FloattoLL(ir_node *node) assert(pn == pn_ia32_l_FloattoLL_res_low); } - proj = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res); + proj = new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res); return proj; } @@ -4178,20 +4445,19 @@ static ir_node *gen_Proj_be_AddSP(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); if (proj == pn_be_AddSP_sp) { - ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, + ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_SubSP_stack); arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); return res; } else if (proj == pn_be_AddSP_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_SubSP_addr); } else if (proj == pn_be_AddSP_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_SubSP_M); } panic("No idea how to transform proj->AddSP"); @@ -4205,17 +4471,16 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); if (proj == pn_be_SubSP_sp) { - ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, + ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_AddSP_stack); arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); return res; } else if (proj == pn_be_SubSP_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_AddSP_M); } panic("No idea how to transform proj->SubSP"); @@ -4229,7 +4494,6 @@ static ir_node *gen_Proj_Load(ir_node *node) ir_node *new_pred; ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); @@ -4239,12 +4503,13 @@ static ir_node *gen_Proj_Load(ir_node *node) */ if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) { ir_node *res; + ir_node *old_block = get_nodes_block(node); /* this is needed, because sometimes we have loops that are only reachable through the ProjM */ be_enqueue_preds(node); /* do it in 2 steps, to silence firm verifier */ - res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M); + res = new_rd_Proj(dbgi, old_block, pred, mode_M, pn_Load_M); set_Proj_proj(res, pn_ia32_mem); return res; } @@ -4254,15 +4519,15 @@ static ir_node *gen_Proj_Load(ir_node *node) if (is_ia32_Load(new_pred)) { switch (proj) { case pn_Load_res: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Load_res); case pn_Load_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Load_M); case pn_Load_X_regular: - return new_rd_Jmp(dbgi, irg, block); + return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Load_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Load_X_exc); default: break; } @@ -4270,37 +4535,37 @@ static ir_node *gen_Proj_Load(ir_node *node) is_ia32_Conv_I2I8Bit(new_pred)) { set_irn_mode(new_pred, mode_T); if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_res); } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_mem); } } else if (is_ia32_xLoad(new_pred)) { switch (proj) { case pn_Load_res: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res); + return new_rd_Proj(dbgi, block, new_pred, mode_xmm, pn_ia32_xLoad_res); case pn_Load_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_xLoad_M); case pn_Load_X_regular: - return new_rd_Jmp(dbgi, irg, block); + return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); default: break; } } else if (is_ia32_vfld(new_pred)) { switch (proj) { case pn_Load_res: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res); + return new_rd_Proj(dbgi, block, new_pred, mode_vfp, pn_ia32_vfld_res); case pn_Load_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_vfld_M); case pn_Load_X_regular: - return new_rd_Jmp(dbgi, irg, block); + return new_rd_Jmp(dbgi, block); case pn_Load_X_except: /* This Load might raise an exception. Mark it. */ set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_vfld_X_exc); default: break; } @@ -4314,7 +4579,7 @@ static ir_node *gen_Proj_Load(ir_node *node) if (proj != pn_Load_M) { panic("internal error: transformed node not a Load"); } - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1); + return new_rd_Proj(dbgi, block, new_pred, mode_M, 1); } panic("No idea how to transform proj"); @@ -4328,7 +4593,6 @@ static ir_node *gen_Proj_DivMod(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); @@ -4338,14 +4602,14 @@ static ir_node *gen_Proj_DivMod(ir_node *node) case iro_Div: switch (proj) { case pn_Div_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Div_res: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_div_res); case pn_Div_X_regular: - return new_rd_Jmp(dbgi, irg, block); + return new_rd_Jmp(dbgi, block); case pn_Div_X_except: set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4353,12 +4617,12 @@ static ir_node *gen_Proj_DivMod(ir_node *node) case iro_Mod: switch (proj) { case pn_Mod_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Mod_res: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); case pn_Mod_X_except: set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4366,16 +4630,16 @@ static ir_node *gen_Proj_DivMod(ir_node *node) case iro_DivMod: switch (proj) { case pn_DivMod_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M); case pn_DivMod_res_div: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_div_res); case pn_DivMod_res_mod: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); case pn_DivMod_X_regular: - return new_rd_Jmp(dbgi, irg, block); + return new_rd_Jmp(dbgi, block); case pn_DivMod_X_except: set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); + return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4395,16 +4659,15 @@ static ir_node *gen_Proj_CopyB(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); switch (proj) { case pn_CopyB_M_regular: if (is_ia32_CopyB_i(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_CopyB_i_M); } else if (is_ia32_CopyB(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_CopyB_M); } break; default: @@ -4422,23 +4685,22 @@ static ir_node *gen_Proj_Quot(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); switch (proj) { case pn_Quot_M: if (is_ia32_xDiv(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_xDiv_M); } else if (is_ia32_vfdiv(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M); + return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_vfdiv_M); } break; case pn_Quot_res: if (is_ia32_xDiv(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res); + return new_rd_Proj(dbgi, block, new_pred, mode_xmm, pn_ia32_xDiv_res); } else if (is_ia32_vfdiv(new_pred)) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res); + return new_rd_Proj(dbgi, block, new_pred, mode_vfp, pn_ia32_vfdiv_res); } break; case pn_Quot_X_regular: @@ -4453,7 +4715,6 @@ static ir_node *gen_Proj_Quot(ir_node *node) static ir_node *gen_be_Call(ir_node *node) { dbg_info *const dbgi = get_irn_dbg_info(node); - ir_graph *const irg = current_ir_graph; ir_node *const src_block = get_nodes_block(node); ir_node *const block = be_transform_node(src_block); ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem); @@ -4471,6 +4732,7 @@ static ir_node *gen_be_Call(ir_node *node) ir_node * edx = noreg_GP; unsigned const pop = be_Call_get_pop(node); ir_type *const call_tp = be_Call_get_type(node); + int old_no_pic_adjust; /* Run the x87 simulator if the call returns a float value */ if (get_method_n_ress(call_tp) > 0) { @@ -4485,9 +4747,15 @@ static ir_node *gen_be_Call(ir_node *node) /* We do not want be_Call direct calls */ assert(be_Call_get_entity(node) == NULL); + /* special case for PIC trampoline calls */ + old_no_pic_adjust = no_pic_adjust; + no_pic_adjust = env_cg->birg->main_env->options->pic; + match_arguments(&am, src_block, NULL, src_ptr, src_mem, match_am | match_immediate); + no_pic_adjust = old_no_pic_adjust; + i = get_irn_arity(node) - 1; fpcw = be_transform_node(get_irn_n(node, i--)); for (; i >= be_pos_Call_first_arg; --i) { @@ -4505,7 +4773,7 @@ static ir_node *gen_be_Call(ir_node *node) } } - mem = transform_AM_mem(irg, block, src_ptr, src_mem, addr->mem); + mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem); call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem, am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp); set_am_attributes(call, &am); @@ -4528,7 +4796,8 @@ static ir_node *gen_be_Call(ir_node *node) /** * Transform Builtin trap */ -static ir_node *gen_trap(ir_node *node) { +static ir_node *gen_trap(ir_node *node) +{ dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *mem = be_transform_node(get_Builtin_mem(node)); @@ -4539,7 +4808,8 @@ static ir_node *gen_trap(ir_node *node) { /** * Transform Builtin debugbreak */ -static ir_node *gen_debugbreak(ir_node *node) { +static ir_node *gen_debugbreak(ir_node *node) +{ dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *mem = be_transform_node(get_Builtin_mem(node)); @@ -4550,7 +4820,8 @@ static ir_node *gen_debugbreak(ir_node *node) { /** * Transform Builtin return_address */ -static ir_node *gen_return_address(ir_node *node) { +static ir_node *gen_return_address(ir_node *node) +{ ir_node *param = get_Builtin_param(node, 0); ir_node *frame = get_Builtin_param(node, 1); dbg_info *dbgi = get_irn_dbg_info(node); @@ -4586,13 +4857,14 @@ static ir_node *gen_return_address(ir_node *node) { } SET_IA32_ORIG_NODE(load, node); - return new_r_Proj(current_ir_graph, block, load, mode_Iu, pn_ia32_Load_res); + return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res); } /** * Transform Builtin frame_address */ -static ir_node *gen_frame_address(ir_node *node) { +static ir_node *gen_frame_address(ir_node *node) +{ ir_node *param = get_Builtin_param(node, 0); ir_node *frame = get_Builtin_param(node, 1); dbg_info *dbgi = get_irn_dbg_info(node); @@ -4635,13 +4907,14 @@ static ir_node *gen_frame_address(ir_node *node) { } SET_IA32_ORIG_NODE(load, node); - return new_r_Proj(current_ir_graph, block, load, mode_Iu, pn_ia32_Load_res); + return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res); } /** * Transform Builtin frame_address */ -static ir_node *gen_prefetch(ir_node *node) { +static ir_node *gen_prefetch(ir_node *node) +{ dbg_info *dbgi; ir_node *ptr, *block, *mem, *base, *index; ir_node *param, *new_node; @@ -4719,7 +4992,7 @@ static ir_node *gen_prefetch(ir_node *node) { SET_IA32_ORIG_NODE(new_node, node); be_dep_on_frame(new_node); - return new_r_Proj(current_ir_graph, block, new_node, mode_M, pn_ia32_Prefetch_M); + return new_r_Proj(block, new_node, mode_M, pn_ia32_Prefetch_M); } /** @@ -4761,13 +5034,13 @@ static ir_node *gen_ffs(ir_node *node) /* bsf x */ if (get_irn_mode(real) != mode_T) { set_irn_mode(real, mode_T); - bsf = new_r_Proj(current_ir_graph, block, real, mode_Iu, pn_ia32_res); + bsf = new_r_Proj(block, real, mode_Iu, pn_ia32_res); } - flag = new_r_Proj(current_ir_graph, block, real, mode_b, pn_ia32_flags); + flag = new_r_Proj(block, real, mode_b, pn_ia32_flags); /* sete */ - set = new_bd_ia32_Set(dbgi, block, flag, pn_Cmp_Eq, 0); + set = new_bd_ia32_Setcc(dbgi, block, flag, pn_Cmp_Eq); SET_IA32_ORIG_NODE(set, node); /* conv to 32bit */ @@ -4837,7 +5110,7 @@ static ir_node *gen_parity(ir_node *node) cmp = fix_mem_proj(cmp, &am); /* setp */ - new_node = new_bd_ia32_Set(dbgi, new_block, cmp, ia32_pn_Cmp_parity, 0); + new_node = new_bd_ia32_Setcc(dbgi, new_block, cmp, ia32_pn_Cmp_parity); SET_IA32_ORIG_NODE(new_node, node); /* conv to 32bit */ @@ -4850,7 +5123,8 @@ static ir_node *gen_parity(ir_node *node) /** * Transform builtin popcount */ -static ir_node *gen_popcount(ir_node *node) { +static ir_node *gen_popcount(ir_node *node) +{ ir_node *param = get_Builtin_param(node, 0); dbg_info *dbgi = get_irn_dbg_info(node); @@ -4951,7 +5225,8 @@ static ir_node *gen_popcount(ir_node *node) { /** * Transform builtin byte swap. */ -static ir_node *gen_bswap(ir_node *node) { +static ir_node *gen_bswap(ir_node *node) +{ ir_node *param = be_transform_node(get_Builtin_param(node, 0)); dbg_info *dbgi = get_irn_dbg_info(node); @@ -4993,7 +5268,8 @@ static ir_node *gen_bswap(ir_node *node) { /** * Transform builtin outport. */ -static ir_node *gen_outport(ir_node *node) { +static ir_node *gen_outport(ir_node *node) +{ ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0); ir_node *oldv = get_Builtin_param(node, 1); ir_mode *mode = get_irn_mode(oldv); @@ -5010,7 +5286,8 @@ static ir_node *gen_outport(ir_node *node) { /** * Transform builtin inport. */ -static ir_node *gen_inport(ir_node *node) { +static ir_node *gen_inport(ir_node *node) +{ ir_type *tp = get_Builtin_type(node); ir_type *rstp = get_method_res_type(tp, 0); ir_mode *mode = get_type_mode(rstp); @@ -5029,7 +5306,8 @@ static ir_node *gen_inport(ir_node *node) { /** * Transform a builtin inner trampoline */ -static ir_node *gen_inner_trampoline(ir_node *node) { +static ir_node *gen_inner_trampoline(ir_node *node) +{ ir_node *ptr = get_Builtin_param(node, 0); ir_node *callee = get_Builtin_param(node, 1); ir_node *env = be_transform_node(get_Builtin_param(node, 2)); @@ -5096,7 +5374,7 @@ static ir_node *gen_inner_trampoline(ir_node *node) { /* the callee is typically an immediate */ if (is_SymConst(callee)) { - rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, -10); + rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, 0, -10); } else { rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), ia32_create_Immediate(NULL, 0, -10)); } @@ -5112,13 +5390,14 @@ static ir_node *gen_inner_trampoline(ir_node *node) { in[0] = store; in[1] = trampoline; - return new_r_Tuple(current_ir_graph, new_block, 2, in); + return new_r_Tuple(new_block, 2, in); } /** * Transform Builtin node. */ -static ir_node *gen_Builtin(ir_node *node) { +static ir_node *gen_Builtin(ir_node *node) +{ ir_builtin_kind kind = get_Builtin_kind(node); switch (kind) { @@ -5128,7 +5407,7 @@ static ir_node *gen_Builtin(ir_node *node) { return gen_debugbreak(node); case ir_bk_return_address: return gen_return_address(node); - case ir_bk_frame_addess: + case ir_bk_frame_address: return gen_frame_address(node); case ir_bk_prefetch: return gen_prefetch(node); @@ -5157,14 +5436,15 @@ static ir_node *gen_Builtin(ir_node *node) { /** * Transform Proj(Builtin) node. */ -static ir_node *gen_Proj_Builtin(ir_node *proj) { +static ir_node *gen_Proj_Builtin(ir_node *proj) +{ ir_node *node = get_Proj_pred(proj); ir_node *new_node = be_transform_node(node); ir_builtin_kind kind = get_Builtin_kind(node); switch (kind) { case ir_bk_return_address: - case ir_bk_frame_addess: + case ir_bk_frame_address: case ir_bk_ffs: case ir_bk_clz: case ir_bk_ctz: @@ -5181,11 +5461,11 @@ static ir_node *gen_Proj_Builtin(ir_node *proj) { return new_node; case ir_bk_inport: if (get_Proj_proj(proj) == pn_Builtin_1_result) { - return new_r_Proj(current_ir_graph, get_nodes_block(new_node), + return new_r_Proj(get_nodes_block(new_node), new_node, get_irn_mode(proj), pn_ia32_Inport_res); } else { assert(get_Proj_proj(proj) == pn_Builtin_M); - return new_r_Proj(current_ir_graph, get_nodes_block(new_node), + return new_r_Proj(get_nodes_block(new_node), new_node, mode_M, pn_ia32_Inport_M); } case ir_bk_inner_trampoline: @@ -5215,14 +5495,13 @@ static ir_node *gen_Proj_be_Call(ir_node *node) ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *call = get_Proj_pred(node); ir_node *new_call = be_transform_node(call); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); ir_mode *mode = get_irn_mode(node); ir_node *res; if (proj == pn_be_Call_M_regular) { - return new_rd_Proj(dbgi, irg, block, new_call, mode_M, n_ia32_Call_mem); + return new_rd_Proj(dbgi, block, new_call, mode_M, n_ia32_Call_mem); } /* transform call modes */ if (mode_is_data(mode)) { @@ -5244,7 +5523,8 @@ static ir_node *gen_Proj_be_Call(ir_node *node) assert(req->type & arch_register_req_type_limited); for (i = 0; i < n_outs; ++i) { - arch_register_req_t const *const new_req = get_ia32_out_req(new_call, i); + arch_register_req_t const *const new_req + = arch_get_out_register_req(new_call, i); if (!(new_req->type & arch_register_req_type_limited) || new_req->cls != req->cls || @@ -5257,7 +5537,7 @@ static ir_node *gen_Proj_be_Call(ir_node *node) assert(i < n_outs); } - res = new_rd_Proj(dbgi, irg, block, new_call, mode, proj); + res = new_rd_Proj(dbgi, block, new_call, mode, proj); /* TODO arch_set_irn_register() only operates on Projs, need variant with index */ switch (proj) { @@ -5297,11 +5577,11 @@ static ir_node *gen_Proj_Bound(ir_node *node) case pn_Bound_X_regular: new_node = be_transform_node(pred); block = get_nodes_block(new_node); - return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_true); + return new_r_Proj(block, new_node, mode_X, pn_ia32_Jcc_true); case pn_Bound_X_except: new_node = be_transform_node(pred); block = get_nodes_block(new_node); - return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_false); + return new_r_Proj(block, new_node, mode_X, pn_ia32_Jcc_false); case pn_Bound_res: return be_transform_node(get_Bound_index(pred)); default: @@ -5318,7 +5598,7 @@ static ir_node *gen_Proj_ASM(ir_node *node) long pos = get_Proj_proj(node); if (mode == mode_M) { - pos = arch_irn_get_n_outs(new_pred) + 1; + pos = arch_irn_get_n_outs(new_pred)-1; } else if (mode_is_int(mode) || mode_is_reference(mode)) { mode = mode_Iu; } else if (mode_is_float(mode)) { @@ -5327,7 +5607,7 @@ static ir_node *gen_Proj_ASM(ir_node *node) panic("unexpected proj mode at ASM"); } - return new_r_Proj(current_ir_graph, block, new_pred, mode, pos); + return new_r_Proj(block, new_pred, mode, pos); } /** @@ -5378,7 +5658,7 @@ static ir_node *gen_Proj(ir_node *node) ir_node *new_block = be_transform_node(block); dbg_info *dbgi = get_irn_dbg_info(node); /* we exchange the ProjX with a jump */ - ir_node *jump = new_rd_Jmp(dbgi, current_ir_graph, new_block); + ir_node *jump = new_rd_Jmp(dbgi, new_block); return jump; } @@ -5400,7 +5680,7 @@ static ir_node *gen_Proj(ir_node *node) if (ia32_mode_needs_gp_reg(mode)) { ir_node *new_pred = be_transform_node(pred); ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_proj = new_r_Proj(current_ir_graph, block, new_pred, + ir_node *new_proj = new_r_Proj(block, new_pred, mode_Iu, get_Proj_proj(node)); new_proj->node_nr = node->node_nr; return new_proj; @@ -5455,6 +5735,7 @@ static void register_transformers(void) GEN(Mux); GEN(Proj); GEN(Phi); + GEN(Jmp); GEN(IJmp); GEN(Bound); @@ -5581,7 +5862,7 @@ static void add_missing_keep_walker(ir_node *node, void *data) continue; } - req = get_ia32_out_req(node, i); + req = arch_get_out_register_req(node, i); cls = req->cls; if (cls == NULL) { continue; @@ -5591,12 +5872,11 @@ static void add_missing_keep_walker(ir_node *node, void *data) } block = get_nodes_block(node); - in[0] = new_r_Proj(current_ir_graph, block, node, - arch_register_class_mode(cls), i); + in[0] = new_r_Proj(block, node, arch_register_class_mode(cls), i); if (last_keep != NULL) { be_Keep_add_node(last_keep, cls, in[0]); } else { - last_keep = be_new_Keep(cls, current_ir_graph, block, 1, in); + last_keep = be_new_Keep(block, 1, in); if (sched_is_scheduled(node)) { sched_add_after(node, last_keep); } @@ -5619,7 +5899,8 @@ void ia32_add_missing_keeps(ia32_code_gen_t *cg) * The ABI requires that the results are in st0, copy them * to a xmm register. */ -static void postprocess_fp_call_results(void) { +static void postprocess_fp_call_results(void) +{ int i; for (i = ARR_LEN(call_list) - 1; i >= 0; --i) { @@ -5679,7 +5960,7 @@ static void postprocess_fp_call_results(void) { ir_node *block = get_nodes_block(call); ir_node *frame = get_irg_frame(current_ir_graph); ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M); - ir_node *call_mem = new_r_Proj(current_ir_graph, block, call, mode_M, pn_ia32_Call_M); + ir_node *call_mem = new_r_Proj(block, call, mode_M, pn_ia32_Call_M); ir_node *vfst, *xld, *new_mem; /* store st(0) on stack */ @@ -5692,8 +5973,8 @@ static void postprocess_fp_call_results(void) { set_ia32_op_type(xld, ia32_AddrModeS); set_ia32_use_frame(xld); - new_res = new_r_Proj(current_ir_graph, block, xld, mode, pn_ia32_xLoad_res); - new_mem = new_r_Proj(current_ir_graph, block, xld, mode_M, pn_ia32_xLoad_M); + new_res = new_r_Proj(block, xld, mode, pn_ia32_xLoad_res); + new_mem = new_r_Proj(block, xld, mode_M, pn_ia32_xLoad_M); if (old_mem != NULL) { edges_reroute(old_mem, new_mem, current_ir_graph); @@ -5713,12 +5994,13 @@ void ia32_transform_graph(ia32_code_gen_t *cg) int cse_last; register_transformers(); - env_cg = cg; - initial_fpcw = NULL; + env_cg = cg; + initial_fpcw = NULL; + no_pic_adjust = 0; - BE_TIMER_PUSH(t_heights); + be_timer_push(T_HEIGHTS); heights = heights_new(cg->irg); - BE_TIMER_POP(t_heights); + be_timer_pop(T_HEIGHTS); ia32_calculate_non_address_mode_nodes(cg->birg); /* the transform phase is not safe for CSE (yet) because several nodes get