X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=41ae3496a3b1d085dae4602a8bdbc1d1dad2bef7;hb=a950773f1f6101a90fae9c565e4f236b0300327c;hp=ee8b3d8ad67828abb4d2704450ad669043cb2f5d;hpb=9539cba0634cc8f125bd802baab7d4dc0f7caeca;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index ee8b3d8ad..41ae3496a 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -55,6 +55,7 @@ #include "../beutil.h" #include "../beirg_t.h" #include "../betranshlp.h" +#include "../be_t.h" #include "bearch_ia32_t.h" #include "ia32_nodes_attr.h" @@ -65,6 +66,7 @@ #include "ia32_optimize.h" #include "ia32_util.h" #include "ia32_address_mode.h" +#include "ia32_architecture.h" #include "gen_ia32_regalloc_if.h" @@ -102,6 +104,10 @@ typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2); +typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg, + ir_node *block, ir_node *base, ir_node *index, ir_node *mem, + ir_node *op1, ir_node *op2, ir_node *flags); + typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *op1, ir_node *op2); @@ -119,16 +125,6 @@ typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg, typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *op); -/**************************************************************************************************** - * _ _ __ _ _ - * | | | | / _| | | (_) - * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __ - * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \ - * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | | - * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_| - * - ****************************************************************************************************/ - static ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type); @@ -145,6 +141,8 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, static INLINE int mode_needs_gp_reg(ir_mode *mode) { if(mode == mode_fpcw) return 0; + if(get_mode_size_bits(mode) > 32) + return 0; return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b; } @@ -186,10 +184,11 @@ static ir_type *get_prim_type(pmap *types, ir_mode *mode) /** * Get an atomic entity that is initialized with a tarval */ -static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst) +static ir_entity *create_float_const_entity(ir_node *cnst) { - tarval *tv = get_Const_tarval(cnst); - pmap_entry *e = pmap_find(isa->tv_ent, tv); + ia32_isa_t *isa = env_cg->isa; + tarval *tv = get_Const_tarval(cnst); + pmap_entry *e = pmap_find(isa->tv_ent, tv); ir_entity *res; ir_graph *rem; @@ -222,33 +221,29 @@ static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst) } static int is_Const_0(ir_node *node) { - if(!is_Const(node)) - return 0; - - return classify_Const(node) == CNST_NULL; + return is_Const(node) && is_Const_null(node); } static int is_Const_1(ir_node *node) { - if(!is_Const(node)) - return 0; - - return classify_Const(node) == CNST_ONE; + return is_Const(node) && is_Const_one(node); } static int is_Const_Minus_1(ir_node *node) { - tarval *tv; - ir_mode *mode; - if(!is_Const(node)) - return 0; + return is_Const(node) && is_Const_all_one(node); +} - mode = get_irn_mode(node); - if(!mode_is_signed(mode)) - return 0; +/** + * returns true if constant can be created with a simple float command + */ +static int is_simple_x87_Const(ir_node *node) +{ + tarval *tv = get_Const_tarval(node); - tv = get_Const_tarval(node); - tv = tarval_neg(tv); + if(tarval_is_null(tv) || tarval_is_one(tv)) + return 1; - return classify_tarval(tv) == CNST_ONE; + /* TODO: match all the other float constants */ + return 0; } /** @@ -261,21 +256,22 @@ static ir_node *gen_Const(ir_node *node) { dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); + assert(is_Const(node)); + if (mode_is_float(mode)) { ir_node *res = NULL; ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_node *nomem = new_NoMem(); ir_node *load; ir_entity *floatent; - cnst_classify_t clss = classify_Const(node); - if (USE_SSE2(env_cg)) { - if (clss == CNST_NULL) { + if (ia32_cg_config.use_sse2) { + if (is_Const_null(node)) { load = new_rd_ia32_xZero(dbgi, irg, block); set_ia32_ls_mode(load, mode); res = load; } else { - floatent = ia32_get_entity_for_tv(env_cg->isa, node); + floatent = create_float_const_entity(node); load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode); @@ -285,14 +281,14 @@ static ir_node *gen_Const(ir_node *node) { res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res); } } else { - if (clss == CNST_NULL) { + if (is_Const_null(node)) { load = new_rd_ia32_vfldz(dbgi, irg, block); res = load; - } else if (clss == CNST_ONE) { + } else if (is_Const_one(node)) { load = new_rd_ia32_vfld1(dbgi, irg, block); res = load; } else { - floatent = ia32_get_entity_for_tv(env_cg->isa, node); + floatent = create_float_const_entity(node); load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode); set_ia32_op_type(load, ia32_AddrModeS); @@ -356,7 +352,7 @@ static ir_node *gen_SymConst(ir_node *node) { ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_node *nomem = new_NoMem(); - if (USE_SSE2(env_cg)) + if (ia32_cg_config.use_sse2) cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E); else cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E); @@ -460,13 +456,28 @@ const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) { } #endif /* NDEBUG */ -static int use_source_address_mode(ir_node *block, ir_node *node, - ir_node *other) +/** + * return true if the node is a Proj(Load) and could be used in source address + * mode for another node. Will return only true if the @p other node is not + * dependent on the memory of the Load (for binary operations use the other + * input here, for unary operations use NULL). + */ +static int ia32_use_source_address_mode(ir_node *block, ir_node *node, + ir_node *other, ir_node *other2) { - ir_mode *mode; + ir_mode *mode = get_irn_mode(node); ir_node *load; long pn; + /* float constants are always available */ + if(is_Const(node) && mode_is_float(mode)) { + if(!is_simple_x87_Const(node)) + return 0; + if(get_irn_n_edges(node) > 1) + return 0; + return 1; + } + if(!is_Proj(node)) return 0; load = get_Proj_pred(node); @@ -478,23 +489,19 @@ static int use_source_address_mode(ir_node *block, ir_node *node, /* we only use address mode if we're the only user of the load */ if(get_irn_n_edges(node) > 1) return 0; - - mode = get_irn_mode(node); - if(!mode_needs_gp_reg(mode)) - return 0; - /* - * Matze: the unresolved question here is wether 8/16bit operations - * are a good idea if they define registers (as writing to an 8/16 - * bit reg is bad on modern cpu as it confuses the dependency calculation - * for the full reg) - */ - if(other != NULL && get_Load_mode(load) != get_irn_mode(other)) + /* in some edge cases with address mode we might reach the load normally + * and through some AM sequence, if it is already materialized then we + * can't create an AM node from it */ + if(be_is_transformed(node)) return 0; /* don't do AM if other node inputs depend on the load (via mem-proj) */ if(other != NULL && get_nodes_block(other) == block && heights_reachable_in_block(heights, other, load)) return 0; + if(other2 != NULL && get_nodes_block(other2) == block + && heights_reachable_in_block(heights, other2, load)) + return 0; return 1; } @@ -507,46 +514,62 @@ struct ia32_address_mode_t { ia32_op_type_t op_type; ir_node *new_op1; ir_node *new_op2; - int commutative; - int flipped; + op_pin_state pinned; + unsigned commutative : 1; + unsigned ins_permuted : 1; }; +static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem) +{ + ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); + + /* construct load address */ + memset(addr, 0, sizeof(addr[0])); + ia32_create_address_mode(addr, ptr, /*force=*/0); + + addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp; + addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp; + addr->mem = be_transform_node(mem); +} + static void build_address(ia32_address_mode_t *am, ir_node *node) { - ia32_address_t *addr = &am->addr; - ir_node *load = get_Proj_pred(node); - ir_node *ptr = get_Load_ptr(load); - ir_node *mem = get_Load_mem(load); - ir_node *new_mem = be_transform_node(mem); - ir_node *base; - ir_node *index; + ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); + ia32_address_t *addr = &am->addr; + ir_node *load; + ir_node *ptr; + ir_node *mem; + ir_node *new_mem; + + if(is_Const(node)) { + ir_entity *entity = create_float_const_entity(node); + addr->base = noreg_gp; + addr->index = noreg_gp; + addr->mem = new_NoMem(); + addr->symconst_ent = entity; + addr->use_frame = 1; + am->ls_mode = get_irn_mode(node); + am->pinned = op_pin_state_floats; + return; + } + load = get_Proj_pred(node); + ptr = get_Load_ptr(load); + mem = get_Load_mem(load); + new_mem = be_transform_node(mem); + am->pinned = get_irn_pinned(load); am->ls_mode = get_Load_mode(load); am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M); /* construct load address */ - ia32_create_address_mode(addr, ptr, 0); - base = addr->base; - index = addr->index; - - if(base == NULL) { - base = ia32_new_NoReg_gp(env_cg); - } else { - base = be_transform_node(base); - } - - if(index == NULL) { - index = ia32_new_NoReg_gp(env_cg); - } else { - index = be_transform_node(index); - } + ia32_create_address_mode(addr, ptr, /*force=*/0); - addr->base = base; - addr->index = index; + addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp; + addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp; addr->mem = new_mem; } -static void set_address(ir_node *node, ia32_address_t *addr) +static void set_address(ir_node *node, const ia32_address_t *addr) { set_ia32_am_scale(node, addr->scale); set_ia32_am_sc(node, addr->symconst_ent); @@ -558,53 +581,188 @@ static void set_address(ir_node *node, ia32_address_t *addr) set_ia32_frame_ent(node, addr->frame_entity); } -static void set_am_attributes(ir_node *node, ia32_address_mode_t *am) +static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am) { set_address(node, &am->addr); set_ia32_op_type(node, am->op_type); set_ia32_ls_mode(node, am->ls_mode); + if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) { + set_irn_pinned(node, am->pinned); + } if(am->commutative) set_ia32_commutative(node); } +/** + * Check, if a given node is a Down-Conv, ie. a integer Conv + * from a mode with a mode with more bits to a mode with lesser bits. + * Moreover, we return only true if the node has not more than 1 user. + * + * @param node the node + * @return non-zero if node is a Down-Conv + */ +static int is_downconv(const ir_node *node) +{ + ir_mode *src_mode; + ir_mode *dest_mode; + + if(!is_Conv(node)) + return 0; + + /* we only want to skip the conv when we're the only user + * (not optimal but for now...) + */ + if(get_irn_n_edges(node) > 1) + return 0; + + src_mode = get_irn_mode(get_Conv_op(node)); + dest_mode = get_irn_mode(node); + return mode_needs_gp_reg(src_mode) + && mode_needs_gp_reg(dest_mode) + && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode); +} + +/* Skip all Down-Conv's on a given node and return the resulting node. */ +ir_node *ia32_skip_downconv(ir_node *node) { + while (is_downconv(node)) + node = get_Conv_op(node); + + return node; +} + +#if 0 +static ir_node *create_upconv(ir_node *node, ir_node *orig_node) +{ + ir_mode *mode = get_irn_mode(node); + ir_node *block; + ir_mode *tgt_mode; + dbg_info *dbgi; + + if(mode_is_signed(mode)) { + tgt_mode = mode_Is; + } else { + tgt_mode = mode_Iu; + } + block = get_nodes_block(node); + dbgi = get_irn_dbg_info(node); + + return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node); +} +#endif + +/** + * matches operands of a node into ia32 addressing/operand modes. This covers + * usage of source address mode, immediates, operations with non 32-bit modes, + * ... + * The resulting data is filled into the @p am struct. block is the block + * of the node whose arguments are matched. op1, op2 are the first and second + * input that are matched (op1 may be NULL). other_op is another unrelated + * input that is not matched! but which is needed sometimes to check if AM + * for op1/op2 is legal. + * @p flags describes the supported modes of the operation in detail. + */ static void match_arguments(ia32_address_mode_t *am, ir_node *block, - ir_node *op1, ir_node *op2, int commutative, - int use_am_and_immediates, int use_am, - int use_8_16_bit_am) + ir_node *op1, ir_node *op2, ir_node *other_op, + match_flags_t flags) { ia32_address_t *addr = &am->addr; ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); ir_node *new_op1; ir_node *new_op2; + ir_mode *mode = get_irn_mode(op2); + int use_am; + unsigned commutative; + int use_am_and_immediates; + int use_immediate; + int mode_bits = get_mode_size_bits(mode); memset(am, 0, sizeof(am[0])); - if(!use_8_16_bit_am && get_mode_size_bits(get_irn_mode(op1)) < 32) - use_am = 0; + commutative = (flags & match_commutative) != 0; + use_am_and_immediates = (flags & match_am_and_immediates) != 0; + use_am = (flags & match_am) != 0; + use_immediate = (flags & match_immediate) != 0; + assert(!use_am_and_immediates || use_immediate); + + assert(op2 != NULL); + assert(!commutative || op1 != NULL); + assert(use_am || !(flags & match_8bit_am)); + assert(use_am || !(flags & match_16bit_am)); + + if(mode_bits == 8) { + if (! (flags & match_8bit_am)) + use_am = 0; + /* we don't automatically add upconvs yet */ + assert((flags & match_mode_neutral) || (flags & match_8bit)); + } else if(mode_bits == 16) { + if(! (flags & match_16bit_am)) + use_am = 0; + /* we don't automatically add upconvs yet */ + assert((flags & match_mode_neutral) || (flags & match_16bit)); + } + + /* we can simply skip downconvs for mode neutral nodes: the upper bits + * can be random for these operations */ + if(flags & match_mode_neutral) { + op2 = ia32_skip_downconv(op2); + if(op1 != NULL) { + op1 = ia32_skip_downconv(op1); + } + } + + /* match immediates. firm nodes are normalized: constants are always on the + * op2 input */ + new_op2 = NULL; + if(! (flags & match_try_am) && use_immediate) { + new_op2 = try_create_Immediate(op2, 0); + } - new_op2 = try_create_Immediate(op2, 0); - if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) { + if(new_op2 == NULL + && use_am && ia32_use_source_address_mode(block, op2, op1, other_op)) { build_address(am, op2); - new_op1 = be_transform_node(op1); - new_op2 = noreg_gp; + new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); + if(mode_is_float(mode)) { + new_op2 = ia32_new_NoReg_vfp(env_cg); + } else { + new_op2 = noreg_gp; + } am->op_type = ia32_AddrModeS; } else if(commutative && (new_op2 == NULL || use_am_and_immediates) && - use_am && use_source_address_mode(block, op1, op2)) { + use_am + && ia32_use_source_address_mode(block, op1, op2, other_op)) { + ir_node *noreg; build_address(am, op1); + + if(mode_is_float(mode)) { + noreg = ia32_new_NoReg_vfp(env_cg); + } else { + noreg = noreg_gp; + } + if(new_op2 != NULL) { - new_op1 = noreg_gp; + new_op1 = noreg; } else { new_op1 = be_transform_node(op2); - new_op2 = noreg_gp; - am->flipped = 1; + new_op2 = noreg; + am->ins_permuted = 1; } am->op_type = ia32_AddrModeS; } else { - new_op1 = be_transform_node(op1); + if(flags & match_try_am) { + am->new_op1 = NULL; + am->new_op2 = NULL; + am->op_type = ia32_Normal; + return; + } + + new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); if(new_op2 == NULL) new_op2 = be_transform_node(op2); am->op_type = ia32_Normal; + am->ls_mode = get_irn_mode(op2); + if(flags & match_mode_neutral) + am->ls_mode = mode_Iu; } if(addr->base == NULL) addr->base = noreg_gp; @@ -651,19 +809,19 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) * @return The constructed ia32 node. */ static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2, - construct_binop_func *func, int commutative) + construct_binop_func *func, match_flags_t flags) { - ir_node *src_block = get_nodes_block(node); - ir_node *block = be_transform_node(src_block); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - match_arguments(&am, src_block, op1, op2, commutative, 0, 1, 0); + match_arguments(&am, block, op1, op2, NULL, flags); - new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem, + new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2); set_am_attributes(new_node, &am); /* we can't use source address mode anymore when using immediates */ @@ -676,36 +834,53 @@ static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2, return new_node; } +enum { + n_ia32_l_binop_left, + n_ia32_l_binop_right, + n_ia32_l_binop_eflags +}; +COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left) +COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right) +COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags) +COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left) +COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right) +COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags) + /** - * Construct a standard binary operation, set AM and immediate if required. + * Construct a binary operation which also consumes the eflags. * - * @param op1 The first operand - * @param op2 The second operand + * @param node The node to transform * @param func The node constructor function - * @return The constructed ia32 node. + * @param flags The match flags + * @return The constructor ia32 node */ -static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2, - construct_binop_func *func) +static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, + match_flags_t flags) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_op1 = be_transform_node(op1); - ir_node *new_op2 = be_transform_node(op2); - ir_node *new_node = NULL; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_graph *irg = current_ir_graph; - ir_mode *mode = get_irn_mode(node); - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); + ir_node *src_block = get_nodes_block(node); + ir_node *block = be_transform_node(src_block); + ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left); + ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right); + ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags); + ir_node *new_eflags = be_transform_node(eflags); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_node; + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; - new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1, - new_op2); - if (is_op_commutative(get_irn_op(node))) { - set_ia32_commutative(new_node); - } - set_ia32_ls_mode(new_node, mode); + match_arguments(&am, src_block, op1, op2, NULL, flags); + new_node = func(dbgi, irg, block, addr->base, addr->index, + addr->mem, am.new_op1, am.new_op2, new_eflags); + set_am_attributes(new_node, &am); + /* we can't use source address mode anymore when using immediates */ + if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) + set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + new_node = fix_mem_proj(new_node, &am); + return new_node; } @@ -731,25 +906,32 @@ static ir_node *get_fpcw(void) * @return The constructed ia32 node. */ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, - construct_binop_float_func *func) + construct_binop_float_func *func, + match_flags_t flags) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_op1 = be_transform_node(op1); - ir_node *new_op2 = be_transform_node(op2); - ir_node *new_node = NULL; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_graph *irg = current_ir_graph; - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_mode *mode = get_irn_mode(node); + ir_node *new_node; + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; - new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1, new_op2, - get_fpcw()); - if (is_op_commutative(get_irn_op(node))) { - set_ia32_commutative(new_node); - } + /* cannot use addresmode with long double on x87 */ + if (get_mode_size_bits(mode) > 64) + flags &= ~match_am; + + match_arguments(&am, block, op1, op2, NULL, flags); + + new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem, + am.new_op1, am.new_op2, get_fpcw()); + set_am_attributes(new_node, &am); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + new_node = fix_mem_proj(new_node, &am); + return new_node; } @@ -762,30 +944,45 @@ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, * @return The constructed ia32 node. */ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, - construct_shift_func *func) + construct_shift_func *func, + match_flags_t flags) { dbg_info *dbgi = get_irn_dbg_info(node); ir_graph *irg = current_ir_graph; ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); - ir_node *new_op1 = be_transform_node(op1); - ir_node *new_op2 = create_immediate_or_transform(op2, 0); - ir_node *res; + ir_node *new_op1; + ir_node *new_op2; + ir_node *new_node; + + assert(! mode_is_float(get_irn_mode(node))); + assert(flags & match_immediate); + assert((flags & ~(match_mode_neutral | match_immediate)) == 0); - assert(! mode_is_float(get_irn_mode(node)) - && "Shift/Rotate with float not supported"); + if(flags & match_mode_neutral) { + op1 = ia32_skip_downconv(op1); + } + new_op1 = be_transform_node(op1); - res = func(dbgi, irg, new_block, new_op1, new_op2); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + /* the shift amount can be any mode that is bigger than 5 bits, since all + * other bits are ignored anyway */ + while (is_Conv(op2) && get_irn_n_edges(op2) == 1) { + op2 = get_Conv_op(op2); + assert(get_mode_size_bits(get_irn_mode(op2)) >= 5); + } + new_op2 = create_immediate_or_transform(op2, 0); + + new_node = func(dbgi, irg, new_block, new_op1, new_op2); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); /* lowered shift instruction may have a dependency operand, handle it here */ if (get_irn_arity(node) == 3) { /* we have a dependency */ ir_node *new_dep = be_transform_node(get_irn_n(node, 2)); - add_irn_dep(res, new_dep); + add_irn_dep(new_node, new_dep); } - return res; + return new_node; } @@ -796,15 +993,23 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, * @param func The node constructor function * @return The constructed ia32 node. */ -static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func) +static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, + match_flags_t flags) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_op = be_transform_node(op); - ir_node *new_node = NULL; - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *new_op; + ir_node *new_node; + + assert(flags == 0 || flags == match_mode_neutral); + if(flags & match_mode_neutral) { + op = ia32_skip_downconv(op); + } - new_node = func(dbgi, irg, block, new_op); + new_op = be_transform_node(op); + new_node = func(dbgi, irg, new_block, new_op); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -849,27 +1054,32 @@ static int am_has_immediates(const ia32_address_t *addr) * @return the created ia32 Add node */ static ir_node *gen_Add(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op1 = get_Add_left(node); - ir_node *op2 = get_Add_right(node); - ir_node *new_op; - ir_node *new_op1; - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *src_block = get_nodes_block(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *op1 = get_Add_left(node); + ir_node *op2 = get_Add_right(node); + ir_mode *mode = get_irn_mode(node); + ir_node *new_node; ir_node *add_immediate_op; ia32_address_t addr; ia32_address_mode_t am; if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) - return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd); + if (ia32_cg_config.use_sse2) + return gen_binop(node, op1, op2, new_rd_ia32_xAdd, + match_commutative | match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, + match_commutative | match_am); } + ia32_mark_non_am(node); + + op2 = ia32_skip_downconv(op2); + op1 = ia32_skip_downconv(op1); + /** * Rules for an Add: * 0. Immediate Trees (example Add(Symconst, Const) -> Const) @@ -878,15 +1088,15 @@ static ir_node *gen_Add(ir_node *node) { * 3. Otherwise -> Lea */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, node, 1); + ia32_create_address_mode(&addr, node, /*force=*/1); add_immediate_op = NULL; /* a constant? */ if(addr.base == NULL && addr.index == NULL) { - new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent, - addr.symconst_sign, addr.offset); - add_irn_dep(new_op, get_irg_frame(irg)); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); - return new_op; + new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent, + addr.symconst_sign, addr.offset); + add_irn_dep(new_node, get_irg_frame(irg)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + return new_node; } /* add with immediate? */ if(addr.index == NULL) { @@ -904,41 +1114,33 @@ static ir_node *gen_Add(ir_node *node) { return be_transform_node(add_immediate_op); } - new_op = create_lea_from_address(dbgi, block, &addr); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); - return new_op; + new_node = create_lea_from_address(dbgi, new_block, &addr); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + return new_node; } /* test if we can use source address mode */ - memset(&am, 0, sizeof(am)); - new_op1 = NULL; - if(use_source_address_mode(src_block, op2, op1)) { - build_address(&am, op2); - new_op1 = be_transform_node(op1); - } else if(use_source_address_mode(src_block, op1, op2)) { - build_address(&am, op1); - new_op1 = be_transform_node(op2); - } + match_arguments(&am, block, op1, op2, NULL, match_commutative + | match_mode_neutral | match_am | match_immediate | match_try_am); + /* construct an Add with source address mode */ - if(new_op1 != NULL) { + if (am.op_type == ia32_AddrModeS) { ia32_address_t *am_addr = &am.addr; - new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base, am_addr->index, - am_addr->mem, new_op1, noreg); - set_address(new_op, am_addr); - set_ia32_op_type(new_op, ia32_AddrModeS); - set_ia32_ls_mode(new_op, am.ls_mode); - set_ia32_commutative(new_op); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); + new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base, + am_addr->index, am_addr->mem, am.new_op1, + am.new_op2); + set_am_attributes(new_node, &am); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - new_op = fix_mem_proj(new_op, &am); + new_node = fix_mem_proj(new_node, &am); - return new_op; + return new_node; } /* otherwise construct a lea */ - new_op = create_lea_from_address(dbgi, block, &addr); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); - return new_op; + new_node = create_lea_from_address(dbgi, new_block, &addr); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + return new_node; } /** @@ -952,18 +1154,20 @@ static ir_node *gen_Mul(ir_node *node) { ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) - return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul); + if (ia32_cg_config.use_sse2) + return gen_binop(node, op1, op2, new_rd_ia32_xMul, + match_commutative | match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, + match_commutative | match_am); } - /* - for the lower 32bit of the result it doesn't matter whether we use - signed or unsigned multiplication so we use IMul as it has fewer - constraints - */ - return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1); + /* for the lower 32bit of the result it doesn't matter whether we use + * signed or unsigned multiplication so we use IMul as it has fewer + * constraints */ + return gen_binop(node, op1, op2, new_rd_ia32_IMul, + match_commutative | match_am | match_mode_neutral | + match_immediate | match_am_and_immediates); } /** @@ -973,32 +1177,50 @@ static ir_node *gen_Mul(ir_node *node) { * * @return the created ia32 Mulh node */ -static ir_node *gen_Mulh(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op1 = get_irn_n(node, 0); - ir_node *new_op1 = be_transform_node(op1); - ir_node *op2 = get_irn_n(node, 1); - ir_node *new_op2 = be_transform_node(op2); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_mode *mode = get_irn_mode(node); - ir_node *proj_EDX, *res; +static ir_node *gen_Mulh(ir_node *node) +{ + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_node *op1 = get_Mulh_left(node); + ir_node *op2 = get_Mulh_right(node); + ir_node *proj_res_high; + ir_node *new_node; + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; assert(!mode_is_float(mode) && "Mulh with float not supported"); + assert(get_mode_size_bits(mode) == 32); + + match_arguments(&am, block, op1, op2, NULL, match_commutative | match_am); + if (mode_is_signed(mode)) { - res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(), - new_op1, new_op2); + new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2); } else { - res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1, - new_op2); + new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2); } - set_ia32_commutative(res); + set_am_attributes(new_node, &am); + /* we can't use source address mode anymore when using immediates */ + if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) + set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + + assert(get_irn_mode(new_node) == mode_T); - proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX); + fix_mem_proj(new_node, &am); - return proj_EDX; + assert(pn_ia32_IMul1OP_res_high == pn_ia32_Mul_res_high); + proj_res_high = new_rd_Proj(dbgi, irg, block, new_node, + mode_Iu, pn_ia32_IMul1OP_res_high); + + return proj_res_high; } @@ -1036,7 +1258,9 @@ static ir_node *gen_And(ir_node *node) { } } - return gen_binop(node, op1, op2, new_rd_ia32_And, 1); + return gen_binop(node, op1, op2, new_rd_ia32_And, + match_commutative | match_mode_neutral | match_am + | match_immediate); } @@ -1051,7 +1275,8 @@ static ir_node *gen_Or(ir_node *node) { ir_node *op2 = get_Or_right(node); assert (! mode_is_float(get_irn_mode(node))); - return gen_binop(node, op1, op2, new_rd_ia32_Or, 1); + return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative + | match_mode_neutral | match_am | match_immediate); } @@ -1066,7 +1291,8 @@ static ir_node *gen_Eor(ir_node *node) { ir_node *op2 = get_Eor_right(node); assert(! mode_is_float(get_irn_mode(node))); - return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1); + return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative + | match_mode_neutral | match_am | match_immediate); } @@ -1081,10 +1307,11 @@ static ir_node *gen_Sub(ir_node *node) { ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) - return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub); + if (ia32_cg_config.use_sse2) + return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am); else - return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, + match_am); } if(is_Const(op2)) { @@ -1092,114 +1319,110 @@ static ir_node *gen_Sub(ir_node *node) { node); } - return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0); + return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral + | match_am | match_immediate); } - - /** * Generates an ia32 DivMod with additional infrastructure for the * register allocator if needed. - * - * @param dividend -no comment- :) - * @param divisor -no comment- :) - * @param dm_flav flavour_Div/Mod/DivMod - * @return The created ia32 DivMod node */ -static ir_node *generate_DivMod(ir_node *node, ir_node *dividend, - ir_node *divisor, ia32_op_flavour_t dm_flav) +static ir_node *create_Div(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_dividend = be_transform_node(dividend); - ir_node *new_divisor = be_transform_node(divisor); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *res, *proj_div, *proj_mod; + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *mem; + ir_node *new_mem; + ir_node *op1; + ir_node *op2; + ir_node *new_node; + ir_mode *mode; ir_node *sign_extension; - ir_node *mem, *new_mem; - int has_exc; - - proj_div = proj_mod = NULL; - has_exc = 0; - switch (dm_flav) { - case flavour_Div: - mem = get_Div_mem(node); - mode = get_Div_resmode(node); - proj_div = be_get_Proj_for_pn(node, pn_Div_res); - has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL; - break; - case flavour_Mod: - mem = get_Mod_mem(node); - mode = get_Mod_resmode(node); - proj_mod = be_get_Proj_for_pn(node, pn_Mod_res); - has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL; - break; - case flavour_DivMod: - mem = get_DivMod_mem(node); - mode = get_DivMod_resmode(node); - proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div); - proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod); - has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL; - break; - default: - panic("invalid divmod flavour!"); + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; + + /* the upper bits have random contents for smaller modes */ + switch (get_irn_opcode(node)) { + case iro_Div: + op1 = get_Div_left(node); + op2 = get_Div_right(node); + mem = get_Div_mem(node); + mode = get_Div_resmode(node); + break; + case iro_Mod: + op1 = get_Mod_left(node); + op2 = get_Mod_right(node); + mem = get_Mod_mem(node); + mode = get_Mod_resmode(node); + break; + case iro_DivMod: + op1 = get_DivMod_left(node); + op2 = get_DivMod_right(node); + mem = get_DivMod_mem(node); + mode = get_DivMod_resmode(node); + break; + default: + panic("invalid divmod node %+F", node); } - new_mem = be_transform_node(mem); - if (mode_is_signed(mode)) { - /* in signed mode, we need to sign extend the dividend */ - ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block); - add_irn_dep(produceval, get_irg_frame(irg)); - sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend, - produceval); + match_arguments(&am, block, op1, op2, NULL, match_am); + + /* Beware: We don't need a Sync, if the memory predecessor of the Div node + is the memory of the consumed address. We can have only the second op as address + in Div nodes, so check only op2. */ + if(!is_NoMem(mem) && skip_Proj(mem) != skip_Proj(op2)) { + new_mem = be_transform_node(mem); + if(!is_NoMem(addr->mem)) { + ir_node *in[2]; + in[0] = new_mem; + in[1] = addr->mem; + new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in); + } } else { - sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0); - add_irn_dep(sign_extension, get_irg_frame(irg)); + new_mem = addr->mem; } if (mode_is_signed(mode)) { - res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem, - new_dividend, sign_extension, new_divisor, dm_flav); + ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block); + add_irn_dep(produceval, get_irg_frame(irg)); + sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1, + produceval); + + new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base, + addr->index, new_mem, am.new_op1, + sign_extension, am.new_op2); } else { - res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend, - sign_extension, new_divisor, dm_flav); + sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0); + add_irn_dep(sign_extension, get_irg_frame(irg)); + + new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base, + addr->index, new_mem, am.new_op1, + sign_extension, am.new_op2); } - set_ia32_exc_label(res, has_exc); - set_irn_pinned(res, get_irn_pinned(node)); + set_irn_pinned(new_node, get_irn_pinned(node)); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + set_am_attributes(new_node, &am); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + new_node = fix_mem_proj(new_node, &am); + + return new_node; } -/** - * Wrapper for generate_DivMod. Sets flavour_Mod. - * - */ static ir_node *gen_Mod(ir_node *node) { - return generate_DivMod(node, get_Mod_left(node), - get_Mod_right(node), flavour_Mod); + return create_Div(node); } -/** - * Wrapper for generate_DivMod. Sets flavour_Div. - * - */ static ir_node *gen_Div(ir_node *node) { - return generate_DivMod(node, get_Div_left(node), - get_Div_right(node), flavour_Div); + return create_Div(node); } -/** - * Wrapper for generate_DivMod. Sets flavour_DivMod. - */ static ir_node *gen_DivMod(ir_node *node) { - return generate_DivMod(node, get_DivMod_left(node), - get_DivMod_right(node), flavour_DivMod); + return create_Div(node); } @@ -1209,29 +1432,16 @@ static ir_node *gen_DivMod(ir_node *node) { * * @return The created ia32 xDiv node */ -static ir_node *gen_Quot(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); +static ir_node *gen_Quot(ir_node *node) +{ ir_node *op1 = get_Quot_left(node); - ir_node *new_op1 = be_transform_node(op1); ir_node *op2 = get_Quot_right(node); - ir_node *new_op2 = be_transform_node(op2); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_rd_NoMem(current_ir_graph); - ir_node *new_op; - if (USE_SSE2(env_cg)) { - ir_mode *mode = get_irn_mode(op1); - new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, nomem, new_op1, - new_op2); - set_ia32_ls_mode(new_op, mode); + if (ia32_cg_config.use_sse2) { + return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am); } else { - new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, nomem, new_op1, - new_op2, get_fpcw()); + return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am); } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); - return new_op; } @@ -1241,41 +1451,23 @@ static ir_node *gen_Quot(ir_node *node) { * @return The created ia32 Shl node */ static ir_node *gen_Shl(ir_node *node) { + ir_node *left = get_Shl_left(node); ir_node *right = get_Shl_right(node); - /* test whether we can build a lea */ - if(is_Const(right)) { - tarval *tv = get_Const_tarval(right); - if(tarval_is_long(tv)) { - long val = get_tarval_long(tv); - if(val >= 0 && val <= 3) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *base = ia32_new_NoReg_gp(env_cg); - ir_node *index = be_transform_node(get_Shl_left(node)); - ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index); - set_ia32_am_scale(res, val); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); - return res; - } - } - } - - return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node), - new_rd_ia32_Shl); + return gen_shift_binop(node, left, right, new_rd_ia32_Shl, + match_mode_neutral | match_immediate); } - - /** * Creates an ia32 Shr. * * @return The created ia32 Shr node */ static ir_node *gen_Shr(ir_node *node) { - return gen_shift_binop(node, get_Shr_left(node), - get_Shr_right(node), new_rd_ia32_Shr); + ir_node *left = get_Shr_left(node); + ir_node *right = get_Shr_right(node); + + return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate); } @@ -1289,6 +1481,7 @@ static ir_node *gen_Shrs(ir_node *node) { ir_node *left = get_Shrs_left(node); ir_node *right = get_Shrs_right(node); ir_mode *mode = get_irn_mode(node); + if(is_Const(right) && mode == mode_Is) { tarval *tv = get_Const_tarval(right); long val = get_tarval_long(tv); @@ -1336,7 +1529,7 @@ static ir_node *gen_Shrs(ir_node *node) { } } - return gen_shift_binop(node, left, right, new_rd_ia32_Sar); + return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate); } @@ -1348,9 +1541,8 @@ static ir_node *gen_Shrs(ir_node *node) { * @param op2 The second operator * @return The created ia32 RotL node */ -static ir_node *gen_RotL(ir_node *node, - ir_node *op1, ir_node *op2) { - return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol); +static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) { + return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate); } @@ -1364,9 +1556,8 @@ static ir_node *gen_RotL(ir_node *node, * @param op2 The second operator * @return The created ia32 RotR node */ -static ir_node *gen_RotR(ir_node *node, ir_node *op1, - ir_node *op2) { - return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror); +static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) { + return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate); } @@ -1396,7 +1587,8 @@ static ir_node *gen_Rot(ir_node *node) { if (get_irn_op(left) == op_Minus && tarval_is_long(tv) && - get_tarval_long(tv) == bits) + get_tarval_long(tv) == bits && + bits == 32) { DB((dbg, LEVEL_1, "RotL into RotR ... ")); rotate = gen_RotR(node, op1, get_Minus_op(left)); @@ -1416,77 +1608,48 @@ static ir_node *gen_Rot(ir_node *node) { /** * Transforms a Minus node. * - * @param op The Minus operand * @return The created ia32 Minus node */ -ir_node *gen_Minus_ex(ir_node *node, ir_node *op) { +static ir_node *gen_Minus(ir_node *node) +{ + ir_node *op = get_Minus_op(node); ir_node *block = be_transform_node(get_nodes_block(node)); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_mode *mode = get_irn_mode(node); ir_entity *ent; - ir_node *res; - int size; + ir_node *new_node; + int size; if (mode_is_float(mode)) { ir_node *new_op = be_transform_node(op); - if (USE_SSE2(env_cg)) { - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg); - ir_node *nomem = new_rd_NoMem(irg); + if (ia32_cg_config.use_sse2) { + /* TODO: non-optimal... if we have many xXors, then we should + * rather create a load for the const and use that instead of + * several AM nodes... */ + ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); + ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg); + ir_node *nomem = new_rd_NoMem(irg); - res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, - new_op, noreg_fp); + new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, + nomem, new_op, noreg_xmm); size = get_mode_size_bits(mode); ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN); - set_ia32_am_sc(res, ent); - set_ia32_op_type(res, ia32_AddrModeS); - set_ia32_ls_mode(res, mode); + set_ia32_am_sc(new_node, ent); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode); } else { - res = new_rd_ia32_vfchs(dbgi, irg, block, new_op); + new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op); } } else { - res = gen_unop(node, op, new_rd_ia32_Neg); + new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral); } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); - - return res; -} - -/** - * Transforms a Minus node. - * - * @return The created ia32 Minus node - */ -static ir_node *gen_Minus(ir_node *node) { - return gen_Minus_ex(node, get_Minus_op(node)); -} - -static ir_node *create_Immediate_from_int(int val) -{ - ir_graph *irg = current_ir_graph; - ir_node *start_block = get_irg_start_block(irg); - ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val); - arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]); - - return immediate; -} - -static ir_node *gen_bin_Not(ir_node *node) -{ - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op = get_Not_op(node); - ir_node *new_op = be_transform_node(op); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); - ir_node *one = create_Immediate_from_int(1); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, nomem, new_op, one); + return new_node; } /** @@ -1496,14 +1659,11 @@ static ir_node *gen_bin_Not(ir_node *node) */ static ir_node *gen_Not(ir_node *node) { ir_node *op = get_Not_op(node); - ir_mode *mode = get_irn_mode(node); - - if(mode == mode_b) { - return gen_bin_Not(node); - } + assert(get_irn_mode(node) != mode_b); /* should be lowered already */ assert (! mode_is_float(get_irn_mode(node))); - return gen_unop(node, op, new_rd_ia32_Not); + + return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral); } @@ -1513,58 +1673,100 @@ static ir_node *gen_Not(ir_node *node) { * * @return The created ia32 Abs node */ -static ir_node *gen_Abs(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op = get_Abs_op(node); - ir_node *new_op = be_transform_node(op); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg); - ir_node *nomem = new_NoMem(); - ir_node *res; - int size; +static ir_node *gen_Abs(ir_node *node) +{ + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *op = get_Abs_op(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_mode *mode = get_irn_mode(node); + ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); + ir_node *nomem = new_NoMem(); + ir_node *new_op; + ir_node *new_node; + int size; ir_entity *ent; if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) { - res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp); + new_op = be_transform_node(op); + + if (ia32_cg_config.use_sse2) { + ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg); + new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp, + nomem, new_op, noreg_fp); size = get_mode_size_bits(mode); ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS); - set_ia32_am_sc(res, ent); + set_ia32_am_sc(new_node, ent); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - set_ia32_op_type(res, ia32_AddrModeS); - set_ia32_ls_mode(res, mode); - } - else { - res = new_rd_ia32_vfabs(dbgi, irg, block, new_op); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode); + } else { + new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); } } else { - ir_node *xor; - ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block); - ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op, - pval); + ir_node *xor, *pval, *sign_extension; + + if (get_mode_size_bits(mode) == 32) { + new_op = be_transform_node(op); + } else { + new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node); + } + + pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block); + sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, + new_op, pval); add_irn_dep(pval, get_irg_frame(irg)); - SET_IA32_ORIG_NODE(sign_extension, - ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node)); - xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op, - sign_extension); + xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp, + nomem, new_op, sign_extension); SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node)); - res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor, - sign_extension); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp, + nomem, xor, sign_extension); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); } - return res; + return new_node; +} + +static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) +{ + ir_graph *irg = current_ir_graph; + ir_node *flags; + ir_node *new_op; + ir_node *noreg; + ir_node *nomem; + ir_node *new_block; + dbg_info *dbgi; + + /* we have a Cmp as input */ + if(is_Proj(node)) { + ir_node *pred = get_Proj_pred(node); + if(is_Cmp(pred)) { + flags = be_transform_node(pred); + *pnc_out = get_Proj_proj(node); + return flags; + } + } + + /* a mode_b value, we have to compare it against 0 */ + dbgi = get_irn_dbg_info(node); + new_block = be_transform_node(get_nodes_block(node)); + new_op = be_transform_node(node); + noreg = ia32_new_NoReg_gp(env_cg); + nomem = new_NoMem(); + flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem, + new_op, new_op, 0, 0); + *pnc_out = pn_Cmp_Lg; + return flags; } /** @@ -1585,12 +1787,12 @@ static ir_node *gen_Load(ir_node *node) { ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_mode *mode = get_Load_mode(node); ir_mode *res_mode; - ir_node *new_op; + ir_node *new_node; ia32_address_t addr; /* construct load address */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, ptr, 0); + ia32_create_address_mode(&addr, ptr, /*force=*/0); base = addr.base; index = addr.index; @@ -1607,49 +1809,51 @@ static ir_node *gen_Load(ir_node *node) { } if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) { - new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem, - mode); + if (ia32_cg_config.use_sse2) { + new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem, + mode); res_mode = mode_xmm; } else { - new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem, + new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem, mode); res_mode = mode_vfp; } } else { - if(mode == mode_b) - mode = mode_Iu; + assert(mode != mode_b); /* create a conv node with address mode for smaller modes */ if(get_mode_size_bits(mode) < 32) { - new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, new_mem, - noreg, mode); + new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, + new_mem, noreg, mode); } else { - new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem); + new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem); } res_mode = mode_Iu; } - set_irn_pinned(new_op, get_irn_pinned(node)); - set_ia32_op_type(new_op, ia32_AddrModeS); - set_ia32_ls_mode(new_op, mode); - set_address(new_op, &addr); + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeS); + set_ia32_ls_mode(new_node, mode); + set_address(new_node, &addr); + + if(get_irn_pinned(node) == op_pin_state_floats) { + add_ia32_flags(new_node, arch_irn_flags_rematerializable); + } /* make sure we are scheduled behind the initial IncSP/Barrier * to avoid spills being placed before it */ if (block == get_irg_start_block(irg)) { - add_irn_dep(new_op, get_irg_frame(irg)); + add_irn_dep(new_node, get_irg_frame(irg)); } - set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return new_op; + return new_node; } static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem, - ir_node *ptr, ir_mode *mode, ir_node *other) + ir_node *ptr, ir_node *other) { ir_node *load; @@ -1678,30 +1882,35 @@ static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem, && heights_reachable_in_block(heights, other, load)) return 0; - assert(get_Load_mode(load) == mode); - return 1; } static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, ir_node *mem, ir_node *ptr, ir_mode *mode, - construct_binop_dest_func *func, int commutative) + construct_binop_dest_func *func, + construct_binop_dest_func *func8bit, + match_flags_t flags) { - ir_node *src_block = get_nodes_block(node); - ir_node *block; - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); + ir_node *src_block = get_nodes_block(node); + ir_node *block; + ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); ir_graph *irg = current_ir_graph; dbg_info *dbgi; - ir_node *new_node; - ir_node *new_op; + ir_node *new_node; + ir_node *new_op; + int commutative; ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; + ia32_address_t *addr = &am.addr; memset(&am, 0, sizeof(am)); - if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) { + assert(flags & match_dest_am); + assert(flags & match_immediate); /* there is no destam node without... */ + commutative = (flags & match_commutative) != 0; + + if(use_dest_am(src_block, op1, mem, ptr, op2)) { build_address(&am, op1); new_op = create_immediate_or_transform(op2, 0); - } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) { + } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) { build_address(&am, op2); new_op = create_immediate_or_transform(op1, 0); } else { @@ -1715,9 +1924,15 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, if(addr->mem == NULL) addr->mem = new_NoMem(); - dbgi = get_irn_dbg_info(node); - block = be_transform_node(src_block); - new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem, new_op); + dbgi = get_irn_dbg_info(node); + block = be_transform_node(src_block); + if(get_mode_size_bits(mode) == 8) { + new_node = func8bit(dbgi, irg, block, addr->base, addr->index, + addr->mem, new_op); + } else { + new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem, + new_op); + } set_address(new_node, addr); set_ia32_op_type(new_node, ia32_AddrModeD); set_ia32_ls_mode(new_node, mode); @@ -1730,28 +1945,20 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, ir_node *ptr, ir_mode *mode, construct_unop_dest_func *func) { + ir_graph *irg = current_ir_graph; ir_node *src_block = get_nodes_block(node); ir_node *block; - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_graph *irg = current_ir_graph; dbg_info *dbgi; ir_node *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; memset(&am, 0, sizeof(am)); - if(!use_dest_am(src_block, op, mem, ptr, mode, NULL)) + if(!use_dest_am(src_block, op, mem, ptr, NULL)) return NULL; build_address(&am, op); - if(addr->base == NULL) - addr->base = noreg_gp; - if(addr->index == NULL) - addr->index = noreg_gp; - if(addr->mem == NULL) - addr->mem = new_NoMem(); - dbgi = get_irn_dbg_info(node); block = be_transform_node(src_block); new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem); @@ -1763,11 +1970,58 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, return new_node; } +static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) { + ir_mode *mode = get_irn_mode(node); + ir_node *psi_true = get_Psi_val(node, 0); + ir_node *psi_default = get_Psi_default(node); + ir_graph *irg; + ir_node *cond; + ir_node *new_mem; + dbg_info *dbgi; + ir_node *block; + ir_node *new_block; + ir_node *flags; + ir_node *new_node; + int negated; + pn_Cmp pnc; + ia32_address_t addr; + + if(get_mode_size_bits(mode) != 8) + return NULL; + + if(is_Const_1(psi_true) && is_Const_0(psi_default)) { + negated = 0; + } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) { + negated = 1; + } else { + return NULL; + } + + build_address_ptr(&addr, ptr, mem); + + irg = current_ir_graph; + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + new_block = be_transform_node(block); + cond = get_Psi_cond(node, 0); + flags = get_flags_node(cond, &pnc); + new_mem = be_transform_node(mem); + new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base, + addr.index, addr.mem, flags, pnc, negated); + set_address(new_node, &addr); + set_ia32_op_type(new_node, ia32_AddrModeD); + set_ia32_ls_mode(new_node, mode); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + + return new_node; +} + static ir_node *try_create_dest_am(ir_node *node) { - ir_node *val = get_Store_value(node); - ir_node *mem = get_Store_mem(node); - ir_node *ptr = get_Store_ptr(node); - ir_mode *mode = get_irn_mode(val); + ir_node *val = get_Store_value(node); + ir_node *mem = get_Store_mem(node); + ir_node *ptr = get_Store_ptr(node); + ir_mode *mode = get_irn_mode(val); + unsigned bits = get_mode_size_bits(mode); ir_node *op1; ir_node *op2; ir_node *new_node; @@ -1776,8 +2030,24 @@ static ir_node *try_create_dest_am(ir_node *node) { if(!mode_needs_gp_reg(mode)) return NULL; - /* store must be the only user of the val node */ - if(get_irn_n_edges(val) > 1) + while(1) { + /* store must be the only user of the val node */ + if(get_irn_n_edges(val) > 1) + return NULL; + /* skip pointless convs */ + if(is_Conv(val)) { + ir_node *conv_op = get_Conv_op(val); + ir_mode *pred_mode = get_irn_mode(conv_op); + if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) { + val = conv_op; + continue; + } + } + break; + } + + /* value must be in the same block */ + if(get_nodes_block(node) != get_nodes_block(val)) return NULL; switch(get_irn_opcode(val)) { @@ -1794,65 +2064,85 @@ static ir_node *try_create_dest_am(ir_node *node) { break; } new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_AddMem, 1); + new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, + match_dest_am | match_commutative | + match_immediate); break; case iro_Sub: op1 = get_Sub_left(val); op2 = get_Sub_right(val); + if(is_Const(op2)) { + ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C" + "found\n"); + } new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_SubMem, 0); + new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, + match_dest_am | match_immediate | + match_immediate); break; case iro_And: op1 = get_And_left(val); op2 = get_And_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_AndMem, 1); + new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, + match_dest_am | match_commutative | + match_immediate); break; case iro_Or: op1 = get_Or_left(val); op2 = get_Or_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_OrMem, 1); + new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, + match_dest_am | match_commutative | + match_immediate); break; case iro_Eor: op1 = get_Eor_left(val); op2 = get_Eor_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_XorMem, 1); + new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, + match_dest_am | match_commutative | + match_immediate); break; case iro_Shl: op1 = get_Shl_left(val); op2 = get_Shl_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_ShlMem, 0); + new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, + match_dest_am | match_immediate); break; case iro_Shr: op1 = get_Shr_left(val); op2 = get_Shr_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_ShrMem, 0); + new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, + match_dest_am | match_immediate); break; case iro_Shrs: op1 = get_Shrs_left(val); op2 = get_Shrs_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_SarMem, 0); + new_rd_ia32_SarMem, new_rd_ia32_SarMem, + match_dest_am | match_immediate); break; case iro_Rot: op1 = get_Rot_left(val); op2 = get_Rot_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, - new_rd_ia32_RolMem, 0); + new_rd_ia32_RolMem, new_rd_ia32_RolMem, + match_dest_am | match_immediate); break; /* TODO: match ROR patterns... */ + case iro_Psi: + new_node = try_create_SetMem(val, ptr, mem); + break; case iro_Minus: op1 = get_Minus_op(val); new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem); break; case iro_Not: - /* TODO this would be ^ 1 with DestAM */ - if(mode == mode_b) - return NULL; + /* should be lowered already */ + assert(mode != mode_b); op1 = get_Not_op(val); new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem); break; @@ -1860,146 +2150,139 @@ static ir_node *try_create_dest_am(ir_node *node) { return NULL; } + if(new_node != NULL) { + if(get_irn_pinned(new_node) != op_pin_state_pinned && + get_irn_pinned(node) == op_pin_state_pinned) { + set_irn_pinned(new_node, op_pin_state_pinned); + } + } + return new_node; } +static int is_float_to_int32_conv(const ir_node *node) +{ + ir_mode *mode = get_irn_mode(node); + ir_node *conv_op; + ir_mode *conv_mode; + + if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode)) + return 0; + + if(!is_Conv(node)) + return 0; + conv_op = get_Conv_op(node); + conv_mode = get_irn_mode(conv_op); + + if(!mode_is_float(conv_mode)) + return 0; + + return 1; +} + /** * Transforms a Store. * * @return the created ia32 Store node */ -static ir_node *gen_Store(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *ptr = get_Store_ptr(node); - ir_node *base; - ir_node *index; - ir_node *val = get_Store_value(node); +static ir_node *gen_Store(ir_node *node) +{ + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *ptr = get_Store_ptr(node); + ir_node *val = get_Store_value(node); + ir_node *mem = get_Store_mem(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + ir_mode *mode = get_irn_mode(val); ir_node *new_val; - ir_node *mem = get_Store_mem(node); - ir_node *new_mem = be_transform_node(mem); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_mode *mode = get_irn_mode(val); - ir_node *new_op; + ir_node *new_node; ia32_address_t addr; /* check for destination address mode */ - new_op = try_create_dest_am(node); - if(new_op != NULL) - return new_op; + new_node = try_create_dest_am(node); + if(new_node != NULL) + return new_node; /* construct store address */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, ptr, 0); - base = addr.base; - index = addr.index; + ia32_create_address_mode(&addr, ptr, /*force=*/0); - if(base == NULL) { - base = noreg; + if(addr.base == NULL) { + addr.base = noreg; } else { - base = be_transform_node(base); + addr.base = be_transform_node(addr.base); } - if(index == NULL) { - index = noreg; + if(addr.index == NULL) { + addr.index = noreg; } else { - index = be_transform_node(index); + addr.index = be_transform_node(addr.index); } + addr.mem = be_transform_node(mem); if (mode_is_float(mode)) { + /* convs (and strict-convs) before stores are unnecessary if the mode + is the same */ + while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) { + val = get_Conv_op(val); + } new_val = be_transform_node(val); - if (USE_SSE2(env_cg)) { - new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem, - new_val); + if (ia32_cg_config.use_sse2) { + new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base, + addr.index, addr.mem, new_val); } else { - new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val, - mode); + new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base, + addr.index, addr.mem, new_val, mode); } + } else if(is_float_to_int32_conv(val)) { + ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); + val = get_Conv_op(val); + + /* convs (and strict-convs) before stores are unnecessary if the mode + is the same */ + while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) { + val = get_Conv_op(val); + } + new_val = be_transform_node(val); + + new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base, + addr.index, addr.mem, new_val, trunc_mode); } else { new_val = create_immediate_or_transform(val, 0); - if(mode == mode_b) - mode = mode_Iu; + assert(mode != mode_b); if (get_mode_size_bits(mode) == 8) { - new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem, - new_val); + new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base, + addr.index, addr.mem, new_val); } else { - new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem, - new_val); + new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base, + addr.index, addr.mem, new_val); } } - set_irn_pinned(new_op, get_irn_pinned(node)); - set_ia32_op_type(new_op, ia32_AddrModeD); - set_ia32_ls_mode(new_op, mode); - - set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL); - set_address(new_op, &addr); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); - - return new_op; -} - -static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc, - ir_node *cmp_left, ir_node *cmp_right, - int use_am) -{ - ir_node *arg_left; - ir_node *arg_right; - ir_node *res; - ir_mode *mode; - long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned; - ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; - - if(cmp_right != NULL && !is_Const_0(cmp_right)) - return NULL; - - if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) { - mode = get_irn_mode(cmp_left); - arg_left = get_And_left(cmp_left); - arg_right = get_And_right(cmp_left); - } else { - mode = get_irn_mode(cmp_left); - arg_left = cmp_left; - arg_right = cmp_left; - } - - if(mode == mode_b) - mode = mode_Iu; - - assert(get_mode_size_bits(mode) <= 32); - match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am, 1); - if(am.flipped) - pnc = get_inversed_pnc(pnc); - - if(get_mode_size_bits(mode) == 8) { - res = new_rd_ia32_TestJmp8Bit(dbgi, current_ir_graph, block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2, pnc); - } else { - res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, addr->base, - addr->index, addr->mem, am.new_op1, am.new_op2, - pnc); - } - set_am_attributes(res, &am); - set_ia32_ls_mode(res, mode); + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeD); + set_ia32_ls_mode(new_node, mode); - res = fix_mem_proj(res, &am); + set_address(new_node, &addr); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + return new_node; } static ir_node *create_Switch(ir_node *node) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *sel = get_Cond_selector(node); - ir_node *new_sel = be_transform_node(sel); - ir_node *res; - int switch_min = INT_MAX; + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *sel = get_Cond_selector(node); + ir_node *new_sel = be_transform_node(sel); + int switch_min = INT_MAX; + int switch_max = INT_MIN; + long default_pn = get_Cond_defaultProj(node); + ir_node *new_node; const ir_edge_t *edge; assert(get_mode_size_bits(get_irn_mode(sel)) == 32); @@ -2007,9 +2290,18 @@ static ir_node *create_Switch(ir_node *node) /* determine the smallest switch case value */ foreach_out_edge(node, edge) { ir_node *proj = get_edge_src_irn(edge); - int pn = get_Proj_proj(proj); + long pn = get_Proj_proj(proj); + if(pn == default_pn) + continue; + if(pn < switch_min) switch_min = pn; + if(pn > switch_max) + switch_max = pn; + } + + if((unsigned) (switch_max - switch_min) > 256000) { + panic("Size of switch %+F bigger than 256000", node); } if (switch_min != 0) { @@ -2023,106 +2315,34 @@ static ir_node *create_Switch(ir_node *node) SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node)); } - res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel); - set_ia32_pncode(res, get_Cond_defaultProj(node)); - - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, default_pn); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + return new_node; } -/** - * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp - * - * @return The transformed node. - */ static ir_node *gen_Cond(ir_node *node) { - ir_node *src_block = get_nodes_block(node); - ir_node *block = be_transform_node(src_block); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *sel = get_Cond_selector(node); - ir_mode *sel_mode = get_irn_mode(sel); - ir_node *res = NULL; - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); - ir_node *cmp; - ir_node *cmp_a; - ir_node *cmp_b; - ir_node *new_cmp_a; - ir_node *new_cmp_b; - ir_mode *cmp_mode; - long pnc; - int use_am; + ir_mode *sel_mode = get_irn_mode(sel); + ir_node *flags = NULL; + ir_node *new_node; + pn_Cmp pnc; if (sel_mode != mode_b) { return create_Switch(node); } - if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) { - /* it's some mode_b value but not a direct comparison -> create a - * testjmp */ - res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL, 1); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); - return res; - } - - /* address mode makes only sense when we're the only user of the cmp */ - use_am = get_irn_n_edges(node) <= 1; - - cmp = get_Proj_pred(sel); - cmp_a = get_Cmp_left(cmp); - cmp_b = get_Cmp_right(cmp); - cmp_mode = get_irn_mode(cmp_a); - pnc = get_Proj_proj(sel); - if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) { - pnc |= ia32_pn_Cmp_Unsigned; - } - - if(mode_needs_gp_reg(cmp_mode)) { - res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b, use_am); - if(res != NULL) { - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); - return res; - } - } - - if (mode_is_float(cmp_mode)) { - new_cmp_a = be_transform_node(cmp_a); - new_cmp_b = create_immediate_or_transform(cmp_b, 0); - if (USE_SSE2(env_cg)) { - res = new_rd_ia32_xCmpJmp(dbgi, irg, block, noreg, noreg, nomem, cmp_a, - cmp_b, pnc); - set_ia32_commutative(res); - set_ia32_ls_mode(res, cmp_mode); - } else { - res = new_rd_ia32_vfCmpJmp(dbgi, irg, block, cmp_a, cmp_b, pnc); - set_ia32_commutative(res); - } - } else { - ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; - match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1, use_am, 1); - if(am.flipped) - pnc = get_inversed_pnc(pnc); - - if(get_mode_size_bits(cmp_mode) == 8) { - res = new_rd_ia32_CmpJmp8Bit(dbgi, irg, block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, pnc); - } else { - res = new_rd_ia32_CmpJmp(dbgi, irg, block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, pnc); - } - set_am_attributes(res, &am); - assert(cmp_mode != NULL); - set_ia32_ls_mode(res, cmp_mode); - - res = fix_mem_proj(res, &am); - } + /* we get flags from a cmp */ + flags = get_flags_node(sel, &pnc); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + return new_node; } @@ -2153,14 +2373,15 @@ static ir_node *gen_CopyB(ir_node *node) { size >>= 2; res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size); - add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi)); + add_irn_dep(res, get_irg_frame(irg)); - res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem); - /* we misuse the pncode field for the copyb size */ - set_ia32_pncode(res, rem); + res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem); } else { - res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem); - set_ia32_pncode(res, size); + if(size == 0) { + ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n", + node); + } + res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size); } SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); @@ -2168,239 +2389,306 @@ static ir_node *gen_CopyB(ir_node *node) { return res; } -static -ir_node *gen_be_Copy(ir_node *node) +static ir_node *gen_be_Copy(ir_node *node) { - ir_node *result = be_duplicate_node(node); - ir_mode *mode = get_irn_mode(result); + ir_node *new_node = be_duplicate_node(node); + ir_mode *mode = get_irn_mode(new_node); if (mode_needs_gp_reg(mode)) { - set_irn_mode(result, mode_Iu); + set_irn_mode(new_node, mode_Iu); } - return result; + return new_node; } - -static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right, - dbg_info *dbgi, ir_node *block, int use_am) +static ir_node *create_Fucom(ir_node *node) { ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_rd_NoMem(irg); - ir_mode *mode; - ir_node *arg_left; - ir_node *arg_right; - ir_node *res; - ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; + ir_node *left = get_Cmp_left(node); + ir_node *new_left = be_transform_node(left); + ir_node *right = get_Cmp_right(node); + ir_node *new_right; + ir_node *new_node; - /* can we use a test instruction? */ - if(cmp_right == NULL || is_Const_0(cmp_right)) { - long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned; - if(is_And(cmp_left) && - (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) { - ir_node *and_left = get_And_left(cmp_left); - ir_node *and_right = get_And_right(cmp_left); - - mode = get_irn_mode(and_left); - arg_left = and_left; - arg_right = and_right; + if(ia32_cg_config.use_fucomi) { + new_right = be_transform_node(right); + new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, + new_right, 0); + set_ia32_commutative(new_node); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + } else { + if(ia32_cg_config.use_ftst && is_Const_0(right)) { + new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, + 0); } else { - mode = get_irn_mode(cmp_left); - arg_left = cmp_left; - arg_right = cmp_left; + new_right = be_transform_node(right); + new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left, + new_right, 0); } - assert(get_mode_size_bits(mode) <= 32); + set_ia32_commutative(new_node); - match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am, 1); - if(am.flipped) - pnc = get_inversed_pnc(pnc); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - if(get_mode_size_bits(mode) == 8) { - res = new_rd_ia32_TestSet8Bit(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, am.new_op1, - am.new_op2, pnc); - } else { - res = new_rd_ia32_TestSet(dbgi, irg, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, pnc); - } - set_am_attributes(res, &am); - set_ia32_ls_mode(res, mode); + new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + } + + return new_node; +} + +static ir_node *create_Ucomi(ir_node *node) +{ + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *src_block = get_nodes_block(node); + ir_node *new_block = be_transform_node(src_block); + ir_node *left = get_Cmp_left(node); + ir_node *right = get_Cmp_right(node); + ir_node *new_node; + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; - res = fix_mem_proj(res, &am); + match_arguments(&am, src_block, left, right, NULL, + match_commutative | match_am); - res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, nomem, - res, mode_Bu); + new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index, + addr->mem, am.new_op1, am.new_op2, + am.ins_permuted); + set_am_attributes(new_node, &am); - return res; + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + + new_node = fix_mem_proj(new_node, &am); + + return new_node; +} + +/** + * helper function: checks wether all Cmp projs are Lg or Eq which is needed + * to fold an and into a test node + */ +static int can_fold_test_and(ir_node *node) +{ + const ir_edge_t *edge; + + /** we can only have eq and lg projs */ + foreach_out_edge(node, edge) { + ir_node *proj = get_edge_src_irn(edge); + pn_Cmp pnc = get_Proj_proj(proj); + if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) + return 0; } - mode = get_irn_mode(cmp_left); - assert(get_mode_size_bits(mode) <= 32); + return 1; +} + +static ir_node *gen_Cmp(ir_node *node) +{ + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *left = get_Cmp_left(node); + ir_node *right = get_Cmp_right(node); + ir_mode *cmp_mode = get_irn_mode(left); + ir_node *new_node; + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; + int cmp_unsigned; - match_arguments(&am, block, cmp_left, cmp_right, 1, 1, use_am, 1); - if(am.flipped) - pnc = get_inversed_pnc(pnc); + if(mode_is_float(cmp_mode)) { + if (ia32_cg_config.use_sse2) { + return create_Ucomi(node); + } else { + return create_Fucom(node); + } + } - if(get_mode_size_bits(mode) == 8) { - res = new_rd_ia32_CmpSet8Bit(dbgi, irg, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, pnc); + assert(mode_needs_gp_reg(cmp_mode)); + + /* we prefer the Test instruction where possible except cases where + * we can use SourceAM */ + cmp_unsigned = !mode_is_signed(cmp_mode); + if (is_Const_0(right)) { + if (is_And(left) && + get_irn_n_edges(left) == 1 && + can_fold_test_and(node)) { + /* Test(and_left, and_right) */ + ir_node *and_left = get_And_left(left); + ir_node *and_right = get_And_right(left); + ir_mode *mode = get_irn_mode(and_left); + + match_arguments(&am, block, and_left, and_right, NULL, + match_commutative | + match_am | match_8bit_am | match_16bit_am | + match_am_and_immediates | match_immediate | + match_8bit | match_16bit); + if (get_mode_size_bits(mode) == 8) { + new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2, am.ins_permuted, + cmp_unsigned); + } else { + new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2, am.ins_permuted, cmp_unsigned); + } + } else { + match_arguments(&am, block, NULL, left, NULL, + match_am | match_8bit_am | match_16bit_am | + match_8bit | match_16bit); + if (am.op_type == ia32_AddrModeS) { + /* Cmp(AM, 0) */ + ir_node *imm_zero = try_create_Immediate(right, 0); + if (get_mode_size_bits(cmp_mode) == 8) { + new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op2, + imm_zero, am.ins_permuted, + cmp_unsigned); + } else { + new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op2, + imm_zero, am.ins_permuted, cmp_unsigned); + } + } else { + /* Test(left, left) */ + if (get_mode_size_bits(cmp_mode) == 8) { + new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op2, + am.new_op2, am.ins_permuted, + cmp_unsigned); + } else { + new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op2, + am.new_op2, am.ins_permuted, + cmp_unsigned); + } + } + } } else { - res = new_rd_ia32_CmpSet(dbgi, irg, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, pnc); + /* Cmp(left, right) */ + match_arguments(&am, block, left, right, NULL, + match_commutative | match_am | match_8bit_am | + match_16bit_am | match_am_and_immediates | + match_immediate | match_8bit | match_16bit); + if (get_mode_size_bits(cmp_mode) == 8) { + new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2, am.ins_permuted, + cmp_unsigned); + } else { + new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op1, + am.new_op2, am.ins_permuted, cmp_unsigned); + } } - set_am_attributes(res, &am); - set_ia32_ls_mode(res, mode); + set_am_attributes(new_node, &am); + assert(cmp_mode != NULL); + set_ia32_ls_mode(new_node, cmp_mode); - res = fix_mem_proj(res, &am); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, nomem, res, - mode_Bu); + new_node = fix_mem_proj(new_node, &am); - return res; + return new_node; } -static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right, - ir_node *val_true, ir_node *val_false, - dbg_info *dbgi, ir_node *block) +static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, + pn_Cmp pnc) { - ir_graph *irg = current_ir_graph; - ir_node *new_block = be_transform_node(block); - ir_node *new_val_true = be_transform_node(val_true); - ir_node *new_val_false = be_transform_node(val_false); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); - ir_node *new_cmp_left; - ir_node *new_cmp_right; - ir_node *res; - ir_mode *mode; + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *val_true = get_Psi_val(node, 0); + ir_node *val_false = get_Psi_default(node); + ir_node *new_node; + match_flags_t match_flags; + ia32_address_mode_t am; + ia32_address_t *addr; - /* cmovs with unknowns are pointless... */ - if(is_Unknown(val_true)) { -#ifdef DEBUG_libfirm - ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n"); -#endif - return new_val_false; - } - if(is_Unknown(val_false)) { -#ifdef DEBUG_libfirm - ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n"); -#endif - return new_val_true; - } + assert(ia32_cg_config.use_cmov); + assert(mode_needs_gp_reg(get_irn_mode(val_true))); - /* can we use a test instruction? */ - if(is_Const_0(cmp_right)) { - long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned; - if(is_And(cmp_left) && - (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) { - ir_node *and_left = get_And_left(cmp_left); - ir_node *and_right = get_And_right(cmp_left); + addr = &am.addr; - mode = get_irn_mode(and_left); - new_cmp_left = be_transform_node(and_left); - new_cmp_right = create_immediate_or_transform(and_right, 0); - } else { - mode = get_irn_mode(cmp_left); - new_cmp_left = be_transform_node(cmp_left); - new_cmp_right = be_transform_node(cmp_left); - } + match_flags = match_commutative | match_am | match_16bit_am | + match_mode_neutral; - assert(get_mode_size_bits(mode) <= 32); + match_arguments(&am, block, val_false, val_true, flags, match_flags); - if(get_mode_size_bits(mode) == 8) { - res = new_rd_ia32_TestCMov8Bit(dbgi, current_ir_graph, new_block, noreg, - noreg, nomem, new_cmp_left, new_cmp_right, - new_val_true, new_val_false, pnc); - } else { - res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, new_block, noreg, - noreg, nomem, new_cmp_left, new_cmp_right, - new_val_true, new_val_false, pnc); - } - set_ia32_ls_mode(res, mode); + new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index, + addr->mem, am.new_op1, am.new_op2, new_flags, + am.ins_permuted, pnc); + set_am_attributes(new_node, &am); - return res; - } + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + + new_node = fix_mem_proj(new_node, &am); - mode = get_irn_mode(cmp_left); - new_cmp_left = be_transform_node(cmp_left); - new_cmp_right = create_immediate_or_transform(cmp_right, 0); + return new_node; +} - /* no support for 8,16 bit modes yet */ - assert(get_mode_size_bits(mode) <= 32); - if(get_mode_size_bits(mode) == 8) { - res = new_rd_ia32_CmpCMov8Bit(dbgi, irg, new_block, noreg, noreg, nomem, - new_cmp_left, new_cmp_right, new_val_true, - new_val_false, pnc); - } else { - res = new_rd_ia32_CmpCMov(dbgi, irg, new_block, noreg, noreg, nomem, - new_cmp_left, new_cmp_right, new_val_true, - new_val_false, pnc); + +static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, + ir_node *flags, pn_Cmp pnc, ir_node *orig_node, + int ins_permuted) +{ + ir_graph *irg = current_ir_graph; + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + ir_node *nomem = new_NoMem(); + ir_mode *mode = get_irn_mode(orig_node); + ir_node *new_node; + + new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node)); + + /* we might need to conv the result up */ + if(get_mode_size_bits(mode) > 8) { + new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, + nomem, new_node, mode_Bu); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node)); } - set_ia32_ls_mode(res, mode); - return res; + return new_node; } - /** * Transforms a Psi node into CMov. * * @return The transformed node. */ -static ir_node *gen_Psi(ir_node *node) { +static ir_node *gen_Psi(ir_node *node) +{ + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); ir_node *psi_true = get_Psi_val(node, 0); ir_node *psi_default = get_Psi_default(node); - ia32_code_gen_t *cg = env_cg; ir_node *cond = get_Psi_cond(node, 0); - ir_node *block = get_nodes_block(node); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_op; - ir_node *cmp_left; - ir_node *cmp_right; - ir_mode *cmp_mode; - long pnc; + ir_node *flags = NULL; + ir_node *new_node; + pn_Cmp pnc; assert(get_Psi_n_conds(node) == 1); assert(get_irn_mode(cond) == mode_b); assert(mode_needs_gp_reg(get_irn_mode(node))); - if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) { - /* a mode_b value, we have to compare it against 0 */ - cmp_left = cond; - cmp_right = new_Const_long(mode_Iu, 0); - pnc = pn_Cmp_Lg; - cmp_mode = mode_Iu; - } else { - ir_node *cmp = get_Proj_pred(cond); - - cmp_left = get_Cmp_left(cmp); - cmp_right = get_Cmp_right(cmp); - cmp_mode = get_irn_mode(cmp_left); - pnc = get_Proj_proj(cond); - - assert(!mode_is_float(cmp_mode)); - - if (!mode_is_signed(cmp_mode)) { - pnc |= ia32_pn_Cmp_Unsigned; - } - } + flags = get_flags_node(cond, &pnc); if(is_Const_1(psi_true) && is_Const_0(psi_default)) { - new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1); + new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0); } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) { - pnc = get_negated_pnc(pnc, cmp_mode); - new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1); + new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1); } else { - new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default, - dbgi, block); + new_node = create_CMov(node, cond, flags, pnc); } - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node)); - return new_op; + return new_node; } @@ -2468,7 +2756,7 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) ir_node *nomem = new_NoMem(); ir_node *frame = get_irg_frame(irg); ir_node *store, *load; - ir_node *res; + ir_node *new_node; store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node, tgt_mode); @@ -2482,26 +2770,69 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) set_ia32_op_type(load, ia32_AddrModeS); SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); - res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res); - return res; + new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res); + return new_node; +} + +static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val) +{ + ir_graph *irg = current_ir_graph; + ir_node *start_block = get_irg_start_block(irg); + ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, + symconst, symconst_sign, val); + arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]); + + return immediate; } /** * Create a conversion from general purpose to x87 register */ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *op = get_Conv_op(node); - ir_node *new_op = be_transform_node(op); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); - ir_mode *mode = get_irn_mode(op); - ir_mode *store_mode; - ir_node *fild, *store; - ir_node *res; - int src_bits; + ir_node *src_block = get_nodes_block(node); + ir_node *block = be_transform_node(src_block); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *op = get_Conv_op(node); + ir_node *new_op = NULL; + ir_node *noreg; + ir_node *nomem; + ir_mode *mode; + ir_mode *store_mode; + ir_node *fild; + ir_node *store; + ir_node *new_node; + int src_bits; + + /* fild can use source AM if the operand is a signed 32bit integer */ + if (src_mode == mode_Is) { + ia32_address_mode_t am; + + match_arguments(&am, src_block, NULL, op, NULL, + match_am | match_try_am); + if (am.op_type == ia32_AddrModeS) { + ia32_address_t *addr = &am.addr; + + fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, + addr->index, addr->mem); + new_node = new_r_Proj(irg, block, fild, mode_vfp, + pn_ia32_vfild_res); + + set_am_attributes(fild, &am); + SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node)); + + fix_mem_proj(fild, &am); + + return new_node; + } + } + if(new_op == NULL) { + new_op = be_transform_node(op); + } + + noreg = ia32_new_NoReg_gp(env_cg); + nomem = new_NoMem(); + mode = get_irn_mode(op); /* first convert to 32 bit signed if necessary */ src_bits = get_mode_size_bits(src_mode); @@ -2531,7 +2862,7 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { if(!mode_is_signed(mode)) { ir_node *in[2]; /* store a zero */ - ir_node *zero_const = create_Immediate_from_int(0); + ir_node *zero_const = create_Immediate(NULL, 0, 0); ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem, @@ -2558,13 +2889,13 @@ static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) { set_ia32_op_type(fild, ia32_AddrModeS); set_ia32_ls_mode(fild, store_mode); - res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); + new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); - return res; + return new_node; } /** - * Crete a conversion from one integer mode into another one + * Create a conversion from one integer mode into another one */ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, dbg_info *dbgi, ir_node *block, ir_node *op, @@ -2574,14 +2905,13 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, int src_bits = get_mode_size_bits(src_mode); int tgt_bits = get_mode_size_bits(tgt_mode); ir_node *new_block = be_transform_node(block); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *new_op; - ir_node *res; + ir_node *new_node; ir_mode *smaller_mode; int smaller_bits; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; + (void) node; if (src_bits < tgt_bits) { smaller_mode = src_mode; smaller_bits = src_bits; @@ -2590,39 +2920,32 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, smaller_bits = tgt_bits; } - memset(&am, 0, sizeof(am)); - if(use_source_address_mode(block, op, NULL)) { - build_address(&am, op); - new_op = noreg; - am.op_type = ia32_AddrModeS; - } else { - new_op = be_transform_node(op); - am.op_type = ia32_Normal; +#ifdef DEBUG_libfirm + if(is_Const(op)) { + ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n", + op); } - if(addr->base == NULL) - addr->base = noreg; - if(addr->index == NULL) - addr->index = noreg; - if(addr->mem == NULL) - addr->mem = new_NoMem(); +#endif - DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode)); + match_arguments(&am, block, NULL, op, NULL, + match_8bit | match_16bit | + match_am | match_8bit_am | match_16bit_am); if (smaller_bits == 8) { - res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, new_op, - smaller_mode); + new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op2, + smaller_mode); } else { - res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base, - addr->index, addr->mem, new_op, - smaller_mode); + new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base, + addr->index, addr->mem, am.new_op2, + smaller_mode); } - - set_am_attributes(res, &am); - set_ia32_ls_mode(res, smaller_mode); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); - res = fix_mem_proj(res, &am); - - return res; + set_am_attributes(new_node, &am); + /* match_arguments assume that out-mode = in-mode, this isn't true here + * so fix it */ + set_ia32_ls_mode(new_node, smaller_mode); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + new_node = fix_mem_proj(new_node, &am); + return new_node; } /** @@ -2646,14 +2969,14 @@ static ir_node *gen_Conv(ir_node *node) { ir_node *res = NULL; if (src_mode == mode_b) { - assert(mode_is_int(tgt_mode)); + assert(mode_is_int(tgt_mode) || mode_is_reference(tgt_mode)); /* nothing to do, we already model bools as 0/1 ints */ return be_transform_node(op); } if (src_mode == tgt_mode) { if (get_Conv_strict(node)) { - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { /* when we are in SSE mode, we can kill all strict no-op conversion */ return be_transform_node(op); } @@ -2676,7 +2999,7 @@ static ir_node *gen_Conv(ir_node *node) { } /* ... to float */ - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { DB((dbg, LEVEL_1, "create Conv(float, float) ...")); res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg, nomem, new_op); @@ -2693,7 +3016,7 @@ static ir_node *gen_Conv(ir_node *node) { } else { /* ... to int */ DB((dbg, LEVEL_1, "create Conv(float, int) ...")); - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg, nomem, new_op); set_ia32_ls_mode(res, src_mode); @@ -2706,7 +3029,7 @@ static ir_node *gen_Conv(ir_node *node) { if (mode_is_float(tgt_mode)) { /* ... to float */ DB((dbg, LEVEL_1, "create Conv(int, float) ...")); - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { new_op = be_transform_node(op); res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg, nomem, new_op); @@ -2741,8 +3064,7 @@ static ir_node *gen_Conv(ir_node *node) { return res; } -static -int check_immediate_constraint(long val, char immediate_constraint_type) +static int check_immediate_constraint(long val, char immediate_constraint_type) { switch (immediate_constraint_type) { case 0: @@ -2768,8 +3090,8 @@ int check_immediate_constraint(long val, char immediate_constraint_type) return 0; } -static -ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) +static ir_node *try_create_Immediate(ir_node *node, + char immediate_constraint_type) { int minus = 0; tarval *offset = NULL; @@ -2780,10 +3102,7 @@ ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) ir_mode *mode; ir_node *cnst = NULL; ir_node *symconst = NULL; - ir_node *res; - ir_graph *irg; - dbg_info *dbgi; - ir_node *block; + ir_node *new_node; mode = get_irn_mode(node); if(!mode_is_int(mode) && !mode_is_reference(mode)) { @@ -2839,8 +3158,6 @@ ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) offset = get_Const_tarval(cnst); if(tarval_is_long(offset)) { val = get_tarval_long(offset); - } else if(tarval_is_null(offset)) { - val = 0; } else { ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a " "long?\n", cnst); @@ -2856,6 +3173,10 @@ ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) return NULL; } + /* unfortunately the assembler/linker doesn't support -symconst */ + if(symconst_sign) + return NULL; + if(get_SymConst_kind(symconst) != symconst_addr_ent) return NULL; symconst_ent = get_SymConst_entity(symconst); @@ -2867,18 +3188,13 @@ ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) offset = tarval_neg(offset); } - irg = current_ir_graph; - dbgi = get_irn_dbg_info(node); - block = get_irg_start_block(irg); - res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, - symconst_sign, val); - arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]); + new_node = create_Immediate(symconst_ent, symconst_sign, val); - return res; + return new_node; } -static -ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type) +static ir_node *create_immediate_or_transform(ir_node *node, + char immediate_constraint_type) { ir_node *new_node = try_create_Immediate(node, immediate_constraint_type); if (new_node == NULL) { @@ -2887,6 +3203,17 @@ ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_ return new_node; } +static const arch_register_req_t no_register_req = { + arch_register_req_type_none, + NULL, /* regclass */ + NULL, /* limit bitset */ + 0, /* same pos */ + 0 /* different pos */ +}; + +/** + * An assembler constraint. + */ typedef struct constraint_t constraint_t; struct constraint_t { int is_in; @@ -2898,7 +3225,7 @@ struct constraint_t { char immediate_type; }; -void parse_asm_constraint(int pos, constraint_t *constraint, const char *c) +static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c) { int immediate_possible = 0; char immediate_type = 0; @@ -2907,13 +3234,19 @@ void parse_asm_constraint(int pos, constraint_t *constraint, const char *c) ir_graph *irg = current_ir_graph; struct obstack *obst = get_irg_obstack(irg); arch_register_req_t *req; - unsigned *limited_ptr; + unsigned *limited_ptr = NULL; int p; int same_as = -1; /* TODO: replace all the asserts with nice error messages */ - printf("Constraint: %s\n", c); + if(*c == 0) { + /* a memory constraint: no need to do anything in backend about it + * (the dependencies are already respected by the memory edge of + * the node) */ + constraint->req = &no_register_req; + return; + } while(*c != 0) { switch(*c) { @@ -3047,11 +3380,17 @@ void parse_asm_constraint(int pos, constraint_t *constraint, const char *c) } break; + case 'm': + /* memory constraint no need to do anything in backend about it + * (the dependencies are already respected by the memory edge of + * the node) */ + constraint->req = &no_register_req; + return; + case 'E': /* no float consts yet */ case 'F': /* no float consts yet */ case 's': /* makes no sense on x86 */ case 'X': /* we can't support that in firm */ - case 'm': case 'o': case 'V': case '<': /* no autodecrement on x86 */ @@ -3061,10 +3400,12 @@ void parse_asm_constraint(int pos, constraint_t *constraint, const char *c) case 'y': /* we don't support mmx registers yet */ case 'Z': /* not available in 32 bit mode */ case 'e': /* not available in 32 bit mode */ - assert(0 && "asm constraint not supported"); + panic("unsupported asm constraint '%c' found in (%+F)", + *c, current_ir_graph); break; default: - assert(0 && "unknown asm constraint found"); + panic("unknown asm constraint '%c' found in (%+F)", *c, + current_ir_graph); break; } ++c; @@ -3085,8 +3426,8 @@ void parse_asm_constraint(int pos, constraint_t *constraint, const char *c) req->cls = other_constr->cls; req->type = arch_register_req_type_should_be_same; req->limited = NULL; - req->other_same = pos; - req->other_different = -1; + req->other_same = 1U << pos; + req->other_different = 0; /* switch constraints. This is because in firm we have same_as * constraints on the output constraints while in the gcc asm syntax @@ -3105,7 +3446,7 @@ void parse_asm_constraint(int pos, constraint_t *constraint, const char *c) if(immediate_possible) { assert(constraint->is_in - && "imeediates make no sense for output constraints"); + && "immediate make no sense for output constraints"); } /* todo: check types (no float input on 'r' constrained in and such... */ @@ -3131,15 +3472,68 @@ void parse_asm_constraint(int pos, constraint_t *constraint, const char *c) constraint->immediate_type = immediate_type; } -static -void parse_clobber(ir_node *node, int pos, constraint_t *constraint, - const char *c) +static void parse_clobber(ir_node *node, int pos, constraint_t *constraint, + const char *clobber) { - (void) node; + ir_graph *irg = get_irn_irg(node); + struct obstack *obst = get_irg_obstack(irg); + const arch_register_t *reg = NULL; + int c; + size_t r; + arch_register_req_t *req; + const arch_register_class_t *cls; + unsigned *limited; + (void) pos; - (void) constraint; - (void) c; - panic("Clobbers not supported yet"); + + /* TODO: construct a hashmap instead of doing linear search for clobber + * register */ + for(c = 0; c < N_CLASSES; ++c) { + cls = & ia32_reg_classes[c]; + for(r = 0; r < cls->n_regs; ++r) { + const arch_register_t *temp_reg = arch_register_for_index(cls, r); + if(strcmp(temp_reg->name, clobber) == 0 + || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) { + reg = temp_reg; + break; + } + } + if(reg != NULL) + break; + } + if(reg == NULL) { + panic("Register '%s' mentioned in asm clobber is unknown\n", clobber); + return; + } + + assert(reg->index < 32); + + limited = obstack_alloc(obst, sizeof(limited[0])); + *limited = 1 << reg->index; + + req = obstack_alloc(obst, sizeof(req[0])); + memset(req, 0, sizeof(req[0])); + req->type = arch_register_req_type_limited; + req->cls = cls; + req->limited = limited; + + constraint->req = req; + constraint->immediate_possible = 0; + constraint->immediate_type = 0; +} + +static int is_memory_op(const ir_asm_constraint *constraint) +{ + ident *id = constraint->constraint; + const char *str = get_id_str(id); + const char *c; + + for(c = str; *c != '\0'; ++c) { + if(*c == 'm') + return 1; + } + + return 0; } /** @@ -3147,65 +3541,85 @@ void parse_clobber(ir_node *node, int pos, constraint_t *constraint, */ static ir_node *gen_ASM(ir_node *node) { - int i, arity; - ir_graph *irg = current_ir_graph; - ir_node *block = be_transform_node(get_nodes_block(node)); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node **in; - ir_node *res; - int out_arity; - int n_outs; - int n_clobbers; - void *generic_attr; - ia32_asm_attr_t *attr; - const arch_register_req_t **out_reqs; - const arch_register_req_t **in_reqs; - struct obstack *obst; - constraint_t parsed_constraint; + int i, arity; + ir_graph *irg = current_ir_graph; + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node **in; + ir_node *new_node; + int out_arity; + int n_out_constraints; + int n_clobbers; + const arch_register_req_t **out_reg_reqs; + const arch_register_req_t **in_reg_reqs; + ia32_asm_reg_t *register_map; + unsigned reg_map_size = 0; + struct obstack *obst; + const ir_asm_constraint *in_constraints; + const ir_asm_constraint *out_constraints; + ident **clobbers; + constraint_t parsed_constraint; - /* transform inputs */ arity = get_irn_arity(node); in = alloca(arity * sizeof(in[0])); memset(in, 0, arity * sizeof(in[0])); - n_outs = get_ASM_n_output_constraints(node); - n_clobbers = get_ASM_n_clobbers(node); - out_arity = n_outs + n_clobbers; - - /* construct register constraints */ - obst = get_irg_obstack(irg); - out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0])); - parsed_constraint.out_reqs = out_reqs; - parsed_constraint.n_outs = n_outs; + n_out_constraints = get_ASM_n_output_constraints(node); + n_clobbers = get_ASM_n_clobbers(node); + out_arity = n_out_constraints + n_clobbers; + /* hack to keep space for mem proj */ + if(n_clobbers > 0) + out_arity += 1; + + in_constraints = get_ASM_input_constraints(node); + out_constraints = get_ASM_output_constraints(node); + clobbers = get_ASM_clobbers(node); + + /* construct output constraints */ + obst = get_irg_obstack(irg); + out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0])); + parsed_constraint.out_reqs = out_reg_reqs; + parsed_constraint.n_outs = n_out_constraints; parsed_constraint.is_in = 0; + for(i = 0; i < out_arity; ++i) { const char *c; - if(i < n_outs) { - const ir_asm_constraint *constraint; - constraint = & get_ASM_output_constraints(node) [i]; + if(i < n_out_constraints) { + const ir_asm_constraint *constraint = &out_constraints[i]; c = get_id_str(constraint->constraint); parse_asm_constraint(i, &parsed_constraint, c); - } else { - ident *glob_id = get_ASM_clobbers(node) [i - n_outs]; + + if(constraint->pos > reg_map_size) + reg_map_size = constraint->pos; + + out_reg_reqs[i] = parsed_constraint.req; + } else if(i < out_arity - 1) { + ident *glob_id = clobbers [i - n_out_constraints]; + assert(glob_id != NULL); c = get_id_str(glob_id); parse_clobber(node, i, &parsed_constraint, c); + + out_reg_reqs[i+1] = parsed_constraint.req; } - out_reqs[i] = parsed_constraint.req; } + if(n_clobbers > 1) + out_reg_reqs[n_out_constraints] = &no_register_req; - in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0])); + /* construct input constraints */ + in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0])); parsed_constraint.is_in = 1; for(i = 0; i < arity; ++i) { - const ir_asm_constraint *constraint; - ident *constr_id; - const char *c; + const ir_asm_constraint *constraint = &in_constraints[i]; + ident *constr_id = constraint->constraint; + const char *c = get_id_str(constr_id); - constraint = & get_ASM_input_constraints(node) [i]; - constr_id = constraint->constraint; - c = get_id_str(constr_id); parse_asm_constraint(i, &parsed_constraint, c); - in_reqs[i] = parsed_constraint.req; + in_reg_reqs[i] = parsed_constraint.req; + + if(constraint->pos > reg_map_size) + reg_map_size = constraint->pos; if(parsed_constraint.immediate_possible) { ir_node *pred = get_irn_n(node, i); @@ -3217,43 +3631,55 @@ static ir_node *gen_ASM(ir_node *node) } } } + reg_map_size++; + + register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size); + memset(register_map, 0, reg_map_size * sizeof(register_map[0])); + + for(i = 0; i < n_out_constraints; ++i) { + const ir_asm_constraint *constraint = &out_constraints[i]; + unsigned pos = constraint->pos; + + assert(pos < reg_map_size); + register_map[pos].use_input = 0; + register_map[pos].valid = 1; + register_map[pos].memory = is_memory_op(constraint); + register_map[pos].inout_pos = i; + register_map[pos].mode = constraint->mode; + } /* transform inputs */ for(i = 0; i < arity; ++i) { - ir_node *pred; - ir_node *transformed; + const ir_asm_constraint *constraint = &in_constraints[i]; + unsigned pos = constraint->pos; + ir_node *pred = get_irn_n(node, i); + ir_node *transformed; + + assert(pos < reg_map_size); + register_map[pos].use_input = 1; + register_map[pos].valid = 1; + register_map[pos].memory = is_memory_op(constraint); + register_map[pos].inout_pos = i; + register_map[pos].mode = constraint->mode; if(in[i] != NULL) continue; - pred = get_irn_n(node, i); transformed = be_transform_node(pred); in[i] = transformed; } - res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity); + new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity, + get_ASM_text(node), register_map); - generic_attr = get_irn_generic_attr(res); - attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr); - attr->asm_text = get_ASM_text(node); - set_ia32_out_req_all(res, out_reqs); - set_ia32_in_req_all(res, in_reqs); + set_ia32_out_req_all(new_node, out_reg_reqs); + set_ia32_in_req_all(new_node, in_reg_reqs); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + return new_node; } -/******************************************** - * _ _ - * | | | | - * | |__ ___ _ __ ___ __| | ___ ___ - * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __| - * | |_) | __/ | | | (_) | (_| | __/\__ \ - * |_.__/ \___|_| |_|\___/ \__,_|\___||___/ - * - ********************************************/ - /** * Transforms a FrameAddr into an ia32 Add. */ @@ -3264,15 +3690,15 @@ static ir_node *gen_be_FrameAddr(ir_node *node) { ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *res; + ir_node *new_node; - res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg); - set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node)); - set_ia32_use_frame(res); + new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg); + set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node)); + set_ia32_use_frame(new_node); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return res; + return new_node; } /** @@ -3295,7 +3721,7 @@ static ir_node *gen_be_Return(ir_node *node) { int pn_ret_val, pn_ret_mem, arity, i; assert(ret_val != NULL); - if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) { + if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) { return be_duplicate_node(node); } @@ -3378,53 +3804,25 @@ static ir_node *gen_be_Return(ir_node *node) { } /** - * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes. + * Transform a be_AddSP into an ia32_SubSP. */ -static ir_node *gen_be_AddSP(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *sz = get_irn_n(node, be_pos_AddSP_size); - ir_node *new_sz; - ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); - ir_node *new_sp = be_transform_node(sp); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); - ir_node *new_op; - - new_sz = create_immediate_or_transform(sz, 0); - - /* ia32 stack grows in reverse direction, make a SubSP */ - new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, nomem, new_sp, - new_sz); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); +static ir_node *gen_be_AddSP(ir_node *node) +{ + ir_node *sz = get_irn_n(node, be_pos_AddSP_size); + ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp); - return new_op; + return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am); } /** - * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes. + * Transform a be_SubSP into an ia32_AddSP */ -static ir_node *gen_be_SubSP(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *sz = get_irn_n(node, be_pos_SubSP_size); - ir_node *new_sz; - ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); - ir_node *new_sp = be_transform_node(sp); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_node *nomem = new_NoMem(); - ir_node *new_op; - - new_sz = create_immediate_or_transform(sz, 0); - - /* ia32 stack grows in reverse direction, make an AddSP */ - new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, nomem, new_sp, - new_sz); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); +static ir_node *gen_be_SubSP(ir_node *node) +{ + ir_node *sz = get_irn_n(node, be_pos_SubSP_size); + ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp); - return new_op; + return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am); } /** @@ -3436,7 +3834,7 @@ static ir_node *gen_Unknown(ir_node *node) { ir_mode *mode = get_irn_mode(node); if (mode_is_float(mode)) { - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { return ia32_new_Unknown_xmm(env_cg); } else { /* Unknown nodes are buggy in x87 sim, use zero for now... */ @@ -3448,9 +3846,8 @@ static ir_node *gen_Unknown(ir_node *node) { } else if (mode_needs_gp_reg(mode)) { return ia32_new_Unknown_gp(env_cg); } else { - assert(0 && "unsupported Unknown-Mode"); + panic("unsupported Unknown-Mode"); } - return NULL; } @@ -3470,7 +3867,7 @@ static ir_node *gen_Phi(ir_node *node) { /* all integer operations are on 32bit registers now */ mode = mode_Iu; } else if(mode_is_float(mode)) { - if (USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2) { mode = mode_xmm; } else { mode = mode_vfp; @@ -3493,23 +3890,32 @@ static ir_node *gen_Phi(ir_node *node) { /** * Transform IJmp */ -static ir_node *gen_IJmp(ir_node *node) { - /* TODO: support AM */ - return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp); -} +static ir_node *gen_IJmp(ir_node *node) +{ + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *op = get_IJmp_target(node); + ir_node *new_node; + ia32_address_mode_t am; + ia32_address_t *addr = &am.addr; + assert(get_irn_mode(op) == mode_P); -/********************************************************************** - * _ _ _ - * | | | | | | - * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___ - * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __| - * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \ - * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/ - * - **********************************************************************/ + match_arguments(&am, block, NULL, op, NULL, + match_am | match_8bit_am | match_16bit_am | + match_immediate | match_8bit | match_16bit); + + new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index, + addr->mem, am.new_op2); + set_am_attributes(new_node, &am); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + + new_node = fix_mem_proj(new_node, &am); -/* These nodes are created in intrinsic lowering (64bit -> 32bit) */ + return new_node; +} typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \ ir_node *mem); @@ -3586,45 +3992,37 @@ static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func) return new_op; } +static ir_node *gen_ia32_l_ShlDep(ir_node *node) +{ + ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val); + ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count); -/** - * Transforms an ia32_l_XXX into a "real" XXX node - * - * @param node The node to transform - * @return the created ia32 XXX node - */ -#define GEN_LOWERED_OP(op) \ - static ir_node *gen_ia32_l_##op(ir_node *node) { \ - return gen_binop(node, get_binop_left(node), \ - get_binop_right(node), new_rd_ia32_##op,0); \ - } - -#define GEN_LOWERED_x87_OP(op) \ - static ir_node *gen_ia32_l_##op(ir_node *node) { \ - ir_node *new_op; \ - new_op = gen_binop_x87_float(node, get_binop_left(node), \ - get_binop_right(node), new_rd_ia32_##op); \ - return new_op; \ - } + return gen_shift_binop(node, left, right, new_rd_ia32_Shl, + match_immediate | match_mode_neutral); +} -#define GEN_LOWERED_SHIFT_OP(l_op, op) \ - static ir_node *gen_ia32_##l_op(ir_node *node) { \ - return gen_shift_binop(node, get_irn_n(node, 0), \ - get_irn_n(node, 1), new_rd_ia32_##op); \ - } +static ir_node *gen_ia32_l_ShrDep(ir_node *node) +{ + ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val); + ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count); + return gen_shift_binop(node, left, right, new_rd_ia32_Shr, + match_immediate); +} -GEN_LOWERED_x87_OP(vfprem) -GEN_LOWERED_x87_OP(vfmul) -GEN_LOWERED_x87_OP(vfsub) -GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl) -GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr) -GEN_LOWERED_SHIFT_OP(l_Sar, Sar) -GEN_LOWERED_SHIFT_OP(l_SarDep, Sar) +static ir_node *gen_ia32_l_SarDep(ir_node *node) +{ + ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val); + ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count); + return gen_shift_binop(node, left, right, new_rd_ia32_Sar, + match_immediate); +} static ir_node *gen_ia32_l_Add(ir_node *node) { ir_node *left = get_irn_n(node, n_ia32_l_Add_left); ir_node *right = get_irn_n(node, n_ia32_l_Add_right); - ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1); + ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, + match_commutative | match_am | match_immediate | + match_mode_neutral); if(is_Proj(lowered)) { lowered = get_Proj_pred(lowered); @@ -3636,42 +4034,11 @@ static ir_node *gen_ia32_l_Add(ir_node *node) { return lowered; } -static ir_node *gen_ia32_l_Adc(ir_node *node) { - ir_node *src_block = get_nodes_block(node); - ir_node *block = be_transform_node(src_block); - ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left); - ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right); - ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags); - ir_node *new_flags = be_transform_node(flags); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_node; - ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; - - match_arguments(&am, src_block, op1, op2, 1, 0, 1, 0); - - new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index, am.new_op1, - am.new_op2, addr->mem, new_flags); - set_am_attributes(new_node, &am); - /* we can't use source address mode anymore when using immediates */ - if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) - set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - - new_node = fix_mem_proj(new_node, &am); - - return new_node; -} - -/** - * Transforms an ia32_l_Neg into a "real" ia32_Neg node - * - * @param node The node to transform - * @return the created ia32 Neg node - */ -static ir_node *gen_ia32_l_Neg(ir_node *node) { - return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg); +static ir_node *gen_ia32_l_Adc(ir_node *node) +{ + return gen_binop_flags(node, new_rd_ia32_Adc, + match_commutative | match_am | match_immediate | + match_mode_neutral); } /** @@ -3742,113 +4109,51 @@ static ir_node *gen_ia32_l_vfist(ir_node *node) { return new_op; } -/** - * Transforms a l_vfdiv into a "real" vfdiv node. - * - * @param env The transformation environment - * @return the created ia32 vfdiv node - */ -static ir_node *gen_ia32_l_vfdiv(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *left = get_binop_left(node); - ir_node *new_left = be_transform_node(left); - ir_node *right = get_binop_right(node); - ir_node *new_right = be_transform_node(right); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *fpcw = get_fpcw(); - ir_node *vfdiv; - - vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(), - new_left, new_right, fpcw); - clear_ia32_commutative(vfdiv); - - SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node)); - - return vfdiv; -} - /** * Transforms a l_MulS into a "real" MulS node. * - * @param env The transformation environment * @return the created ia32 Mul node */ static ir_node *gen_ia32_l_Mul(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *left = get_binop_left(node); - ir_node *new_left = be_transform_node(left); - ir_node *right = get_binop_right(node); - ir_node *new_right = be_transform_node(right); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *left = get_binop_left(node); + ir_node *right = get_binop_right(node); - /* l_Mul is already a mode_T node, so we create the Mul in the normal way */ - /* and then skip the result Proj, because all needed Projs are already there. */ - ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), - new_left, new_right); - clear_ia32_commutative(muls); - - SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node)); - - return muls; + return gen_binop(node, left, right, new_rd_ia32_Mul, + match_commutative | match_am | match_mode_neutral); } /** * Transforms a l_IMulS into a "real" IMul1OPS node. * - * @param env The transformation environment * @return the created ia32 IMul1OP node */ static ir_node *gen_ia32_l_IMul(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *left = get_binop_left(node); - ir_node *new_left = be_transform_node(left); ir_node *right = get_binop_right(node); - ir_node *new_right = be_transform_node(right); - ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */ - /* and then skip the result Proj, because all needed Projs are already there. */ - ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, - new_NoMem(), new_left, new_right); - clear_ia32_commutative(muls); + return gen_binop(node, left, right, new_rd_ia32_IMul1OP, + match_commutative | match_am | match_mode_neutral); +} - SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node)); +static ir_node *gen_ia32_l_Sub(ir_node *node) { + ir_node *left = get_irn_n(node, n_ia32_l_Sub_left); + ir_node *right = get_irn_n(node, n_ia32_l_Sub_right); + ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, + match_am | match_immediate | match_mode_neutral); - return muls; -} + if(is_Proj(lowered)) { + lowered = get_Proj_pred(lowered); + } else { + assert(is_ia32_Sub(lowered)); + set_irn_mode(lowered, mode_T); + } -static ir_node *gen_ia32_Add64Bit(ir_node *node) -{ - ir_node *a_l = be_transform_node(get_irn_n(node, 0)); - ir_node *a_h = be_transform_node(get_irn_n(node, 1)); - ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0); - ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0); - ir_node *block = be_transform_node(get_nodes_block(node)); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_graph *irg = current_ir_graph; - ir_node *new_op = new_rd_ia32_Add64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); - return new_op; + return lowered; } -static ir_node *gen_ia32_Sub64Bit(ir_node *node) -{ - ir_node *a_l = be_transform_node(get_irn_n(node, 0)); - ir_node *a_h = be_transform_node(get_irn_n(node, 1)); - ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0); - ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0); - ir_node *block = be_transform_node(get_nodes_block(node)); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_graph *irg = current_ir_graph; - ir_node *new_op = new_rd_ia32_Sub64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); - return new_op; +static ir_node *gen_ia32_l_Sbb(ir_node *node) { + return gen_binop_flags(node, new_rd_ia32_Sbb, + match_am | match_immediate | match_mode_neutral); } /** @@ -3858,150 +4163,132 @@ static ir_node *gen_ia32_Sub64Bit(ir_node *node) * op3 - shift count * Only op3 can be an immediate. */ -static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1, - ir_node *op2, ir_node *count) +static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high, + ir_node *low, ir_node *count) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *new_op = NULL; + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_op1 = be_transform_node(op1); - ir_node *new_op2 = be_transform_node(op2); - ir_node *new_count = create_immediate_or_transform(count, 'I'); - - /* TODO proper AM support */ + ir_node *new_high = be_transform_node(high); + ir_node *new_low = be_transform_node(low); + ir_node *new_count; + ir_node *new_node; - if (is_ia32_l_ShlD(node)) - new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count); - else - new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count); + /* the shift amount can be any mode that is bigger than 5 bits, since all + * other bits are ignored anyway */ + while (is_Conv(count) && get_irn_n_edges(count) == 1) { + assert(get_mode_size_bits(get_irn_mode(count)) >= 5); + count = get_Conv_op(count); + } + new_count = create_immediate_or_transform(count, 0); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); + if (is_ia32_l_ShlD(node)) { + new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low, + new_count); + } else { + new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low, + new_count); + } + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); - return new_op; + return new_node; } -static ir_node *gen_ia32_l_ShlD(ir_node *node) { - return gen_lowered_64bit_shifts(node, get_irn_n(node, 0), - get_irn_n(node, 1), get_irn_n(node, 2)); +static ir_node *gen_ia32_l_ShlD(ir_node *node) +{ + ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high); + ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low); + ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count); + return gen_lowered_64bit_shifts(node, high, low, count); } -static ir_node *gen_ia32_l_ShrD(ir_node *node) { - return gen_lowered_64bit_shifts(node, get_irn_n(node, 0), - get_irn_n(node, 1), get_irn_n(node, 2)); +static ir_node *gen_ia32_l_ShrD(ir_node *node) +{ + ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high); + ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low); + ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count); + return gen_lowered_64bit_shifts(node, high, low, count); } -/** - * In case SSE Unit is used, the node is transformed into a vfst + xLoad. - */ -static ir_node *gen_ia32_l_X87toSSE(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *val = get_irn_n(node, 1); - ir_node *new_val = be_transform_node(val); - ia32_code_gen_t *cg = env_cg; - ir_node *res = NULL; - ir_graph *irg = current_ir_graph; - dbg_info *dbgi; - ir_node *noreg, *new_ptr, *new_mem; - ir_node *ptr, *mem; - - if (USE_SSE2(cg)) { - return new_val; - } - - mem = get_irn_n(node, 2); - new_mem = be_transform_node(mem); - ptr = get_irn_n(node, 0); - new_ptr = be_transform_node(ptr); - noreg = ia32_new_NoReg_gp(cg); - dbgi = get_irn_dbg_info(node); - - /* Store x87 -> MEM */ - res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val, - get_ia32_ls_mode(node)); - set_ia32_frame_ent(res, get_ia32_frame_ent(node)); - set_ia32_use_frame(res); - set_ia32_ls_mode(res, get_ia32_ls_mode(node)); - set_ia32_op_type(res, ia32_AddrModeD); - - /* Load MEM -> SSE */ - res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res, - get_ia32_ls_mode(node)); - set_ia32_frame_ent(res, get_ia32_frame_ent(node)); - set_ia32_use_frame(res); - set_ia32_op_type(res, ia32_AddrModeS); - res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res); +static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) { + ir_node *src_block = get_nodes_block(node); + ir_node *block = be_transform_node(src_block); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *frame = get_irg_frame(irg); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + ir_node *nomem = new_NoMem(); + ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low); + ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high); + ir_node *new_val_low = be_transform_node(val_low); + ir_node *new_val_high = be_transform_node(val_high); + ir_node *in[2]; + ir_node *sync; + ir_node *fild; + ir_node *store_low; + ir_node *store_high; + + if(!mode_is_signed(get_irn_mode(val_high))) { + panic("unsigned long long -> float not supported yet (%+F)", node); + } - return res; -} + /* do a store */ + store_low = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem, + new_val_low); + store_high = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem, + new_val_high); + SET_IA32_ORIG_NODE(store_low, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(store_high, ia32_get_old_node_name(env_cg, node)); + + set_ia32_use_frame(store_low); + set_ia32_use_frame(store_high); + set_ia32_op_type(store_low, ia32_AddrModeD); + set_ia32_op_type(store_high, ia32_AddrModeD); + set_ia32_ls_mode(store_low, mode_Iu); + set_ia32_ls_mode(store_high, mode_Is); + add_ia32_am_offs_int(store_high, 4); + + in[0] = store_low; + in[1] = store_high; + sync = new_rd_Sync(dbgi, irg, block, 2, in); -/** - * In case SSE Unit is used, the node is transformed into a xStore + vfld. - */ -static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *val = get_irn_n(node, 1); - ir_node *new_val = be_transform_node(val); - ia32_code_gen_t *cg = env_cg; - ir_graph *irg = current_ir_graph; - ir_node *res = NULL; - ir_entity *fent = get_ia32_frame_ent(node); - ir_mode *lsmode = get_ia32_ls_mode(node); - int offs = 0; - ir_node *noreg, *new_ptr, *new_mem; - ir_node *ptr, *mem; - dbg_info *dbgi; - - if (! USE_SSE2(cg)) { - /* SSE unit is not used -> skip this node. */ - return new_val; - } - - ptr = get_irn_n(node, 0); - new_ptr = be_transform_node(ptr); - mem = get_irn_n(node, 2); - new_mem = be_transform_node(mem); - noreg = ia32_new_NoReg_gp(cg); - dbgi = get_irn_dbg_info(node); - - /* Store SSE -> MEM */ - if (is_ia32_xLoad(skip_Proj(new_val))) { - ir_node *ld = skip_Proj(new_val); - - /* we can vfld the value directly into the fpu */ - fent = get_ia32_frame_ent(ld); - ptr = get_irn_n(ld, 0); - offs = get_ia32_am_offs_int(ld); - } else { - res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem, - new_val); - set_ia32_frame_ent(res, fent); - set_ia32_use_frame(res); - set_ia32_ls_mode(res, lsmode); - set_ia32_op_type(res, ia32_AddrModeD); - mem = res; - } - - /* Load MEM -> x87 */ - res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode); - set_ia32_frame_ent(res, fent); - set_ia32_use_frame(res); - add_ia32_am_offs_int(res, offs); - set_ia32_op_type(res, ia32_AddrModeS); - res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res); + /* do a fild */ + fild = new_rd_ia32_vfild(dbgi, irg, block, frame, noreg, sync); - return res; + set_ia32_use_frame(fild); + set_ia32_op_type(fild, ia32_AddrModeS); + set_ia32_ls_mode(fild, mode_Ls); + + SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node)); + + return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res); } -/********************************************************* - * _ _ _ - * (_) | | (_) - * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __ - * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__| - * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ | - * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_| - * - *********************************************************/ +static ir_node *gen_ia32_l_FloattoLL(ir_node *node) { + ir_node *src_block = get_nodes_block(node); + ir_node *block = be_transform_node(src_block); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *frame = get_irg_frame(irg); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + ir_node *nomem = new_NoMem(); + ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val); + ir_node *new_val = be_transform_node(val); + ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); + + ir_node *fist; + + /* do a fist */ + fist = new_rd_ia32_vfist(dbgi, irg, block, frame, noreg, nomem, new_val, + trunc_mode); + SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node)); + set_ia32_use_frame(fist); + set_ia32_op_type(fist, ia32_AddrModeD); + set_ia32_ls_mode(fist, mode_Ls); + + return fist; +} /** * the BAD transformer. @@ -4011,6 +4298,40 @@ static ir_node *bad_transform(ir_node *node) { return NULL; } +static ir_node *gen_Proj_l_FloattoLL(ir_node *node) { + ir_graph *irg = current_ir_graph; + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + ir_node *frame = get_irg_frame(irg); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + dbg_info *dbgi = get_irn_dbg_info(node); + long pn = get_Proj_proj(node); + ir_node *load; + ir_node *proj; + ia32_attr_t *attr; + + load = new_rd_ia32_Load(dbgi, irg, block, frame, noreg, new_pred); + SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); + set_ia32_use_frame(load); + set_ia32_op_type(load, ia32_AddrModeS); + set_ia32_ls_mode(load, mode_Iu); + /* we need a 64bit stackslot (fist stores 64bit) even though we only load + * 32 bit from it with this particular load */ + attr = get_ia32_attr(load); + attr->data.need_64bit_stackent = 1; + + if (pn == pn_ia32_l_FloattoLL_res_high) { + add_ia32_am_offs_int(load, 4); + } else { + assert(pn == pn_ia32_l_FloattoLL_res_low); + } + + proj = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res); + + return proj; +} + /** * Transform the Projs of an AddSP. */ @@ -4095,14 +4416,22 @@ static ir_node *gen_Proj_Load(ir_node *node) { /* renumber the proj */ new_pred = be_transform_node(pred); if (is_ia32_Load(new_pred)) { - if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, - pn_ia32_Load_res); - } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, - pn_ia32_Load_M); + switch (proj) { + case pn_Load_res: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res); + case pn_Load_M: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M); + case pn_Load_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Load_X_exc); + default: + break; } - } else if(is_ia32_Conv_I2I(new_pred)) { + } else if (is_ia32_Conv_I2I(new_pred) || + is_ia32_Conv_I2I8Bit(new_pred)) { set_irn_mode(new_pred, mode_T); if (proj == pn_Load_res) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res); @@ -4110,20 +4439,34 @@ static ir_node *gen_Proj_Load(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem); } } else if (is_ia32_xLoad(new_pred)) { - if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, - pn_ia32_xLoad_res); - } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, - pn_ia32_xLoad_M); + switch (proj) { + case pn_Load_res: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res); + case pn_Load_M: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M); + case pn_Load_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); + default: + break; } } else if (is_ia32_vfld(new_pred)) { - if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, - pn_ia32_vfld_res); - } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, - pn_ia32_vfld_M); + switch (proj) { + case pn_Load_res: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res); + case pn_Load_M: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M); + case pn_Load_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); + default: + break; } } else { /* can happen for ProJMs when source address mode happened for the @@ -4132,7 +4475,7 @@ static ir_node *gen_Proj_Load(ir_node *node) { /* however it should not be the result proj, as that would mean the load had multiple users and should not have been used for SourceAM */ - if(proj != pn_Load_M) { + if (proj != pn_Load_M) { panic("internal error: transformed node not a Load"); } return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1); @@ -4163,6 +4506,11 @@ static ir_node *gen_Proj_DivMod(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Div_res: return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); + case pn_Div_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Div_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4173,6 +4521,9 @@ static ir_node *gen_Proj_DivMod(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Mod_res: return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + case pn_Mod_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4185,6 +4536,11 @@ static ir_node *gen_Proj_DivMod(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); case pn_DivMod_res_mod: return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + case pn_DivMod_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_DivMod_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4225,30 +4581,6 @@ static ir_node *gen_Proj_CopyB(ir_node *node) { return new_rd_Unknown(irg, mode); } -/** - * Transform and renumber the Projs from a vfdiv. - */ -static ir_node *gen_Proj_l_vfdiv(ir_node *node) { - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_node *pred = get_Proj_pred(node); - ir_node *new_pred = be_transform_node(pred); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_mode *mode = get_irn_mode(node); - long proj = get_Proj_proj(node); - - switch (proj) { - case pn_ia32_l_vfdiv_M: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M); - case pn_ia32_l_vfdiv_res: - return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res); - default: - assert(0); - } - - return new_rd_Unknown(irg, mode); -} - /** * Transform and renumber the Projs from a Quot. */ @@ -4296,6 +4628,20 @@ static ir_node *gen_Proj_tls(ir_node *node) { return res; } +static ir_node *gen_be_Call(ir_node *node) { + ir_node *res = be_duplicate_node(node); + be_node_add_flags(res, -1, arch_irn_flags_modify_flags); + + return res; +} + +static ir_node *gen_be_IncSP(ir_node *node) { + ir_node *res = be_duplicate_node(node); + be_node_add_flags(res, -1, arch_irn_flags_modify_flags); + + return res; +} + /** * Transform the Projs from a be_Call. */ @@ -4338,9 +4684,8 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { pn_ia32_xLoad_M); } } - if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res - && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode) - && USE_SSE2(env_cg)) { + if (ia32_cg_config.use_sse2 && proj >= pn_be_Call_first_res + && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)) { ir_node *fstp; ir_node *frame = get_irg_frame(irg); ir_node *noreg = ia32_new_NoReg_gp(env_cg); @@ -4387,34 +4732,9 @@ static ir_node *gen_Proj_be_Call(ir_node *node) { */ static ir_node *gen_Proj_Cmp(ir_node *node) { - /* normally Cmps are processed when looking at Cond nodes, but this case - * can happen in complicated Psi conditions */ - - ir_node *cmp = get_Proj_pred(node); - long pnc = get_Proj_proj(node); - ir_node *cmp_left = get_Cmp_left(cmp); - ir_node *cmp_right = get_Cmp_right(cmp); - ir_mode *cmp_mode = get_irn_mode(cmp_left); - dbg_info *dbgi = get_irn_dbg_info(cmp); - ir_node *block = get_nodes_block(node); - ir_node *res; - int use_am; - - assert(!mode_is_float(cmp_mode)); - - if(!mode_is_signed(cmp_mode)) { - pnc |= ia32_pn_Cmp_Unsigned; - } - - /** - * address mode makes only sense when we'll be the only node using the cmp - */ - use_am = get_irn_n_edges(cmp) <= 1; - - res = create_set(pnc, cmp_left, cmp_right, dbgi, block, use_am); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp)); - - return res; + /* this probably means not all mode_b nodes were lowered... */ + panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)", + node); } /** @@ -4441,8 +4761,6 @@ static ir_node *gen_Proj(ir_node *node) { return gen_Proj_CopyB(node); } else if (is_Quot(pred)) { return gen_Proj_Quot(node); - } else if (is_ia32_l_vfdiv(pred)) { - return gen_Proj_l_vfdiv(node); } else if (be_is_SubSP(pred)) { return gen_Proj_be_SubSP(node); } else if (be_is_AddSP(pred)) { @@ -4464,6 +4782,8 @@ static ir_node *gen_Proj(ir_node *node) { if (node == be_get_old_anchor(anchor_tls)) { return gen_Proj_tls(node); } + } else if (is_ia32_l_FloattoLL(pred)) { + return gen_Proj_l_FloattoLL(node); #ifdef FIRM_EXT_GRS } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization #else @@ -4525,6 +4845,7 @@ static void register_transformers(void) GEN(Store); GEN(Cond); + GEN(Cmp); GEN(ASM); GEN(CopyB); BAD(Mux); @@ -4534,29 +4855,23 @@ static void register_transformers(void) GEN(IJmp); /* transform ops from intrinsic lowering */ - GEN(ia32_Add64Bit); - GEN(ia32_Sub64Bit); GEN(ia32_l_Add); GEN(ia32_l_Adc); - GEN(ia32_l_Neg); GEN(ia32_l_Mul); GEN(ia32_l_IMul); GEN(ia32_l_ShlDep); GEN(ia32_l_ShrDep); - GEN(ia32_l_Sar); GEN(ia32_l_SarDep); GEN(ia32_l_ShlD); GEN(ia32_l_ShrD); - GEN(ia32_l_vfdiv); - GEN(ia32_l_vfprem); - GEN(ia32_l_vfmul); - GEN(ia32_l_vfsub); + GEN(ia32_l_Sub); + GEN(ia32_l_Sbb); GEN(ia32_l_vfild); GEN(ia32_l_Load); GEN(ia32_l_vfist); GEN(ia32_l_Store); - GEN(ia32_l_X87toSSE); - GEN(ia32_l_SSEtoX87); + GEN(ia32_l_LLtoFloat); + GEN(ia32_l_FloattoLL); GEN(Const); GEN(SymConst); @@ -4579,7 +4894,8 @@ static void register_transformers(void) /* handle generic backend nodes */ GEN(be_FrameAddr); - //GEN(be_Call); + GEN(be_Call); + GEN(be_IncSP); GEN(be_Return); GEN(be_AddSP); GEN(be_SubSP); @@ -4612,8 +4928,7 @@ static void ia32_pretransform_node(void *arch_cg) { * Walker, checks if all ia32 nodes producing more than one result have * its Projs, other wise creates new projs and keep them using a be_Keep node. */ -static -void add_missing_keep_walker(ir_node *node, void *data) +static void add_missing_keep_walker(ir_node *node, void *data) { int n_outs, i; unsigned found_projs = 0; @@ -4689,14 +5004,28 @@ void ia32_add_missing_keeps(ia32_code_gen_t *cg) /* do the transformation */ void ia32_transform_graph(ia32_code_gen_t *cg) { + int cse_last; + ir_graph *irg = cg->irg; + register_transformers(); env_cg = cg; initial_fpcw = NULL; - heights = heights_new(cg->irg); +BE_TIMER_PUSH(t_heights); + heights = heights_new(irg); +BE_TIMER_POP(t_heights); + ia32_calculate_non_address_mode_nodes(cg->birg); + + /* the transform phase is not safe for CSE (yet) because several nodes get + * attributes set after their creation */ + cse_last = get_opt_cse(); + set_opt_cse(0); be_transform_graph(cg->birg, ia32_pretransform_node, cg); + set_opt_cse(cse_last); + + ia32_free_non_address_mode_nodes(); heights_free(heights); heights = NULL; }