X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=3e03f84e34af02c623e9694126da4a01bc59e147;hb=f1522129041d11a7b887abb5a3d8d5a2908758bb;hp=cceca5141c182f97253cc82cdb84e62672f47c2c;hpb=57fb9fc8605ae538d91ca191301e0d3c111cc3ba;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index cceca5141..3e03f84e3 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -138,7 +138,7 @@ static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode, /** * Return true if a mode can be stored in the GP register set */ -static INLINE int mode_needs_gp_reg(ir_mode *mode) { +int ia32_mode_needs_gp_reg(ir_mode *mode) { if(mode == mode_fpcw) return 0; if(get_mode_size_bits(mode) > 32) @@ -164,7 +164,7 @@ static ident *unique_id(const char *tag) /** * Get a primitive type for a mode. */ -static ir_type *get_prim_type(pmap *types, ir_mode *mode) +ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode) { pmap_entry *e = pmap_find(types, mode); ir_type *res; @@ -182,21 +182,64 @@ static ir_type *get_prim_type(pmap *types, ir_mode *mode) } /** - * Get an atomic entity that is initialized with a tarval + * Creates an immediate. + * + * @param symconst if set, create a SymConst immediate + * @param symconst_sign sign for the symconst + * @param val integer value for the immediate + */ +static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val) +{ + ir_graph *irg = current_ir_graph; + ir_node *start_block = get_irg_start_block(irg); + ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, + symconst, symconst_sign, val); + arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]); + + return immediate; +} + +/** + * Get an atomic entity that is initialized with a tarval forming + * a given constant. + * + * @param cnst the node representing the constant */ static ir_entity *create_float_const_entity(ir_node *cnst) { ia32_isa_t *isa = env_cg->isa; - tarval *tv = get_Const_tarval(cnst); - pmap_entry *e = pmap_find(isa->tv_ent, tv); + tarval *key = get_Const_tarval(cnst); + pmap_entry *e = pmap_find(isa->tv_ent, key); ir_entity *res; ir_graph *rem; - if (! e) { - ir_mode *mode = get_irn_mode(cnst); - ir_type *tp = get_Const_type(cnst); - if (tp == firm_unknown_type) - tp = get_prim_type(isa->types, mode); + if (e == NULL) { + tarval *tv = key; + ir_mode *mode = get_tarval_mode(tv); + ir_type *tp; + + if (! ia32_cg_config.use_sse2) { + /* try to reduce the mode to produce smaller sized entities */ + if (mode != mode_F) { + if (tarval_ieee754_can_conv_lossless(tv, mode_F)) { + mode = mode_F; + tv = tarval_convert_to(tv, mode); + } else if (mode != mode_D) { + if (tarval_ieee754_can_conv_lossless(tv, mode_D)) { + mode = mode_D; + tv = tarval_convert_to(tv, mode); + } + } + } + } + + if (mode == get_irn_mode(cnst)) { + /* mode was not changed */ + tp = get_Const_type(cnst); + if (tp == firm_unknown_type) + tp = ia32_get_prim_type(isa->types, mode); + } else + tp = ia32_get_prim_type(isa->types, mode); res = new_entity(get_glob_type(), unique_id(".LC%u"), tp); @@ -212,7 +255,7 @@ static ir_entity *create_float_const_entity(ir_node *cnst) set_atomic_ent_value(res, new_Const_type(tv, tp)); current_ir_graph = rem; - pmap_insert(isa->tv_ent, tv, res); + pmap_insert(isa->tv_ent, key, res); } else { res = e->value; } @@ -220,14 +263,17 @@ static ir_entity *create_float_const_entity(ir_node *cnst) return res; } +/** Return non-zero is a node represents the 0 constant. */ static int is_Const_0(ir_node *node) { return is_Const(node) && is_Const_null(node); } +/** Return non-zero is a node represents the 1 constant. */ static int is_Const_1(ir_node *node) { return is_Const(node) && is_Const_one(node); } +/** Return non-zero is a node represents the -1 constant. */ static int is_Const_Minus_1(ir_node *node) { return is_Const(node) && is_Const_all_one(node); } @@ -238,10 +284,37 @@ static int is_Const_Minus_1(ir_node *node) { static int is_simple_x87_Const(ir_node *node) { tarval *tv = get_Const_tarval(node); + if (tarval_is_null(tv) || tarval_is_one(tv)) + return 1; + + /* TODO: match all the other float constants */ + return 0; +} + +/** + * returns true if constant can be created with a simple float command + */ +static int is_simple_sse_Const(ir_node *node) +{ + tarval *tv = get_Const_tarval(node); + ir_mode *mode = get_tarval_mode(tv); - if(tarval_is_null(tv) || tarval_is_one(tv)) + if (mode == mode_F) return 1; + if (tarval_is_null(tv) || tarval_is_one(tv)) + return 1; + + if (mode == mode_D) { + unsigned val = get_tarval_sub_bits(tv, 0) | + (get_tarval_sub_bits(tv, 1) << 8) | + (get_tarval_sub_bits(tv, 2) << 16) | + (get_tarval_sub_bits(tv, 3) << 24); + if (val == 0) + /* lower 32bit are zero, really a 32bit constant */ + return 1; + } + /* TODO: match all the other float constants */ return 0; } @@ -266,15 +339,62 @@ static ir_node *gen_Const(ir_node *node) { ir_entity *floatent; if (ia32_cg_config.use_sse2) { - if (is_Const_null(node)) { + tarval *tv = get_Const_tarval(node); + if (tarval_is_null(tv)) { load = new_rd_ia32_xZero(dbgi, irg, block); set_ia32_ls_mode(load, mode); res = load; + } else if (tarval_is_one(tv)) { + int cnst = mode == mode_F ? 26 : 55; + ir_node *imm1 = create_Immediate(NULL, 0, cnst); + ir_node *imm2 = create_Immediate(NULL, 0, 2); + ir_node *pslld, *psrld; + + load = new_rd_ia32_xAllOnes(dbgi, irg, block); + set_ia32_ls_mode(load, mode); + pslld = new_rd_ia32_xPslld(dbgi, irg, block, load, imm1); + set_ia32_ls_mode(pslld, mode); + psrld = new_rd_ia32_xPsrld(dbgi, irg, block, pslld, imm2); + set_ia32_ls_mode(psrld, mode); + res = psrld; + } else if (mode == mode_F) { + /* we can place any 32bit constant by using a movd gp, sse */ + unsigned val = get_tarval_sub_bits(tv, 0) | + (get_tarval_sub_bits(tv, 1) << 8) | + (get_tarval_sub_bits(tv, 2) << 16) | + (get_tarval_sub_bits(tv, 3) << 24); + ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val); + load = new_rd_ia32_xMovd(dbgi, irg, block, cnst); + set_ia32_ls_mode(load, mode); + res = load; } else { + if (mode == mode_D) { + unsigned val = get_tarval_sub_bits(tv, 0) | + (get_tarval_sub_bits(tv, 1) << 8) | + (get_tarval_sub_bits(tv, 2) << 16) | + (get_tarval_sub_bits(tv, 3) << 24); + if (val == 0) { + ir_node *imm32 = create_Immediate(NULL, 0, 32); + ir_node *cnst, *psllq; + + /* fine, lower 32bit are zero, produce 32bit value */ + val = get_tarval_sub_bits(tv, 4) | + (get_tarval_sub_bits(tv, 5) << 8) | + (get_tarval_sub_bits(tv, 6) << 16) | + (get_tarval_sub_bits(tv, 7) << 24); + cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val); + load = new_rd_ia32_xMovd(dbgi, irg, block, cnst); + set_ia32_ls_mode(load, mode); + psllq = new_rd_ia32_xPsllq(dbgi, irg, block, load, imm32); + set_ia32_ls_mode(psllq, mode); + res = psllq; + goto end; + } + } floatent = create_float_const_entity(node); load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, - mode); + mode); set_ia32_op_type(load, ia32_AddrModeS); set_ia32_am_sc(load, floatent); set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable); @@ -284,9 +404,11 @@ static ir_node *gen_Const(ir_node *node) { if (is_Const_null(node)) { load = new_rd_ia32_vfldz(dbgi, irg, block); res = load; + set_ia32_ls_mode(load, mode); } else if (is_Const_one(node)) { load = new_rd_ia32_vfld1(dbgi, irg, block); res = load; + set_ia32_ls_mode(load, mode); } else { floatent = create_float_const_entity(node); @@ -295,12 +417,11 @@ static ir_node *gen_Const(ir_node *node) { set_ia32_am_sc(load, floatent); set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable); res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res); + /* take the mode from the entity */ + set_ia32_ls_mode(load, get_type_mode(get_entity_type(floatent))); } - set_ia32_ls_mode(load, mode); } - - SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); - +end: /* Const Nodes before the initial IncSP are a bad idea, because * they could be spilled and we have no SP ready at that point yet. * So add a dependency to the initial frame pointer calculation to @@ -312,15 +433,15 @@ static ir_node *gen_Const(ir_node *node) { SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); return res; - } else { + } else { /* non-float mode */ ir_node *cnst; tarval *tv = get_Const_tarval(node); long val; tv = tarval_convert_to(tv, mode_Iu); - if(tv == get_tarval_bad() || tv == get_tarval_undefined() - || tv == NULL) { + if (tv == get_tarval_bad() || tv == get_tarval_undefined() || + tv == NULL) { panic("couldn't convert constant tarval (%+F)", node); } val = get_tarval_long(tv); @@ -448,7 +569,7 @@ ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) { * Prints the old node name on cg obst and returns a pointer to it. */ const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) { - ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa; + ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env; lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn); obstack_1grow(isa->name_obst, 0); @@ -463,44 +584,51 @@ const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) { * input here, for unary operations use NULL). */ static int ia32_use_source_address_mode(ir_node *block, ir_node *node, - ir_node *other, ir_node *other2) + ir_node *other, ir_node *other2, match_flags_t flags) { - ir_mode *mode = get_irn_mode(node); ir_node *load; long pn; /* float constants are always available */ - if(is_Const(node) && mode_is_float(mode)) { - if(!is_simple_x87_Const(node)) - return 0; - if(get_irn_n_edges(node) > 1) - return 0; - return 1; + if (is_Const(node)) { + ir_mode *mode = get_irn_mode(node); + if (mode_is_float(mode)) { + if (ia32_cg_config.use_sse2) { + if (is_simple_sse_Const(node)) + return 0; + } else { + if (is_simple_x87_Const(node)) + return 0; + } + if (get_irn_n_edges(node) > 1) + return 0; + return 1; + } } - if(!is_Proj(node)) + if (!is_Proj(node)) return 0; load = get_Proj_pred(node); pn = get_Proj_proj(node); - if(!is_Load(load) || pn != pn_Load_res) + if (!is_Load(load) || pn != pn_Load_res) return 0; - if(get_nodes_block(load) != block) + if (get_nodes_block(load) != block) return 0; /* we only use address mode if we're the only user of the load */ - if(get_irn_n_edges(node) > 1) + if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1)) return 0; /* in some edge cases with address mode we might reach the load normally * and through some AM sequence, if it is already materialized then we * can't create an AM node from it */ - if(be_is_transformed(node)) + if (be_is_transformed(node)) return 0; /* don't do AM if other node inputs depend on the load (via mem-proj) */ - if(other != NULL && get_nodes_block(other) == block - && heights_reachable_in_block(heights, other, load)) + if (other != NULL && get_nodes_block(other) == block && + heights_reachable_in_block(heights, other, load)) return 0; - if(other2 != NULL && get_nodes_block(other2) == block - && heights_reachable_in_block(heights, other2, load)) + if (other2 != NULL && get_nodes_block(other2) == block && + heights_reachable_in_block(heights, other2, load)) return 0; return 1; @@ -521,12 +649,13 @@ struct ia32_address_mode_t { static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem) { - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); + ir_node *noreg_gp; /* construct load address */ memset(addr, 0, sizeof(addr[0])); ia32_create_address_mode(addr, ptr, /*force=*/0); + noreg_gp = ia32_new_NoReg_gp(env_cg); addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp; addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp; addr->mem = be_transform_node(mem); @@ -541,14 +670,14 @@ static void build_address(ia32_address_mode_t *am, ir_node *node) ir_node *mem; ir_node *new_mem; - if(is_Const(node)) { + if (is_Const(node)) { ir_entity *entity = create_float_const_entity(node); addr->base = noreg_gp; addr->index = noreg_gp; addr->mem = new_NoMem(); addr->symconst_ent = entity; addr->use_frame = 1; - am->ls_mode = get_irn_mode(node); + am->ls_mode = get_type_mode(get_entity_type(entity)); am->pinned = op_pin_state_floats; return; } @@ -581,16 +710,21 @@ static void set_address(ir_node *node, const ia32_address_t *addr) set_ia32_frame_ent(node, addr->frame_entity); } +/** + * Apply attributes of a given address mode to a node. + */ static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am) { set_address(node, &am->addr); set_ia32_op_type(node, am->op_type); set_ia32_ls_mode(node, am->ls_mode); - if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) { - set_irn_pinned(node, am->pinned); + if (am->pinned == op_pin_state_pinned) { + /* beware: some nodes are already pinned and did not allow to change the state */ + if (get_irn_pinned(node) != op_pin_state_pinned) + set_irn_pinned(node, op_pin_state_pinned); } - if(am->commutative) + if (am->commutative) set_ia32_commutative(node); } @@ -618,8 +752,8 @@ static int is_downconv(const ir_node *node) src_mode = get_irn_mode(get_Conv_op(node)); dest_mode = get_irn_mode(node); - return mode_needs_gp_reg(src_mode) - && mode_needs_gp_reg(dest_mode) + return ia32_mode_needs_gp_reg(src_mode) + && ia32_mode_needs_gp_reg(dest_mode) && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode); } @@ -631,7 +765,6 @@ ir_node *ia32_skip_downconv(ir_node *node) { return node; } -#if 0 static ir_node *create_upconv(ir_node *node, ir_node *orig_node) { ir_mode *mode = get_irn_mode(node); @@ -649,7 +782,6 @@ static ir_node *create_upconv(ir_node *node, ir_node *orig_node) return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node); } -#endif /** * matches operands of a node into ia32 addressing/operand modes. This covers @@ -666,16 +798,14 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, ir_node *op1, ir_node *op2, ir_node *other_op, match_flags_t flags) { - ia32_address_t *addr = &am->addr; - ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg); - ir_node *new_op1; - ir_node *new_op2; - ir_mode *mode = get_irn_mode(op2); + ia32_address_t *addr = &am->addr; + ir_mode *mode = get_irn_mode(op2); + int mode_bits = get_mode_size_bits(mode); + ir_node *noreg_gp, *new_op1, *new_op2; int use_am; unsigned commutative; int use_am_and_immediates; int use_immediate; - int mode_bits = get_mode_size_bits(mode); memset(am, 0, sizeof(am[0])); @@ -690,13 +820,13 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, assert(use_am || !(flags & match_8bit_am)); assert(use_am || !(flags & match_16bit_am)); - if(mode_bits == 8) { - if (! (flags & match_8bit_am)) + if (mode_bits == 8) { + if (!(flags & match_8bit_am)) use_am = 0; /* we don't automatically add upconvs yet */ assert((flags & match_mode_neutral) || (flags & match_8bit)); - } else if(mode_bits == 16) { - if(! (flags & match_16bit_am)) + } else if (mode_bits == 16) { + if (!(flags & match_16bit_am)) use_am = 0; /* we don't automatically add upconvs yet */ assert((flags & match_mode_neutral) || (flags & match_16bit)); @@ -704,9 +834,9 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, /* we can simply skip downconvs for mode neutral nodes: the upper bits * can be random for these operations */ - if(flags & match_mode_neutral) { + if (flags & match_mode_neutral) { op2 = ia32_skip_downconv(op2); - if(op1 != NULL) { + if (op1 != NULL) { op1 = ia32_skip_downconv(op1); } } @@ -714,33 +844,34 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, /* match immediates. firm nodes are normalized: constants are always on the * op2 input */ new_op2 = NULL; - if(! (flags & match_try_am) && use_immediate) { + if (!(flags & match_try_am) && use_immediate) { new_op2 = try_create_Immediate(op2, 0); } - if(new_op2 == NULL - && use_am && ia32_use_source_address_mode(block, op2, op1, other_op)) { + noreg_gp = ia32_new_NoReg_gp(env_cg); + if (new_op2 == NULL && + use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) { build_address(am, op2); new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); - if(mode_is_float(mode)) { + if (mode_is_float(mode)) { new_op2 = ia32_new_NoReg_vfp(env_cg); } else { new_op2 = noreg_gp; } am->op_type = ia32_AddrModeS; - } else if(commutative && (new_op2 == NULL || use_am_and_immediates) && - use_am - && ia32_use_source_address_mode(block, op1, op2, other_op)) { + } else if (commutative && (new_op2 == NULL || use_am_and_immediates) && + use_am && + ia32_use_source_address_mode(block, op1, op2, other_op, flags)) { ir_node *noreg; build_address(am, op1); - if(mode_is_float(mode)) { + if (mode_is_float(mode)) { noreg = ia32_new_NoReg_vfp(env_cg); } else { noreg = noreg_gp; } - if(new_op2 != NULL) { + if (new_op2 != NULL) { new_op1 = noreg; } else { new_op1 = be_transform_node(op2); @@ -749,7 +880,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } am->op_type = ia32_AddrModeS; } else { - if(flags & match_try_am) { + if (flags & match_try_am) { am->new_op1 = NULL; am->new_op2 = NULL; am->op_type = ia32_Normal; @@ -757,18 +888,18 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); - if(new_op2 == NULL) + if (new_op2 == NULL) new_op2 = be_transform_node(op2); am->op_type = ia32_Normal; am->ls_mode = get_irn_mode(op2); - if(flags & match_mode_neutral) + if (flags & match_mode_neutral) am->ls_mode = mode_Iu; } - if(addr->base == NULL) + if (addr->base == NULL) addr->base = noreg_gp; - if(addr->index == NULL) + if (addr->index == NULL) addr->index = noreg_gp; - if(addr->mem == NULL) + if (addr->mem == NULL) addr->mem = new_NoMem(); am->new_op1 = new_op1; @@ -778,11 +909,10 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) { - ir_graph *irg = current_ir_graph; ir_mode *mode; ir_node *load; - if(am->mem_proj == NULL) + if (am->mem_proj == NULL) return node; /* we have to create a mode_T so the old MemProj can attach to us */ @@ -792,9 +922,9 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) mark_irn_visited(load); be_set_transformed_node(load, node); - if(mode != mode_T) { + if (mode != mode_T) { set_irn_mode(node, mode_T); - return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res); + return new_rd_Proj(NULL, current_ir_graph, get_nodes_block(node), node, mode, pn_ia32_res); } else { return node; } @@ -803,6 +933,7 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) /** * Construct a standard binary operation, set AM and immediate if required. * + * @param node The original node for which the binop is created * @param op1 The first operand * @param op2 The second operand * @param func The node constructor function @@ -811,21 +942,22 @@ static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am) static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2, construct_binop_func *func, match_flags_t flags) { - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_block, *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; + block = get_nodes_block(node); match_arguments(&am, block, op1, op2, NULL, flags); - new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem, - am.new_op1, am.new_op2); + dbgi = get_irn_dbg_info(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, + addr->base, addr->index, addr->mem, + am.new_op1, am.new_op2); set_am_attributes(new_node, &am); /* we can't use source address mode anymore when using immediates */ - if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) + if (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -839,12 +971,12 @@ enum { n_ia32_l_binop_right, n_ia32_l_binop_eflags }; -COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left) -COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right) -COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags) -COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left) -COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right) -COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags) +COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left) +COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right) +COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags) +COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_minuend, n_Sbb_minuend) +COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend) +COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags) /** * Construct a binary operation which also consumes the eflags. @@ -858,21 +990,21 @@ static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, match_flags_t flags) { ir_node *src_block = get_nodes_block(node); - ir_node *block = be_transform_node(src_block); ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left); ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right); - ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags); - ir_node *new_eflags = be_transform_node(eflags); - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_node, *eflags, *new_eflags; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; match_arguments(&am, src_block, op1, op2, NULL, flags); - new_node = func(dbgi, irg, block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, new_eflags); + dbgi = get_irn_dbg_info(node); + block = be_transform_node(src_block); + eflags = get_irn_n(node, n_ia32_l_binop_eflags); + new_eflags = be_transform_node(eflags); + new_node = func(dbgi, current_ir_graph, block, addr->base, addr->index, + addr->mem, am.new_op1, am.new_op2, new_eflags); set_am_attributes(new_node, &am); /* we can't use source address mode anymore when using immediates */ if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)) @@ -887,7 +1019,7 @@ static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func, static ir_node *get_fpcw(void) { ir_node *fpcw; - if(initial_fpcw != NULL) + if (initial_fpcw != NULL) return initial_fpcw; fpcw = be_abi_get_ignore_irn(env_cg->birg->abi, @@ -909,23 +1041,24 @@ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, construct_binop_float_func *func, match_flags_t flags) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_mode *mode = get_irn_mode(node); - ir_node *new_node; + ir_mode *mode = get_irn_mode(node); + dbg_info *dbgi; + ir_node *block, *new_block, *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - /* cannot use addresmode with long double on x87 */ + /* cannot use address mode with long double on x87 */ if (get_mode_size_bits(mode) > 64) flags &= ~match_am; + block = get_nodes_block(node); match_arguments(&am, block, op1, op2, NULL, flags); - new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem, - am.new_op1, am.new_op2, get_fpcw()); + dbgi = get_irn_dbg_info(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, + addr->base, addr->index, addr->mem, + am.new_op1, am.new_op2, get_fpcw()); set_am_attributes(new_node, &am); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -947,22 +1080,21 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, construct_shift_func *func, match_flags_t flags) { - dbg_info *dbgi = get_irn_dbg_info(node); - ir_graph *irg = current_ir_graph; - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *new_op1; - ir_node *new_op2; - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_block, *new_op1, *new_op2, *new_node; assert(! mode_is_float(get_irn_mode(node))); assert(flags & match_immediate); assert((flags & ~(match_mode_neutral | match_immediate)) == 0); - if(flags & match_mode_neutral) { - op1 = ia32_skip_downconv(op1); + if (flags & match_mode_neutral) { + op1 = ia32_skip_downconv(op1); + new_op1 = be_transform_node(op1); + } else if (get_mode_size_bits(get_irn_mode(node)) != 32) { + new_op1 = create_upconv(op1, node); + } else { + new_op1 = be_transform_node(op1); } - new_op1 = be_transform_node(op1); /* the shift amount can be any mode that is bigger than 5 bits, since all * other bits are ignored anyway */ @@ -972,7 +1104,10 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, } new_op2 = create_immediate_or_transform(op2, 0); - new_node = func(dbgi, irg, new_block, new_op1, new_op2); + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, new_op1, new_op2); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); /* lowered shift instruction may have a dependency operand, handle it here */ @@ -996,20 +1131,19 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, match_flags_t flags) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *new_op; - ir_node *new_node; + dbg_info *dbgi; + ir_node *block, *new_block, *new_op, *new_node; assert(flags == 0 || flags == match_mode_neutral); - if(flags & match_mode_neutral) { + if (flags & match_mode_neutral) { op = ia32_skip_downconv(op); } - new_op = be_transform_node(op); - new_node = func(dbgi, irg, new_block, new_op); + new_op = be_transform_node(op); + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + new_block = be_transform_node(block); + new_node = func(dbgi, current_ir_graph, new_block, new_op); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -1019,29 +1153,32 @@ static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, ia32_address_t *addr) { - ir_graph *irg = current_ir_graph; - ir_node *base = addr->base; - ir_node *index = addr->index; - ir_node *res; + ir_node *base, *index, *res; - if(base == NULL) { + base = addr->base; + if (base == NULL) { base = ia32_new_NoReg_gp(env_cg); } else { base = be_transform_node(base); } - if(index == NULL) { + index = addr->index; + if (index == NULL) { index = ia32_new_NoReg_gp(env_cg); } else { index = be_transform_node(index); } - res = new_rd_ia32_Lea(dbgi, irg, block, base, index); + res = new_rd_ia32_Lea(dbgi, current_ir_graph, block, base, index); set_address(res, addr); return res; } +/** + * Returns non-zero if a given address mode has a symbolic or + * numerical offset != 0. + */ static int am_has_immediates(const ia32_address_t *addr) { return addr->offset != 0 || addr->symconst_ent != NULL @@ -1054,15 +1191,11 @@ static int am_has_immediates(const ia32_address_t *addr) * @return the created ia32 Add node */ static ir_node *gen_Add(ir_node *node) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *op1 = get_Add_left(node); - ir_node *op2 = get_Add_right(node); - ir_mode *mode = get_irn_mode(node); - ir_node *new_node; - ir_node *add_immediate_op; + ir_mode *mode = get_irn_mode(node); + ir_node *op1 = get_Add_left(node); + ir_node *op2 = get_Add_right(node); + dbg_info *dbgi; + ir_node *block, *new_block, *new_node, *add_immediate_op; ia32_address_t addr; ia32_address_mode_t am; @@ -1090,8 +1223,14 @@ static ir_node *gen_Add(ir_node *node) { memset(&addr, 0, sizeof(addr)); ia32_create_address_mode(&addr, node, /*force=*/1); add_immediate_op = NULL; + + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + new_block = be_transform_node(block); + /* a constant? */ if(addr.base == NULL && addr.index == NULL) { + ir_graph *irg = current_ir_graph; new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent, addr.symconst_sign, addr.offset); add_irn_dep(new_node, get_irg_frame(irg)); @@ -1125,6 +1264,7 @@ static ir_node *gen_Add(ir_node *node) { /* construct an Add with source address mode */ if (am.op_type == ia32_AddrModeS) { + ir_graph *irg = current_ir_graph; ia32_address_t *am_addr = &am.addr; new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base, am_addr->index, am_addr->mem, am.new_op1, @@ -1161,10 +1301,6 @@ static ir_node *gen_Mul(ir_node *node) { return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, match_commutative | match_am); } - - /* for the lower 32bit of the result it doesn't matter whether we use - * signed or unsigned multiplication so we use IMul as it has fewer - * constraints */ return gen_binop(node, op1, op2, new_rd_ia32_IMul, match_commutative | match_am | match_mode_neutral | match_immediate | match_am_and_immediates); @@ -1257,7 +1393,6 @@ static ir_node *gen_And(ir_node *node) { return res; } } - return gen_binop(node, op1, op2, new_rd_ia32_And, match_commutative | match_mode_neutral | match_am | match_immediate); @@ -1314,7 +1449,7 @@ static ir_node *gen_Sub(ir_node *node) { match_am); } - if(is_Const(op2)) { + if (is_Const(op2)) { ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n", node); } @@ -1340,33 +1475,28 @@ static ir_node *create_Div(ir_node *node) ir_node *new_node; ir_mode *mode; ir_node *sign_extension; - int has_exc; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; /* the upper bits have random contents for smaller modes */ - has_exc = 0; switch (get_irn_opcode(node)) { case iro_Div: op1 = get_Div_left(node); op2 = get_Div_right(node); mem = get_Div_mem(node); mode = get_Div_resmode(node); - has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL; break; case iro_Mod: op1 = get_Mod_left(node); op2 = get_Mod_right(node); mem = get_Mod_mem(node); mode = get_Mod_resmode(node); - has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL; break; case iro_DivMod: op1 = get_DivMod_left(node); op2 = get_DivMod_right(node); mem = get_DivMod_mem(node); mode = get_DivMod_resmode(node); - has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL; break; default: panic("invalid divmod node %+F", node); @@ -1374,7 +1504,10 @@ static ir_node *create_Div(ir_node *node) match_arguments(&am, block, op1, op2, NULL, match_am); - if(!is_NoMem(mem)) { + /* Beware: We don't need a Sync, if the memory predecessor of the Div node + is the memory of the consumed address. We can have only the second op as address + in Div nodes, so check only op2. */ + if(!is_NoMem(mem) && skip_Proj(mem) != skip_Proj(op2)) { new_mem = be_transform_node(mem); if(!is_NoMem(addr->mem)) { ir_node *in[2]; @@ -1393,18 +1526,17 @@ static ir_node *create_Div(ir_node *node) produceval); new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base, - addr->index, new_mem, am.new_op1, - sign_extension, am.new_op2); + addr->index, new_mem, am.new_op2, + am.new_op1, sign_extension); } else { sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0); add_irn_dep(sign_extension, get_irg_frame(irg)); new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base, - addr->index, new_mem, am.new_op1, - sign_extension, am.new_op2); + addr->index, new_mem, am.new_op2, + am.new_op1, sign_extension); } - set_ia32_exc_label(new_node, has_exc); set_irn_pinned(new_node, get_irn_pinned(node)); set_am_attributes(new_node, &am); @@ -1437,8 +1569,8 @@ static ir_node *gen_DivMod(ir_node *node) { */ static ir_node *gen_Quot(ir_node *node) { - ir_node *op1 = get_Quot_left(node); - ir_node *op2 = get_Quot_right(node); + ir_node *op1 = get_Quot_left(node); + ir_node *op2 = get_Quot_right(node); if (ia32_cg_config.use_sse2) { return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am); @@ -1538,20 +1670,20 @@ static ir_node *gen_Shrs(ir_node *node) { /** - * Creates an ia32 RotL. + * Creates an ia32 Rol. * * @param op1 The first operator * @param op2 The second operator * @return The created ia32 RotL node */ -static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) { +static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) { return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate); } /** - * Creates an ia32 RotR. + * Creates an ia32 Ror. * NOTE: There is no RotR with immediate because this would always be a RotL * "imm-mode_size_bits" which can be pre-calculated. * @@ -1559,7 +1691,7 @@ static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) { * @param op2 The second operator * @return The created ia32 RotR node */ -static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) { +static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) { return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate); } @@ -1570,16 +1702,16 @@ static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) { * * @return The created ia32 RotL or RotR node */ -static ir_node *gen_Rot(ir_node *node) { +static ir_node *gen_Rotl(ir_node *node) { ir_node *rotate = NULL; - ir_node *op1 = get_Rot_left(node); - ir_node *op2 = get_Rot_right(node); + ir_node *op1 = get_Rotl_left(node); + ir_node *op2 = get_Rotl_right(node); - /* Firm has only Rot (which is a RotL), so we are looking for a right (op2) + /* Firm has only RotL, so we are looking for a right (op2) operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e", that means we can create a RotR instead of an Add and a RotL */ - if (get_irn_op(op2) == op_Add) { + if (is_Add(op2)) { ir_node *add = op2; ir_node *left = get_Add_left(add); ir_node *right = get_Add_right(add); @@ -1588,19 +1720,19 @@ static ir_node *gen_Rot(ir_node *node) { ir_mode *mode = get_irn_mode(node); long bits = get_mode_size_bits(mode); - if (get_irn_op(left) == op_Minus && - tarval_is_long(tv) && - get_tarval_long(tv) == bits && - bits == 32) + if (is_Minus(left) && + tarval_is_long(tv) && + get_tarval_long(tv) == bits && + bits == 32) { DB((dbg, LEVEL_1, "RotL into RotR ... ")); - rotate = gen_RotR(node, op1, get_Minus_op(left)); + rotate = gen_Ror(node, op1, get_Minus_op(left)); } } } if (rotate == NULL) { - rotate = gen_RotL(node, op1, op2); + rotate = gen_Rol(node, op1, op2); } return rotate; @@ -1740,9 +1872,27 @@ static ir_node *gen_Abs(ir_node *node) return new_node; } +/** + * Create a bt instruction for x & (1 << n) and place it into the block of cmp. + */ +static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) { + dbg_info *dbgi = get_irn_dbg_info(cmp); + ir_node *block = get_nodes_block(cmp); + ir_node *new_block = be_transform_node(block); + ir_node *op1 = be_transform_node(x); + ir_node *op2 = be_transform_node(n); + + return new_rd_ia32_Bt(dbgi, current_ir_graph, new_block, op1, op2); +} + +/** + * Transform a node returning a "flag" result. + * + * @param node the node to transform + * @param pnc_out the compare mode to use + */ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) { - ir_graph *irg = current_ir_graph; ir_node *flags; ir_node *new_op; ir_node *noreg; @@ -1751,11 +1901,48 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) dbg_info *dbgi; /* we have a Cmp as input */ - if(is_Proj(node)) { + if (is_Proj(node)) { ir_node *pred = get_Proj_pred(node); - if(is_Cmp(pred)) { + if (is_Cmp(pred)) { + pn_Cmp pnc = get_Proj_proj(node); + if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) { + ir_node *l = get_Cmp_left(pred); + ir_node *r = get_Cmp_right(pred); + if (is_And(l)) { + ir_node *la = get_And_left(l); + ir_node *ra = get_And_right(l); + if (is_Shl(la)) { + ir_node *c = get_Shl_left(la); + if (is_Const_1(c) && (is_Const_0(r) || r == la)) { + /* (1 << n) & ra) */ + ir_node *n = get_Shl_right(la); + flags = gen_bt(pred, ra, n); + /* we must generate a Jc/Jnc jump */ + pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge; + if (r == la) + pnc ^= pn_Cmp_Leg; + *pnc_out = ia32_pn_Cmp_unsigned | pnc; + return flags; + } + } + if (is_Shl(ra)) { + ir_node *c = get_Shl_left(ra); + if (is_Const_1(c) && (is_Const_0(r) || r == ra)) { + /* la & (1 << n)) */ + ir_node *n = get_Shl_right(ra); + flags = gen_bt(pred, la, n); + /* we must generate a Jc/Jnc jump */ + pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge; + if (r == ra) + pnc ^= pn_Cmp_Leg; + *pnc_out = ia32_pn_Cmp_unsigned | pnc; + return flags; + } + } + } + } flags = be_transform_node(pred); - *pnc_out = get_Proj_proj(node); + *pnc_out = pnc; return flags; } } @@ -1766,8 +1953,8 @@ static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) new_op = be_transform_node(node); noreg = ia32_new_NoReg_gp(env_cg); nomem = new_NoMem(); - flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem, - new_op, new_op, 0, 0); + flags = new_rd_ia32_Test(dbgi, current_ir_graph, new_block, noreg, noreg, nomem, + new_op, new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0); *pnc_out = pn_Cmp_Lg; return flags; } @@ -1850,8 +2037,6 @@ static ir_node *gen_Load(ir_node *node) { add_irn_dep(new_node, get_irg_frame(irg)); } - set_ia32_exc_label(new_node, - be_get_Proj_for_pn(node, pn_Load_X_except) != NULL); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); return new_node; @@ -1890,6 +2075,12 @@ static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem, return 1; } +static void set_transformed_and_mark(ir_node *const old_node, ir_node *const new_node) +{ + mark_irn_visited(old_node); + be_set_transformed_node(old_node, new_node); +} + static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, ir_node *mem, ir_node *ptr, ir_mode *mode, construct_binop_dest_func *func, @@ -1903,6 +2094,7 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, dbg_info *dbgi; ir_node *new_node; ir_node *new_op; + ir_node *mem_proj; int commutative; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; @@ -1943,6 +2135,10 @@ static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2, set_ia32_ls_mode(new_node, mode); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + set_transformed_and_mark(get_Proj_pred(am.mem_proj), new_node); + mem_proj = be_transform_node(am.mem_proj); + set_transformed_and_mark(mem_proj ? mem_proj : am.mem_proj, new_node); + return new_node; } @@ -1955,6 +2151,7 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, ir_node *block; dbg_info *dbgi; ir_node *new_node; + ir_node *mem_proj; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; memset(&am, 0, sizeof(am)); @@ -1972,6 +2169,10 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, set_ia32_ls_mode(new_node, mode); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + set_transformed_and_mark(get_Proj_pred(am.mem_proj), new_node); + mem_proj = be_transform_node(am.mem_proj); + set_transformed_and_mark(mem_proj ? mem_proj : am.mem_proj, new_node); + return new_node; } @@ -2032,7 +2233,7 @@ static ir_node *try_create_dest_am(ir_node *node) { ir_node *new_node; /* handle only GP modes for now... */ - if(!mode_needs_gp_reg(mode)) + if(!ia32_mode_needs_gp_reg(mode)) return NULL; while(1) { @@ -2055,7 +2256,7 @@ static ir_node *try_create_dest_am(ir_node *node) { if(get_nodes_block(node) != get_nodes_block(val)) return NULL; - switch(get_irn_opcode(val)) { + switch (get_irn_opcode(val)) { case iro_Add: op1 = get_Add_left(val); op2 = get_Add_right(val); @@ -2130,9 +2331,9 @@ static ir_node *try_create_dest_am(ir_node *node) { new_rd_ia32_SarMem, new_rd_ia32_SarMem, match_dest_am | match_immediate); break; - case iro_Rot: - op1 = get_Rot_left(val); - op2 = get_Rot_right(val); + case iro_Rotl: + op1 = get_Rotl_left(val); + op2 = get_Rotl_right(val); new_node = dest_am_binop(val, op1, op2, mem, ptr, mode, new_rd_ia32_RolMem, new_rd_ia32_RolMem, match_dest_am | match_immediate); @@ -2171,7 +2372,7 @@ static int is_float_to_int32_conv(const ir_node *node) ir_node *conv_op; ir_mode *conv_mode; - if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode)) + if(get_mode_size_bits(mode) != 32 || !ia32_mode_needs_gp_reg(mode)) return 0; if(!is_Conv(node)) @@ -2186,41 +2387,146 @@ static int is_float_to_int32_conv(const ir_node *node) } /** - * Transforms a Store. + * Transform a Store(floatConst). * * @return the created ia32 Store node */ -static ir_node *gen_Store(ir_node *node) -{ +static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) { + ir_mode *mode = get_irn_mode(cns); + int size = get_mode_size_bits(mode); + tarval *tv = get_Const_tarval(cns); ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); ir_node *ptr = get_Store_ptr(node); - ir_node *val = get_Store_value(node); ir_node *mem = get_Store_mem(node); ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *noreg = ia32_new_NoReg_gp(env_cg); - ir_mode *mode = get_irn_mode(val); - ir_node *new_val; + int ofs = 4; ir_node *new_node; ia32_address_t addr; + unsigned val = get_tarval_sub_bits(tv, 0) | + (get_tarval_sub_bits(tv, 1) << 8) | + (get_tarval_sub_bits(tv, 2) << 16) | + (get_tarval_sub_bits(tv, 3) << 24); + ir_node *imm = create_Immediate(NULL, 0, val); + + /* construct store address */ + memset(&addr, 0, sizeof(addr)); + ia32_create_address_mode(&addr, ptr, /*force=*/0); + + if (addr.base == NULL) { + addr.base = noreg; + } else { + addr.base = be_transform_node(addr.base); + } + + if (addr.index == NULL) { + addr.index = noreg; + } else { + addr.index = be_transform_node(addr.index); + } + addr.mem = be_transform_node(mem); + + new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base, + addr.index, addr.mem, imm); + + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeD); + set_ia32_ls_mode(new_node, mode_Iu); + + set_address(new_node, &addr); + + /** add more stores if needed */ + while (size > 32) { + unsigned val = get_tarval_sub_bits(tv, ofs) | + (get_tarval_sub_bits(tv, ofs + 1) << 8) | + (get_tarval_sub_bits(tv, ofs + 2) << 16) | + (get_tarval_sub_bits(tv, ofs + 3) << 24); + ir_node *imm = create_Immediate(NULL, 0, val); + + addr.offset += 4; + addr.mem = new_node; + + new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base, + addr.index, addr.mem, imm); + + set_irn_pinned(new_node, get_irn_pinned(node)); + set_ia32_op_type(new_node, ia32_AddrModeD); + set_ia32_ls_mode(new_node, mode_Iu); + + set_address(new_node, &addr); + size -= 32; + ofs += 4; + } + + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + return new_node; +} + +/** + * Generate a vfist or vfisttp instruction. + */ +static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, + ir_node *mem, ir_node *val, ir_node **fist) +{ + ir_node *new_node; + + if (ia32_cg_config.use_fisttp) { + /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied + if other users exists */ + const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp]; + ir_node *vfisttp = new_rd_ia32_vfisttp(dbgi, irg, block, base, index, mem, val); + ir_node *value = new_r_Proj(irg, block, vfisttp, mode_E, pn_ia32_vfisttp_res); + be_new_Keep(reg_class, irg, block, 1, &value); + + new_node = new_r_Proj(irg, block, vfisttp, mode_M, pn_ia32_vfisttp_M); + *fist = vfisttp; + } else { + ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); + + /* do a fist */ + new_node = new_rd_ia32_vfist(dbgi, irg, block, base, index, mem, val, trunc_mode); + *fist = new_node; + } + return new_node; +} +/** + * Transforms a normal Store. + * + * @return the created ia32 Store node + */ +static ir_node *gen_normal_Store(ir_node *node) +{ + ir_node *val = get_Store_value(node); + ir_mode *mode = get_irn_mode(val); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *ptr = get_Store_ptr(node); + ir_node *mem = get_Store_mem(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + ir_node *new_val, *new_node, *store; + ia32_address_t addr; + /* check for destination address mode */ new_node = try_create_dest_am(node); - if(new_node != NULL) + if (new_node != NULL) return new_node; /* construct store address */ memset(&addr, 0, sizeof(addr)); ia32_create_address_mode(&addr, ptr, /*force=*/0); - if(addr.base == NULL) { + if (addr.base == NULL) { addr.base = noreg; } else { addr.base = be_transform_node(addr.base); } - if(addr.index == NULL) { + if (addr.index == NULL) { addr.index = noreg; } else { addr.index = be_transform_node(addr.index); @@ -2228,10 +2534,13 @@ static ir_node *gen_Store(ir_node *node) addr.mem = be_transform_node(mem); if (mode_is_float(mode)) { - /* convs (and strict-convs) before stores are unnecessary if the mode - is the same */ - while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) { - val = get_Conv_op(val); + /* Convs (and strict-Convs) before stores are unnecessary if the mode + is the same. */ + while (is_Conv(val) && mode == get_irn_mode(val)) { + ir_node *op = get_Conv_op(val); + if (!mode_is_float(get_irn_mode(op))) + break; + val = op; } new_val = be_transform_node(val); if (ia32_cg_config.use_sse2) { @@ -2241,19 +2550,16 @@ static ir_node *gen_Store(ir_node *node) new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val, mode); } - } else if(is_float_to_int32_conv(val)) { - ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); + store = new_node; + } else if (!ia32_cg_config.use_sse2 && is_float_to_int32_conv(val)) { val = get_Conv_op(val); - /* convs (and strict-convs) before stores are unnecessary if the mode - is the same */ - while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) { + /* We can skip ALL Convs (and strict-Convs) before stores. */ + while (is_Conv(val)) { val = get_Conv_op(val); } - new_val = be_transform_node(val); - - new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base, - addr.index, addr.mem, new_val, trunc_mode); + new_val = be_transform_node(val); + new_node = gen_vfist(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val, &store); } else { new_val = create_immediate_or_transform(val, 0); assert(mode != mode_b); @@ -2265,20 +2571,49 @@ static ir_node *gen_Store(ir_node *node) new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val); } + store = new_node; } - set_irn_pinned(new_node, get_irn_pinned(node)); - set_ia32_op_type(new_node, ia32_AddrModeD); - set_ia32_ls_mode(new_node, mode); + set_irn_pinned(store, get_irn_pinned(node)); + set_ia32_op_type(store, ia32_AddrModeD); + set_ia32_ls_mode(store, mode); - set_ia32_exc_label(new_node, - be_get_Proj_for_pn(node, pn_Store_X_except) != NULL); - set_address(new_node, &addr); - SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + set_address(store, &addr); + SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node)); return new_node; } +/** + * Transforms a Store. + * + * @return the created ia32 Store node + */ +static ir_node *gen_Store(ir_node *node) +{ + ir_node *val = get_Store_value(node); + ir_mode *mode = get_irn_mode(val); + + if (mode_is_float(mode) && is_Const(val)) { + int transform = 1; + + /* we are storing a floating point constant */ + if (ia32_cg_config.use_sse2) { + transform = !is_simple_sse_Const(val); + } else { + transform = !is_simple_x87_Const(val); + } + if (transform) + return gen_float_const_Store(node, val); + } + return gen_normal_Store(node); +} + +/** + * Transforms a Switch. + * + * @return the created ia32 SwitchJmp node + */ static ir_node *create_Switch(ir_node *node) { ir_graph *irg = current_ir_graph; @@ -2328,6 +2663,9 @@ static ir_node *create_Switch(ir_node *node) return new_node; } +/** + * Transform a Cond node. + */ static ir_node *gen_Cond(ir_node *node) { ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); @@ -2343,7 +2681,7 @@ static ir_node *gen_Cond(ir_node *node) { return create_Switch(node); } - /* we get flags from a cmp */ + /* we get flags from a Cmp */ flags = get_flags_node(sel, &pnc); new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc); @@ -2352,8 +2690,6 @@ static ir_node *gen_Cond(ir_node *node) { return new_node; } - - /** * Transforms a CopyB node. * @@ -2401,7 +2737,7 @@ static ir_node *gen_be_Copy(ir_node *node) ir_node *new_node = be_duplicate_node(node); ir_mode *mode = get_irn_mode(new_node); - if (mode_needs_gp_reg(mode)) { + if (ia32_mode_needs_gp_reg(mode)) { set_irn_mode(new_node, mode_Iu); } @@ -2493,6 +2829,9 @@ static int can_fold_test_and(ir_node *node) return 1; } +/** + * Generate code for a Cmp. + */ static ir_node *gen_Cmp(ir_node *node) { ir_graph *irg = current_ir_graph; @@ -2515,7 +2854,7 @@ static ir_node *gen_Cmp(ir_node *node) } } - assert(mode_needs_gp_reg(cmp_mode)); + assert(ia32_mode_needs_gp_reg(cmp_mode)); /* we prefer the Test instruction where possible except cases where * we can use SourceAM */ @@ -2619,7 +2958,7 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, ia32_address_t *addr; assert(ia32_cg_config.use_cmov); - assert(mode_needs_gp_reg(get_irn_mode(val_true))); + assert(ia32_mode_needs_gp_reg(get_irn_mode(val_true))); addr = &am.addr; @@ -2640,8 +2979,9 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, return new_node; } - - +/** + * Creates a ia32 Setcc instruction. + */ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, ir_node *flags, pn_Cmp pnc, ir_node *orig_node, int ins_permuted) @@ -2656,7 +2996,7 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node)); /* we might need to conv the result up */ - if(get_mode_size_bits(mode) > 8) { + if (get_mode_size_bits(mode) > 8) { new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, nomem, new_node, mode_Bu); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node)); @@ -2665,6 +3005,41 @@ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, return new_node; } +/** + * Create instruction for an unsigned Difference or Zero. + */ +static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) { + ir_graph *irg = current_ir_graph; + ir_mode *mode = get_irn_mode(psi); + ir_node *new_node, *sub, *sbb, *eflags, *block, *noreg, *tmpreg, *nomem; + dbg_info *dbgi; + + new_node = gen_binop(psi, a, b, new_rd_ia32_Sub, + match_mode_neutral | match_am | match_immediate | match_two_users); + + block = get_nodes_block(new_node); + + if (is_Proj(new_node)) { + sub = get_Proj_pred(new_node); + assert(is_ia32_Sub(sub)); + } else { + sub = new_node; + set_irn_mode(sub, mode_T); + new_node = new_rd_Proj(NULL, irg, block, sub, mode, pn_ia32_res); + } + eflags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags); + + dbgi = get_irn_dbg_info(psi); + noreg = ia32_new_NoReg_gp(env_cg); + tmpreg = new_rd_ia32_ProduceVal(dbgi, irg, block); + nomem = new_NoMem(); + sbb = new_rd_ia32_Sbb(dbgi, irg, block, noreg, noreg, nomem, tmpreg, tmpreg, eflags); + + new_node = new_rd_ia32_And(dbgi, irg, block, noreg, noreg, nomem, new_node, sbb); + set_ia32_commutative(new_node); + return new_node; +} + /** * Transforms a Psi node into CMov. * @@ -2678,24 +3053,90 @@ static ir_node *gen_Psi(ir_node *node) ir_node *psi_true = get_Psi_val(node, 0); ir_node *psi_default = get_Psi_default(node); ir_node *cond = get_Psi_cond(node, 0); - ir_node *flags = NULL; - ir_node *new_node; - pn_Cmp pnc; + ir_mode *mode = get_irn_mode(node); + pn_Cmp pnc; assert(get_Psi_n_conds(node) == 1); assert(get_irn_mode(cond) == mode_b); - assert(mode_needs_gp_reg(get_irn_mode(node))); - flags = get_flags_node(cond, &pnc); + /* Note: a Psi node uses a Load two times IFF it's used in the compare AND in the result */ + if (mode_is_float(mode)) { + ir_node *cmp = get_Proj_pred(cond); + ir_node *cmp_left = get_Cmp_left(cmp); + ir_node *cmp_right = get_Cmp_right(cmp); + pn_Cmp pnc = get_Proj_proj(cond); + + if (ia32_cg_config.use_sse2) { + if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) { + if (cmp_left == psi_true && cmp_right == psi_default) { + /* psi(a <= b, a, b) => MIN */ + return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin, + match_commutative | match_am | match_two_users); + } else if (cmp_left == psi_default && cmp_right == psi_true) { + /* psi(a <= b, b, a) => MAX */ + return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax, + match_commutative | match_am | match_two_users); + } + } else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) { + if (cmp_left == psi_true && cmp_right == psi_default) { + /* psi(a >= b, a, b) => MAX */ + return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax, + match_commutative | match_am | match_two_users); + } else if (cmp_left == psi_default && cmp_right == psi_true) { + /* psi(a >= b, b, a) => MIN */ + return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin, + match_commutative | match_am | match_two_users); + } + } + } + panic("cannot transform floating point Psi"); - if(is_Const_1(psi_true) && is_Const_0(psi_default)) { - new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0); - } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) { - new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1); } else { - new_node = create_CMov(node, cond, flags, pnc); + ir_node *flags; + ir_node *new_node; + + assert(ia32_mode_needs_gp_reg(mode)); + + if (is_Proj(cond)) { + ir_node *cmp = get_Proj_pred(cond); + if (is_Cmp(cmp)) { + ir_node *cmp_left = get_Cmp_left(cmp); + ir_node *cmp_right = get_Cmp_right(cmp); + pn_Cmp pnc = get_Proj_proj(cond); + + /* check for unsigned Doz first */ + if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) && + is_Const_0(psi_default) && is_Sub(psi_true) && + get_Sub_left(psi_true) == cmp_left && get_Sub_right(psi_true) == cmp_right) { + /* Psi(a >=u b, a - b, 0) unsigned Doz */ + return create_Doz(node, cmp_left, cmp_right); + } else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) && + is_Const_0(psi_true) && is_Sub(psi_default) && + get_Sub_left(psi_default) == cmp_left && get_Sub_right(psi_default) == cmp_right) { + /* Psi(a <=u b, 0, a - b) unsigned Doz */ + return create_Doz(node, cmp_left, cmp_right); + } + } + } + + flags = get_flags_node(cond, &pnc); + + if (is_Const(psi_true) && is_Const(psi_default)) { + /* both are const, good */ + if (is_Const_1(psi_true) && is_Const_0(psi_default)) { + new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0); + } else if (is_Const_0(psi_true) && is_Const_1(psi_default)) { + new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/1); + } else { + /* Not that simple. */ + goto need_cmov; + } + } else { +need_cmov: + new_node = create_CMov(node, cond, flags, pnc); + } + return new_node; } - return new_node; } @@ -2710,14 +3151,10 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) { ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *noreg = ia32_new_NoReg_gp(cg); - ir_node *trunc_mode = ia32_new_Fpu_truncate(cg); ir_mode *mode = get_irn_mode(node); - ir_node *fist, *load; - - /* do a fist */ - fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, - new_NoMem(), new_op, trunc_mode); + ir_node *fist, *load, *mem; + mem = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, new_NoMem(), new_op, &fist); set_irn_pinned(fist, op_pin_state_floats); set_ia32_use_frame(fist); set_ia32_op_type(fist, ia32_AddrModeD); @@ -2733,7 +3170,7 @@ static ir_node *gen_x87_fp_to_gp(ir_node *node) { SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node)); /* do a Load */ - load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist); + load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, mem); set_irn_pinned(load, op_pin_state_floats); set_ia32_use_frame(load); @@ -2781,17 +3218,6 @@ static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node) return new_node; } -static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val) -{ - ir_graph *irg = current_ir_graph; - ir_node *start_block = get_irg_start_block(irg); - ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, - symconst, symconst_sign, val); - arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]); - - return immediate; -} - /** * Create a conversion from general purpose to x87 register */ @@ -2976,7 +3402,7 @@ static ir_node *gen_Conv(ir_node *node) { ir_node *res = NULL; if (src_mode == mode_b) { - assert(mode_is_int(tgt_mode)); + assert(mode_is_int(tgt_mode) || mode_is_reference(tgt_mode)); /* nothing to do, we already model bools as 0/1 ints */ return be_transform_node(op); } @@ -3071,11 +3497,12 @@ static ir_node *gen_Conv(ir_node *node) { return res; } -static int check_immediate_constraint(long val, char immediate_constraint_type) +static bool check_immediate_constraint(long val, char immediate_constraint_type) { switch (immediate_constraint_type) { case 0: - return 1; + case 'i': + return true; case 'I': return val >= 0 && val <= 32; case 'J': @@ -3094,7 +3521,7 @@ static int check_immediate_constraint(long val, char immediate_constraint_type) break; } panic("Invalid immediate constraint found"); - return 0; + return false; } static ir_node *try_create_Immediate(ir_node *node, @@ -3210,51 +3637,32 @@ static ir_node *create_immediate_or_transform(ir_node *node, return new_node; } -static const arch_register_req_t no_register_req = { - arch_register_req_type_none, - NULL, /* regclass */ - NULL, /* limit bitset */ - 0, /* same pos */ - 0 /* different pos */ -}; -/** - * An assembler constraint. - */ -typedef struct constraint_t constraint_t; -struct constraint_t { - int is_in; - int n_outs; - const arch_register_req_t **out_reqs; - - const arch_register_req_t *req; - unsigned immediate_possible; - char immediate_type; -}; -static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c) +void parse_asm_constraints(constraint_t *constraint, const char *c, + bool is_output) { - int immediate_possible = 0; - char immediate_type = 0; + asm_constraint_flags_t flags = 0; + char immediate_type = '\0'; unsigned limited = 0; const arch_register_class_t *cls = NULL; - ir_graph *irg = current_ir_graph; - struct obstack *obst = get_irg_obstack(irg); - arch_register_req_t *req; - unsigned *limited_ptr = NULL; + bool memory_possible = false; + bool all_registers_allowed = false; int p; int same_as = -1; - /* TODO: replace all the asserts with nice error messages */ + memset(constraint, 0, sizeof(constraint[0])); + constraint->same_as = -1; if(*c == 0) { /* a memory constraint: no need to do anything in backend about it * (the dependencies are already respected by the memory edge of * the node) */ - constraint->req = &no_register_req; return; } + /* TODO: improve error messages with node and source info. (As users can + * easily hit these) */ while(*c != 0) { switch(*c) { case ' ': @@ -3262,60 +3670,70 @@ static void parse_asm_constraint(int pos, constraint_t *constraint, const char * case '\n': break; + case '=': + flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE + | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ; + break; + + case '+': + flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE + | ASM_CONSTRAINT_FLAG_MODIFIER_READ; + break; + + case '*': + ++c; + break; + case '#': + while(*c != 0 && *c != ',') + ++c; + break; + case 'a': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; limited |= 1 << REG_EAX; break; case 'b': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; limited |= 1 << REG_EBX; break; case 'c': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; limited |= 1 << REG_ECX; break; case 'd': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; limited |= 1 << REG_EDX; break; case 'D': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; limited |= 1 << REG_EDI; break; case 'S': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; limited |= 1 << REG_ESI; break; case 'Q': - case 'q': /* q means lower part of the regs only, this makes no - * difference to Q for us (we only assigne whole registers) */ - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + case 'q': + /* q means lower part of the regs only, this makes no + * difference to Q for us (we only assign whole registers) */ + assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX | 1 << REG_EDX; break; case 'A': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; limited |= 1 << REG_EAX | 1 << REG_EDX; break; case 'l': - assert(cls == NULL || - (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0)); + assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX | 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI | @@ -3325,23 +3743,28 @@ static void parse_asm_constraint(int pos, constraint_t *constraint, const char * case 'R': case 'r': case 'p': - assert(cls == NULL); - cls = &ia32_reg_classes[CLASS_ia32_gp]; + if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp]) + panic("multiple register classes not supported"); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + all_registers_allowed = true; break; case 'f': case 't': case 'u': /* TODO: mark values so the x87 simulator knows about t and u */ - assert(cls == NULL); - cls = &ia32_reg_classes[CLASS_ia32_vfp]; + if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp]) + panic("multiple register classes not supported"); + cls = &ia32_reg_classes[CLASS_ia32_vfp]; + all_registers_allowed = true; break; case 'Y': case 'x': - assert(cls == NULL); - /* TODO: check that sse2 is supported */ - cls = &ia32_reg_classes[CLASS_ia32_xmm]; + if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm]) + panic("multiple register classes not supproted"); + cls = &ia32_reg_classes[CLASS_ia32_xmm]; + all_registers_allowed = true; break; case 'I': @@ -3351,20 +3774,33 @@ static void parse_asm_constraint(int pos, constraint_t *constraint, const char * case 'M': case 'N': case 'O': - assert(!immediate_possible); - immediate_possible = 1; - immediate_type = *c; + if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp]) + panic("multiple register classes not supported"); + if (immediate_type != '\0') + panic("multiple immediate types not supported"); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + immediate_type = *c; break; case 'n': case 'i': - assert(!immediate_possible); - immediate_possible = 1; + if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp]) + panic("multiple register classes not supported"); + if (immediate_type != '\0') + panic("multiple immediate types not supported"); + cls = &ia32_reg_classes[CLASS_ia32_gp]; + immediate_type = 'i'; break; + case 'X': case 'g': - assert(!immediate_possible && cls == NULL); - immediate_possible = 1; - cls = &ia32_reg_classes[CLASS_ia32_gp]; + if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp]) + panic("multiple register classes not supported"); + if (immediate_type != '\0') + panic("multiple immediate types not supported"); + immediate_type = 'i'; + cls = &ia32_reg_classes[CLASS_ia32_gp]; + all_registers_allowed = true; + memory_possible = true; break; case '0': @@ -3377,8 +3813,8 @@ static void parse_asm_constraint(int pos, constraint_t *constraint, const char * case '7': case '8': case '9': - assert(constraint->is_in && "can only specify same constraint " - "on input"); + if (is_output) + panic("can only specify same constraint on input"); sscanf(c, "%d%n", &same_as, &p); if(same_as >= 0) { @@ -3388,18 +3824,17 @@ static void parse_asm_constraint(int pos, constraint_t *constraint, const char * break; case 'm': + case 'o': + case 'V': /* memory constraint no need to do anything in backend about it * (the dependencies are already respected by the memory edge of * the node) */ - constraint->req = &no_register_req; - return; + memory_possible = true; + break; case 'E': /* no float consts yet */ case 'F': /* no float consts yet */ case 's': /* makes no sense on x86 */ - case 'X': /* we can't support that in firm */ - case 'o': - case 'V': case '<': /* no autodecrement on x86 */ case '>': /* no autoincrement on x86 */ case 'C': /* sse constant not supported yet */ @@ -3419,15 +3854,39 @@ static void parse_asm_constraint(int pos, constraint_t *constraint, const char * } if(same_as >= 0) { + if (cls != NULL) + panic("same as and register constraint not supported"); + if (immediate_type != '\0') + panic("same as and immediate constraint not supported"); + } + + if (cls == NULL && same_as < 0) { + if (!memory_possible) + panic("no constraint specified for assembler input"); + } + + constraint->same_as = same_as; + constraint->cls = cls; + constraint->allowed_registers = limited; + constraint->all_registers_allowed = all_registers_allowed; + constraint->memory_possible = memory_possible; + constraint->immediate_type = immediate_type; +} + +const arch_register_req_t *make_register_req(const constraint_t *constraint, + int n_outs, const arch_register_req_t **out_reqs, int pos) +{ + struct obstack *obst = get_irg_obstack(current_ir_graph); + int same_as = constraint->same_as; + arch_register_req_t *req; + + if (same_as >= 0) { const arch_register_req_t *other_constr; - assert(cls == NULL && "same as and register constraint not supported"); - assert(!immediate_possible && "same as and immediate constraint not " - "supported"); - assert(same_as < constraint->n_outs && "wrong constraint number in " - "same_as constraint"); + if (same_as >= n_outs) + panic("invalid output number in same_as constraint"); - other_constr = constraint->out_reqs[same_as]; + other_constr = out_reqs[same_as]; req = obstack_alloc(obst, sizeof(req[0])); req->cls = other_constr->cls; @@ -3439,68 +3898,85 @@ static void parse_asm_constraint(int pos, constraint_t *constraint, const char * /* switch constraints. This is because in firm we have same_as * constraints on the output constraints while in the gcc asm syntax * they are specified on the input constraints */ - constraint->req = other_constr; - constraint->out_reqs[same_as] = req; - constraint->immediate_possible = 0; - return; + out_reqs[same_as] = req; + return other_constr; } - if(immediate_possible && cls == NULL) { - cls = &ia32_reg_classes[CLASS_ia32_gp]; + /* pure memory ops */ + if (constraint->cls == NULL) { + return &no_register_req; } - assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]); - assert(cls != NULL); - if(immediate_possible) { - assert(constraint->is_in - && "immediate make no sense for output constraints"); - } - /* todo: check types (no float input on 'r' constrained in and such... */ + if (constraint->allowed_registers != 0 + && !constraint->all_registers_allowed) { + unsigned *limited_ptr; - if(limited != 0) { - req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned)); - limited_ptr = (unsigned*) (req+1); - } else { - req = obstack_alloc(obst, sizeof(req[0])); - } - memset(req, 0, sizeof(req[0])); + req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned)); + memset(req, 0, sizeof(req[0])); + limited_ptr = (unsigned*) (req+1); - if(limited != 0) { req->type = arch_register_req_type_limited; - *limited_ptr = limited; + *limited_ptr = constraint->allowed_registers; req->limited = limited_ptr; } else { - req->type = arch_register_req_type_normal; + req = obstack_alloc(obst, sizeof(req[0])); + memset(req, 0, sizeof(req[0])); + req->type = arch_register_req_type_normal; } - req->cls = cls; + req->cls = constraint->cls; - constraint->req = req; - constraint->immediate_possible = immediate_possible; - constraint->immediate_type = immediate_type; + return req; } -static void parse_clobber(ir_node *node, int pos, constraint_t *constraint, - const char *c) +const arch_register_t *ia32_get_clobber_register(const char *clobber) { - (void) node; - (void) pos; - (void) constraint; - (void) c; - panic("Clobbers not supported yet"); + const arch_register_t *reg = NULL; + int c; + size_t r; + const arch_register_class_t *cls; + + /* TODO: construct a hashmap instead of doing linear search for clobber + * register */ + for(c = 0; c < N_CLASSES; ++c) { + cls = & ia32_reg_classes[c]; + for(r = 0; r < cls->n_regs; ++r) { + const arch_register_t *temp_reg = arch_register_for_index(cls, r); + if(strcmp(temp_reg->name, clobber) == 0 + || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) { + reg = temp_reg; + break; + } + } + if(reg != NULL) + break; + } + + return reg; } -static int is_memory_op(const ir_asm_constraint *constraint) +const arch_register_req_t *parse_clobber(const char *clobber) { - ident *id = constraint->constraint; - const char *str = get_id_str(id); - const char *c; + struct obstack *obst = get_irg_obstack(current_ir_graph); + const arch_register_t *reg = ia32_get_clobber_register(clobber); + arch_register_req_t *req; + unsigned *limited; - for(c = str; *c != '\0'; ++c) { - if(*c == 'm') - return 1; + if(reg == NULL) { + panic("Register '%s' mentioned in asm clobber is unknown\n", clobber); } - return 0; + assert(reg->index < 32); + + limited = obstack_alloc(obst, sizeof(limited[0])); + *limited = 1 << reg->index; + + req = obstack_alloc(obst, sizeof(req[0])); + memset(req, 0, sizeof(req[0])); + req->type = arch_register_req_type_limited; + req->cls = arch_register_get_class(reg); + req->limited = limited; + + return req; } /** @@ -3508,11 +3984,12 @@ static int is_memory_op(const ir_asm_constraint *constraint) */ static ir_node *gen_ASM(ir_node *node) { - int i, arity; ir_graph *irg = current_ir_graph; ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); dbg_info *dbgi = get_irn_dbg_info(node); + int i, arity; + int out_idx; ir_node **in; ir_node *new_node; int out_arity; @@ -3526,106 +4003,130 @@ static ir_node *gen_ASM(ir_node *node) const ir_asm_constraint *in_constraints; const ir_asm_constraint *out_constraints; ident **clobbers; - constraint_t parsed_constraint; + bool clobbers_flags = false; + + /* workaround for lots of buggy code out there as most people think volatile + * asm is enough for everything and forget the flags (linux kernel, etc.) + */ + if (get_irn_pinned(node) == op_pin_state_pinned) { + clobbers_flags = true; + } arity = get_irn_arity(node); in = alloca(arity * sizeof(in[0])); memset(in, 0, arity * sizeof(in[0])); + clobbers = get_ASM_clobbers(node); + n_clobbers = 0; + for(i = 0; i < get_ASM_n_clobbers(node); ++i) { + const char *c = get_id_str(clobbers[i]); + if (strcmp(c, "memory") == 0) + continue; + if (strcmp(c, "cc") == 0) { + clobbers_flags = true; + continue; + } + n_clobbers++; + } n_out_constraints = get_ASM_n_output_constraints(node); - n_clobbers = get_ASM_n_clobbers(node); out_arity = n_out_constraints + n_clobbers; in_constraints = get_ASM_input_constraints(node); out_constraints = get_ASM_output_constraints(node); - clobbers = get_ASM_clobbers(node); - /* construct output constraints */ - obst = get_irg_obstack(irg); - out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0])); - parsed_constraint.out_reqs = out_reg_reqs; - parsed_constraint.n_outs = n_out_constraints; - parsed_constraint.is_in = 0; - - for(i = 0; i < out_arity; ++i) { - const char *c; - - if(i < n_out_constraints) { - const ir_asm_constraint *constraint = &out_constraints[i]; - c = get_id_str(constraint->constraint); - parse_asm_constraint(i, &parsed_constraint, c); - - if(constraint->pos > reg_map_size) - reg_map_size = constraint->pos; - } else { - ident *glob_id = clobbers [i - n_out_constraints]; - c = get_id_str(glob_id); - parse_clobber(node, i, &parsed_constraint, c); - } - - out_reg_reqs[i] = parsed_constraint.req; + /* determine size of register_map */ + for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) { + const ir_asm_constraint *constraint = &out_constraints[out_idx]; + if (constraint->pos > reg_map_size) + reg_map_size = constraint->pos; } - - /* construct input constraints */ - in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0])); - parsed_constraint.is_in = 1; for(i = 0; i < arity; ++i) { const ir_asm_constraint *constraint = &in_constraints[i]; - ident *constr_id = constraint->constraint; - const char *c = get_id_str(constr_id); - - parse_asm_constraint(i, &parsed_constraint, c); - in_reg_reqs[i] = parsed_constraint.req; - if(constraint->pos > reg_map_size) reg_map_size = constraint->pos; - - if(parsed_constraint.immediate_possible) { - ir_node *pred = get_irn_n(node, i); - char imm_type = parsed_constraint.immediate_type; - ir_node *immediate = try_create_Immediate(pred, imm_type); - - if(immediate != NULL) { - in[i] = immediate; - } - } } - reg_map_size++; + ++reg_map_size; + obst = get_irg_obstack(irg); register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size); memset(register_map, 0, reg_map_size * sizeof(register_map[0])); - for(i = 0; i < n_out_constraints; ++i) { - const ir_asm_constraint *constraint = &out_constraints[i]; - unsigned pos = constraint->pos; + /* construct output constraints */ + out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0])); - assert(pos < reg_map_size); - register_map[pos].use_input = 0; - register_map[pos].valid = 1; - register_map[pos].memory = is_memory_op(constraint); - register_map[pos].inout_pos = i; + for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) { + const ir_asm_constraint *constraint = &out_constraints[out_idx]; + const char *c = get_id_str(constraint->constraint); + unsigned pos = constraint->pos; + constraint_t parsed_constraint; + const arch_register_req_t *req; + + parse_asm_constraints(&parsed_constraint, c, true); + req = make_register_req(&parsed_constraint, n_out_constraints, + out_reg_reqs, out_idx); + out_reg_reqs[out_idx] = req; + + register_map[pos].use_input = false; + register_map[pos].valid = true; + register_map[pos].memory = false; + register_map[pos].inout_pos = out_idx; register_map[pos].mode = constraint->mode; } - /* transform inputs */ + /* inputs + input constraints */ + in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0])); for(i = 0; i < arity; ++i) { - const ir_asm_constraint *constraint = &in_constraints[i]; - unsigned pos = constraint->pos; - ir_node *pred = get_irn_n(node, i); - ir_node *transformed; - - assert(pos < reg_map_size); - register_map[pos].use_input = 1; - register_map[pos].valid = 1; - register_map[pos].memory = is_memory_op(constraint); + ir_node *pred = get_irn_n(node, i); + const ir_asm_constraint *constraint = &in_constraints[i]; + ident *constr_id = constraint->constraint; + const char *c = get_id_str(constr_id); + unsigned pos = constraint->pos; + bool is_memory_op = false; + ir_node *input = NULL; + constraint_t parsed_constraint; + const arch_register_req_t *req; + + parse_asm_constraints(&parsed_constraint, c, false); + req = make_register_req(&parsed_constraint, n_out_constraints, + out_reg_reqs, i); + in_reg_reqs[i] = req; + + if (parsed_constraint.immediate_type != '\0') { + char imm_type = parsed_constraint.immediate_type; + input = try_create_Immediate(pred, imm_type); + } + + if (input == NULL) { + ir_node *pred = get_irn_n(node, i); + input = be_transform_node(pred); + + if (parsed_constraint.cls == NULL + && parsed_constraint.same_as < 0) { + is_memory_op = true; + } else if(parsed_constraint.memory_possible) { + /* TODO: match Load or Load/Store if memory possible is set */ + } + } + in[i] = input; + + register_map[pos].use_input = true; + register_map[pos].valid = true; + register_map[pos].memory = is_memory_op; register_map[pos].inout_pos = i; register_map[pos].mode = constraint->mode; + } + + /* parse clobbers */ + for(i = 0; i < get_ASM_n_clobbers(node); ++i) { + const char *c = get_id_str(clobbers[i]); + const arch_register_req_t *req; - if(in[i] != NULL) + if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0) continue; - transformed = be_transform_node(pred); - in[i] = transformed; + req = parse_clobber(c); + out_reg_reqs[out_idx] = req; + ++out_idx; } new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity, @@ -3796,13 +4297,21 @@ static ir_node *gen_Unknown(ir_node *node) { if (ia32_cg_config.use_sse2) { return ia32_new_Unknown_xmm(env_cg); } else { - /* Unknown nodes are buggy in x87 sim, use zero for now... */ + /* Unknown nodes are buggy in x87 simulator, use zero for now... */ ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_irg_start_block(irg); - return new_rd_ia32_vfldz(dbgi, irg, block); + ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block); + + /* Const Nodes before the initial IncSP are a bad idea, because + * they could be spilled and we have no SP ready at that point yet. + * So add a dependency to the initial frame pointer calculation to + * avoid that situation. + */ + add_irn_dep(ret, get_irg_frame(irg)); + return ret; } - } else if (mode_needs_gp_reg(mode)) { + } else if (ia32_mode_needs_gp_reg(mode)) { return ia32_new_Unknown_gp(env_cg); } else { panic("unsupported Unknown-Mode"); @@ -3820,7 +4329,7 @@ static ir_node *gen_Phi(ir_node *node) { ir_mode *mode = get_irn_mode(node); ir_node *phi; - if(mode_needs_gp_reg(mode)) { + if(ia32_mode_needs_gp_reg(mode)) { /* we shouldn't have any 64bit stuff around anymore */ assert(get_mode_size_bits(mode) <= 32); /* all integer operations are on 32bit registers now */ @@ -3853,7 +4362,6 @@ static ir_node *gen_IJmp(ir_node *node) { ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); - ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); ir_node *op = get_IJmp_target(node); ir_node *new_node; @@ -3866,8 +4374,9 @@ static ir_node *gen_IJmp(ir_node *node) match_am | match_8bit_am | match_16bit_am | match_immediate | match_8bit | match_16bit); - new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index, - addr->mem, am.new_op2); + new_node = new_rd_ia32_IJmp(dbgi, current_ir_graph, new_block, + addr->base, addr->index, addr->mem, + am.new_op2); set_am_attributes(new_node, &am); SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); @@ -3876,6 +4385,41 @@ static ir_node *gen_IJmp(ir_node *node) return new_node; } +/** + * Transform a Bound node. + */ +static ir_node *gen_Bound(ir_node *node) +{ + ir_node *new_node; + ir_node *lower = get_Bound_lower(node); + dbg_info *dbgi = get_irn_dbg_info(node); + + if (is_Const_0(lower)) { + /* typical case for Java */ + ir_node *sub, *res, *flags, *block; + ir_graph *irg = current_ir_graph; + + res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node), + new_rd_ia32_Sub, match_mode_neutral | match_am | match_immediate); + + block = get_nodes_block(res); + if (! is_Proj(res)) { + sub = res; + set_irn_mode(sub, mode_T); + res = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_res); + } else { + sub = get_Proj_pred(res); + } + flags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags); + new_node = new_rd_ia32_Jcc(dbgi, irg, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned); + SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node)); + } else { + panic("generic Bound not supported in ia32 Backend"); + } + return new_node; +} + + typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \ ir_node *mem); @@ -4048,24 +4592,21 @@ static ir_node *gen_ia32_l_vfist(ir_node *node) { dbg_info *dbgi = get_irn_dbg_info(node); ir_node *noreg = ia32_new_NoReg_gp(env_cg); ir_mode *mode = get_ia32_ls_mode(node); - ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); - ir_node *new_op; + ir_node *memres, *fist; long am_offs; - new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem, - new_val, trunc_mode); - + memres = gen_vfist(dbgi, irg, block, new_ptr, noreg, new_mem, new_val, &fist); am_offs = get_ia32_am_offs_int(node); - add_ia32_am_offs_int(new_op, am_offs); + add_ia32_am_offs_int(fist, am_offs); - set_ia32_op_type(new_op, ia32_AddrModeD); - set_ia32_ls_mode(new_op, mode); - set_ia32_frame_ent(new_op, get_ia32_frame_ent(node)); - set_ia32_use_frame(new_op); + set_ia32_op_type(fist, ia32_AddrModeD); + set_ia32_ls_mode(fist, mode); + set_ia32_frame_ent(fist, get_ia32_frame_ent(node)); + set_ia32_use_frame(fist); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node)); + SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node)); - return new_op; + return memres; } /** @@ -4087,16 +4628,16 @@ static ir_node *gen_ia32_l_Mul(ir_node *node) { * @return the created ia32 IMul1OP node */ static ir_node *gen_ia32_l_IMul(ir_node *node) { - ir_node *left = get_binop_left(node); - ir_node *right = get_binop_right(node); + ir_node *left = get_binop_left(node); + ir_node *right = get_binop_right(node); return gen_binop(node, left, right, new_rd_ia32_IMul1OP, match_commutative | match_am | match_mode_neutral); } static ir_node *gen_ia32_l_Sub(ir_node *node) { - ir_node *left = get_irn_n(node, n_ia32_l_Sub_left); - ir_node *right = get_irn_n(node, n_ia32_l_Sub_right); + ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend); + ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend); ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, match_am | match_immediate | match_mode_neutral); @@ -4225,8 +4766,24 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) { } static ir_node *gen_ia32_l_FloattoLL(ir_node *node) { - (void) node; - panic("LLtoFloat NIY"); + ir_node *src_block = get_nodes_block(node); + ir_node *block = be_transform_node(src_block); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *frame = get_irg_frame(irg); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + ir_node *nomem = new_NoMem(); + ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val); + ir_node *new_val = be_transform_node(val); + ir_node *fist, *mem; + + mem = gen_vfist(dbgi, irg, block, frame, noreg, nomem, new_val, &fist); + SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node)); + set_ia32_use_frame(fist); + set_ia32_op_type(fist, ia32_AddrModeD); + set_ia32_ls_mode(fist, mode_Ls); + + return mem; } /** @@ -4237,6 +4794,40 @@ static ir_node *bad_transform(ir_node *node) { return NULL; } +static ir_node *gen_Proj_l_FloattoLL(ir_node *node) { + ir_graph *irg = current_ir_graph; + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *pred = get_Proj_pred(node); + ir_node *new_pred = be_transform_node(pred); + ir_node *frame = get_irg_frame(irg); + ir_node *noreg = ia32_new_NoReg_gp(env_cg); + dbg_info *dbgi = get_irn_dbg_info(node); + long pn = get_Proj_proj(node); + ir_node *load; + ir_node *proj; + ia32_attr_t *attr; + + load = new_rd_ia32_Load(dbgi, irg, block, frame, noreg, new_pred); + SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node)); + set_ia32_use_frame(load); + set_ia32_op_type(load, ia32_AddrModeS); + set_ia32_ls_mode(load, mode_Iu); + /* we need a 64bit stackslot (fist stores 64bit) even though we only load + * 32 bit from it with this particular load */ + attr = get_ia32_attr(load); + attr->data.need_64bit_stackent = 1; + + if (pn == pn_ia32_l_FloattoLL_res_high) { + add_ia32_am_offs_int(load, 4); + } else { + assert(pn == pn_ia32_l_FloattoLL_res_low); + } + + proj = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res); + + return proj; +} + /** * Transform the Projs of an AddSP. */ @@ -4299,37 +4890,41 @@ static ir_node *gen_Proj_Load(ir_node *node) { dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); - /* loads might be part of source address mode matches, so we don't - transform the ProjMs yet (with the exception of loads whose result is - not used) + * transform the ProjMs yet (with the exception of loads whose result is + * not used) */ if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) { ir_node *res; - assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM - nodes is 1 */ /* this is needed, because sometimes we have loops that are only reachable through the ProjM */ be_enqueue_preds(node); /* do it in 2 steps, to silence firm verifier */ res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M); - set_Proj_proj(res, pn_ia32_Load_M); + set_Proj_proj(res, pn_ia32_mem); return res; } /* renumber the proj */ new_pred = be_transform_node(pred); if (is_ia32_Load(new_pred)) { - if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, - pn_ia32_Load_res); - } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, - pn_ia32_Load_M); + switch (proj) { + case pn_Load_res: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res); + case pn_Load_M: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M); + case pn_Load_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Load_X_exc); + default: + break; } - } else if(is_ia32_Conv_I2I(new_pred) - || is_ia32_Conv_I2I8Bit(new_pred)) { + } else if (is_ia32_Conv_I2I(new_pred) || + is_ia32_Conv_I2I8Bit(new_pred)) { set_irn_mode(new_pred, mode_T); if (proj == pn_Load_res) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res); @@ -4337,20 +4932,34 @@ static ir_node *gen_Proj_Load(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem); } } else if (is_ia32_xLoad(new_pred)) { - if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, - pn_ia32_xLoad_res); - } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, - pn_ia32_xLoad_M); + switch (proj) { + case pn_Load_res: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res); + case pn_Load_M: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M); + case pn_Load_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); + default: + break; } } else if (is_ia32_vfld(new_pred)) { - if (proj == pn_Load_res) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, - pn_ia32_vfld_res); - } else if (proj == pn_Load_M) { - return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, - pn_ia32_vfld_M); + switch (proj) { + case pn_Load_res: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res); + case pn_Load_M: + return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M); + case pn_Load_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Load_X_except: + /* This Load might raise an exception. Mark it. */ + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc); + default: + break; } } else { /* can happen for ProJMs when source address mode happened for the @@ -4359,7 +4968,7 @@ static ir_node *gen_Proj_Load(ir_node *node) { /* however it should not be the result proj, as that would mean the load had multiple users and should not have been used for SourceAM */ - if(proj != pn_Load_M) { + if (proj != pn_Load_M) { panic("internal error: transformed node not a Load"); } return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1); @@ -4390,6 +4999,11 @@ static ir_node *gen_Proj_DivMod(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Div_res: return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); + case pn_Div_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_Div_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4400,6 +5014,9 @@ static ir_node *gen_Proj_DivMod(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M); case pn_Mod_res: return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + case pn_Mod_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4412,6 +5029,11 @@ static ir_node *gen_Proj_DivMod(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res); case pn_DivMod_res_mod: return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res); + case pn_DivMod_X_regular: + return new_rd_Jmp(dbgi, irg, block); + case pn_DivMod_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } @@ -4479,6 +5101,8 @@ static ir_node *gen_Proj_Quot(ir_node *node) { return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res); } break; + case pn_Quot_X_regular: + case pn_Quot_X_except: default: break; } @@ -4608,69 +5232,106 @@ static ir_node *gen_Proj_Cmp(ir_node *node) node); } +/** + * Transform the Projs from a Bound. + */ +static ir_node *gen_Proj_Bound(ir_node *node) +{ + ir_node *new_node, *block; + ir_node *pred = get_Proj_pred(node); + + switch (get_Proj_proj(node)) { + case pn_Bound_M: + return be_transform_node(get_Bound_mem(pred)); + case pn_Bound_X_regular: + new_node = be_transform_node(pred); + block = get_nodes_block(new_node); + return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_true); + case pn_Bound_X_except: + new_node = be_transform_node(pred); + block = get_nodes_block(new_node); + return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_false); + case pn_Bound_res: + return be_transform_node(get_Bound_index(pred)); + default: + panic("unsupported Proj from Bound"); + } +} + /** * Transform and potentially renumber Proj nodes. */ static ir_node *gen_Proj(ir_node *node) { - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *pred = get_Proj_pred(node); - long proj = get_Proj_proj(node); + ir_node *pred = get_Proj_pred(node); + long proj; - if (is_Store(pred)) { + switch (get_irn_opcode(pred)) { + case iro_Store: + proj = get_Proj_proj(node); if (proj == pn_Store_M) { return be_transform_node(pred); } else { assert(0); - return new_r_Bad(irg); + return new_r_Bad(current_ir_graph); } - } else if (is_Load(pred)) { + case iro_Load: return gen_Proj_Load(node); - } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) { + case iro_Div: + case iro_Mod: + case iro_DivMod: return gen_Proj_DivMod(node); - } else if (is_CopyB(pred)) { + case iro_CopyB: return gen_Proj_CopyB(node); - } else if (is_Quot(pred)) { + case iro_Quot: return gen_Proj_Quot(node); - } else if (be_is_SubSP(pred)) { + case beo_SubSP: return gen_Proj_be_SubSP(node); - } else if (be_is_AddSP(pred)) { + case beo_AddSP: return gen_Proj_be_AddSP(node); - } else if (be_is_Call(pred)) { + case beo_Call: return gen_Proj_be_Call(node); - } else if (is_Cmp(pred)) { + case iro_Cmp: return gen_Proj_Cmp(node); - } else if (get_irn_op(pred) == op_Start) { + case iro_Bound: + return gen_Proj_Bound(node); + case iro_Start: + proj = get_Proj_proj(node); if (proj == pn_Start_X_initial_exec) { ir_node *block = get_nodes_block(pred); + dbg_info *dbgi = get_irn_dbg_info(node); ir_node *jump; /* we exchange the ProjX with a jump */ block = be_transform_node(block); - jump = new_rd_Jmp(dbgi, irg, block); + jump = new_rd_Jmp(dbgi, current_ir_graph, block); return jump; } if (node == be_get_old_anchor(anchor_tls)) { return gen_Proj_tls(node); } + break; + + default: + if (is_ia32_l_FloattoLL(pred)) { + return gen_Proj_l_FloattoLL(node); #ifdef FIRM_EXT_GRS - } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization + } else if (!is_ia32_irn(pred)) { // Quick hack for SIMD optimization #else - } else { + } else { #endif - ir_node *new_pred = be_transform_node(pred); - ir_node *block = be_transform_node(get_nodes_block(node)); - ir_mode *mode = get_irn_mode(node); - if (mode_needs_gp_reg(mode)) { - ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu, - get_Proj_proj(node)); + ir_mode *mode = get_irn_mode(node); + if (ia32_mode_needs_gp_reg(mode)) { + ir_node *new_pred = be_transform_node(pred); + ir_node *block = be_transform_node(get_nodes_block(node)); + ir_node *new_proj = new_r_Proj(current_ir_graph, block, new_pred, + mode_Iu, get_Proj_proj(node)); #ifdef DEBUG_libfirm - new_proj->node_nr = node->node_nr; + new_proj->node_nr = node->node_nr; #endif - return new_proj; + return new_proj; + } } } - return be_duplicate_node(node); } @@ -4697,7 +5358,7 @@ static void register_transformers(void) GEN(Shl); GEN(Shr); GEN(Shrs); - GEN(Rot); + GEN(Rotl); GEN(Quot); @@ -4722,6 +5383,7 @@ static void register_transformers(void) GEN(Proj); GEN(Phi); GEN(IJmp); + GEN(Bound); /* transform ops from intrinsic lowering */ GEN(ia32_l_Add); @@ -4795,7 +5457,7 @@ static void ia32_pretransform_node(void *arch_cg) { /** * Walker, checks if all ia32 nodes producing more than one result have - * its Projs, other wise creates new projs and keep them using a be_Keep node. + * its Projs, otherwise creates new Projs and keep them using a be_Keep node. */ static void add_missing_keep_walker(ir_node *node, void *data) { @@ -4832,28 +5494,28 @@ static void add_missing_keep_walker(ir_node *node, void *data) ir_node *block; ir_node *in[1]; const arch_register_req_t *req; - const arch_register_class_t *class; + const arch_register_class_t *cls; if(found_projs & (1 << i)) { continue; } req = get_ia32_out_req(node, i); - class = req->cls; - if(class == NULL) { + cls = req->cls; + if(cls == NULL) { continue; } - if(class == &ia32_reg_classes[CLASS_ia32_flags]) { + if(cls == &ia32_reg_classes[CLASS_ia32_flags]) { continue; } block = get_nodes_block(node); in[0] = new_r_Proj(current_ir_graph, block, node, - arch_register_class_mode(class), i); + arch_register_class_mode(cls), i); if(last_keep != NULL) { - be_Keep_add_node(last_keep, class, in[0]); + be_Keep_add_node(last_keep, cls, in[0]); } else { - last_keep = be_new_Keep(class, current_ir_graph, block, 1, in); + last_keep = be_new_Keep(cls, current_ir_graph, block, 1, in); if(sched_is_scheduled(node)) { sched_add_after(node, last_keep); } @@ -4880,9 +5542,9 @@ void ia32_transform_graph(ia32_code_gen_t *cg) { env_cg = cg; initial_fpcw = NULL; -BE_TIMER_PUSH(t_heights); + BE_TIMER_PUSH(t_heights); heights = heights_new(irg); -BE_TIMER_POP(t_heights); + BE_TIMER_POP(t_heights); ia32_calculate_non_address_mode_nodes(cg->birg); /* the transform phase is not safe for CSE (yet) because several nodes get