X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=1cec30fd6652c2bdc1c00a2316758d2a65023d63;hb=1b5f541f8cbdf52f7700557beda6130562bac5fb;hp=25e0c1f14fdbb04773cd5d66f58c9f975be1b679;hpb=503617365f85975763b86b1398d4d9efc2d825ad;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 25e0c1f14..1cec30fd6 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -24,15 +24,25 @@ #include "debug.h" #include "../benode_t.h" +#include "../besched.h" + #include "bearch_ia32_t.h" #include "ia32_nodes_attr.h" #include "../arch/archop.h" /* we need this for Min and Max nodes */ #include "ia32_transform.h" #include "ia32_new_nodes.h" +#include "ia32_map_regs.h" #include "gen_ia32_regalloc_if.h" +#ifdef NDEBUG +#define SET_IA32_ORIG_NODE(n, o) +#else +#define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o); +#endif /* NDEBUG */ + + #define SFP_SIGN "0x80000000" #define DFP_SIGN "0x8000000000000000" #define SFP_ABS "0x7FFFFFFF" @@ -57,7 +67,7 @@ typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block ir_node *op, ir_node *mem, ir_mode *mode); typedef enum { - ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS + ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max } ia32_known_const_t; /**************************************************************************************************** @@ -70,66 +80,33 @@ typedef enum { * ****************************************************************************************************/ -struct tv_ent { - entity *ent; - tarval *tv; -}; - -/* Compares two (entity, tarval) combinations */ -static int cmp_tv_ent(const void *a, const void *b, size_t len) { - const struct tv_ent *e1 = a; - const struct tv_ent *e2 = b; - - return !(e1->tv == e2->tv); -} - /* Generates an entity for a known FP const (used for FP Neg + Abs) */ -static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) { - static set *const_set = NULL; - struct tv_ent key; - struct tv_ent *entry; - char *tp_name; - char *ent_name; - char *cnst_str; +static const char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) { + static const struct { + const char *tp_name; + const char *ent_name; + const char *cnst_str; + } names [ia32_known_const_max] = { + { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */ + { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */ + { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */ + { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */ + }; + static struct entity *ent_cache[ia32_known_const_max]; + + const char *tp_name, *ent_name, *cnst_str; ir_type *tp; ir_node *cnst; ir_graph *rem; entity *ent; + tarval *tv; - if (! const_set) { - const_set = new_set(cmp_tv_ent, 10); - } - - switch (kct) { - case ia32_SSIGN: - tp_name = TP_SFP_SIGN; - ent_name = ENT_SFP_SIGN; - cnst_str = SFP_SIGN; - break; - case ia32_DSIGN: - tp_name = TP_DFP_SIGN; - ent_name = ENT_DFP_SIGN; - cnst_str = DFP_SIGN; - break; - case ia32_SABS: - tp_name = TP_SFP_ABS; - ent_name = ENT_SFP_ABS; - cnst_str = SFP_ABS; - break; - case ia32_DABS: - tp_name = TP_DFP_ABS; - ent_name = ENT_DFP_ABS; - cnst_str = DFP_ABS; - break; - } - - - key.tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode); - key.ent = NULL; + ent_name = names[kct].ent_name; + if (! ent_cache[kct]) { + tp_name = names[kct].tp_name; + cnst_str = names[kct].cnst_str; - entry = set_insert(const_set, &key, sizeof(key), HASH_PTR(key.tv)); - - if (! entry->ent) { + tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode); tp = new_type_primitive(new_id_from_str(tp_name), mode); ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp); @@ -142,15 +119,14 @@ static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) { const code irg */ rem = current_ir_graph; current_ir_graph = get_const_code_irg(); - cnst = new_Const(mode, key.tv); + cnst = new_Const(mode, tv); current_ir_graph = rem; set_atomic_ent_value(ent, cnst); - /* set the entry for hashmap */ - entry->ent = ent; + /* cache the entry */ + ent_cache[kct] = ent; } - return ent_name; } @@ -159,16 +135,11 @@ static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) { * Prints the old node name on cg obst and returns a pointer to it. */ const char *get_old_node_name(ia32_transform_env_t *env) { - static int name_cnt = 0; ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa; lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn); obstack_1grow(isa->name_obst, 0); isa->name_obst_size += obstack_object_size(isa->name_obst); - name_cnt++; - if (name_cnt % 1024 == 0) { - printf("name obst size reached %d bytes after %d nodes\n", isa->name_obst_size, name_cnt); - } return obstack_finish(isa->name_obst); } #endif /* NDEBUG */ @@ -264,9 +235,7 @@ static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, } } -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); set_ia32_res_mode(new_op, mode); @@ -343,9 +312,7 @@ static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node /* set AM support */ set_ia32_am_support(new_op, ia32_am_Dest); -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); set_ia32_res_mode(new_op, mode); @@ -383,9 +350,7 @@ static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_ set_ia32_am_support(new_op, ia32_am_Dest); } -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); set_ia32_res_mode(new_op, mode); @@ -505,9 +470,7 @@ static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { } } -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); set_ia32_res_mode(new_op, mode); @@ -555,7 +518,7 @@ static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) ir_node *proj_EAX, *proj_EDX, *mulh; ir_node *in[1]; - assert(mode_is_float(env->mode) && "Mulh with float not supported"); + assert(!mode_is_float(env->mode) && "Mulh with float not supported"); proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh); mulh = get_Proj_pred(proj_EAX); proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX); @@ -656,9 +619,7 @@ static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { else { new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode); set_ia32_am_support(new_op, ia32_am_None); -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); } return new_op; @@ -683,9 +644,7 @@ static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { else { new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode); set_ia32_am_support(new_op, ia32_am_None); -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); } return new_op; @@ -802,16 +761,27 @@ static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { } } -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); set_ia32_res_mode(new_op, mode); return new_rd_Proj(dbg, irg, block, new_op, mode, 0); } +static ir_node *get_proj_for_pn(const ir_node *irn, long pn) { + const ir_edge_t *edge; + ir_node *proj; + assert(get_irn_mode(irn) == mode_T && "need mode_T"); + + foreach_out_edge(irn, edge) { + proj = get_edge_src_irn(edge); + if (get_Proj_proj(proj) == pn) + return proj; + } + + return NULL; +} /** * Generates an ia32 DivMod with additional infrastructure for the @@ -836,13 +806,16 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir switch (dm_flav) { case flavour_Div: - mem = get_Div_mem(irn); + mem = get_Div_mem(irn); + mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res)); break; case flavour_Mod: - mem = get_Mod_mem(irn); + mem = get_Mod_mem(irn); + mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res)); break; case flavour_DivMod: - mem = get_DivMod_mem(irn); + mem = get_DivMod_mem(irn); + mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div)); break; default: assert(0); @@ -882,9 +855,7 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep); } -#ifndef NDEBUG - set_ia32_orig_node(res, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(res, get_old_node_name(env)); set_ia32_res_mode(res, mode_Is); @@ -935,9 +906,7 @@ static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, env->mode); set_ia32_am_support(new_op, ia32_am_Source); -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); return new_op; } @@ -1071,7 +1040,7 @@ static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) { * @return The created ia32 Minus node */ static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) { - char *name; + const char *name; ir_node *new_op; ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg); ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg); @@ -1086,9 +1055,7 @@ static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) { set_ia32_sc(new_op, name); -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); set_ia32_res_mode(new_op, env->mode); @@ -1142,7 +1109,7 @@ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) { ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg); ir_node *nomem = new_NoMem(); int size; - char *name; + const char *name; if (mode_is_float(mode)) { res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T); @@ -1152,9 +1119,7 @@ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) { set_ia32_sc(res, name); -#ifndef NDEBUG - set_ia32_orig_node(res, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(res, get_old_node_name(env)); set_ia32_res_mode(res, mode); @@ -1162,26 +1127,20 @@ static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) { } else { res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T); -#ifndef NDEBUG - set_ia32_orig_node(res, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(res, get_old_node_name(env)); set_ia32_res_mode(res, mode); p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX); p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX); res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T); -#ifndef NDEBUG - set_ia32_orig_node(res, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(res, get_old_node_name(env)); set_ia32_res_mode(res, mode); res = new_rd_Proj(dbg, irg, block, res, mode, 0); res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T); -#ifndef NDEBUG - set_ia32_orig_node(res, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(res, get_old_node_name(env)); set_ia32_res_mode(res, mode); res = new_rd_Proj(dbg, irg, block, res, mode, 0); @@ -1218,9 +1177,7 @@ static ir_node *gen_Load(ia32_transform_env_t *env) { set_ia32_am_flavour(new_op, ia32_B); set_ia32_ls_mode(new_op, get_Load_mode(node)); -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); return new_op; } @@ -1242,23 +1199,27 @@ static ir_node *gen_Store(ia32_transform_env_t *env) { ir_node *val = get_Store_value(node); ir_node *ptr = get_Store_ptr(node); ir_node *mem = get_Store_mem(node); + ir_mode *mode = get_irn_mode(val); ir_node *sval = val; ir_node *new_op; - /* in case of storing a const -> make it an attribute */ - if (is_ia32_Cnst(val)) { + /* in case of storing a const (but not a symconst) -> make it an attribute */ + if (is_ia32_Const(val)) { sval = noreg; } - if (mode_is_float(env->mode)) { - new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode); + if (mode_is_float(mode)) { + new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T); + } + else if (get_mode_size_bits(mode) == 8) { + new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T); } else { - new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode); + new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T); } /* stored const is an attribute (saves a register) */ - if (is_ia32_Cnst(val)) { + if (is_ia32_Const(val)) { set_ia32_Immop_attr(new_op, val); } @@ -1267,9 +1228,7 @@ static ir_node *gen_Store(ia32_transform_env_t *env) { set_ia32_am_flavour(new_op, ia32_B); set_ia32_ls_mode(new_op, get_irn_mode(val)); -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); return new_op; } @@ -1277,7 +1236,7 @@ static ir_node *gen_Store(ia32_transform_env_t *env) { /** - * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i + * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp * * @param env The transformation environment * @return The transformed node. @@ -1292,10 +1251,11 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) { ir_node *res = NULL; ir_node *pred = NULL; ir_node *noreg = ia32_new_NoReg_gp(env->cg); - ir_node *nomem = new_NoMem(); ir_node *cmp_a, *cmp_b, *cnst, *expr; if (is_Proj(sel) && sel_mode == mode_b) { + ir_node *nomem = new_NoMem(); + pred = get_Proj_pred(sel); /* get both compare operators */ @@ -1307,6 +1267,32 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) { expr = get_expr_op(cmp_a, cmp_b); if (cnst && expr) { + if (mode_is_int(get_irn_mode(expr))) { + if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) { + /* a Cmp A, 0 */ + ir_node *op1 = expr; + ir_node *op2 = expr; + ir_node *and = skip_Proj(expr); + char *cnst = NULL; + + /* check, if expr is an only once used And operation */ + if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) { + op1 = get_irn_n(and, 2); + op2 = get_irn_n(and, 3); + + cnst = get_ia32_cnst(and); + } + res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T); + set_ia32_pncode(res, get_Proj_proj(sel)); + + if (cnst) { + copy_ia32_Immop_attr(res, and); + } + + SET_IA32_ORIG_NODE(res, get_old_node_name(env)); + return res; + } + } res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T); set_ia32_Immop_attr(res, cnst); } @@ -1322,10 +1308,7 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) { set_ia32_pncode(res, get_Cond_defaultProj(node)); } -#ifndef NDEBUG - set_ia32_orig_node(res, get_old_node_name(env)); -#endif /* NDEBUG */ - + SET_IA32_ORIG_NODE(res, get_old_node_name(env)); return res; } @@ -1368,9 +1351,7 @@ static ir_node *gen_CopyB(ia32_transform_env_t *env) { set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is)); } -#ifndef NDEBUG - set_ia32_orig_node(res, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(res, get_old_node_name(env)); return res; } @@ -1388,14 +1369,74 @@ static ir_node *gen_Mux(ia32_transform_env_t *env) { ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \ get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode); -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); return new_op; } +/** + * Following conversion rules apply: + * + * INT -> INT + * ============ + * 1) n bit -> m bit n < m (upscale) + * always ignored + * 2) n bit -> m bit n == m (sign change) + * always ignored + * 3) n bit -> m bit n > m (downscale) + * a) Un -> Um = AND Un, (1 << m) - 1 + * b) Sn -> Um same as a) + * c) Un -> Sm same as a) + * d) Sn -> Sm = ASHL Sn, (n - m); ASHR Sn, (n - m) + * + * INT -> FLOAT + * ============== + * SSE(1/2) convert to float or double (cvtsi2ss/sd) + * + * FLOAT -> INT + * ============== + * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si) + * if target mode < 32bit: additional INT -> INT conversion (see above) + * + * FLOAT -> FLOAT + * ================ + * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss) + */ + +static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op, + ir_mode *src_mode, ir_mode *tgt_mode) +{ + int n = get_mode_size_bits(src_mode); + int m = get_mode_size_bits(tgt_mode); + dbg_info *dbg = env->dbg; + ir_graph *irg = env->irg; + ir_node *block = env->block; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *nomem = new_rd_NoMem(irg); + ir_node *new_op, *proj; + + assert(n > m && "downscale expected"); + + if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) { + /* ASHL Sn, n - m */ + new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T); + proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0); + set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is)); + set_ia32_am_support(new_op, ia32_am_Source); + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); + + /* ASHR Sn, n - m */ + new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T); + set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is)); + } + else { + new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T); + set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is)); + } + + return new_op; +} /** * Transforms a Conv node. @@ -1414,6 +1455,7 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) { ir_node *noreg = ia32_new_NoReg_gp(env->cg); ir_node *nomem = new_rd_NoMem(irg); firm_dbg_module_t *mod = env->mod; + ir_node *proj; if (src_mode == tgt_mode) { /* this can happen when changing mode_P to mode_Is */ @@ -1431,6 +1473,15 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) { /* ... to int */ DB((mod, LEVEL_1, "create Conv(float, int) ...")); new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T); + /* if target mode is not int: add an additional downscale convert */ + if (get_mode_size_bits(tgt_mode) < 32) { + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); + set_ia32_res_mode(new_op, tgt_mode); + set_ia32_am_support(new_op, ia32_am_Source); + + proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0); + new_op = gen_int_downscale_conv(env, proj, src_mode, tgt_mode); + } } } else { @@ -1442,15 +1493,19 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) { } else { /* ... to int */ - DB((mod, LEVEL_1, "omitting Conv(Int, Int) ...")); - edges_reroute(env->irn, op, irg); + if (get_mode_size_bits(src_mode) <= get_mode_size_bits(tgt_mode)) { + DB((mod, LEVEL_1, "omitting upscale Conv(%+F, %+F) ...", src_mode, tgt_mode)); + edges_reroute(env->irn, op, irg); + } + else { + DB((mod, LEVEL_1, "create downscale Conv(%+F, %+F) ...", src_mode, tgt_mode)); + new_op = gen_int_downscale_conv(env, op, src_mode, tgt_mode); + } } } if (new_op) { -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); set_ia32_res_mode(new_op, tgt_mode); set_ia32_am_support(new_op, ia32_am_Source); @@ -1473,6 +1528,35 @@ static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) { * ********************************************/ +static ir_node *gen_StackParam(ia32_transform_env_t *env) { + ir_node *new_op = NULL; + ir_node *node = env->irn; + ir_node *noreg = ia32_new_NoReg_gp(env->cg); + ir_node *mem = new_rd_NoMem(env->irg); + ir_node *ptr = get_irn_n(node, 0); + entity *ent = be_get_frame_entity(node); + ir_mode *mode = env->mode; + + if (mode_is_float(mode)) { + new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); + } + else { + new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); + } + + set_ia32_frame_ent(new_op, ent); + set_ia32_use_frame(new_op); + + set_ia32_am_support(new_op, ia32_am_Source); + set_ia32_op_type(new_op, ia32_AddrModeS); + set_ia32_am_flavour(new_op, ia32_B); + set_ia32_ls_mode(new_op, mode); + + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); + + return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0); +} + /** * Transforms a FrameAddr into an ia32 Add. */ @@ -1488,9 +1572,7 @@ static ir_node *gen_FrameAddr(ia32_transform_env_t *env) { set_ia32_am_support(new_op, ia32_am_Full); set_ia32_use_frame(new_op); -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0); } @@ -1515,15 +1597,14 @@ static ir_node *gen_FrameLoad(ia32_transform_env_t *env) { } set_ia32_frame_ent(new_op, ent); + set_ia32_use_frame(new_op); set_ia32_am_support(new_op, ia32_am_Source); set_ia32_op_type(new_op, ia32_AddrModeS); set_ia32_am_flavour(new_op, ia32_B); set_ia32_ls_mode(new_op, mode); -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); return new_op; } @@ -1545,19 +1626,22 @@ static ir_node *gen_FrameStore(ia32_transform_env_t *env) { if (mode_is_float(mode)) { new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); } + else if (get_mode_size_bits(mode) == 8) { + new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); + } else { new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T); } + set_ia32_frame_ent(new_op, ent); + set_ia32_use_frame(new_op); set_ia32_am_support(new_op, ia32_am_Dest); set_ia32_op_type(new_op, ia32_AddrModeD); set_ia32_am_flavour(new_op, ia32_B); set_ia32_ls_mode(new_op, mode); -#ifndef NDEBUG - set_ia32_orig_node(new_op, get_old_node_name(env)); -#endif /* NDEBUG */ + SET_IA32_ORIG_NODE(new_op, get_old_node_name(env)); return new_op; } @@ -1574,6 +1658,184 @@ static ir_node *gen_FrameStore(ia32_transform_env_t *env) { * *********************************************************/ +/** + * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG. + * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION. + */ +void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { + ia32_transform_env_t tenv; + ir_node *in1, *in2, *noreg, *nomem, *res; + const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots; + + /* Return if AM node or not a Sub or fSub */ + if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn))) + return; + + noreg = ia32_new_NoReg_gp(cg); + nomem = new_rd_NoMem(cg->irg); + in1 = get_irn_n(irn, 2); + in2 = get_irn_n(irn, 3); + in1_reg = arch_get_irn_register(cg->arch_env, in1); + in2_reg = arch_get_irn_register(cg->arch_env, in2); + out_reg = get_ia32_out_reg(irn, 0); + + tenv.block = get_nodes_block(irn); + tenv.dbg = get_irn_dbg_info(irn); + tenv.irg = cg->irg; + tenv.irn = irn; + tenv.mod = cg->mod; + tenv.mode = get_ia32_res_mode(irn); + tenv.cg = cg; + + /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */ + if (REGS_ARE_EQUAL(out_reg, in2_reg)) { + /* generate the neg src2 */ + res = gen_Minus(&tenv, in2); + arch_set_irn_register(cg->arch_env, res, in2_reg); + + /* add to schedule */ + sched_add_before(irn, res); + + /* generate the add */ + if (mode_is_float(tenv.mode)) { + res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T); + set_ia32_am_support(res, ia32_am_Source); + } + else { + res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T); + set_ia32_am_support(res, ia32_am_Full); + } + + SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv)); + /* copy register */ + slots = get_ia32_slots(res); + slots[0] = in2_reg; + + /* add to schedule */ + sched_add_before(irn, res); + + /* remove the old sub */ + sched_remove(irn); + + /* exchange the add and the sub */ + exchange(irn, res); + } +} + +/** + * Transforms a LEA into an Add if possible + * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION. + */ +void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) { + ia32_am_flavour_t am_flav; + int imm = 0; + ir_node *res = NULL; + ir_node *nomem, *noreg, *base, *index, *op1, *op2; + char *offs; + ia32_transform_env_t tenv; + const arch_register_t *out_reg, *base_reg, *index_reg; + + /* must be a LEA */ + if (! is_ia32_Lea(irn)) + return; + + am_flav = get_ia32_am_flavour(irn); + + /* only some LEAs can be transformed to an Add */ + if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI) + return; + + noreg = ia32_new_NoReg_gp(cg); + nomem = new_rd_NoMem(cg->irg); + op1 = noreg; + op2 = noreg; + base = get_irn_n(irn, 0); + index = get_irn_n(irn,1); + + offs = get_ia32_am_offs(irn); + + /* offset has a explicit sign -> we need to skip + */ + if (offs && offs[0] == '+') + offs++; + + out_reg = arch_get_irn_register(cg->arch_env, irn); + base_reg = arch_get_irn_register(cg->arch_env, base); + index_reg = arch_get_irn_register(cg->arch_env, index); + + tenv.block = get_nodes_block(irn); + tenv.dbg = get_irn_dbg_info(irn); + tenv.irg = cg->irg; + tenv.irn = irn; + tenv.mod = cg->mod; + tenv.mode = get_irn_mode(irn); + tenv.cg = cg; + + switch(get_ia32_am_flavour(irn)) { + case ia32_am_B: + /* out register must be same as base register */ + if (! REGS_ARE_EQUAL(out_reg, base_reg)) + return; + + op1 = base; + break; + case ia32_am_OB: + /* out register must be same as base register */ + if (! REGS_ARE_EQUAL(out_reg, base_reg)) + return; + + op1 = base; + imm = 1; + break; + case ia32_am_OI: + /* out register must be same as index register */ + if (! REGS_ARE_EQUAL(out_reg, index_reg)) + return; + + op1 = index; + imm = 1; + break; + case ia32_am_BI: + /* out register must be same as one in register */ + if (REGS_ARE_EQUAL(out_reg, base_reg)) { + op1 = base; + op2 = index; + } + else if (REGS_ARE_EQUAL(out_reg, index_reg)) { + op1 = index; + op2 = base; + } + else { + /* in registers a different from out -> no Add possible */ + return; + } + default: + break; + } + + res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T); + arch_set_irn_register(cg->arch_env, res, out_reg); + set_ia32_op_type(res, ia32_Normal); + + if (imm) + set_ia32_cnst(res, offs); + + SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv)); + + /* add Add to schedule */ + sched_add_before(irn, res); + + res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0); + + /* add result Proj to schedule */ + sched_add_before(irn, res); + + /* remove the old LEA */ + sched_remove(irn); + + /* exchange the Add and the LEA */ + exchange(irn, res); +} + /** * Transforms the given firm node (and maybe some other related nodes) * into one or more assembler nodes. @@ -1583,7 +1845,7 @@ static ir_node *gen_FrameStore(ia32_transform_env_t *env) { */ void ia32_transform_node(ir_node *node, void *env) { ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env; - opcode code = get_irn_opcode(node); + opcode code; ir_node *asm_node = NULL; ia32_transform_env_t tenv; @@ -1616,6 +1878,7 @@ void ia32_transform_node(ir_node *node, void *env) { DBG((tenv.mod, LEVEL_1, "check %+F ... ", node)); + code = get_irn_opcode(node); switch (code) { BINOP(Add); BINOP(Sub); @@ -1688,6 +1951,7 @@ void ia32_transform_node(ir_node *node, void *env) { BE_GEN(FrameAddr); BE_GEN(FrameLoad); BE_GEN(FrameStore); + BE_GEN(StackParam); break; bad: fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));