X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_transform.c;h=0ea0a0083b4b093879ad3c8aba5da98b20c6cd4b;hb=ed85eaaf130c68efbc2b671eee2910071bbc6c8d;hp=12e844f694b35edb3318e207b8cd2ac5eee6c222;hpb=3f57d89fcb7055fc726a41aa63214aab97854cdf;p=libfirm diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c index 12e844f69..0ea0a0083 100644 --- a/ir/be/ia32/ia32_transform.c +++ b/ir/be/ia32/ia32_transform.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -45,7 +45,7 @@ #include "irdom.h" #include "error.h" #include "array_t.h" -#include "height.h" +#include "heights.h" #include "../benode.h" #include "../besched.h" @@ -60,7 +60,6 @@ #include "ia32_nodes_attr.h" #include "ia32_transform.h" #include "ia32_new_nodes.h" -#include "ia32_map_regs.h" #include "ia32_dbg_stat.h" #include "ia32_optimize.h" #include "ia32_util.h" @@ -86,13 +85,13 @@ #define ENT_DFP_ABS "C_ia32_dfp_abs" #define ENT_ULL_BIAS "C_ia32_ull_bias" -#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode) +#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode) #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode) DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) static ir_node *initial_fpcw = NULL; -int no_pic_adjust; +int ia32_no_pic_adjust; typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, @@ -154,7 +153,7 @@ static bool is_Const_Minus_1(ir_node *node) */ static bool is_simple_x87_Const(ir_node *node) { - tarval *tv = get_Const_tarval(node); + ir_tarval *tv = get_Const_tarval(node); if (tarval_is_null(tv) || tarval_is_one(tv)) return true; @@ -167,8 +166,8 @@ static bool is_simple_x87_Const(ir_node *node) */ static bool is_simple_sse_Const(ir_node *node) { - tarval *tv = get_Const_tarval(node); - ir_mode *mode = get_tarval_mode(tv); + ir_tarval *tv = get_Const_tarval(node); + ir_mode *mode = get_tarval_mode(tv); if (mode == mode_F) return true; @@ -200,8 +199,11 @@ static bool is_simple_sse_Const(ir_node *node) */ static ir_node *get_symconst_base(void) { - if (be_get_irg_options(env_cg->irg)->pic) { - return arch_code_generator_get_pic_base(env_cg); + ir_graph *irg = current_ir_graph; + + if (be_get_irg_options(irg)->pic) { + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + return arch_env->impl->get_pic_base(irg); } return noreg_GP; @@ -226,7 +228,7 @@ static ir_node *gen_Const(ir_node *node) ir_entity *floatent; if (ia32_cg_config.use_sse2) { - tarval *tv = get_Const_tarval(node); + ir_tarval *tv = get_Const_tarval(node); if (tarval_is_null(tv)) { load = new_bd_ia32_xZero(dbgi, block); set_ia32_ls_mode(load, mode); @@ -282,7 +284,7 @@ static ir_node *gen_Const(ir_node *node) } } #endif /* CONSTRUCT_SSE_CONST */ - floatent = create_float_const_entity(node); + floatent = ia32_create_float_const_entity(node); base = get_symconst_base(); load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem, @@ -305,7 +307,7 @@ static ir_node *gen_Const(ir_node *node) ir_mode *ls_mode; ir_node *base; - floatent = create_float_const_entity(node); + floatent = ia32_create_float_const_entity(node); /* create_float_const_ent is smart and sometimes creates smaller entities */ ls_mode = get_type_mode(get_entity_type(floatent)); @@ -326,9 +328,9 @@ end: be_dep_on_frame(load); return res; } else { /* non-float mode */ - ir_node *cnst; - tarval *tv = get_Const_tarval(node); - long val; + ir_node *cnst; + ir_tarval *tv = get_Const_tarval(node); + long val; tv = tarval_convert_to(tv, mode_Iu); @@ -495,11 +497,11 @@ ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) }; static ir_entity *ent_cache[ia32_known_const_max]; - const char *ent_name, *cnst_str; - ir_type *tp; - ir_entity *ent; - tarval *tv; - ir_mode *mode; + const char *ent_name, *cnst_str; + ir_type *tp; + ir_entity *ent; + ir_tarval *tv; + ir_mode *mode; ent_name = names[kct].ent_name; if (! ent_cache[kct]) { @@ -588,10 +590,10 @@ static int ia32_use_source_address_mode(ir_node *block, ir_node *node, return 0; /* don't do AM if other node inputs depend on the load (via mem-proj) */ - if (other != NULL && prevents_AM(block, load, other)) + if (other != NULL && ia32_prevents_AM(block, load, other)) return 0; - if (other2 != NULL && prevents_AM(block, load, other2)) + if (other2 != NULL && ia32_prevents_AM(block, load, other2)) return 0; return 1; @@ -615,7 +617,7 @@ static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem) { /* construct load address */ memset(addr, 0, sizeof(addr[0])); - ia32_create_address_mode(addr, ptr, 0); + ia32_create_address_mode(addr, ptr, ia32_create_am_normal); addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP; addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP; @@ -633,7 +635,7 @@ static void build_address(ia32_address_mode_t *am, ir_node *node, /* floating point immediates */ if (is_Const(node)) { - ir_entity *entity = create_float_const_entity(node); + ir_entity *entity = ia32_create_float_const_entity(node); addr->base = get_symconst_base(); addr->index = noreg_GP; addr->mem = nomem; @@ -839,15 +841,15 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, * op2 input */ new_op2 = NULL; if (!(flags & match_try_am) && use_immediate) { - new_op2 = try_create_Immediate(op2, 0); + new_op2 = ia32_try_create_Immediate(op2, 0); } if (new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) { - build_address(am, op2, 0); + build_address(am, op2, ia32_create_am_normal); new_op1 = (op1 == NULL ? NULL : be_transform_node(op1)); if (mode_is_float(mode)) { - new_op2 = ia32_new_NoReg_vfp(env_cg); + new_op2 = ia32_new_NoReg_vfp(current_ir_graph); } else { new_op2 = noreg_GP; } @@ -856,10 +858,10 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, use_am && ia32_use_source_address_mode(block, op1, op2, other_op, flags)) { ir_node *noreg; - build_address(am, op1, 0); + build_address(am, op1, ia32_create_am_normal); if (mode_is_float(mode)) { - noreg = ia32_new_NoReg_vfp(env_cg); + noreg = ia32_new_NoReg_vfp(current_ir_graph); } else { noreg = noreg_GP; } @@ -869,7 +871,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block, } else { new_op1 = be_transform_node(op2); new_op2 = noreg; - am->ins_permuted = 1; + am->ins_permuted = true; } am->op_type = ia32_AddrModeS; } else { @@ -983,12 +985,12 @@ enum { n_ia32_l_binop_right, /**< ia32 right input */ n_ia32_l_binop_eflags /**< ia32 eflags input */ }; -COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left) -COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right) -COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags) -COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_minuend, n_Sbb_minuend) -COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend) -COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags) +COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Adc_left, n_Adc_left) +COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Adc_right, n_Adc_right) +COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Adc_eflags, n_Adc_eflags) +COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Sbb_minuend, n_Sbb_minuend) +COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend) +COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Sbb_eflags, n_Sbb_eflags) /** * Construct a binary operation which also consumes the eflags. @@ -1035,8 +1037,8 @@ static ir_node *get_fpcw(void) if (initial_fpcw != NULL) return initial_fpcw; - fpcw = be_abi_get_ignore_irn(be_get_irg_abi(env_cg->irg), - &ia32_fp_cw_regs[REG_FPCW]); + fpcw = be_abi_get_ignore_irn(be_get_irg_abi(current_ir_graph), + &ia32_registers[REG_FPCW]); initial_fpcw = be_transform_node(fpcw); return initial_fpcw; @@ -1064,8 +1066,12 @@ static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2, match_flags_t flags = match_commutative; /* happens for div nodes... */ - if (mode == mode_T) - mode = get_divop_resmod(node); + if (mode == mode_T) { + if (is_Div(node)) + mode = get_Div_resmode(node); + else + panic("can't determine mode"); + } /* cannot use address mode with long double on x87 */ if (get_mode_size_bits(mode) <= 64) @@ -1138,8 +1144,12 @@ static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2, /* lowered shift instruction may have a dependency operand, handle it here */ if (get_irn_arity(node) == 3) { /* we have a dependency */ - ir_node *new_dep = be_transform_node(get_irn_n(node, 2)); - add_irn_dep(new_node, new_dep); + ir_node* dep = get_irn_n(node, 2); + if (get_irn_n_edges(dep) > 1) { + /* ... which has at least one user other than 'node' */ + ir_node *new_dep = be_transform_node(dep); + add_irn_dep(new_node, new_dep); + } } return new_node; @@ -1175,7 +1185,7 @@ static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func, return new_node; } -static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, +static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block, ia32_address_t *addr) { ir_node *base, *index, *res; @@ -1372,8 +1382,8 @@ static ir_node *gen_And(ir_node *node) /* is it a zero extension? */ if (is_Const(op2)) { - tarval *tv = get_Const_tarval(op2); - long v = get_tarval_long(tv); + ir_tarval *tv = get_Const_tarval(op2); + long v = get_tarval_long(tv); if (v == 0xFF || v == 0xFFFF) { dbg_info *dbgi = get_irn_dbg_info(node); @@ -1492,8 +1502,13 @@ static ir_node *transform_AM_mem(ir_node *const block, ins[n++] = be_transform_node(pred); } - ins[n++] = am_mem; + if (n==1 && ins[0] == am_mem) { + return am_mem; + /* creating a new Sync and relying on CSE may fail, + * if am_mem is a ProjM, which does not yet verify. */ + } + ins[n++] = am_mem; return new_r_Sync(block, n, ins); } else { ir_node *ins[2]; @@ -1531,7 +1546,7 @@ static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block, } /** - * Generates an ia32 DivMod with additional infrastructure for the + * Generates an ia32 Div with additional infrastructure for the * register allocator if needed. */ static ir_node *create_Div(ir_node *node) @@ -1563,12 +1578,6 @@ static ir_node *create_Div(ir_node *node) mem = get_Mod_mem(node); mode = get_Mod_resmode(node); break; - case iro_DivMod: - op1 = get_DivMod_left(node); - op2 = get_DivMod_right(node); - mem = get_DivMod_mem(node); - mode = get_DivMod_resmode(node); - break; default: panic("invalid divmod node %+F", node); } @@ -1616,36 +1625,20 @@ static ir_node *gen_Mod(ir_node *node) */ static ir_node *gen_Div(ir_node *node) { - return create_Div(node); -} - -/** - * Generates an ia32 DivMod. - */ -static ir_node *gen_DivMod(ir_node *node) -{ - return create_Div(node); -} - - - -/** - * Creates an ia32 floating Div. - * - * @return The created ia32 xDiv node - */ -static ir_node *gen_Quot(ir_node *node) -{ - ir_node *op1 = get_Quot_left(node); - ir_node *op2 = get_Quot_right(node); + ir_mode *mode = get_Div_resmode(node); + if (mode_is_float(mode)) { + ir_node *op1 = get_Div_left(node); + ir_node *op2 = get_Div_right(node); - if (ia32_cg_config.use_sse2) { - return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am); - } else { - return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv); + if (ia32_cg_config.use_sse2) { + return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am); + } else { + return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv); + } } -} + return create_Div(node); +} /** * Creates an ia32 Shl. @@ -1687,8 +1680,8 @@ static ir_node *gen_Shrs(ir_node *node) ir_node *right = get_Shrs_right(node); if (is_Const(right)) { - tarval *tv = get_Const_tarval(right); - long val = get_tarval_long(tv); + ir_tarval *tv = get_Const_tarval(right); + long val = get_tarval_long(tv); if (val == 31) { /* this is a sign extension */ dbg_info *dbgi = get_irn_dbg_info(node); @@ -1704,8 +1697,8 @@ static ir_node *gen_Shrs(ir_node *node) ir_node *shl_left = get_Shl_left(left); ir_node *shl_right = get_Shl_right(left); if (is_Const(shl_right)) { - tarval *tv1 = get_Const_tarval(right); - tarval *tv2 = get_Const_tarval(shl_right); + ir_tarval *tv1 = get_Const_tarval(right); + ir_tarval *tv2 = get_Const_tarval(shl_right); if (tv1 == tv2 && tarval_is_long(tv1)) { long val = get_tarval_long(tv1); if (val == 16 || val == 24) { @@ -1804,7 +1797,7 @@ static ir_node *gen_Minus(ir_node *node) /* TODO: non-optimal... if we have many xXors, then we should * rather create a load for the const and use that instead of * several AM nodes... */ - ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg); + ir_node *noreg_xmm = ia32_new_NoReg_xmm(current_ir_graph); new_node = new_bd_ia32_xXor(dbgi, block, get_symconst_base(), noreg_GP, nomem, new_op, noreg_xmm); @@ -1856,7 +1849,7 @@ static ir_node *create_abs(dbg_info *dbgi, ir_node *block, ir_node *op, new_op = be_transform_node(op); if (ia32_cg_config.use_sse2) { - ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg); + ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph); new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(), noreg_GP, nomem, new_op, noreg_fp); @@ -1881,7 +1874,7 @@ static ir_node *create_abs(dbg_info *dbgi, ir_node *block, ir_node *op, } } } else { - ir_node *xor; + ir_node *xorn; ir_node *sign_extension; if (get_mode_size_bits(mode) == 32) { @@ -1892,16 +1885,16 @@ static ir_node *create_abs(dbg_info *dbgi, ir_node *block, ir_node *op, sign_extension = create_sex_32_64(dbgi, new_block, new_op, node); - xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, + xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, sign_extension); - SET_IA32_ORIG_NODE(xor, node); + SET_IA32_ORIG_NODE(xorn, node); if (negate) { new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, - nomem, sign_extension, xor); + nomem, sign_extension, xorn); } else { new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, - nomem, xor, sign_extension); + nomem, xorn, sign_extension); } SET_IA32_ORIG_NODE(new_node, node); } @@ -1923,85 +1916,151 @@ static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) return new_bd_ia32_Bt(dbgi, new_block, op1, op2); } -/** - * Transform a node returning a "flag" result. - * - * @param node the node to transform - * @param pnc_out the compare mode to use - */ -static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out) +static ia32_condition_code_t pnc_to_condition_code(pn_Cmp pnc, ir_mode *mode) +{ + if (mode_is_float(mode)) { + switch (pnc) { + case pn_Cmp_Eq: return ia32_cc_float_equal; + case pn_Cmp_Lt: return ia32_cc_float_below; + case pn_Cmp_Le: return ia32_cc_float_below_equal; + case pn_Cmp_Gt: return ia32_cc_float_above; + case pn_Cmp_Ge: return ia32_cc_float_above_equal; + case pn_Cmp_Lg: return ia32_cc_not_equal; + case pn_Cmp_Leg: return ia32_cc_not_parity; + case pn_Cmp_Uo: return ia32_cc_parity; + case pn_Cmp_Ue: return ia32_cc_equal; + case pn_Cmp_Ul: return ia32_cc_float_unordered_below; + case pn_Cmp_Ule: return ia32_cc_float_unordered_below_equal; + case pn_Cmp_Ug: return ia32_cc_float_unordered_above; + case pn_Cmp_Uge: return ia32_cc_float_unordered_above_equal; + case pn_Cmp_Ne: return ia32_cc_float_not_equal; + case pn_Cmp_False: + case pn_Cmp_True: + case pn_Cmp_max: + /* should we introduce a jump always/jump never? */ + break; + } + panic("Unexpected float pnc"); + } else if (mode_is_signed(mode)) { + switch (pnc) { + case pn_Cmp_Ue: + case pn_Cmp_Eq: return ia32_cc_equal; + case pn_Cmp_Ul: + case pn_Cmp_Lt: return ia32_cc_less; + case pn_Cmp_Ule: + case pn_Cmp_Le: return ia32_cc_less_equal; + case pn_Cmp_Ug: + case pn_Cmp_Gt: return ia32_cc_greater; + case pn_Cmp_Uge: + case pn_Cmp_Ge: return ia32_cc_greater_equal; + case pn_Cmp_Lg: + case pn_Cmp_Ne: return ia32_cc_not_equal; + case pn_Cmp_Leg: + case pn_Cmp_Uo: + case pn_Cmp_False: + case pn_Cmp_True: + case pn_Cmp_max: + /* introduce jump always/jump never? */ + break; + } + panic("Unexpected pnc"); + } else { + switch (pnc) { + case pn_Cmp_Ue: + case pn_Cmp_Eq: return ia32_cc_equal; + case pn_Cmp_Ul: + case pn_Cmp_Lt: return ia32_cc_below; + case pn_Cmp_Ule: + case pn_Cmp_Le: return ia32_cc_below_equal; + case pn_Cmp_Ug: + case pn_Cmp_Gt: return ia32_cc_above; + case pn_Cmp_Uge: + case pn_Cmp_Ge: return ia32_cc_above_equal; + case pn_Cmp_Lg: + case pn_Cmp_Ne: return ia32_cc_not_equal; + case pn_Cmp_Leg: + case pn_Cmp_Uo: + case pn_Cmp_False: + case pn_Cmp_True: + case pn_Cmp_max: + /* introduce jump always/jump never? */ + break; + } + panic("Unexpected pnc"); + } +} + +static ir_node *get_flags_mode_b(ir_node *node, ia32_condition_code_t *cc_out) { + /* a mode_b value, we have to compare it against 0 */ + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *new_block = be_transform_node(get_nodes_block(node)); + ir_node *new_op = be_transform_node(node); + ir_node *flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, new_op, false); + *cc_out = ia32_cc_not_equal; + return flags; +} + +static ir_node *get_flags_node_cmp(ir_node *node, ia32_condition_code_t *cc_out) +{ + /* must have a Proj(Cmp) as input */ + ir_node *cmp = get_Proj_pred(node); + int pnc = get_Proj_pn_cmp(node); + ir_node *l = get_Cmp_left(cmp); + ir_mode *mode = get_irn_mode(l); ir_node *flags; - ir_node *new_op; - ir_node *new_block; - dbg_info *dbgi; - /* we have a Cmp as input */ - if (is_Proj(node)) { - ir_node *pred = get_Proj_pred(node); - if (is_Cmp(pred)) { - pn_Cmp pnc = get_Proj_proj(node); - if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) { - ir_node *l = get_Cmp_left(pred); - ir_node *r = get_Cmp_right(pred); - if (is_And(l)) { - ir_node *la = get_And_left(l); - ir_node *ra = get_And_right(l); - if (is_Shl(la)) { - ir_node *c = get_Shl_left(la); - if (is_Const_1(c) && (is_Const_0(r) || r == la)) { - /* (1 << n) & ra) */ - ir_node *n = get_Shl_right(la); - flags = gen_bt(pred, ra, n); - /* we must generate a Jc/Jnc jump */ - pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge; - if (r == la) - pnc ^= pn_Cmp_Leg; - *pnc_out = ia32_pn_Cmp_unsigned | pnc; - return flags; - } - } - if (is_Shl(ra)) { - ir_node *c = get_Shl_left(ra); - if (is_Const_1(c) && (is_Const_0(r) || r == ra)) { - /* la & (1 << n)) */ - ir_node *n = get_Shl_right(ra); - flags = gen_bt(pred, la, n); - /* we must generate a Jc/Jnc jump */ - pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge; - if (r == ra) - pnc ^= pn_Cmp_Leg; - *pnc_out = ia32_pn_Cmp_unsigned | pnc; - return flags; - } - } - } + /* check for bit-test */ + if (ia32_cg_config.use_bt + && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq || pnc == pn_Cmp_Ne + || pnc == pn_Cmp_Ue)) { + ir_node *l = get_Cmp_left(cmp); + ir_node *r = get_Cmp_right(cmp); + if (is_And(l)) { + ir_node *la = get_And_left(l); + ir_node *ra = get_And_right(l); + if (is_Shl(ra)) { + ir_node *tmp = la; + la = ra; + ra = tmp; } - /* add ia32 compare flags */ - { - ir_node *l = get_Cmp_left(pred); - ir_mode *mode = get_irn_mode(l); - if (mode_is_float(mode)) - pnc |= ia32_pn_Cmp_float; - else if (! mode_is_signed(mode)) - pnc |= ia32_pn_Cmp_unsigned; + if (is_Shl(la)) { + ir_node *c = get_Shl_left(la); + if (is_Const_1(c) && is_Const_0(r)) { + /* (1 << n) & ra) */ + ir_node *n = get_Shl_right(la); + flags = gen_bt(cmp, ra, n); + /* the bit is copied into the CF flag */ + if (pnc & pn_Cmp_Eq) + *cc_out = ia32_cc_above_equal; /* test for CF=0 */ + else + *cc_out = ia32_cc_below; /* test for CF=1 */ + return flags; + } } - *pnc_out = pnc; - flags = be_transform_node(pred); - return flags; } } - /* a mode_b value, we have to compare it against 0 */ - dbgi = get_irn_dbg_info(node); - new_block = be_transform_node(get_nodes_block(node)); - new_op = be_transform_node(node); - flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, - new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0); - *pnc_out = pn_Cmp_Lg; + /* just do a normal transformation of the Cmp */ + *cc_out = pnc_to_condition_code(pnc, mode); + flags = be_transform_node(cmp); return flags; } +/** + * Transform a node returning a "flag" result. + * + * @param node the node to transform + * @param cc_out the compare mode to use + */ +static ir_node *get_flags_node(ir_node *node, ia32_condition_code_t *cc_out) +{ + if (is_Proj(node) && is_Cmp(get_Proj_pred(node))) + return get_flags_node_cmp(node, cc_out); + assert(get_irn_mode(node) == mode_b); + return get_flags_mode_b(node, cc_out); +} + /** * Transforms a Load. * @@ -2023,7 +2082,7 @@ static ir_node *gen_Load(ir_node *node) /* construct load address */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, ptr, 0); + ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); base = addr.base; index = addr.index; @@ -2065,9 +2124,9 @@ static ir_node *gen_Load(ir_node *node) set_address(new_node, &addr); if (get_irn_pinned(node) == op_pin_state_floats) { - assert(pn_ia32_xLoad_res == pn_ia32_vfld_res - && pn_ia32_vfld_res == pn_ia32_Load_res - && pn_ia32_Load_res == pn_ia32_res); + assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res + && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res + && (int)pn_ia32_Load_res == (int)pn_ia32_res); arch_irn_add_flags(new_node, arch_irn_flags_rematerializable); } @@ -2102,14 +2161,14 @@ static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem, /* don't do AM if other node inputs depend on the load (via mem-proj) */ if (other != NULL && get_nodes_block(other) == block && - heights_reachable_in_block(heights, other, load)) { + heights_reachable_in_block(ia32_heights, other, load)) { return 0; } - if (prevents_AM(block, load, mem)) + if (ia32_prevents_AM(block, load, mem)) return 0; /* Store should be attached to the load via mem */ - assert(heights_reachable_in_block(heights, mem, load)); + assert(heights_reachable_in_block(ia32_heights, mem, load)); return 1; } @@ -2208,26 +2267,20 @@ static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem, return new_node; } -static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc) -{ - ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu; - return get_negated_pnc(pnc, mode); -} - static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) { - ir_mode *mode = get_irn_mode(node); - ir_node *mux_true = get_Mux_true(node); - ir_node *mux_false = get_Mux_false(node); - ir_node *cond; - dbg_info *dbgi; - ir_node *block; - ir_node *new_block; - ir_node *flags; - ir_node *new_node; - bool negated; - pn_Cmp pnc; - ia32_address_t addr; + ir_mode *mode = get_irn_mode(node); + ir_node *mux_true = get_Mux_true(node); + ir_node *mux_false = get_Mux_false(node); + ir_node *cond; + dbg_info *dbgi; + ir_node *block; + ir_node *new_block; + ir_node *flags; + ir_node *new_node; + bool negated; + ia32_condition_code_t cc; + ia32_address_t addr; if (get_mode_size_bits(mode) != 8) return NULL; @@ -2241,12 +2294,12 @@ static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) } cond = get_Mux_sel(node); - flags = get_flags_node(cond, &pnc); + flags = get_flags_node(cond, &cc); /* we can't handle the float special cases with SetM */ - if (pnc & ia32_pn_Cmp_float) + if (cc & ia32_cc_additional_float_cases) return NULL; if (negated) - pnc = ia32_get_negated_pnc(pnc); + cc = ia32_negate_condition_code(cc); build_address_ptr(&addr, ptr, mem); @@ -2254,7 +2307,7 @@ static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) block = get_nodes_block(node); new_block = be_transform_node(block); new_node = new_bd_ia32_SetccMem(dbgi, new_block, addr.base, - addr.index, addr.mem, flags, pnc); + addr.index, addr.mem, flags, cc); set_address(new_node, &addr); set_ia32_op_type(new_node, ia32_AddrModeD); set_ia32_ls_mode(new_node, mode); @@ -2447,14 +2500,14 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) { ir_mode *mode = get_irn_mode(cns); unsigned size = get_mode_size_bytes(mode); - tarval *tv = get_Const_tarval(cns); + ir_tarval *tv = get_Const_tarval(cns); ir_node *block = get_nodes_block(node); ir_node *new_block = be_transform_node(block); ir_node *ptr = get_Store_ptr(node); ir_node *mem = get_Store_mem(node); dbg_info *dbgi = get_irn_dbg_info(node); int ofs = 0; - size_t i = 0; + int i = 0; ir_node *ins[4]; ia32_address_t addr; @@ -2513,7 +2566,7 @@ static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node new_node = new_r_Proj(vfisttp, mode_M, pn_ia32_vfisttp_M); *fist = vfisttp; } else { - ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg); + ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph); /* do a fist */ new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode); @@ -2545,7 +2598,7 @@ static ir_node *gen_general_Store(ir_node *node) /* construct store address */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, ptr, 0); + ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); if (addr.base == NULL) { addr.base = noreg_GP; @@ -2694,23 +2747,23 @@ static ir_node *create_Switch(ir_node *node) */ static ir_node *gen_Cond(ir_node *node) { - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *sel = get_Cond_selector(node); - ir_mode *sel_mode = get_irn_mode(sel); - ir_node *flags = NULL; - ir_node *new_node; - pn_Cmp pnc; + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *sel = get_Cond_selector(node); + ir_mode *sel_mode = get_irn_mode(sel); + ir_node *flags = NULL; + ir_node *new_node; + ia32_condition_code_t cc; if (sel_mode != mode_b) { return create_Switch(node); } /* we get flags from a Cmp */ - flags = get_flags_node(sel, &pnc); + flags = get_flags_node(sel, &cc); - new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, pnc); + new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, cc); SET_IA32_ORIG_NODE(new_node, node); return new_node; @@ -2804,7 +2857,7 @@ static bool can_fold_test_and(ir_node *node) /** we can only have eq and lg projs */ foreach_out_edge(node, edge) { ir_node *proj = get_edge_src_irn(edge); - pn_Cmp pnc = get_Proj_proj(proj); + pn_Cmp pnc = get_Proj_pn_cmp(proj); if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) return false; } @@ -2906,7 +2959,6 @@ static ir_node *gen_Cmp(ir_node *node) ir_node *new_node; ia32_address_mode_t am; ia32_address_t *addr = &am.addr; - int cmp_unsigned; if (mode_is_float(cmp_mode)) { if (ia32_cg_config.use_sse2) { @@ -2919,7 +2971,6 @@ static ir_node *gen_Cmp(ir_node *node) assert(ia32_mode_needs_gp_reg(cmp_mode)); /* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */ - cmp_unsigned = !mode_is_signed(cmp_mode); if (is_Const_0(right) && is_And(left) && get_irn_n_edges(left) == 1 && @@ -2947,11 +2998,10 @@ static ir_node *gen_Cmp(ir_node *node) if (get_mode_size_bits(cmp_mode) == 8) { new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base, - addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted, - cmp_unsigned); + addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted); } else { new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned); + addr->mem, am.new_op1, am.new_op2, am.ins_permuted); } } else { /* Cmp(left, right) */ @@ -2968,11 +3018,10 @@ static ir_node *gen_Cmp(ir_node *node) if (get_mode_size_bits(cmp_mode) == 8) { new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, - am.new_op2, am.ins_permuted, - cmp_unsigned); + am.new_op2, am.ins_permuted); } else { new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index, - addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned); + addr->mem, am.new_op1, am.new_op2, am.ins_permuted); } } set_am_attributes(new_node, &am); @@ -2986,7 +3035,7 @@ static ir_node *gen_Cmp(ir_node *node) } static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, - pn_Cmp pnc) + ia32_condition_code_t cc) { dbg_info *dbgi = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); @@ -3006,11 +3055,11 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, match_commutative | match_am | match_16bit_am | match_mode_neutral); if (am.ins_permuted) - pnc = ia32_get_negated_pnc(pnc); + cc = ia32_invert_condition_code(cc); new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, new_flags, - pnc); + cc); set_am_attributes(new_node, &am); SET_IA32_ORIG_NODE(new_node, node); @@ -3024,13 +3073,13 @@ static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags, * Creates a ia32 Setcc instruction. */ static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block, - ir_node *flags, pn_Cmp pnc, + ir_node *flags, ia32_condition_code_t cc, ir_node *orig_node) { ir_mode *mode = get_irn_mode(orig_node); ir_node *new_node; - new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, pnc); + new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, cc); SET_IA32_ORIG_NODE(new_node, orig_node); /* we might need to conv the result up */ @@ -3052,7 +3101,7 @@ static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b) ir_node *new_node; ir_node *sub; ir_node *sbb; - ir_node *not; + ir_node *notn; ir_node *eflags; ir_node *block; @@ -3073,11 +3122,11 @@ static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b) } eflags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags); - dbgi = get_irn_dbg_info(psi); - sbb = new_bd_ia32_Sbb0(dbgi, block, eflags); - not = new_bd_ia32_Not(dbgi, block, sbb); + dbgi = get_irn_dbg_info(psi); + sbb = new_bd_ia32_Sbb0(dbgi, block, eflags); + notn = new_bd_ia32_Not(dbgi, block, sbb); - new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, not); + new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, notn); set_ia32_commutative(new_node); return new_node; } @@ -3096,8 +3145,8 @@ static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **ne ir_mode *mode = *new_mode; ir_type *tp; ir_initializer_t *initializer; - tarval *tv0 = get_Const_tarval(c0); - tarval *tv1 = get_Const_tarval(c1); + ir_tarval *tv0 = get_Const_tarval(c0); + ir_tarval *tv1 = get_Const_tarval(c1); if (mode == NULL) { /* detect the best mode for the constants */ @@ -3158,8 +3207,8 @@ enum setcc_transform_insn { }; typedef struct setcc_transform { - unsigned num_steps; - pn_Cmp pnc; + unsigned num_steps; + ia32_condition_code_t cc; struct { enum setcc_transform_insn transform; long val; @@ -3172,7 +3221,8 @@ typedef struct setcc_transform { * Find a transformation that creates 0 and 1 from * tv_t and tv_f. */ -static void find_const_transform(pn_Cmp pnc, tarval *t, tarval *f, +static void find_const_transform(ia32_condition_code_t cc, + ir_tarval *t, ir_tarval *f, setcc_transform_t *res) { unsigned step = 0; @@ -3180,21 +3230,21 @@ static void find_const_transform(pn_Cmp pnc, tarval *t, tarval *f, res->num_steps = 0; if (tarval_is_null(t)) { - tarval *tmp = t; + ir_tarval *tmp = t; t = f; f = tmp; - pnc = ia32_get_negated_pnc(pnc); + cc = ia32_negate_condition_code(cc); } else if (tarval_cmp(t, f) == pn_Cmp_Lt) { // now, t is the bigger one - tarval *tmp = t; + ir_tarval *tmp = t; t = f; f = tmp; - pnc = ia32_get_negated_pnc(pnc); + cc = ia32_negate_condition_code(cc); } - res->pnc = pnc; + res->cc = cc; if (! tarval_is_null(f)) { - tarval *t_sub = tarval_sub(t, f, NULL); + ir_tarval *t_sub = tarval_sub(t, f, NULL); t = t_sub; res->steps[step].transform = SETCC_TR_ADD; @@ -3296,17 +3346,17 @@ static void find_const_transform(pn_Cmp pnc, tarval *t, tarval *f, */ static ir_node *gen_Mux(ir_node *node) { - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_nodes_block(node); - ir_node *new_block = be_transform_node(block); - ir_node *mux_true = get_Mux_true(node); - ir_node *mux_false = get_Mux_false(node); - ir_node *cond = get_Mux_sel(node); - ir_mode *mode = get_irn_mode(node); - ir_node *flags; - ir_node *new_node; - int is_abs; - pn_Cmp pnc; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *mux_true = get_Mux_true(node); + ir_node *mux_false = get_Mux_false(node); + ir_node *cond = get_Mux_sel(node); + ir_mode *mode = get_irn_mode(node); + ir_node *flags; + ir_node *new_node; + int is_abs; + ia32_condition_code_t cc; assert(get_irn_mode(cond) == mode_b); @@ -3320,7 +3370,7 @@ static ir_node *gen_Mux(ir_node *node) ir_node *cmp = get_Proj_pred(cond); ir_node *cmp_left = get_Cmp_left(cmp); ir_node *cmp_right = get_Cmp_right(cmp); - pn_Cmp pnc = get_Proj_proj(cond); + int pnc = get_Proj_proj(cond); if (ia32_cg_config.use_sse2) { if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) { @@ -3352,8 +3402,8 @@ static ir_node *gen_Mux(ir_node *node) ir_mode *new_mode; unsigned scale; - flags = get_flags_node(cond, &pnc); - new_node = create_set_32bit(dbgi, new_block, flags, pnc, node); + flags = get_flags_node(cond, &cc); + new_node = create_set_32bit(dbgi, new_block, flags, cc, node); if (ia32_cg_config.use_sse2) { /* cannot load from different mode on SSE */ @@ -3387,7 +3437,7 @@ static ir_node *gen_Mux(ir_node *node) case 16: /* arg, shift 16 NOT supported */ scale = 3; - new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, new_node); + new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); break; default: panic("Unsupported constant size"); @@ -3408,7 +3458,7 @@ static ir_node *gen_Mux(ir_node *node) am.new_op2 = NULL; am.pinned = op_pin_state_floats; am.commutative = 1; - am.ins_permuted = 0; + am.ins_permuted = false; if (ia32_cg_config.use_sse2) load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode); @@ -3430,13 +3480,13 @@ static ir_node *gen_Mux(ir_node *node) ir_node *cmp_right = get_Cmp_right(cmp); ir_node *val_true = mux_true; ir_node *val_false = mux_false; - pn_Cmp pnc = get_Proj_proj(cond); + int pnc = get_Proj_proj(cond); if (is_Const(val_true) && is_Const_null(val_true)) { ir_node *tmp = val_false; val_false = val_true; val_true = tmp; - pnc = ia32_get_negated_pnc(pnc); + pnc = get_negated_pnc(pnc, get_irn_mode(cmp_left)); } if (is_Const_0(val_false) && is_Sub(val_true)) { if ((pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) @@ -3453,24 +3503,24 @@ static ir_node *gen_Mux(ir_node *node) } } - flags = get_flags_node(cond, &pnc); + flags = get_flags_node(cond, &cc); if (is_Const(mux_true) && is_Const(mux_false)) { /* both are const, good */ - tarval *tv_true = get_Const_tarval(mux_true); - tarval *tv_false = get_Const_tarval(mux_false); + ir_tarval *tv_true = get_Const_tarval(mux_true); + ir_tarval *tv_false = get_Const_tarval(mux_false); setcc_transform_t res; int step; - find_const_transform(pnc, tv_true, tv_false, &res); + find_const_transform(cc, tv_true, tv_false, &res); new_node = node; for (step = (int)res.num_steps - 1; step >= 0; --step) { ir_node *imm; switch (res.steps[step].transform) { case SETCC_TR_ADD: - imm = ia32_immediate_from_long(res.steps[step].val); - new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm); + new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, noreg_GP); + add_ia32_am_offs_int(new_node, res.steps[step].val); break; case SETCC_TR_ADDxx: new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node); @@ -3500,7 +3550,7 @@ static ir_node *gen_Mux(ir_node *node) new_node = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm); break; case SETCC_TR_SET: - new_node = create_set_32bit(dbgi, new_block, flags, res.pnc, node); + new_node = create_set_32bit(dbgi, new_block, flags, res.cc, node); break; case SETCC_TR_SBB: new_node = new_bd_ia32_Sbb0(dbgi, new_block, flags); @@ -3510,7 +3560,7 @@ static ir_node *gen_Mux(ir_node *node) } } } else { - new_node = create_CMov(node, cond, flags, pnc); + new_node = create_CMov(node, cond, flags, cc); } return new_node; } @@ -3801,8 +3851,7 @@ static ir_node *gen_Conv(ir_node *node) /* if fp_no_float_fold is not set then we assume that we * don't have any float operations in a non * mode_float_arithmetic mode and can skip strict upconvs */ - if (src_bits < tgt_bits - && !(get_irg_fp_model(current_ir_graph) & fp_no_float_fold)) { + if (src_bits < tgt_bits) { DB((dbg, LEVEL_1, "killed Conv(float, float) ...")); return new_op; } else { @@ -3872,7 +3921,7 @@ static ir_node *gen_Conv(ir_node *node) static ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type) { - ir_node *new_node = try_create_Immediate(node, immediate_constraint_type); + ir_node *new_node = ia32_try_create_Immediate(node, immediate_constraint_type); if (new_node == NULL) { new_node = be_transform_node(node); } @@ -4106,40 +4155,6 @@ static ir_node *gen_IJmp(ir_node *node) return new_node; } -/** - * Transform a Bound node. - */ -static ir_node *gen_Bound(ir_node *node) -{ - ir_node *new_node; - ir_node *lower = get_Bound_lower(node); - dbg_info *dbgi = get_irn_dbg_info(node); - - if (is_Const_0(lower)) { - /* typical case for Java */ - ir_node *sub, *res, *flags, *block; - - res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node), - new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate); - - block = get_nodes_block(res); - if (! is_Proj(res)) { - sub = res; - set_irn_mode(sub, mode_T); - res = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_res); - } else { - sub = get_Proj_pred(res); - } - flags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags); - new_node = new_bd_ia32_Jcc(dbgi, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned); - SET_IA32_ORIG_NODE(new_node, node); - } else { - panic("generic Bound not supported in ia32 Backend"); - } - return new_node; -} - - static ir_node *gen_ia32_l_ShlDep(ir_node *node) { ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val); @@ -4174,7 +4189,7 @@ static ir_node *gen_ia32_l_Add(ir_node *node) match_mode_neutral); if (is_Proj(lowered)) { - lowered = get_Proj_pred(lowered); + lowered = get_Proj_pred(lowered); } else { assert(is_ia32_Add(lowered)); set_irn_mode(lowered, mode_T); @@ -4226,7 +4241,7 @@ static ir_node *gen_ia32_l_Sub(ir_node *node) match_am | match_immediate | match_mode_neutral); if (is_Proj(lowered)) { - lowered = get_Proj_pred(lowered); + lowered = get_Proj_pred(lowered); } else { assert(is_ia32_Sub(lowered)); set_irn_mode(lowered, mode_T); @@ -4366,10 +4381,10 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) am.mem_proj = nomem; am.op_type = ia32_AddrModeS; am.new_op1 = res; - am.new_op2 = ia32_new_NoReg_vfp(env_cg); + am.new_op2 = ia32_new_NoReg_vfp(current_ir_graph); am.pinned = op_pin_state_floats; am.commutative = 1; - am.ins_permuted = 0; + am.ins_permuted = false; fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, am.new_op1, am.new_op2, get_fpcw()); @@ -4448,7 +4463,7 @@ static ir_node *gen_Proj_be_AddSP(ir_node *node) if (proj == pn_be_AddSP_sp) { ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_SubSP_stack); - arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); + arch_set_irn_register(res, &ia32_registers[REG_ESP]); return res; } else if (proj == pn_be_AddSP_res) { return new_rd_Proj(dbgi, new_pred, mode_Iu, @@ -4473,7 +4488,7 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node) if (proj == pn_be_SubSP_sp) { ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_AddSP_stack); - arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); + arch_set_irn_register(res, &ia32_registers[REG_ESP]); return res; } else if (proj == pn_be_SubSP_M) { return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_AddSP_M); @@ -4581,9 +4596,9 @@ static ir_node *gen_Proj_Load(ir_node *node) } /** - * Transform and renumber the Projs from a DivMod like instruction. + * Transform and renumber the Projs from a Div or Mod instruction. */ -static ir_node *gen_Proj_DivMod(ir_node *node) +static ir_node *gen_Proj_Div(ir_node *node) { ir_node *block = be_transform_node(get_nodes_block(node)); ir_node *pred = get_Proj_pred(node); @@ -4591,90 +4606,74 @@ static ir_node *gen_Proj_DivMod(ir_node *node) dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); - assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)); + assert(pn_ia32_Div_M == pn_ia32_IDiv_M); + assert(pn_ia32_Div_div_res == pn_ia32_IDiv_div_res); - switch (get_irn_opcode(pred)) { - case iro_Div: - switch (proj) { - case pn_Div_M: - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); - case pn_Div_res: - return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res); - case pn_Div_X_regular: - return new_rd_Jmp(dbgi, block); - case pn_Div_X_except: - set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); - default: - break; - } - break; - case iro_Mod: - switch (proj) { - case pn_Mod_M: + switch (proj) { + case pn_Div_M: + if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) { return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); - case pn_Mod_res: - return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res); - case pn_Mod_X_except: - set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); - default: - break; + } else if (is_ia32_xDiv(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M); + } else if (is_ia32_vfdiv(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfdiv_M); + } else { + panic("Div transformed to unexpected thing %+F", new_pred); } - break; - case iro_DivMod: - switch (proj) { - case pn_DivMod_M: - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); - case pn_DivMod_res_div: + case pn_Div_res: + if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) { return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res); - case pn_DivMod_res_mod: - return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res); - case pn_DivMod_X_regular: - return new_rd_Jmp(dbgi, block); - case pn_DivMod_X_except: - set_ia32_exc_label(new_pred, 1); - return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); - default: - break; + } else if (is_ia32_xDiv(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res); + } else if (is_ia32_vfdiv(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfdiv_res); + } else { + panic("Div transformed to unexpected thing %+F", new_pred); } - break; + case pn_Div_X_regular: + return new_rd_Jmp(dbgi, block); + case pn_Div_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } - panic("No idea how to transform proj->DivMod"); + panic("No idea how to transform proj->Div"); } /** - * Transform and renumber the Projs from a CopyB. + * Transform and renumber the Projs from a Div or Mod instruction. */ -static ir_node *gen_Proj_CopyB(ir_node *node) +static ir_node *gen_Proj_Mod(ir_node *node) { ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); dbg_info *dbgi = get_irn_dbg_info(node); long proj = get_Proj_proj(node); + assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)); + assert(pn_ia32_Div_M == pn_ia32_IDiv_M); + assert(pn_ia32_Div_mod_res == pn_ia32_IDiv_mod_res); + switch (proj) { - case pn_CopyB_M: - if (is_ia32_CopyB_i(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M); - } else if (is_ia32_CopyB(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M); - } - break; + case pn_Mod_M: + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M); + case pn_Mod_res: + return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res); + case pn_Mod_X_except: + set_ia32_exc_label(new_pred, 1); + return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc); default: break; } - - panic("No idea how to transform proj->CopyB"); + panic("No idea how to transform proj->Mod"); } /** - * Transform and renumber the Projs from a Quot. + * Transform and renumber the Projs from a CopyB. */ -static ir_node *gen_Proj_Quot(ir_node *node) +static ir_node *gen_Proj_CopyB(ir_node *node) { ir_node *pred = get_Proj_pred(node); ir_node *new_pred = be_transform_node(pred); @@ -4682,27 +4681,18 @@ static ir_node *gen_Proj_Quot(ir_node *node) long proj = get_Proj_proj(node); switch (proj) { - case pn_Quot_M: - if (is_ia32_xDiv(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M); - } else if (is_ia32_vfdiv(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfdiv_M); - } - break; - case pn_Quot_res: - if (is_ia32_xDiv(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res); - } else if (is_ia32_vfdiv(new_pred)) { - return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfdiv_res); + case pn_CopyB_M: + if (is_ia32_CopyB_i(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M); + } else if (is_ia32_CopyB(new_pred)) { + return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M); } break; - case pn_Quot_X_regular: - case pn_Quot_X_except: default: break; } - panic("No idea how to transform proj->Quot"); + panic("No idea how to transform proj->CopyB"); } static ir_node *gen_be_Call(ir_node *node) @@ -4733,7 +4723,9 @@ static ir_node *gen_be_Call(ir_node *node) ir_mode *const res_mode = get_type_mode(res_type); if (res_mode != NULL && mode_is_float(res_mode)) { - env_cg->do_x87_sim = 1; + ir_graph *irg = current_ir_graph; + ia32_irg_data_t *irg_data = ia32_get_irg_data(irg); + irg_data->do_x87_sim = 1; } } @@ -4741,13 +4733,13 @@ static ir_node *gen_be_Call(ir_node *node) assert(be_Call_get_entity(node) == NULL); /* special case for PIC trampoline calls */ - old_no_pic_adjust = no_pic_adjust; - no_pic_adjust = be_get_irg_options(env_cg->irg)->pic; + old_no_pic_adjust = ia32_no_pic_adjust; + ia32_no_pic_adjust = be_get_irg_options(current_ir_graph)->pic; match_arguments(&am, src_block, NULL, src_ptr, src_mem, match_am | match_immediate); - no_pic_adjust = old_no_pic_adjust; + ia32_no_pic_adjust = old_no_pic_adjust; i = get_irn_arity(node) - 1; fpcw = be_transform_node(get_irn_n(node, i--)); @@ -4759,9 +4751,9 @@ static ir_node *gen_be_Call(ir_node *node) assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]); switch (*req->limited) { - case 1 << REG_EAX: assert(eax == noreg_GP); eax = reg_parm; break; - case 1 << REG_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break; - case 1 << REG_EDX: assert(edx == noreg_GP); edx = reg_parm; break; + case 1 << REG_GP_EAX: assert(eax == noreg_GP); eax = reg_parm; break; + case 1 << REG_GP_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break; + case 1 << REG_GP_EDX: assert(edx == noreg_GP); edx = reg_parm; break; default: panic("Invalid GP register for register parameter"); } } @@ -4815,10 +4807,10 @@ static ir_node *gen_debugbreak(ir_node *node) */ static ir_node *gen_return_address(ir_node *node) { - ir_node *param = get_Builtin_param(node, 0); - ir_node *frame = get_Builtin_param(node, 1); - dbg_info *dbgi = get_irn_dbg_info(node); - tarval *tv = get_Const_tarval(param); + ir_node *param = get_Builtin_param(node, 0); + ir_node *frame = get_Builtin_param(node, 1); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_tarval *tv = get_Const_tarval(param); unsigned long value = get_tarval_long(tv); ir_node *block = be_transform_node(get_nodes_block(node)); @@ -4843,9 +4835,9 @@ static ir_node *gen_return_address(ir_node *node) set_ia32_frame_ent(load, ia32_get_return_address_entity()); if (get_irn_pinned(node) == op_pin_state_floats) { - assert(pn_ia32_xLoad_res == pn_ia32_vfld_res - && pn_ia32_vfld_res == pn_ia32_Load_res - && pn_ia32_Load_res == pn_ia32_res); + assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res + && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res + && (int)pn_ia32_Load_res == (int)pn_ia32_res); arch_irn_add_flags(load, arch_irn_flags_rematerializable); } @@ -4858,10 +4850,10 @@ static ir_node *gen_return_address(ir_node *node) */ static ir_node *gen_frame_address(ir_node *node) { - ir_node *param = get_Builtin_param(node, 0); - ir_node *frame = get_Builtin_param(node, 1); - dbg_info *dbgi = get_irn_dbg_info(node); - tarval *tv = get_Const_tarval(param); + ir_node *param = get_Builtin_param(node, 0); + ir_node *frame = get_Builtin_param(node, 1); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_tarval *tv = get_Const_tarval(param); unsigned long value = get_tarval_long(tv); ir_node *block = be_transform_node(get_nodes_block(node)); @@ -4893,9 +4885,9 @@ static ir_node *gen_frame_address(ir_node *node) } if (get_irn_pinned(node) == op_pin_state_floats) { - assert(pn_ia32_xLoad_res == pn_ia32_vfld_res - && pn_ia32_vfld_res == pn_ia32_Load_res - && pn_ia32_Load_res == pn_ia32_res); + assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res + && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res + && (int)pn_ia32_Load_res == (int)pn_ia32_res); arch_irn_add_flags(load, arch_irn_flags_rematerializable); } @@ -4912,7 +4904,7 @@ static ir_node *gen_prefetch(ir_node *node) ir_node *ptr, *block, *mem, *base, *index; ir_node *param, *new_node; long rw, locality; - tarval *tv; + ir_tarval *tv; ia32_address_t addr; if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) { @@ -4927,7 +4919,7 @@ static ir_node *gen_prefetch(ir_node *node) /* construct load address */ memset(&addr, 0, sizeof(addr)); ptr = get_Builtin_param(node, 0); - ia32_create_address_mode(&addr, ptr, 0); + ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); base = addr.base; index = addr.index; @@ -5022,7 +5014,7 @@ static ir_node *gen_ffs(ir_node *node) ir_node *real = skip_Proj(bsf); dbg_info *dbgi = get_irn_dbg_info(real); ir_node *block = get_nodes_block(real); - ir_node *flag, *set, *conv, *neg, *or; + ir_node *flag, *set, *conv, *neg, *orn, *add; /* bsf x */ if (get_irn_mode(real) != mode_T) { @@ -5033,7 +5025,7 @@ static ir_node *gen_ffs(ir_node *node) flag = new_r_Proj(real, mode_b, pn_ia32_flags); /* sete */ - set = new_bd_ia32_Setcc(dbgi, block, flag, pn_Cmp_Eq); + set = new_bd_ia32_Setcc(dbgi, block, flag, ia32_cc_equal); SET_IA32_ORIG_NODE(set, node); /* conv to 32bit */ @@ -5044,11 +5036,13 @@ static ir_node *gen_ffs(ir_node *node) neg = new_bd_ia32_Neg(dbgi, block, conv); /* or */ - or = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg); - set_ia32_commutative(or); + orn = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg); + set_ia32_commutative(orn); /* add 1 */ - return new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP, nomem, or, ia32_create_Immediate(NULL, 0, 1)); + add = new_bd_ia32_Lea(dbgi, block, orn, noreg_GP); + add_ia32_am_offs_int(add, 1); + return add; } /** @@ -5078,32 +5072,31 @@ static ir_node *gen_ctz(ir_node *node) */ static ir_node *gen_parity(ir_node *node) { - ir_node *param = get_Builtin_param(node, 0); dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *new_block = be_transform_node(block); + ir_node *param = get_Builtin_param(node, 0); + ir_node *new_param = be_transform_node(param); + ir_node *new_node; - ir_node *block = get_nodes_block(node); - - ir_node *new_block = be_transform_node(block); - ir_node *imm, *cmp, *new_node; - - ia32_address_mode_t am; - ia32_address_t *addr = &am.addr; - - - /* cmp param, 0 */ - match_arguments(&am, block, NULL, param, NULL, match_am); - imm = ia32_create_Immediate(NULL, 0, 0); - cmp = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index, - addr->mem, imm, am.new_op2, am.ins_permuted, 0); - set_am_attributes(cmp, &am); - set_ia32_ls_mode(cmp, mode_Iu); - - SET_IA32_ORIG_NODE(cmp, node); + /* the x86 parity bit is stupid: it only looks at the lowest byte, + * so we have to do complicated xoring first. + * (we should also better lower this before the backend so we still have a + * chance for CSE, constant folding and other goodies for some of these + * operations) + */ + ir_node *count = ia32_create_Immediate(NULL, 0, 16); + ir_node *shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count); + ir_node *xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem, + shr, new_param); + ir_node *xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xor); + ir_node *flags; - cmp = fix_mem_proj(cmp, &am); + set_irn_mode(xor2, mode_T); + flags = new_r_Proj(xor2, mode_Iu, pn_ia32_XorHighLow_flags); /* setp */ - new_node = new_bd_ia32_Setcc(dbgi, new_block, cmp, ia32_pn_Cmp_parity); + new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, ia32_cc_not_parity); SET_IA32_ORIG_NODE(new_node, node); /* conv to 32bit */ @@ -5146,6 +5139,13 @@ static ir_node *gen_popcount(ir_node *node) new_param = be_transform_node(param); /* do the standard popcount algo */ + /* TODO: This is stupid, we should transform this before the backend, + * to get CSE, localopts, etc. for the operations + * TODO: This is also not the optimal algorithm (it is just the starting + * example in hackers delight, they optimize it more on the following page) + * But I'm too lazy to fix this now, as the code should get lowered before + * the backend anyway. + */ /* m1 = x & 0x55555555 */ imm = ia32_create_Immediate(NULL, 0, 0x55555555); @@ -5153,7 +5153,7 @@ static ir_node *gen_popcount(ir_node *node) /* s1 = x >> 1 */ simm = ia32_create_Immediate(NULL, 0, 1); - s1 = new_bd_ia32_Shl(dbgi, new_block, new_param, simm); + s1 = new_bd_ia32_Shr(dbgi, new_block, new_param, simm); /* m2 = s1 & 0x55555555 */ m2 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s1, imm); @@ -5167,7 +5167,7 @@ static ir_node *gen_popcount(ir_node *node) /* s2 = m3 >> 2 */ simm = ia32_create_Immediate(NULL, 0, 2); - s2 = new_bd_ia32_Shl(dbgi, new_block, m3, simm); + s2 = new_bd_ia32_Shr(dbgi, new_block, m3, simm); /* m5 = s2 & 0x33333333 */ m5 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, imm); @@ -5181,7 +5181,7 @@ static ir_node *gen_popcount(ir_node *node) /* s3 = m6 >> 4 */ simm = ia32_create_Immediate(NULL, 0, 4); - s3 = new_bd_ia32_Shl(dbgi, new_block, m6, simm); + s3 = new_bd_ia32_Shr(dbgi, new_block, m6, simm); /* m8 = s3 & 0x0F0F0F0F */ m8 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, imm); @@ -5195,7 +5195,7 @@ static ir_node *gen_popcount(ir_node *node) /* s4 = m9 >> 8 */ simm = ia32_create_Immediate(NULL, 0, 8); - s4 = new_bd_ia32_Shl(dbgi, new_block, m9, simm); + s4 = new_bd_ia32_Shr(dbgi, new_block, m9, simm); /* m11 = s4 & 0x00FF00FF */ m11 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s4, imm); @@ -5209,7 +5209,7 @@ static ir_node *gen_popcount(ir_node *node) /* s5 = m12 >> 16 */ simm = ia32_create_Immediate(NULL, 0, 16); - s5 = new_bd_ia32_Shl(dbgi, new_block, m12, simm); + s5 = new_bd_ia32_Shr(dbgi, new_block, m12, simm); /* res = m13 + s5 */ return new_bd_ia32_Lea(dbgi, new_block, m13, s5); @@ -5317,7 +5317,7 @@ static ir_node *gen_inner_trampoline(ir_node *node) /* construct store address */ memset(&addr, 0, sizeof(addr)); - ia32_create_address_mode(&addr, ptr, 0); + ia32_create_address_mode(&addr, ptr, ia32_create_am_normal); if (addr.base == NULL) { addr.base = noreg_GP; @@ -5369,7 +5369,8 @@ static ir_node *gen_inner_trampoline(ir_node *node) if (is_SymConst(callee)) { rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, 0, -10); } else { - rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), ia32_create_Immediate(NULL, 0, -10)); + rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), noreg_GP); + add_ia32_am_offs_int(rel, -10); } rel = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, rel, trampoline); @@ -5532,11 +5533,11 @@ static ir_node *gen_Proj_be_Call(ir_node *node) /* TODO arch_set_irn_register() only operates on Projs, need variant with index */ switch (proj) { case pn_ia32_Call_stack: - arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]); + arch_set_irn_register(res, &ia32_registers[REG_ESP]); break; case pn_ia32_Call_fpcw: - arch_set_irn_register(res, &ia32_fp_cw_regs[REG_FPCW]); + arch_set_irn_register(res, &ia32_registers[REG_FPCW]); break; } @@ -5553,30 +5554,6 @@ static ir_node *gen_Proj_Cmp(ir_node *node) node); } -/** - * Transform the Projs from a Bound. - */ -static ir_node *gen_Proj_Bound(ir_node *node) -{ - ir_node *new_node; - ir_node *pred = get_Proj_pred(node); - - switch (get_Proj_proj(node)) { - case pn_Bound_M: - return be_transform_node(get_Bound_mem(pred)); - case pn_Bound_X_regular: - new_node = be_transform_node(pred); - return new_r_Proj(new_node, mode_X, pn_ia32_Jcc_true); - case pn_Bound_X_except: - new_node = be_transform_node(pred); - return new_r_Proj(new_node, mode_X, pn_ia32_Jcc_false); - case pn_Bound_res: - return be_transform_node(get_Bound_index(pred)); - default: - panic("unsupported Proj from Bound"); - } -} - static ir_node *gen_Proj_ASM(ir_node *node) { ir_mode *mode = get_irn_mode(node); @@ -5620,13 +5597,11 @@ static ir_node *gen_Proj(ir_node *node) case iro_Builtin: return gen_Proj_Builtin(node); case iro_Div: + return gen_Proj_Div(node); case iro_Mod: - case iro_DivMod: - return gen_Proj_DivMod(node); + return gen_Proj_Mod(node); case iro_CopyB: return gen_Proj_CopyB(node); - case iro_Quot: - return gen_Proj_Quot(node); case beo_SubSP: return gen_Proj_be_SubSP(node); case beo_AddSP: @@ -5635,8 +5610,6 @@ static ir_node *gen_Proj(ir_node *node) return gen_Proj_be_Call(node); case iro_Cmp: return gen_Proj_Cmp(node); - case iro_Bound: - return gen_Proj_Bound(node); case iro_Start: proj = get_Proj_proj(node); switch (proj) { @@ -5651,7 +5624,7 @@ static ir_node *gen_Proj(ir_node *node) } case pn_Start_P_tls: - return gen_Proj_tls(node); + return ia32_gen_Proj_tls(node); } break; @@ -5686,7 +5659,7 @@ static void register_transformers(void) be_set_transform_function(op_Add, gen_Add); be_set_transform_function(op_And, gen_And); - be_set_transform_function(op_ASM, gen_ASM); + be_set_transform_function(op_ASM, ia32_gen_ASM); be_set_transform_function(op_be_AddSP, gen_be_AddSP); be_set_transform_function(op_be_Call, gen_be_Call); be_set_transform_function(op_be_Copy, gen_be_Copy); @@ -5694,15 +5667,13 @@ static void register_transformers(void) be_set_transform_function(op_be_IncSP, gen_be_IncSP); be_set_transform_function(op_be_Return, gen_be_Return); be_set_transform_function(op_be_SubSP, gen_be_SubSP); - be_set_transform_function(op_Bound, gen_Bound); be_set_transform_function(op_Builtin, gen_Builtin); be_set_transform_function(op_Cmp, gen_Cmp); be_set_transform_function(op_Cond, gen_Cond); be_set_transform_function(op_Const, gen_Const); be_set_transform_function(op_Conv, gen_Conv); - be_set_transform_function(op_CopyB, gen_CopyB); + be_set_transform_function(op_CopyB, ia32_gen_CopyB); be_set_transform_function(op_Div, gen_Div); - be_set_transform_function(op_DivMod, gen_DivMod); be_set_transform_function(op_Eor, gen_Eor); be_set_transform_function(op_ia32_l_Adc, gen_ia32_l_Adc); be_set_transform_function(op_ia32_l_Add, gen_ia32_l_Add); @@ -5737,7 +5708,6 @@ static void register_transformers(void) be_set_transform_function(op_Or, gen_Or); be_set_transform_function(op_Phi, gen_Phi); be_set_transform_function(op_Proj, gen_Proj); - be_set_transform_function(op_Quot, gen_Quot); be_set_transform_function(op_Rotl, gen_Rotl); be_set_transform_function(op_Shl, gen_Shl); be_set_transform_function(op_Shr, gen_Shr); @@ -5745,7 +5715,7 @@ static void register_transformers(void) be_set_transform_function(op_Store, gen_Store); be_set_transform_function(op_Sub, gen_Sub); be_set_transform_function(op_SymConst, gen_SymConst); - be_set_transform_function(op_Unknown, gen_Unknown); + be_set_transform_function(op_Unknown, ia32_gen_Unknown); } /** @@ -5753,14 +5723,15 @@ static void register_transformers(void) */ static void ia32_pretransform_node(void) { - ia32_code_gen_t *cg = env_cg; + ir_graph *irg = current_ir_graph; + ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph); - cg->noreg_gp = be_pre_transform_node(cg->noreg_gp); - cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp); - cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm); + irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp); + irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp); + irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm); - nomem = get_irg_no_mem(current_ir_graph); - noreg_GP = ia32_new_NoReg_gp(cg); + nomem = get_irg_no_mem(irg); + noreg_GP = ia32_new_NoReg_gp(irg); get_fpcw(); } @@ -5772,9 +5743,9 @@ static void ia32_pretransform_node(void) */ static void postprocess_fp_call_results(void) { - int i; + size_t i, n; - for (i = ARR_LEN(call_list) - 1; i >= 0; --i) { + for (i = 0, n = ARR_LEN(call_list); i < n; ++i) { ir_node *call = call_list[i]; ir_type *mtp = call_types[i]; int j; @@ -5860,19 +5831,18 @@ static void postprocess_fp_call_results(void) } /* do the transformation */ -void ia32_transform_graph(ia32_code_gen_t *cg) +void ia32_transform_graph(ir_graph *irg) { int cse_last; register_transformers(); - env_cg = cg; - initial_fpcw = NULL; - no_pic_adjust = 0; + initial_fpcw = NULL; + ia32_no_pic_adjust = 0; be_timer_push(T_HEIGHTS); - heights = heights_new(cg->irg); + ia32_heights = heights_new(irg); be_timer_pop(T_HEIGHTS); - ia32_calculate_non_address_mode_nodes(cg->irg); + ia32_calculate_non_address_mode_nodes(irg); /* the transform phase is not safe for CSE (yet) because several nodes get * attributes set after their creation */ @@ -5881,7 +5851,7 @@ void ia32_transform_graph(ia32_code_gen_t *cg) call_list = NEW_ARR_F(ir_node *, 0); call_types = NEW_ARR_F(ir_type *, 0); - be_transform_graph(cg->irg, ia32_pretransform_node); + be_transform_graph(irg, ia32_pretransform_node); if (ia32_cg_config.use_sse2) postprocess_fp_call_results(); @@ -5891,8 +5861,8 @@ void ia32_transform_graph(ia32_code_gen_t *cg) set_opt_cse(cse_last); ia32_free_non_address_mode_nodes(); - heights_free(heights); - heights = NULL; + heights_free(ia32_heights); + ia32_heights = NULL; } void ia32_init_transform(void)