X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=ffcb5e7f73a2dc723028e29b6ec06d8f9a6ab7fe;hb=aef4d3b28b21856e05c0bd91552b51b69ed5ac50;hp=e45464292f7993062a47aed27aec689b87c97dcb;hpb=f94d292525ff2eb4b35dfcb1977612aa9deca775;p=libfirm

diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl
index e45464292..ffcb5e7f7 100644
--- a/ir/be/ia32/ia32_spec.pl
+++ b/ir/be/ia32/ia32_spec.pl
@@ -333,7 +333,7 @@ Immediate => {
 	op_flags  => "c",
 	irn_flags => "I",
 	reg_req   => { out => [ "gp_NOREG" ] },
-	attr      => "ir_entity *symconst, int symconst_sign, tarval *offset",
+	attr      => "ir_entity *symconst, int symconst_sign, long offset",
 	attr_type => "ia32_immediate_attr_t",
 	mode      => $mode_gp,
 },
@@ -913,9 +913,10 @@ FnstCW => {
 Cltd => {
 	# we should not rematrialize this node. It produces 2 results and has
 	# very strict constrains
-	reg_req   => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] },
+	reg_req   => { in => [ "eax" ], out => [ "edx" ] },
+	ins       => [ "val" ],
 	emit      => '. cltd',
-	outs      => [ "EAX", "EDX" ],
+	mode      => $mode_gp,
 	units     => [ "GP" ],
 },
 
@@ -1409,7 +1410,8 @@ vfCMov => {
 
 vfadd => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+	ins       => [ "base", "index", "left", "right", "mem", "fpcw" ],
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => "mode_E",
@@ -1418,7 +1420,8 @@ vfadd => {
 
 vfmul => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+	ins       => [ "base", "index", "left", "right", "mem", "fpcw" ],
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => "mode_E",
@@ -1433,7 +1436,8 @@ l_vfmul => {
 
 vfsub => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+	ins       => [ "base", "index", "left", "right", "mem", "fpcw" ],
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => "mode_E",
@@ -1446,7 +1450,8 @@ l_vfsub => {
 },
 
 vfdiv => {
-	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp", "none" ] },
+	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp", "none" ] },
+	ins       => [ "base", "index", "left", "right", "mem", "fpcw" ],
 	outs      => [ "res", "M" ],
 	latency   => 20,
 	units     => [ "VFP" ],
@@ -1460,7 +1465,8 @@ l_vfdiv => {
 },
 
 vfprem => {
-	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+	ins       => [ "base", "index", "left", "right", "mem", "fpcw" ],
 	latency   => 20,
 	units     => [ "VFP" ],
 	mode      => "mode_E",
@@ -1475,6 +1481,7 @@ l_vfprem => {
 vfabs => {
 	irn_flags => "R",
 	reg_req   => { in => [ "vfp"], out => [ "vfp" ] },
+	ins       => [ "value" ],
 	latency   => 2,
 	units     => [ "VFP" ],
 	mode      => "mode_E",
@@ -1484,39 +1491,13 @@ vfabs => {
 vfchs => {
 	irn_flags => "R",
 	reg_req   => { in => [ "vfp"], out => [ "vfp" ] },
+	ins       => [ "value" ],
 	latency   => 2,
 	units     => [ "VFP" ],
 	mode      => "mode_E",
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfsin => {
-	irn_flags => "R",
-	reg_req   => { in => [ "vfp"], out => [ "vfp" ] },
-	latency   => 150,
-	units     => [ "VFP" ],
-	mode      => "mode_E",
-	attr_type => "ia32_x87_attr_t",
-},
-
-vfcos => {
-	irn_flags => "R",
-	reg_req   => { in => [ "vfp"], out => [ "vfp" ] },
-	latency   => 150,
-	units     => [ "VFP" ],
-	mode      => "mode_E",
-	attr_type => "ia32_x87_attr_t",
-},
-
-vfsqrt => {
-	irn_flags => "R",
-	reg_req   => { in => [ "vfp"], out => [ "vfp" ] },
-	latency   => 30,
-	units     => [ "VFP" ],
-	mode      => "mode_E",
-	attr_type => "ia32_x87_attr_t",
-},
-
 # virtual Load and Store
 
 vfld => {
@@ -1551,6 +1532,7 @@ vfild => {
 	state     => "exc_pinned",
 	reg_req   => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
 	outs      => [ "res", "M" ],
+	ins       => [ "base", "index", "mem" ],
 	latency   => 4,
 	units     => [ "VFP" ],
 	attr_type => "ia32_x87_attr_t",
@@ -1565,6 +1547,7 @@ l_vfild => {
 vfist => {
 	state     => "exc_pinned",
 	reg_req   => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
+	ins       => [ "base", "index", "val", "fpcw", "mem" ],
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => "mode_M",
@@ -1813,30 +1796,6 @@ fchs => {
 	attr_type => "ia32_x87_attr_t",
 },
 
-fsin => {
-	op_flags  => "R",
-	rd_constructor => "NONE",
-	reg_req   => { },
-	emit      => '. fsin',
-	attr_type => "ia32_x87_attr_t",
-},
-
-fcos => {
-	op_flags  => "R",
-	rd_constructor => "NONE",
-	reg_req   => { },
-	emit      => '. fcos',
-	attr_type => "ia32_x87_attr_t",
-},
-
-fsqrt => {
-	op_flags  => "R",
-	rd_constructor => "NONE",
-	reg_req   => { },
-	emit      => '. fsqrt $',
-	attr_type => "ia32_x87_attr_t",
-},
-
 # x87 Load and Store
 
 fld => {