X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=ffcb5e7f73a2dc723028e29b6ec06d8f9a6ab7fe;hb=aef4d3b28b21856e05c0bd91552b51b69ed5ac50;hp=527c46c76c446758bad1dfd2e4baac4860712596;hpb=31066ceea04f37960a894f9fc39b58cef66ae91a;p=libfirm diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index 527c46c76..ffcb5e7f7 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -33,6 +33,7 @@ $arch = "ia32"; # init_attr => "emit attribute initialization template" # rd_constructor => "c source code which constructs an ir_node" # latency => "latency of this operation (can be float)" +# attr_type => "name of the attribute struct", # }, # # ... # (all nodes you need to describe) @@ -121,6 +122,17 @@ $arch = "ia32"; { name => "gp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes { mode => "mode_Iu" } ], + mmx => [ + { name => "mm0", type => 4 }, + { name => "mm1", type => 4 }, + { name => "mm2", type => 4 }, + { name => "mm3", type => 4 }, + { name => "mm4", type => 4 }, + { name => "mm5", type => 4 }, + { name => "mm6", type => 4 }, + { name => "mm7", type => 4 }, + { mode => "mode_E" } + ], xmm => [ { name => "xmm0", type => 1 }, { name => "xmm1", type => 1 }, @@ -255,10 +267,17 @@ $arch = "ia32"; ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n ia32_emit_mode_suffix(env, node);", M => "${arch}_emit_mode_suffix(env, node);", + XM => "${arch}_emit_x87_mode_suffix(env, node);", XXM => "${arch}_emit_xmm_mode_suffix(env, node);", XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);", AM => "${arch}_emit_am(env, node);", - unop => "${arch}_emit_unop(env, node);", + unop0 => "${arch}_emit_unop(env, node, 0);", + unop1 => "${arch}_emit_unop(env, node, 1);", + unop2 => "${arch}_emit_unop(env, node, 2);", + unop3 => "${arch}_emit_unop(env, node, 3);", + unop4 => "${arch}_emit_unop(env, node, 4);", + DAM0 => "${arch}_emit_am_or_dest_register(env, node, 0);", + DAM1 => "${arch}_emit_am_or_dest_register(env, node, 0);", binop => "${arch}_emit_binop(env, node);", x87_binop => "${arch}_emit_x87_binop(env, node);", ); @@ -274,7 +293,28 @@ $arch = "ia32"; # |_| # #--------------------------------------------------# -$default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);"; +$default_attr_type = "ia32_attr_t"; + +%init_attr = ( + ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", + ia32_x87_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_x87_attributes(res);", + ia32_asm_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_x87_attributes(res);". + "\tinit_ia32_asm_attributes(res);", + ia32_immediate_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);" +); + +%compare_attr = ( + ia32_attr_t => "ia32_compare_nodes_attr", + ia32_x87_attr_t => "ia32_compare_x87_attr", + ia32_asm_attr_t => "ia32_compare_asm_attr", + ia32_immediate_attr_t => "ia32_compare_immediate_attr", +); %operands = ( ); @@ -288,6 +328,23 @@ $fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM", %nodes = ( +Immediate => { + state => "pinned", + op_flags => "c", + irn_flags => "I", + reg_req => { out => [ "gp_NOREG" ] }, + attr => "ir_entity *symconst, int symconst_sign, long offset", + attr_type => "ia32_immediate_attr_t", + mode => $mode_gp, +}, + +Asm => { + mode => "mode_T", + arity => "variable", + out_arity => "variable", + attr_type => "ia32_asm_attr_t", +}, + #-----------------------------------------------------------------# # _ _ _ # # (_) | | | | # @@ -311,18 +368,17 @@ $fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM", Add => { irn_flags => "R", - comment => "construct Add: Add(a, b) = Add(b, a) = a + b", reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. addl %binop', + ins => [ "base", "index", "left", "right", "mem" ], + emit => '. add%M %binop', units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags }, Adc => { - comment => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry", reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. adcl %binop', + emit => '. adc%M %binop', units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags @@ -330,7 +386,6 @@ Adc => { Add64Bit => { irn_flags => "R", - comment => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry", arity => 4, reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] }, emit => ' @@ -348,24 +403,22 @@ l_Add => { op_flags => "C", irn_flags => "R", cmp_attr => "return 1;", - comment => "construct lowered Add: Add(a, b) = Add(b, a) = a + b", arity => 2, }, l_Adc => { op_flags => "C", cmp_attr => "return 1;", - comment => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry", arity => 2, }, Mul => { # we should not rematrialize this node. It produces 2 results and has # very strict constrains - comment => "construct MulS: MulS(a, b) = MulS(b, a) = a * b", reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] }, - emit => '. mull %unop', + emit => '. mul%M %unop3', outs => [ "EAX", "EDX", "M" ], + ins => [ "base", "index", "val_high", "val_low", "mem" ], latency => 10, units => [ "GP" ], modified_flags => $status_flags @@ -376,16 +429,14 @@ l_Mul => { # very strict constrains op_flags => "C", cmp_attr => "return 1;", - comment => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b", outs => [ "EAX", "EDX", "M" ], arity => 2 }, IMul => { irn_flags => "R", - comment => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. imull %binop', + emit => '. imul%M %binop', latency => 5, units => [ "GP" ], mode => $mode_gp, @@ -394,10 +445,10 @@ IMul => { IMul1OP => { irn_flags => "R", - comment => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b", reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] }, - emit => '. imull %unop', + emit => '. imul%M %unop3', outs => [ "EAX", "EDX", "M" ], + ins => [ "base", "index", "val_high", "val_low", "mem" ], latency => 5, units => [ "GP" ], modified_flags => $status_flags @@ -406,15 +457,13 @@ IMul1OP => { l_IMul => { op_flags => "C", cmp_attr => "return 1;", - comment => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b", arity => 2 }, And => { irn_flags => "R", - comment => "construct And: And(a, b) = And(b, a) = a AND b", reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. andl %binop', + emit => '. and%M %binop', units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags @@ -422,7 +471,6 @@ And => { Or => { irn_flags => "R", - comment => "construct Or: Or(a, b) = Or(b, a) = a OR b", reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, emit => '. or%M %binop', units => [ "GP" ], @@ -432,9 +480,8 @@ Or => { Xor => { irn_flags => "R", - comment => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b", reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. xorl %binop', + emit => '. xor%M %binop', units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags @@ -443,7 +490,6 @@ Xor => { l_Xor => { op_flags => "C", cmp_attr => "return 1;", - comment => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b", arity => 2, modified_flags => $status_flags }, @@ -452,18 +498,16 @@ l_Xor => { Sub => { irn_flags => "R", - comment => "construct Sub: Sub(a, b) = a - b", reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. subl %binop', + emit => '. sub%M %binop', units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags }, Sbb => { - comment => "construct Sub with Carry: SubC(a, b) = a - b - carry", reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] }, - emit => '. sbbl %binop', + emit => '. sbb%M %binop', units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags @@ -471,7 +515,6 @@ Sbb => { Sub64Bit => { irn_flags => "R", - comment => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow", arity => 4, reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] }, emit => ' @@ -488,13 +531,11 @@ Sub64Bit => { l_Sub => { irn_flags => "R", cmp_attr => "return 1;", - comment => "construct lowered Sub: Sub(a, b) = a - b", arity => 2, }, l_Sbb => { cmp_attr => "return 1;", - comment => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry", arity => 2, }, @@ -504,7 +545,7 @@ IDiv => { reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] }, attr => "ia32_op_flavour_t dm_flav", init_attr => "attr->data.op_flav = dm_flav;", - emit => ". idivl %unop", + emit => ". idiv%M %unop4", outs => [ "div_res", "mod_res", "M" ], latency => 25, units => [ "GP" ], @@ -517,7 +558,7 @@ Div => { reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] }, attr => "ia32_op_flavour_t dm_flav", init_attr => "attr->data.op_flav = dm_flav;", - emit => ". divl %unop", + emit => ". div%M %unop4", outs => [ "div_res", "mod_res", "M" ], latency => 25, units => [ "GP" ], @@ -526,9 +567,12 @@ Div => { Shl => { irn_flags => "R", - comment => "construct Shl: Shl(a, b) = a << b", + # "in_r3" would be enough as out requirement, but the register allocator + # does strange things then and doesn't respect the constraint for in4 + # if the same value is attached to in3 and in4 (if you have "i << i" in C) reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] }, - emit => '. shll %binop', + ins => [ "base", "index", "left", "right", "mem" ], + emit => '. shl%M %binop', units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags @@ -536,35 +580,34 @@ Shl => { l_Shl => { cmp_attr => "return 1;", - comment => "construct lowered Shl: Shl(a, b) = a << b", arity => 2 }, ShlD => { irn_flags => "R", - comment => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)", # Out requirements is: different from all in # This is because, out must be different from LowPart and ShiftCount. # We could say "!ecx !in_r4" but it can occur, that all values live through - # this Shift and the only value dying is the ShiftCount. Then there would be a - # register missing, as result must not be ecx and all other registers are - # occupied. What we should write is "!in_r4 !in_r5", but this is not supported - # (and probably never will). So we create artificial interferences of the result - # with all inputs, so the spiller can always assure a free register. + # this Shift and the only value dying is the ShiftCount. Then there would be + # a register missing, as result must not be ecx and all other registers are + # occupied. What we should write is "!in_r4 !in_r5", but this is not + # supported (and probably never will). So we create artificial interferences + # of the result with all inputs, so the spiller can always assure a free + # register. reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] }, emit => ' if (get_ia32_immop_type(node) == ia32_ImmNone) { if (get_ia32_op_type(node) == ia32_AddrModeD) { - . shldl %%cl, %S3, %AM + . shld%M %%cl, %S3, %AM } else { - . shldl %%cl, %S3, %S2 + . shld%M %%cl, %S3, %S2 } } else { if (get_ia32_op_type(node) == ia32_AddrModeD) { - . shldl %C, %S3, %AM + . shld%M %C, %S3, %AM } else { - . shldl %C, %S3, %S2 + . shld%M %C, %S3, %S2 } } ', @@ -576,15 +619,13 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { l_ShlD => { cmp_attr => "return 1;", - comment => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)", arity => 3, }, Shr => { irn_flags => "R", - comment => "construct Shr: Shr(a, b) = a >> b", reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] }, - emit => '. shrl %binop', + emit => '. shr%M %binop', units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags @@ -592,13 +633,11 @@ Shr => { l_Shr => { cmp_attr => "return 1;", - comment => "construct lowered Shr: Shr(a, b) = a << b", arity => 2 }, ShrD => { irn_flags => "R", - comment => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)", # Out requirements is: different from all in # This is because, out must be different from LowPart and ShiftCount. # We could say "!ecx !in_r4" but it can occur, that all values live through @@ -611,15 +650,15 @@ ShrD => { emit => ' if (get_ia32_immop_type(node) == ia32_ImmNone) { if (get_ia32_op_type(node) == ia32_AddrModeD) { - . shrdl %%cl, %S3, %AM + . shrd%M %%cl, %S3, %AM } else { - . shrdl %%cl, %S3, %S2 + . shrd%M %%cl, %S3, %S2 } } else { if (get_ia32_op_type(node) == ia32_AddrModeD) { - . shrdl %C, %S3, %AM + . shrd%M %C, %S3, %AM } else { - . shrdl %C, %S3, %S2 + . shrd%M %C, %S3, %S2 } } ', @@ -631,15 +670,13 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { l_ShrD => { cmp_attr => "return 1;", - comment => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)", arity => 3 }, Sar => { irn_flags => "R", - comment => "construct Shrs: Shrs(a, b) = a >> b", reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] }, - emit => '. sarl %binop', + emit => '. sar%M %binop', units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags @@ -647,15 +684,13 @@ Sar => { l_Sar => { cmp_attr => "return 1;", - comment => "construct lowered Sar: Sar(a, b) = a << b", arity => 2 }, Ror => { irn_flags => "R", - comment => "construct Ror: Ror(a, b) = a ROR b", reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] }, - emit => '. rorl %binop', + emit => '. ror%M %binop', units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags @@ -663,9 +698,8 @@ Ror => { Rol => { irn_flags => "R", - comment => "construct Rol: Rol(a, b) = a ROL b", reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] }, - emit => '. roll %binop', + emit => '. rol%M %binop', units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags @@ -675,9 +709,9 @@ Rol => { Neg => { irn_flags => "R", - comment => "construct Minus: Minus(a) = -a", reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. negl %unop', + emit => '. neg%M %unop2', + ins => [ "base", "index", "val", "mem" ], units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags @@ -685,8 +719,6 @@ Neg => { Minus64Bit => { irn_flags => "R", - comment => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow", - arity => 4, reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] }, emit => ' . movl %S0, %D0 @@ -702,15 +734,13 @@ Minus64Bit => { l_Neg => { cmp_attr => "return 1;", - comment => "construct lowered Minus: Minus(a) = -a", arity => 1, }, Inc => { irn_flags => "R", - comment => "construct Increment: Inc(a) = a++", reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. incl %unop', + emit => '. inc%M %unop2', units => [ "GP" ], mode => $mode_gp, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] @@ -718,9 +748,8 @@ Inc => { Dec => { irn_flags => "R", - comment => "construct Decrement: Dec(a) = a--", reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. decl %unop', + emit => '. dec%M %unop2', units => [ "GP" ], mode => $mode_gp, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] @@ -728,9 +757,9 @@ Dec => { Not => { irn_flags => "R", - comment => "construct Not: Not(a) = !a", reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. notl %unop', + ins => [ "base", "index", "val", "mem" ], + emit => '. not%M %unop2', units => [ "GP" ], mode => $mode_gp, modified_flags => [] @@ -741,8 +770,7 @@ Not => { CondJmp => { state => "pinned", op_flags => "L|X|Y", - comment => "construct conditional jump: CMP A, B && JMPxx LABEL", - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ] }, + reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none"] }, outs => [ "false", "true" ], latency => 3, units => [ "BRANCH" ], @@ -751,8 +779,7 @@ CondJmp => { TestJmp => { state => "pinned", op_flags => "L|X|Y", - comment => "construct conditional jump: TEST A, B && JMPxx LABEL", - reg_req => { in => [ "gp", "gp" ] }, + reg_req => { in => [ "gp", "gp" ], out => [ "none", "none" ] }, outs => [ "false", "true" ], latency => 3, units => [ "BRANCH" ], @@ -761,7 +788,6 @@ TestJmp => { CJmpAM => { state => "pinned", op_flags => "L|X|Y", - comment => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL", reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] }, outs => [ "false", "true" ], units => [ "BRANCH" ], @@ -770,7 +796,6 @@ CJmpAM => { CJmp => { state => "pinned", op_flags => "L|X|Y", - comment => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL", reg_req => { in => [ "gp", "gp" ] }, units => [ "BRANCH" ], }, @@ -778,7 +803,6 @@ CJmp => { SwitchJmp => { state => "pinned", op_flags => "L|X|Y", - comment => "construct switch", reg_req => { in => [ "gp" ], out => [ "none" ] }, latency => 3, units => [ "BRANCH" ], @@ -787,7 +811,6 @@ SwitchJmp => { Const => { op_flags => "c", irn_flags => "R", - comment => "represents an integer constant", reg_req => { out => [ "gp" ] }, units => [ "GP" ], mode => $mode_gp, @@ -797,7 +820,6 @@ Unknown_GP => { state => "pinned", op_flags => "c", irn_flags => "I", - comment => "unknown value", reg_req => { out => [ "gp_UKNWN" ] }, units => [], emit => "", @@ -808,18 +830,17 @@ Unknown_VFP => { state => "pinned", op_flags => "c", irn_flags => "I", - comment => "unknown value", reg_req => { out => [ "vfp_UKNWN" ] }, units => [], emit => "", - mode => "mode_E" + mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, Unknown_XMM => { state => "pinned", op_flags => "c", irn_flags => "I", - comment => "unknown value", reg_req => { out => [ "xmm_UKNWN" ] }, units => [], emit => "", @@ -830,7 +851,6 @@ NoReg_GP => { state => "pinned", op_flags => "c", irn_flags => "I", - comment => "noreg GP value", reg_req => { out => [ "gp_NOREG" ] }, units => [], emit => "", @@ -841,18 +861,17 @@ NoReg_VFP => { state => "pinned", op_flags => "c", irn_flags => "I", - comment => "noreg VFP value", reg_req => { out => [ "vfp_NOREG" ] }, units => [], emit => "", - mode => "mode_E" + mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, NoReg_XMM => { state => "pinned", op_flags => "c", irn_flags => "I", - comment => "noreg XMM value", reg_req => { out => [ "xmm_NOREG" ] }, units => [], emit => "", @@ -863,7 +882,6 @@ ChangeCW => { state => "pinned", op_flags => "c", irn_flags => "I", - comment => "change floating point control word", reg_req => { out => [ "fp_cw" ] }, mode => $mode_fpcw, latency => 3, @@ -873,8 +891,7 @@ ChangeCW => { FldCW => { op_flags => "L|F", - state => "exc_pinned", - comment => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg", + state => "pinned", reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] }, latency => 5, emit => ". fldcw %AM", @@ -885,8 +902,7 @@ FldCW => { FnstCW => { op_flags => "L|F", - state => "exc_pinned", - comment => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg", + state => "pinned", reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] }, latency => 5, emit => ". fnstcw %AM", @@ -897,21 +913,23 @@ FnstCW => { Cltd => { # we should not rematrialize this node. It produces 2 results and has # very strict constrains - comment => "construct CDQ: sign extend EAX -> EDX:EAX", - reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] }, + reg_req => { in => [ "eax" ], out => [ "edx" ] }, + ins => [ "val" ], emit => '. cltd', - outs => [ "EAX", "EDX" ], + mode => $mode_gp, units => [ "GP" ], }, # Load / Store +# +# Note that we add additional latency values depending on address mode, so a +# lateny of 0 for load is correct Load => { op_flags => "L|F", state => "exc_pinned", - comment => "construct Load: Load(ptr, mem) = LD ptr -> reg", reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] }, - latency => 3, + latency => 0, emit => ". mov%SE%ME%.l %AM, %D0", outs => [ "res", "M" ], units => [ "GP" ], @@ -920,7 +938,6 @@ Load => { l_Load => { op_flags => "L|F", cmp_attr => "return 1;", - comment => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg", outs => [ "res", "M" ], arity => 2, }, @@ -929,7 +946,6 @@ l_Store => { op_flags => "L|F", cmp_attr => "return 1;", state => "exc_pinned", - comment => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val", arity => 3, mode => "mode_M", }, @@ -937,10 +953,9 @@ l_Store => { Store => { op_flags => "L|F", state => "exc_pinned", - comment => "construct Store: Store(ptr, val, mem) = ST ptr,val", reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] }, emit => '. mov%M %binop', - latency => 3, + latency => 2, units => [ "GP" ], mode => "mode_M", }, @@ -948,17 +963,15 @@ Store => { Store8Bit => { op_flags => "L|F", state => "exc_pinned", - comment => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val", reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] }, emit => '. mov%M %binop', - latency => 3, + latency => 2, units => [ "GP" ], mode => "mode_M", }, Lea => { irn_flags => "R", - comment => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8", reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] }, emit => '. leal %AM, %D0', latency => 2, @@ -968,28 +981,27 @@ Lea => { }, Push => { - comment => "push on the stack", reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] }, - emit => '. pushl %unop', + emit => '. push%M %unop2', + ins => [ "base", "index", "val", "stack", "mem" ], outs => [ "stack:I|S", "M" ], - latency => 3, + latency => 2, units => [ "GP" ], modified_flags => [], }, Pop => { - comment => "pop a gp register from the stack", reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] }, - emit => '. popl %unop', + emit => '. pop%M %DAM1', outs => [ "stack:I|S", "res", "M" ], - latency => 4, + ins => [ "base", "index", "stack", "mem" ], + latency => 3, # Pop is more expensive than Push on Athlon units => [ "GP" ], modified_flags => [], }, Enter => { - comment => "create stack frame", - reg_req => { in => [ "esp" ], out => [ "ebp", "esp" ] }, + reg_req => { in => [ "esp" ], out => [ "ebp", "esp", "none" ] }, emit => '. enter', outs => [ "frame:I", "stack:I|S", "M" ], latency => 15, @@ -997,7 +1009,6 @@ Enter => { }, Leave => { - comment => "destroy stack frame", reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] }, emit => '. leave', outs => [ "frame:I", "stack:I|S" ], @@ -1007,7 +1018,6 @@ Leave => { AddSP => { irn_flags => "I", - comment => "allocate space on stack", reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] }, emit => '. addl %binop', outs => [ "stack:S", "M" ], @@ -1017,7 +1027,6 @@ AddSP => { SubSP => { irn_flags => "I", - comment => "free space on stack", reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] }, emit => '. subl %binop', outs => [ "stack:S", "M" ], @@ -1027,11 +1036,20 @@ SubSP => { LdTls => { irn_flags => "R", - comment => "get the TLS base address", reg_req => { out => [ "gp" ] }, units => [ "GP" ], }, +# the int instruction +int => { + reg_req => { in => [ "none" ], out => [ "none" ] }, + mode => "mode_M", + attr => "tarval *tv", + init_attr => "\tset_ia32_Immop_tarval(res, tv);", + emit => '. int %C', + units => [ "GP" ], + cmp_attr => "return 1;", +}, #-----------------------------------------------------------------------------# @@ -1047,7 +1065,6 @@ LdTls => { xAdd => { irn_flags => "R", - comment => "construct SSE Add: Add(a, b) = Add(b, a) = a + b", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, emit => '. add%XXM %binop', latency => 4, @@ -1057,7 +1074,6 @@ xAdd => { xMul => { irn_flags => "R", - comment => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, emit => '. mul%XXM %binop', latency => 4, @@ -1067,7 +1083,6 @@ xMul => { xMax => { irn_flags => "R", - comment => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, emit => '. max%XXM %binop', latency => 2, @@ -1077,7 +1092,6 @@ xMax => { xMin => { irn_flags => "R", - comment => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, emit => '. min%XXM %binop', latency => 2, @@ -1087,7 +1101,6 @@ xMin => { xAnd => { irn_flags => "R", - comment => "construct SSE And: And(a, b) = a AND b", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, emit => '. andp%XSD %binop', latency => 3, @@ -1097,7 +1110,6 @@ xAnd => { xOr => { irn_flags => "R", - comment => "construct SSE Or: Or(a, b) = a OR b", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, emit => '. orp%XSD %binop', units => [ "SSE" ], @@ -1106,7 +1118,6 @@ xOr => { xXor => { irn_flags => "R", - comment => "construct SSE Xor: Xor(a, b) = a XOR b", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, emit => '. xorp%XSD %binop', latency => 3, @@ -1118,7 +1129,6 @@ xXor => { xAndNot => { irn_flags => "R", - comment => "construct SSE AndNot: AndNot(a, b) = a AND NOT b", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] }, emit => '. andnp%XSD %binop', latency => 3, @@ -1128,7 +1138,6 @@ xAndNot => { xSub => { irn_flags => "R", - comment => "construct SSE Sub: Sub(a, b) = a - b", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, emit => '. sub%XXM %binop', latency => 4, @@ -1138,8 +1147,7 @@ xSub => { xDiv => { irn_flags => "R", - comment => "construct SSE Div: Div(a, b) = a / b", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] }, + reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4", "none" ] }, outs => [ "res", "M" ], emit => '. div%XXM %binop', latency => 16, @@ -1150,7 +1158,6 @@ xDiv => { xCmp => { irn_flags => "R", - comment => "construct SSE Compare: Cmp(a, b) == a = a cmp b", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] }, latency => 3, units => [ "SSE" ], @@ -1160,7 +1167,6 @@ xCmp => { xCondJmp => { state => "pinned", op_flags => "L|X|Y", - comment => "construct conditional jump: UCOMIS A, B && JMPxx LABEL", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] }, outs => [ "false", "true" ], latency => 5, @@ -1170,7 +1176,6 @@ xCondJmp => { xConst => { op_flags => "c", irn_flags => "R", - comment => "represents a SSE constant", reg_req => { out => [ "xmm" ] }, emit => '. mov%XXM %C, %D0', latency => 2, @@ -1183,7 +1188,6 @@ xConst => { xLoad => { op_flags => "L|F", state => "exc_pinned", - comment => "construct SSE Load: Load(ptr, mem) = LD ptr", reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] }, emit => '. mov%XXM %AM, %D0', outs => [ "res", "M" ], @@ -1194,7 +1198,6 @@ xLoad => { xStore => { op_flags => "L|F", state => "exc_pinned", - comment => "construct Store: Store(ptr, val, mem) = ST ptr,val", reg_req => { in => [ "gp", "gp", "xmm", "none" ] }, emit => '. mov%XXM %binop', latency => 2, @@ -1205,9 +1208,9 @@ xStore => { xStoreSimple => { op_flags => "L|F", state => "exc_pinned", - comment => "construct Store without index: Store(ptr, val, mem) = ST ptr,val", - reg_req => { in => [ "gp", "xmm", "none" ] }, - emit => '. mov%XXM %S1, %AM', + reg_req => { in => [ "gp", "gp", "xmm", "none" ] }, + ins => [ "base", "index", "val", "mem" ], + emit => '. mov%XXM %S2, %AM', latency => 2, units => [ "SSE" ], mode => "mode_M", @@ -1225,7 +1228,7 @@ CvtSI2SS => { CvtSI2SD => { op_flags => "L|F", reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] }, - emit => '. cvtsi2sd %unop', + emit => '. cvtsi2sd %unop2', latency => 2, units => [ "SSE" ], mode => $mode_xmm @@ -1234,14 +1237,12 @@ CvtSI2SD => { l_X87toSSE => { op_flags => "L|F", - comment => "construct: transfer a value from x87 FPU into a SSE register", cmp_attr => "return 1;", arity => 3, }, l_SSEtoX87 => { op_flags => "L|F", - comment => "construct: transfer a value from SSE register to x87 FPU", cmp_attr => "return 1;", arity => 3, }, @@ -1249,10 +1250,9 @@ l_SSEtoX87 => { GetST0 => { op_flags => "L|F", irn_flags => "I", - state => "exc_pinned", - comment => "store ST0 onto stack", + state => "pinned", reg_req => { in => [ "gp", "gp", "none" ] }, - emit => '. fstp%M %AM', + emit => '. fstp%XM %AM', latency => 4, units => [ "SSE" ], mode => "mode_M", @@ -1261,10 +1261,10 @@ GetST0 => { SetST0 => { op_flags => "L|F", irn_flags => "I", - state => "exc_pinned", - comment => "load ST0 from stack", - reg_req => { in => [ "gp", "none" ], out => [ "vf0", "none" ] }, - emit => '. fld%M %AM', + state => "pinned", + reg_req => { in => [ "gp", "gp", "none" ], out => [ "vf0", "none" ] }, + ins => [ "base", "index", "mem" ], + emit => '. fld%XM %AM', outs => [ "res", "M" ], latency => 2, units => [ "SSE" ], @@ -1275,7 +1275,6 @@ SetST0 => { CopyB => { op_flags => "F|H", state => "pinned", - comment => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)", reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] }, outs => [ "DST", "SRC", "CNT", "M" ], units => [ "GP" ], @@ -1285,7 +1284,6 @@ CopyB => { CopyB_i => { op_flags => "F|H", state => "pinned", - comment => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))", reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] }, outs => [ "DST", "SRC", "M" ], units => [ "GP" ], @@ -1296,15 +1294,15 @@ CopyB_i => { Conv_I2I => { reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] }, - comment => "construct Conv Int -> Int", units => [ "GP" ], + ins => [ "base", "index", "val", "mem" ], mode => $mode_gp, modified_flags => $status_flags }, Conv_I2I8Bit => { reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] }, - comment => "construct Conv Int -> Int", + ins => [ "base", "index", "val", "mem" ], units => [ "GP" ], mode => $mode_gp, modified_flags => $status_flags @@ -1312,7 +1310,6 @@ Conv_I2I8Bit => { Conv_I2FP => { reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] }, - comment => "construct Conv Int -> Floating Point", latency => 10, units => [ "SSE" ], mode => "mode_E", @@ -1320,7 +1317,6 @@ Conv_I2FP => { Conv_FP2I => { reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] }, - comment => "construct Conv Floating Point -> Int", latency => 10, units => [ "SSE" ], mode => $mode_gp, @@ -1328,7 +1324,6 @@ Conv_FP2I => { Conv_FP2FP => { reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] }, - comment => "construct Conv Floating Point -> Floating Point", latency => 8, units => [ "SSE" ], mode => "mode_E", @@ -1336,17 +1331,10 @@ Conv_FP2FP => { CmpCMov => { irn_flags => "R", - comment => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b", reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] }, - latency => 2, - units => [ "GP" ], - mode => $mode_gp, -}, - -PsiCondCMov => { - irn_flags => "R", - comment => "check if Psi condition tree evaluates to true and move result accordingly", - reg_req => { in => [ "gp", "gp", "gp" ], out => [ "in_r3" ] }, + ins => [ "cmp_left", "cmp_right", "val_true", "val_false" ], + attr => "pn_Cmp pn_code", + init_attr => "attr->pn_code = pn_code;", latency => 2, units => [ "GP" ], mode => $mode_gp, @@ -1354,7 +1342,6 @@ PsiCondCMov => { xCmpCMov => { irn_flags => "R", - comment => "construct Conditional Move: SSE Compare + int CMov ", reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] }, latency => 5, units => [ "SSE" ], @@ -1363,26 +1350,19 @@ xCmpCMov => { vfCmpCMov => { irn_flags => "R", - comment => "construct Conditional Move: x87 Compare + int CMov", reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] }, latency => 10, units => [ "VFP" ], mode => $mode_gp, + attr_type => "ia32_x87_attr_t", }, CmpSet => { irn_flags => "R", - comment => "construct Set: Set(sel) == sel ? 1 : 0", reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] }, - latency => 2, - units => [ "GP" ], - mode => $mode_gp, -}, - -PsiCondSet => { - irn_flags => "R", - comment => "check if Psi condition tree evaluates to true and set result accordingly", - reg_req => { in => [ "gp" ], out => [ "eax ebx ecx edx" ] }, + ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ], + attr => "pn_Cmp pn_code", + init_attr => "attr->pn_code = pn_code;", latency => 2, units => [ "GP" ], mode => $mode_gp, @@ -1390,7 +1370,6 @@ PsiCondSet => { xCmpSet => { irn_flags => "R", - comment => "construct Set: SSE Compare + int Set", reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] }, latency => 5, units => [ "SSE" ], @@ -1399,20 +1378,20 @@ xCmpSet => { vfCmpSet => { irn_flags => "R", - comment => "construct Set: x87 Compare + int Set", reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] }, latency => 10, units => [ "VFP" ], mode => $mode_gp, + attr_type => "ia32_x87_attr_t", }, vfCMov => { irn_flags => "R", - comment => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b", reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] }, latency => 10, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, #----------------------------------------------------------# @@ -1431,116 +1410,92 @@ vfCMov => { vfadd => { irn_flags => "R", - comment => "virtual fp Add: Add(a, b) = Add(b, a) = a + b", - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] }, + reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] }, + ins => [ "base", "index", "left", "right", "mem", "fpcw" ], latency => 4, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, vfmul => { irn_flags => "R", - comment => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b", - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] }, + reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] }, + ins => [ "base", "index", "left", "right", "mem", "fpcw" ], latency => 4, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, l_vfmul => { op_flags => "C", cmp_attr => "return 1;", - comment => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b", arity => 2, }, vfsub => { irn_flags => "R", - comment => "virtual fp Sub: Sub(a, b) = a - b", - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] }, + reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] }, + ins => [ "base", "index", "left", "right", "mem", "fpcw" ], latency => 4, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, l_vfsub => { cmp_attr => "return 1;", - comment => "lowered virtual fp Sub: Sub(a, b) = a - b", arity => 2, }, vfdiv => { - comment => "virtual fp Div: Div(a, b) = a / b", - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] }, + reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp", "none" ] }, + ins => [ "base", "index", "left", "right", "mem", "fpcw" ], outs => [ "res", "M" ], latency => 20, units => [ "VFP" ], + attr_type => "ia32_x87_attr_t", }, l_vfdiv => { cmp_attr => "return 1;", - comment => "lowered virtual fp Div: Div(a, b) = a / b", outs => [ "res", "M" ], arity => 2, }, vfprem => { - comment => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)", - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] }, + reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] }, + ins => [ "base", "index", "left", "right", "mem", "fpcw" ], latency => 20, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, l_vfprem => { cmp_attr => "return 1;", - comment => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)", arity => 2, }, vfabs => { irn_flags => "R", - comment => "virtual fp Abs: Abs(a) = |a|", reg_req => { in => [ "vfp"], out => [ "vfp" ] }, + ins => [ "value" ], latency => 2, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, vfchs => { irn_flags => "R", - comment => "virtual fp Chs: Chs(a) = -a", reg_req => { in => [ "vfp"], out => [ "vfp" ] }, + ins => [ "value" ], latency => 2, units => [ "VFP" ], mode => "mode_E", -}, - -vfsin => { - irn_flags => "R", - comment => "virtual fp Sin: Sin(a) = sin(a)", - reg_req => { in => [ "vfp"], out => [ "vfp" ] }, - latency => 150, - units => [ "VFP" ], - mode => "mode_E", -}, - -vfcos => { - irn_flags => "R", - comment => "virtual fp Cos: Cos(a) = cos(a)", - reg_req => { in => [ "vfp"], out => [ "vfp" ] }, - latency => 150, - units => [ "VFP" ], - mode => "mode_E", -}, - -vfsqrt => { - irn_flags => "R", - comment => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5", - reg_req => { in => [ "vfp"], out => [ "vfp" ] }, - latency => 30, - units => [ "VFP" ], - mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, # virtual Load and Store @@ -1548,51 +1503,60 @@ vfsqrt => { vfld => { op_flags => "L|F", state => "exc_pinned", - comment => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg", reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] }, + ins => [ "base", "index", "mem" ], outs => [ "res", "M" ], + attr => "ir_mode *store_mode", + init_attr => "attr->attr.ls_mode = store_mode;", latency => 2, units => [ "VFP" ], + attr_type => "ia32_x87_attr_t", }, vfst => { op_flags => "L|F", state => "exc_pinned", - comment => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val", reg_req => { in => [ "gp", "gp", "vfp", "none" ] }, + ins => [ "base", "index", "val", "mem" ], + attr => "ir_mode *store_mode", + init_attr => "attr->attr.ls_mode = store_mode;", latency => 2, units => [ "VFP" ], mode => "mode_M", + attr_type => "ia32_x87_attr_t", }, # Conversions vfild => { - comment => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] }, outs => [ "res", "M" ], + ins => [ "base", "index", "mem" ], latency => 4, units => [ "VFP" ], + attr_type => "ia32_x87_attr_t", }, l_vfild => { cmp_attr => "return 1;", - comment => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg", outs => [ "res", "M" ], arity => 2, }, vfist => { - comment => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] }, + ins => [ "base", "index", "val", "fpcw", "mem" ], latency => 4, units => [ "VFP" ], mode => "mode_M", + attr_type => "ia32_x87_attr_t", }, l_vfist => { cmp_attr => "return 1;", - comment => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val", + state => "exc_pinned", arity => 3, mode => "mode_M", }, @@ -1602,76 +1566,75 @@ l_vfist => { vfldz => { irn_flags => "R", - comment => "virtual fp Load 0.0: Ld 0.0 -> reg", reg_req => { out => [ "vfp" ] }, latency => 4, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, vfld1 => { irn_flags => "R", - comment => "virtual fp Load 1.0: Ld 1.0 -> reg", reg_req => { out => [ "vfp" ] }, latency => 4, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, vfldpi => { irn_flags => "R", - comment => "virtual fp Load pi: Ld pi -> reg", reg_req => { out => [ "vfp" ] }, latency => 4, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, vfldln2 => { irn_flags => "R", - comment => "virtual fp Load ln 2: Ld ln 2 -> reg", reg_req => { out => [ "vfp" ] }, latency => 4, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, vfldlg2 => { irn_flags => "R", - comment => "virtual fp Load lg 2: Ld lg 2 -> reg", reg_req => { out => [ "vfp" ] }, latency => 4, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, vfldl2t => { irn_flags => "R", - comment => "virtual fp Load ld 10: Ld ld 10 -> reg", reg_req => { out => [ "vfp" ] }, latency => 4, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, vfldl2e => { irn_flags => "R", - comment => "virtual fp Load ld e: Ld ld e -> reg", reg_req => { out => [ "vfp" ] }, latency => 4, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, vfConst => { op_flags => "c", irn_flags => "R", -# init_attr => " set_ia32_ls_mode(res, mode);", - comment => "represents a virtual floating point constant", reg_req => { out => [ "vfp" ] }, latency => 3, units => [ "VFP" ], mode => "mode_E", + attr_type => "ia32_x87_attr_t", }, # other @@ -1679,11 +1642,11 @@ vfConst => { vfCondJmp => { state => "pinned", op_flags => "L|X|Y", - comment => "represents a virtual floating point compare", reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] }, outs => [ "false", "true", "temp_reg_eax" ], latency => 10, units => [ "VFP" ], + attr_type => "ia32_x87_attr_t", }, #------------------------------------------------------------------------# @@ -1700,77 +1663,77 @@ vfCondJmp => { fadd => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 Add: Add(a, b) = Add(b, a) = a + b", reg_req => { }, - emit => '. fadd%M %x87_binop', + emit => '. fadd%XM %x87_binop', + attr_type => "ia32_x87_attr_t", }, faddp => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 Add: Add(a, b) = Add(b, a) = a + b", reg_req => { }, emit => '. faddp %x87_binop', + attr_type => "ia32_x87_attr_t", }, fmul => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b", reg_req => { }, - emit => '. fmul%M %x87_binop', + emit => '. fmul%XM %x87_binop', + attr_type => "ia32_x87_attr_t", }, fmulp => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b", reg_req => { }, emit => '. fmulp %x87_binop',, + attr_type => "ia32_x87_attr_t", }, fsub => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp Sub: Sub(a, b) = a - b", reg_req => { }, - emit => '. fsub%M %x87_binop', + emit => '. fsub%XM %x87_binop', + attr_type => "ia32_x87_attr_t", }, fsubp => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp Sub: Sub(a, b) = a - b", reg_req => { }, # see note about gas bugs emit => '. fsubrp %x87_binop', + attr_type => "ia32_x87_attr_t", }, fsubr => { op_flags => "R", rd_constructor => "NONE", irn_flags => "R", - comment => "x87 fp SubR: SubR(a, b) = b - a", reg_req => { }, - emit => '. fsubr%M %x87_binop', + emit => '. fsubr%XM %x87_binop', + attr_type => "ia32_x87_attr_t", }, fsubrp => { op_flags => "R", rd_constructor => "NONE", irn_flags => "R", - comment => "x87 fp SubR: SubR(a, b) = b - a", reg_req => { }, # see note about gas bugs emit => '. fsubp %x87_binop', + attr_type => "ia32_x87_attr_t", }, fprem => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)", reg_req => { }, emit => '. fprem1', + attr_type => "ia32_x87_attr_t", }, # this node is just here, to keep the simulator running @@ -1778,83 +1741,59 @@ fprem => { fpremp => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)", reg_req => { }, emit => '. fprem1', + attr_type => "ia32_x87_attr_t", }, fdiv => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp Div: Div(a, b) = a / b", reg_req => { }, - emit => '. fdiv%M %x87_binop', + emit => '. fdiv%XM %x87_binop', + attr_type => "ia32_x87_attr_t", }, fdivp => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp Div: Div(a, b) = a / b", reg_req => { }, # see note about gas bugs emit => '. fdivrp %x87_binop', + attr_type => "ia32_x87_attr_t", }, fdivr => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp DivR: DivR(a, b) = b / a", reg_req => { }, - emit => '. fdivr%M %x87_binop', + emit => '. fdivr%XM %x87_binop', + attr_type => "ia32_x87_attr_t", }, fdivrp => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp DivR: DivR(a, b) = b / a", reg_req => { }, # see note about gas bugs emit => '. fdivp %x87_binop', + attr_type => "ia32_x87_attr_t", }, fabs => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp Abs: Abs(a) = |a|", reg_req => { }, emit => '. fabs', + attr_type => "ia32_x87_attr_t", }, fchs => { - op_flags => "R", + op_flags => "R|K", rd_constructor => "NONE", - comment => "x87 fp Chs: Chs(a) = -a", reg_req => { }, emit => '. fchs', -}, - -fsin => { - op_flags => "R", - rd_constructor => "NONE", - comment => "x87 fp Sin: Sin(a) = sin(a)", - reg_req => { }, - emit => '. fsin', -}, - -fcos => { - op_flags => "R", - rd_constructor => "NONE", - comment => "x87 fp Cos: Cos(a) = cos(a)", - reg_req => { }, - emit => '. fcos', -}, - -fsqrt => { - op_flags => "R", - rd_constructor => "NONE", - comment => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5", - reg_req => { }, - emit => '. fsqrt $', + attr_type => "ia32_x87_attr_t", }, # x87 Load and Store @@ -1863,29 +1802,29 @@ fld => { rd_constructor => "NONE", op_flags => "R|L|F", state => "exc_pinned", - comment => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg", reg_req => { }, - emit => '. fld%M %AM', + emit => '. fld%XM %AM', + attr_type => "ia32_x87_attr_t", }, fst => { rd_constructor => "NONE", op_flags => "R|L|F", state => "exc_pinned", - comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val", reg_req => { }, - emit => '. fst%M %AM', + emit => '. fst%XM %AM', mode => "mode_M", + attr_type => "ia32_x87_attr_t", }, fstp => { rd_constructor => "NONE", op_flags => "R|L|F", state => "exc_pinned", - comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val", reg_req => { }, - emit => '. fstp%M %AM', + emit => '. fstp%XM %AM', mode => "mode_M", + attr_type => "ia32_x87_attr_t", }, # Conversions @@ -1893,85 +1832,87 @@ fstp => { fild => { op_flags => "R", rd_constructor => "NONE", - comment => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg", reg_req => { }, - emit => '. fild%M %AM', + emit => '. fild%XM %AM', + attr_type => "ia32_x87_attr_t", }, fist => { op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", - comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val", reg_req => { }, - emit => '. fist%M %AM', + emit => '. fist%XM %AM', mode => "mode_M", + attr_type => "ia32_x87_attr_t", }, fistp => { op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", - comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val", reg_req => { }, - emit => '. fistp%M %AM', + emit => '. fistp%XM %AM', mode => "mode_M", + attr_type => "ia32_x87_attr_t", }, # constants fldz => { - op_flags => "R|c", + op_flags => "R|c|K", irn_flags => "R", - comment => "x87 fp Load 0.0: Ld 0.0 -> reg", reg_req => { }, emit => '. fldz', + attr_type => "ia32_x87_attr_t", }, fld1 => { - op_flags => "R|c", + op_flags => "R|c|K", irn_flags => "R", - comment => "x87 fp Load 1.0: Ld 1.0 -> reg", reg_req => { }, emit => '. fld1', + attr_type => "ia32_x87_attr_t", }, fldpi => { - op_flags => "R|c", + op_flags => "R|c|K", irn_flags => "R", - comment => "x87 fp Load pi: Ld pi -> reg", reg_req => { }, emit => '. fldpi', + attr_type => "ia32_x87_attr_t", }, fldln2 => { - op_flags => "R|c", + op_flags => "R|c|K", irn_flags => "R", - comment => "x87 fp Load ln 2: Ld ln 2 -> reg", reg_req => { }, emit => '. fldln2', + attr_type => "ia32_x87_attr_t", }, fldlg2 => { - op_flags => "R|c", + op_flags => "R|c|K", irn_flags => "R", - comment => "x87 fp Load lg 2: Ld lg 2 -> reg", reg_req => { }, emit => '. fldlg2', + attr_type => "ia32_x87_attr_t", }, fldl2t => { - op_flags => "R|c", + op_flags => "R|c|K", irn_flags => "R", - comment => "x87 fp Load ld 10: Ld ld 10 -> reg", reg_req => { }, emit => '. fldll2t', + attr_type => "ia32_x87_attr_t", }, fldl2e => { - op_flags => "R|c", + op_flags => "R|c|K", irn_flags => "R", - comment => "x87 fp Load ld e: Ld ld e -> reg", reg_req => { }, emit => '. fldl2e', + attr_type => "ia32_x87_attr_t", }, # fxch, fpush, fpop @@ -1980,72 +1921,72 @@ fldl2e => { fxch => { op_flags => "R|K", - comment => "x87 stack exchange", reg_req => { }, cmp_attr => "return 1;", emit => '. fxch %X0', + attr_type => "ia32_x87_attr_t", }, fpush => { op_flags => "R|K", - comment => "x87 stack push", reg_req => {}, cmp_attr => "return 1;", emit => '. fld %X0', + attr_type => "ia32_x87_attr_t", }, fpushCopy => { op_flags => "R", - comment => "x87 stack push", reg_req => { in => [ "vfp"], out => [ "vfp" ] }, cmp_attr => "return 1;", emit => '. fld %X0', + attr_type => "ia32_x87_attr_t", }, fpop => { op_flags => "R|K", - comment => "x87 stack pop", reg_req => { }, cmp_attr => "return 1;", emit => '. fstp %X0', + attr_type => "ia32_x87_attr_t", }, # compare fcomJmp => { op_flags => "L|X|Y", - comment => "floating point compare", reg_req => { }, + attr_type => "ia32_x87_attr_t", }, fcompJmp => { op_flags => "L|X|Y", - comment => "floating point compare and pop", reg_req => { }, + attr_type => "ia32_x87_attr_t", }, fcomppJmp => { op_flags => "L|X|Y", - comment => "floating point compare and pop twice", reg_req => { }, + attr_type => "ia32_x87_attr_t", }, fcomrJmp => { op_flags => "L|X|Y", - comment => "floating point compare reverse", reg_req => { }, + attr_type => "ia32_x87_attr_t", }, fcomrpJmp => { op_flags => "L|X|Y", - comment => "floating point compare reverse and pop", reg_req => { }, + attr_type => "ia32_x87_attr_t", }, fcomrppJmp => { op_flags => "L|X|Y", - comment => "floating point compare reverse and pop twice", reg_req => { }, + attr_type => "ia32_x87_attr_t", }, @@ -2064,7 +2005,6 @@ fcomrppJmp => { xxLoad => { op_flags => "L|F", state => "exc_pinned", - comment => "construct SSE Load: Load(ptr, mem) = LD ptr", reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] }, emit => '. movdqu %D0, %AM', outs => [ "res", "M" ], @@ -2074,7 +2014,6 @@ xxLoad => { xxStore => { op_flags => "L|F", state => "exc_pinned", - comment => "construct Store: Store(ptr, val, mem) = ST ptr,val", reg_req => { in => [ "gp", "gp", "xmm", "none" ] }, emit => '. movdqu %binop', units => [ "SSE" ],