X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=f830e75738206abc0ba57dcec364be23b7d325f6;hb=4be314ae49c26d8b9084200a570bc4a1285bef50;hp=054641fbd422fd6af8497b26f08a7dc8d89dfba2;hpb=6fc4c5b3111680a0fc719388b32ac5ee37280a7c;p=libfirm diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index 054641fbd..f830e7573 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -28,10 +28,14 @@ $arch = "ia32"; # comment => "any comment for constructor", # reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] }, # cmp_attr => "c source code for comparing node attributes", +# outs => { "out1", "out2" } # optional, creates pn_op_out1, ... consts +# ins => { "in1", "in2" } # optional, creates n_op_in1, ... consts +# mode => "mode_Iu" # optional, predefines the mode # emit => "emit code with templates", -# attr => "attitional attribute arguments for constructor" -# init_attr => "emit attribute initialization template" -# rd_constructor => "c source code which constructs an ir_node" +# attr => "attitional attribute arguments for constructor", +# init_attr => "emit attribute initialization template", +# rd_constructor => "c source code which constructs an ir_node", +# hash_func => "name of the hash function for this operation", # latency => "latency of this operation (can be float)" # attr_type => "name of the attribute struct", # }, @@ -52,6 +56,8 @@ $arch = "ia32"; # H irop_flag_highlevel # c irop_flag_constlike # K irop_flag_keep +# NB irop_flag_dump_noblock +# NI irop_flag_dump_noinput # # irn_flags: special node flags, OPTIONAL (default is 0) # following irn_flags are supported: @@ -96,8 +102,6 @@ $arch = "ia32"; # # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3 # -# latency: the latency of the operation, default is 1 -# # register types: # 0 - no special type @@ -147,14 +151,14 @@ $arch = "ia32"; { mode => "mode_E" } ], vfp => [ - { name => "vf0", type => 1 | 16 }, - { name => "vf1", type => 1 | 16 }, - { name => "vf2", type => 1 | 16 }, - { name => "vf3", type => 1 | 16 }, - { name => "vf4", type => 1 | 16 }, - { name => "vf5", type => 1 | 16 }, - { name => "vf6", type => 1 | 16 }, - { name => "vf7", type => 1 | 16 }, + { name => "vf0", type => 1 }, + { name => "vf1", type => 1 }, + { name => "vf2", type => 1 }, + { name => "vf3", type => 1 }, + { name => "vf4", type => 1 }, + { name => "vf5", type => 1 }, + { name => "vf6", type => 1 }, + { name => "vf7", type => 1 }, { name => "vfp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes { name => "vfp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes { mode => "mode_E" } @@ -200,6 +204,7 @@ $arch = "ia32"; SB1 => "${arch}_emit_8bit_source_register_or_immediate(node, 1);", SB2 => "${arch}_emit_8bit_source_register_or_immediate(node, 2);", SB3 => "${arch}_emit_8bit_source_register_or_immediate(node, 3);", + SI1 => "${arch}_emit_source_register_or_immediate(node, 1);", SI3 => "${arch}_emit_source_register_or_immediate(node, 3);", D0 => "${arch}_emit_dest_register(node, 0);", D1 => "${arch}_emit_dest_register(node, 1);", @@ -214,13 +219,12 @@ $arch = "ia32"; XXM => "${arch}_emit_xmm_mode_suffix(node);", XSD => "${arch}_emit_xmm_mode_suffix_s(node);", AM => "${arch}_emit_am(node);", - unop3 => "${arch}_emit_unop(node, 3);", - unop4 => "${arch}_emit_unop(node, 4);", - unop5 => "${arch}_emit_unop(node, 5);", - DAM1 => "${arch}_emit_am_or_dest_register(node, 1);", + unop3 => "${arch}_emit_unop(node, n_ia32_unary_op);", + unop4 => "${arch}_emit_unop(node, n_ia32_binary_right);", binop => "${arch}_emit_binop(node);", x87_binop => "${arch}_emit_x87_binop(node);", CMP0 => "${arch}_emit_cmp_suffix_node(node, 0);", + CMP3 => "${arch}_emit_cmp_suffix_node(node, 3);", ); #--------------------------------------------------# @@ -234,75 +238,81 @@ $arch = "ia32"; # |_| # #--------------------------------------------------# -$default_attr_type = "ia32_attr_t"; -$default_copy_attr = "ia32_copy_attr"; +$default_op_attr_type = "ia32_op_attr_t"; +$default_attr_type = "ia32_attr_t"; +$default_copy_attr = "ia32_copy_attr"; sub ia32_custom_init_attr { my $node = shift; my $name = shift; my $res = ""; + if(defined($node->{modified_flags})) { $res .= "\tset_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);\n"; } if(defined($node->{am})) { my $am = $node->{am}; - if($am eq "full,binary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_binary);"; - } elsif($am eq "full,unary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_unary);"; - } elsif($am eq "source,unary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_unary);"; + if($am eq "source,unary") { + $res .= "\tset_ia32_am_support(res, ia32_am_unary);"; } elsif($am eq "source,binary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_binary);"; - } elsif($am eq "dest,unary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);"; - } elsif($am eq "dest,binary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);"; - } elsif($am eq "dest,ternary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_ternary);"; - } elsif($am eq "source,ternary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_ternary);"; + $res .= "\tset_ia32_am_support(res, ia32_am_binary);"; } elsif($am eq "none") { # nothing to do } else { die("Invalid address mode '$am' specified on op $name"); } + if($am ne "none") { + if($node->{state} ne "exc_pinned" + and $node->{state} ne "pinned") { + die("AM nodes must have pinned or AM pinned state ($name)"); + } + } } return $res; } $custom_init_attr_func = \&ia32_custom_init_attr; %init_attr = ( - ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", - ia32_x87_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". - "\tinit_ia32_x87_attributes(res);", ia32_asm_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_ia32_x87_attributes(res);". "\tinit_ia32_asm_attributes(res);", + ia32_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", + ia32_condcode_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". + "\tinit_ia32_condcode_attributes(res, pnc);", + ia32_copyb_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". + "\tinit_ia32_copyb_attributes(res, size);", ia32_immediate_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". - "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);" + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". + "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);", + ia32_x87_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". + "\tinit_ia32_x87_attributes(res);", ); %compare_attr = ( - ia32_attr_t => "ia32_compare_nodes_attr", - ia32_x87_attr_t => "ia32_compare_x87_attr", ia32_asm_attr_t => "ia32_compare_asm_attr", + ia32_attr_t => "ia32_compare_nodes_attr", + ia32_condcode_attr_t => "ia32_compare_condcode_attr", + ia32_copyb_attr_t => "ia32_compare_copyb_attr", ia32_immediate_attr_t => "ia32_compare_immediate_attr", + ia32_x87_attr_t => "ia32_compare_x87_attr", ); %operands = ( ); -$mode_xmm = "mode_E"; -$mode_gp = "mode_Iu"; -$mode_flags = "mode_Iu"; -$mode_fpcw = "mode_fpcw"; -$status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ]; -$fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM", - "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ]; +$mode_xmm = "mode_E"; +$mode_gp = "mode_Iu"; +$mode_flags = "mode_Iu"; +$mode_fpcw = "mode_fpcw"; +$status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ]; +$status_flags_wo_cf = [ "PF", "AF", "ZF", "SF", "OF" ]; +$fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM", + "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ]; %nodes = ( @@ -313,6 +323,7 @@ Immediate => { reg_req => { out => [ "gp_NOREG" ] }, attr => "ir_entity *symconst, int symconst_sign, long offset", attr_type => "ia32_immediate_attr_t", + hash_func => "ia32_hash_Immediate", latency => 0, mode => $mode_gp, }, @@ -322,9 +333,14 @@ Asm => { arity => "variable", out_arity => "variable", attr_type => "ia32_asm_attr_t", - latency => 100, + attr => "ident *asm_text, const ia32_asm_reg_t *register_map", + init_attr => "attr->asm_text = asm_text;\n". + "\tattr->register_map = register_map;\n", + latency => 10, + modified_flags => 1, }, +# "allocates" a free register ProduceVal => { op_flags => "c", irn_flags => "R", @@ -351,41 +367,53 @@ ProduceVal => { Add => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5", "none", "flags" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "res", "flags", "M" ], emit => '. add%M %binop', - am => "full,binary", + am => "source,binary", units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, AddMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "val" ], emit => ". add%M %SI3, %AM", units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, AddMem8Bit => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "val" ], emit => ". add%M %SB3, %AM", units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, Adc => { - reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 in_r5" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right", "eflags" ], + outs => [ "res", "flags", "M" ], emit => '. adc%M %binop', - am => "full,binary", + am => "source,binary", units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -403,11 +431,13 @@ l_Adc => { Mul => { # we should not rematrialize this node. It produces 2 results and has - # very strict constrains - reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] }, - ins => [ "base", "index", "mem", "val_high", "val_low" ], + # very strict constraints + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], + out => [ "eax", "flags", "edx", "none" ] }, + ins => [ "base", "index", "mem", "left", "right" ], emit => '. mul%M %unop4', - outs => [ "EAX", "EDX", "M" ], + outs => [ "res_low", "flags", "res_high", "M" ], am => "source,binary", latency => 10, units => [ "GP" ], @@ -416,18 +446,22 @@ Mul => { l_Mul => { # we should not rematrialize this node. It produces 2 results and has - # very strict constrains + # very strict constraints op_flags => "C", cmp_attr => "return 1;", - outs => [ "EAX", "EDX", "M" ], + outs => [ "EAX", "flags", "EDX", "M" ], arity => 2 }, IMul => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, + state => "exc_pinned", + # TODO: adjust out requirements for the 3 operand form + # (no need for should_be_same then) + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], - emit => '. imul%M %binop', + outs => [ "res", "flags", "M" ], am => "source,binary", latency => 5, units => [ "GP" ], @@ -437,10 +471,12 @@ IMul => { IMul1OP => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] }, - ins => [ "base", "index", "mem", "val_high", "val_low" ], + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], + out => [ "eax", "edx", "none" ] }, + ins => [ "base", "index", "mem", "left", "right" ], emit => '. imul%M %unop4', - outs => [ "EAX", "EDX", "M" ], + outs => [ "res_low", "res_high", "M" ], am => "source,binary", latency => 5, units => [ "GP" ], @@ -448,103 +484,126 @@ IMul1OP => { }, l_IMul => { - # we should not rematrialize this node. It produces 2 results and has - # very strict constrains op_flags => "C", cmp_attr => "return 1;", - outs => [ "EAX", "EDX", "M" ], + outs => [ "res_low", "res_high", "M" ], arity => 2 }, And => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], - am => "full,binary", + outs => [ "res", "flags", "M" ], + op_modes => "commutative | am | immediate | mode_neutral", + am => "source,binary", emit => '. and%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, AndMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "val" ], emit => '. and%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, AndMem8Bit => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "val" ], emit => '. and%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, Or => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], - am => "full,binary", + outs => [ "res", "flags", "M" ], + am => "source,binary", emit => '. or%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, OrMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "val" ], emit => '. or%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, OrMem8Bit => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "val" ], emit => '. or%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, Xor => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], - am => "full,binary", + outs => [ "res", "flags", "M" ], + am => "source,binary", emit => '. xor%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, XorMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "val" ], emit => '. xor%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, XorMem8Bit => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "val" ], emit => '. xor%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -553,63 +612,76 @@ XorMem8Bit => { Sub => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4", "none", "flags" ] }, - ins => [ "base", "index", "mem", "left", "right" ], - am => "full,binary", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4", "flags", "none" ] }, + ins => [ "base", "index", "mem", "minuend", "subtrahend" ], + outs => [ "res", "flags", "M" ], + am => "source,binary", emit => '. sub%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, SubMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, - ins => [ "base", "index", "mem", "val" ], + ins => [ "base", "index", "mem", "subtrahend" ], emit => '. sub%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => 'mode_M', modified_flags => $status_flags }, SubMem8Bit => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] }, - ins => [ "base", "index", "mem", "val" ], + ins => [ "base", "index", "mem", "subtrahend" ], emit => '. sub%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => 'mode_M', modified_flags => $status_flags }, Sbb => { - reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 !in_r5" ] }, - ins => [ "base", "index", "mem", "left", "right", "eflags" ], - am => "full,binary", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], + out => [ "in_r4 !in_r5", "flags", "none" ] }, + ins => [ "base", "index", "mem", "minuend", "subtrahend", "eflags" ], + outs => [ "res", "flags", "M" ], + am => "source,binary", emit => '. sbb%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, l_Sub => { reg_req => { in => [ "none", "none" ], out => [ "none" ] }, - ins => [ "left", "right" ], + ins => [ "minuend", "subtrahend" ], }, l_Sbb => { reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] }, - ins => [ "left", "right", "eflags" ], + ins => [ "minuend", "subtrahend", "eflags" ], }, IDiv => { op_flags => "F|L", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "edx", "none" ] }, - ins => [ "base", "index", "mem", "left_low", "left_high", "right" ], - outs => [ "div_res", "mod_res", "M" ], - am => "source,ternary", - emit => ". idiv%M %unop5", + reg_req => { in => [ "gp", "gp", "none", "gp", "eax", "edx" ], + out => [ "eax", "flags", "none", "edx", "none" ] }, + ins => [ "base", "index", "mem", "divisor", "dividend_low", "dividend_high" ], + outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ], + am => "source,unary", + emit => ". idiv%M %unop3", latency => 25, units => [ "GP" ], modified_flags => $status_flags @@ -618,11 +690,12 @@ IDiv => { Div => { op_flags => "F|L", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "edx", "none" ] }, - ins => [ "base", "index", "mem", "left_low", "left_high", "right" ], - outs => [ "div_res", "mod_res", "M" ], - am => "source,ternary", - emit => ". div%M %unop5", + reg_req => { in => [ "gp", "gp", "none", "gp", "eax", "edx" ], + out => [ "eax", "flags", "none", "edx", "none" ] }, + ins => [ "base", "index", "mem", "divisor", "dividend_low", "dividend_high" ], + outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ], + am => "source,unary", + emit => ". div%M %unop3", latency => 25, units => [ "GP" ], modified_flags => $status_flags @@ -630,37 +703,42 @@ Div => { Shl => { irn_flags => "R", - reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] }, - ins => [ "left", "right" ], + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, + ins => [ "val", "count" ], + outs => [ "res", "flags" ], emit => '. shl %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, ShlMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "count" ], emit => '. shl%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, l_ShlDep => { - cmp_attr => "return 1;", - # value, cnt, dependency - arity => 3 + cmp_attr => "return 1;", + ins => [ "val", "count", "dep" ], + arity => 3 }, ShlD => { irn_flags => "R", - # see ShrD about the strange out constraint - reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "!in" ] }, - ins => [ "left_high", "left_low", "right" ], - emit => ". shld%M %SB2, %S1, %S0\n". - ". movl %S0, %D0", + reg_req => { in => [ "gp", "gp", "ecx" ], + out => [ "in_r1 !in_r2 !in_r3", "flags" ] }, + ins => [ "val_high", "val_low", "count" ], + outs => [ "res", "flags" ], + emit => ". shld%M %SB2, %S1, %D0", latency => 6, units => [ "GP" ], mode => $mode_gp, @@ -669,55 +747,48 @@ ShlD => { l_ShlD => { cmp_attr => "return 1;", + ins => [ "val_high", "val_low", "count" ], arity => 3, }, Shr => { irn_flags => "R", - reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] }, + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, ins => [ "val", "count" ], + outs => [ "res", "flags" ], emit => '. shr %SB1, %S0', units => [ "GP" ], mode => $mode_gp, + latency => 1, modified_flags => $status_flags }, ShrMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "count" ], emit => '. shr%M %SB3, %AM', units => [ "GP" ], mode => "mode_M", + latency => 1, modified_flags => $status_flags }, l_ShrDep => { cmp_attr => "return 1;", - # value, cnt, dependency + ins => [ "val", "count", "dep" ], arity => 3 }, ShrD => { - # What's going on with the out constraint here? We would like to write - # "in_r2" and be done. However in firm we only support should_be_same - # constraints at the moment. Which means they could be non-fullfilled in - # some cases. Now when all values happen to live through the node, out - # is ecx and in_r2 not ecx, then we're screwed. Because in this case we - # need a 4th Register. - # - # The best solution for this is extending the register allocator to support - # must_be_same constraints which create a copy when the in_r2 value - # lives through (this ensures that we have the 4th register in the cases - # when we need it and can always fix the situation). - # - # For now I'm doing this ultra ugly !in hack which allocates 4 registers - # and creates an extra mov - irn_flags => "R", - reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "!in" ] }, - ins => [ "left_high", "left_low", "right" ], - emit => ". shrd%M %SB2, %S1, %S0\n". - ". movl %S0, %D0", + irn_flags => "R", + reg_req => { in => [ "gp", "gp", "ecx" ], + out => [ "in_r1 !in_r2 !in_r3", "flags" ] }, + ins => [ "val_high", "val_low", "count" ], + outs => [ "res", "flags" ], + emit => ". shrd%M %SB2, %S1, %D0", latency => 6, units => [ "GP" ], mode => $mode_gp, @@ -726,71 +797,87 @@ ShrD => { l_ShrD => { cmp_attr => "return 1;", - arity => 3 + arity => 3, + ins => [ "val_high", "val_low", "count" ], }, Sar => { irn_flags => "R", - reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] }, + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, ins => [ "val", "count" ], + outs => [ "res", "flags" ], emit => '. sar %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, SarMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "count" ], emit => '. sar%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, l_SarDep => { cmp_attr => "return 1;", - # value, cnt, dependency + ins => [ "val", "count", "dep" ], arity => 3 }, Ror => { irn_flags => "R", - reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] }, + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, ins => [ "val", "count" ], + outs => [ "res", "flags" ], emit => '. ror %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, RorMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "count" ], emit => '. ror%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, Rol => { irn_flags => "R", - reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] }, + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, ins => [ "val", "count" ], + outs => [ "res", "flags" ], emit => '. rol %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, RolMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] }, ins => [ "base", "index", "mem", "count" ], emit => '. rol%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -799,101 +886,141 @@ RolMem => { Neg => { irn_flags => "R", - reg_req => { in => [ "gp" ], out => [ "in_r1" ] }, + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, emit => '. neg %S0', ins => [ "val" ], + outs => [ "res", "flags" ], units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, NegMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, ins => [ "base", "index", "mem" ], emit => '. neg%M %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, Minus64Bit => { irn_flags => "R", - reg_req => { in => [ "gp", "gp" ], out => [ "in_r1", "gp" ] }, + reg_req => { in => [ "gp", "gp" ], out => [ "in_r1", "in_r2" ] }, outs => [ "low_res", "high_res" ], units => [ "GP" ], + latency => 3, modified_flags => $status_flags }, -l_Neg => { - cmp_attr => "return 1;", - arity => 1, -}, - Inc => { irn_flags => "R", - reg_req => { in => [ "gp" ], out => [ "in_r1" ] }, + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, + ins => [ "val" ], + outs => [ "res", "flags" ], emit => '. inc %S0', units => [ "GP" ], mode => $mode_gp, - modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] + latency => 1, + modified_flags => $status_flags_wo_cf }, IncMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, ins => [ "base", "index", "mem" ], emit => '. inc%M %AM', units => [ "GP" ], mode => "mode_M", - modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] + latency => 1, + modified_flags => $status_flags_wo_cf }, Dec => { irn_flags => "R", - reg_req => { in => [ "gp" ], out => [ "in_r1" ] }, + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, + ins => [ "val" ], + outs => [ "res", "flags" ], emit => '. dec %S0', units => [ "GP" ], mode => $mode_gp, - modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] + latency => 1, + modified_flags => $status_flags_wo_cf }, DecMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, ins => [ "base", "index", "mem" ], emit => '. dec%M %AM', units => [ "GP" ], mode => "mode_M", - modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] + latency => 1, + modified_flags => $status_flags_wo_cf }, Not => { irn_flags => "R", - reg_req => { in => [ "gp" ], out => [ "in_r1" ] }, + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, ins => [ "val" ], + outs => [ "res", "flags" ], emit => '. not %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, + # no flags modified }, NotMem => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, ins => [ "base", "index", "mem" ], emit => '. not%M %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", + # no flags modified +}, + +Cmc => { + reg_req => { in => [ "flags" ], out => [ "flags" ] }, + emit => '.cmc', + units => [ "GP" ], + latency => 1, + mode => $mode_flags, + modified_flags => $status_flags +}, + +Stc => { + reg_req => { out => [ "flags" ] }, + emit => '.stc', + units => [ "GP" ], + latency => 1, + mode => $mode_flags, + modified_flags => $status_flags }, # other operations Cmp => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "flags", "none", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], - outs => [ "eflags" ], + outs => [ "eflags", "unused", "M" ], am => "source,binary", emit => '. cmp%M %binop', attr => "int ins_permuted, int cmp_unsigned", @@ -907,6 +1034,7 @@ Cmp => { Cmp8Bit => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] }, ins => [ "base", "index", "mem", "left", "right" ], outs => [ "eflags" ], @@ -923,6 +1051,7 @@ Cmp8Bit => { Test => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] }, ins => [ "base", "index", "mem", "left", "right" ], outs => [ "eflags" ], @@ -939,6 +1068,7 @@ Test => { Test8Bit => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] }, ins => [ "base", "index", "mem", "left", "right" ], outs => [ "eflags" ], @@ -957,24 +1087,42 @@ Set => { #irn_flags => "R", reg_req => { in => [ "eflags" ], out => [ "eax ebx ecx edx" ] }, ins => [ "eflags" ], - attr => "pn_Cmp pnc", - init_attr => "attr->pn_code = pnc;\nset_ia32_ls_mode(res, mode_Bu);\n", + attr_type => "ia32_condcode_attr_t", + attr => "pn_Cmp pnc, int ins_permuted", + init_attr => "attr->attr.data.ins_permuted = ins_permuted;\n". + "\tset_ia32_ls_mode(res, mode_Bu);\n", emit => '. set%CMP0 %DB0', latency => 1, units => [ "GP" ], mode => $mode_gp, }, +SetMem => { + #irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eflags" ], out => [ "none" ] }, + ins => [ "base", "index", "mem","eflags" ], + attr_type => "ia32_condcode_attr_t", + attr => "pn_Cmp pnc, int ins_permuted", + init_attr => "attr->attr.data.ins_permuted = ins_permuted;\n". + "\tset_ia32_ls_mode(res, mode_Bu);\n", + emit => '. set%CMP3 %AM', + latency => 1, + units => [ "GP" ], + mode => 'mode_M', +}, + CMov => { #irn_flags => "R", # (note: leave the false,true order intact to make it compatible with other # ia32_binary ops) + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "eflags" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "val_false", "val_true", "eflags" ], am => "source,binary", - attr => "int ins_permuted, pn_Cmp pn_code", - init_attr => "attr->pn_code = pn_code;\n". - "attr->data.ins_permuted = ins_permuted;", + attr_type => "ia32_condcode_attr_t", + attr => "int ins_permuted, pn_Cmp pnc", + init_attr => "attr->attr.data.ins_permuted = ins_permuted;", latency => 1, units => [ "GP" ], mode => $mode_gp, @@ -986,8 +1134,8 @@ Jcc => { reg_req => { in => [ "eflags" ], out => [ "none", "none" ] }, ins => [ "eflags" ], outs => [ "false", "true" ], + attr_type => "ia32_condcode_attr_t", attr => "pn_Cmp pnc", - init_attr => "attr->pn_code = pnc;", latency => 2, units => [ "BRANCH" ], }, @@ -996,17 +1144,22 @@ SwitchJmp => { state => "pinned", op_flags => "L|X|Y", reg_req => { in => [ "gp" ], out => [ "none" ] }, + mode => "mode_T", + attr_type => "ia32_condcode_attr_t", + attr => "long pnc", latency => 3, units => [ "BRANCH" ], - mode => "mode_T", - modified_flags => $status_flags + modified_flags => $status_flags, }, IJmp => { state => "pinned", op_flags => "X", - reg_req => { in => [ "gp" ] }, - emit => '. jmp *%S0', + reg_req => { in => [ "gp", "gp", "none", "gp" ] }, + ins => [ "base", "index", "mem", "target" ], + am => "source,unary", + emit => '. jmp *%unop3', + latency => 1, units => [ "BRANCH" ], mode => "mode_X", }, @@ -1018,70 +1171,84 @@ Const => { units => [ "GP" ], attr => "ir_entity *symconst, int symconst_sign, long offset", attr_type => "ia32_immediate_attr_t", + latency => 1, mode => $mode_gp, -# depends on the const and is set in ia32_transform -# modified_flags => $status_flags +}, + +GetEIP => { + op_flags => "c", + reg_req => { out => [ "gp" ] }, + units => [ "GP" ], + latency => 5, + mode => $mode_gp, + modified_flags => $status_flags, }, Unknown_GP => { state => "pinned", - op_flags => "c", + op_flags => "c|NB", irn_flags => "I", reg_req => { out => [ "gp_UKNWN" ] }, units => [], emit => "", + latency => 0, mode => $mode_gp }, Unknown_VFP => { state => "pinned", - op_flags => "c", + op_flags => "c|NB", irn_flags => "I", reg_req => { out => [ "vfp_UKNWN" ] }, units => [], emit => "", mode => "mode_E", + latency => 0, attr_type => "ia32_x87_attr_t", }, Unknown_XMM => { state => "pinned", - op_flags => "c", + op_flags => "c|NB", irn_flags => "I", reg_req => { out => [ "xmm_UKNWN" ] }, units => [], emit => "", - mode => "mode_E" + latency => 0, + mode => $mode_xmm }, NoReg_GP => { state => "pinned", - op_flags => "c", + op_flags => "c|NB|NI", irn_flags => "I", reg_req => { out => [ "gp_NOREG" ] }, units => [], emit => "", + latency => 0, mode => $mode_gp }, NoReg_VFP => { state => "pinned", - op_flags => "c", + op_flags => "c|NB|NI", irn_flags => "I", reg_req => { out => [ "vfp_NOREG" ] }, units => [], emit => "", mode => "mode_E", + latency => 0, attr_type => "ia32_x87_attr_t", }, NoReg_XMM => { state => "pinned", - op_flags => "c", + op_flags => "c|NB|NI", irn_flags => "I", reg_req => { out => [ "xmm_NOREG" ] }, units => [], emit => "", + latency => 0, mode => "mode_E" }, @@ -1119,11 +1286,22 @@ FnstCW => { units => [ "GP" ], }, +FnstCWNOP => { + op_flags => "L|F", + state => "pinned", + reg_req => { in => [ "fp_cw" ], out => [ "none" ] }, + ins => [ "fpcw" ], + latency => 0, + emit => "", + mode => "mode_M", +}, + Cltd => { # we should not rematrialize this node. It has very strict constraints. reg_req => { in => [ "eax", "edx" ], out => [ "edx" ] }, - ins => [ "val", "globbered" ], + ins => [ "val", "clobbered" ], emit => '. cltd', + latency => 1, mode => $mode_gp, units => [ "GP" ], }, @@ -1136,34 +1314,20 @@ Cltd => { Load => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] }, + reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none", "none" ] }, ins => [ "base", "index", "mem" ], - outs => [ "res", "M" ], + outs => [ "res", "M", "X_exc" ], latency => 0, emit => ". mov%SE%ME%.l %AM, %D0", units => [ "GP" ], }, -l_Load => { - op_flags => "L|F", - cmp_attr => "return 1;", - outs => [ "res", "M" ], - arity => 2, -}, - -l_Store => { - op_flags => "L|F", - cmp_attr => "return 1;", - state => "exc_pinned", - arity => 3, - mode => "mode_M", -}, - Store => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none", "none" ] }, ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], emit => '. mov%M %SI3, %AM', latency => 2, units => [ "GP" ], @@ -1173,8 +1337,9 @@ Store => { Store8Bit => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none" ] }, + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none", "none" ] }, ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], emit => '. mov%M %SB3, %AM', latency => 2, units => [ "GP" ], @@ -1189,27 +1354,38 @@ Lea => { latency => 2, units => [ "GP" ], mode => $mode_gp, -# well this isn't true for Lea, but we often transform Lea back to Add, Inc -# or Dec, so we set the flag +# lea doesn't modify the flags, but setting this seems advantageous since it +# increases chances that the Lea is transformed back to an Add modified_flags => 1, }, Push => { - reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "esp", "none" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "esp" ], out => [ "esp", "none" ] }, ins => [ "base", "index", "mem", "val", "stack" ], - emit => '. push%M %unop4', + emit => '. push%M %unop3', outs => [ "stack:I|S", "M" ], - am => "source,binary", + am => "source,unary", latency => 2, units => [ "GP" ], }, Pop => { - reg_req => { in => [ "gp", "gp", "none", "esp" ], out => [ "esp", "gp", "none" ] }, - emit => '. pop%M %DAM1', - outs => [ "stack:I|S", "res", "M" ], + state => "exc_pinned", + reg_req => { in => [ "none", "esp" ], out => [ "gp", "none", "none", "esp" ] }, + ins => [ "mem", "stack" ], + outs => [ "res", "M", "unused", "stack:I|S" ], + emit => '. pop%M %D0', + latency => 3, # Pop is more expensive than Push on Athlon + units => [ "GP" ], +}, + +PopMem => { + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "esp" ], out => [ "none", "none", "none", "esp" ] }, ins => [ "base", "index", "mem", "stack" ], - am => "dest,unary", + outs => [ "unused0", "M", "unused1", "stack:I|S" ], + emit => '. pop%M %AM', latency => 3, # Pop is more expensive than Push on Athlon units => [ "GP" ], }, @@ -1223,7 +1399,7 @@ Enter => { }, Leave => { - reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] }, + reg_req => { in => [ "ebp" ], out => [ "ebp", "esp" ] }, emit => '. leave', outs => [ "frame:I", "stack:I|S" ], latency => 3, @@ -1237,7 +1413,8 @@ AddSP => { ins => [ "base", "index", "mem", "stack", "size" ], am => "source,binary", emit => '. addl %binop', - outs => [ "stack:S", "M" ], + latency => 1, + outs => [ "stack:I|S", "M" ], units => [ "GP" ], modified_flags => $status_flags }, @@ -1250,17 +1427,38 @@ SubSP => { am => "source,binary", emit => ". subl %binop\n". ". movl %%esp, %D1", + latency => 2, outs => [ "stack:I|S", "addr", "M" ], units => [ "GP" ], modified_flags => $status_flags }, +RepPrefix => { + op_flags => "K", + state => "pinned", + mode => "mode_M", + emit => ". rep", + latency => 0, +}, + LdTls => { irn_flags => "R", reg_req => { out => [ "gp" ] }, units => [ "GP" ], + latency => 1, }, +Bt => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp" ], out => [ "flags" ] }, + ins => [ "left", "right" ], + emit => '. bt%M %S1, %S0', + units => [ "GP" ], + latency => 1, + mode => $mode_flags, + modified_flags => $status_flags # only CF is set, but the other flags are undefined +}, #-----------------------------------------------------------------------------# # _____ _____ ______ __ _ _ _ # @@ -1271,121 +1469,192 @@ LdTls => { # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # #-----------------------------------------------------------------------------# +# produces a 0/+0.0 xZero => { irn_flags => "R", reg_req => { out => [ "xmm" ] }, emit => '. xorp%XSD %D0, %D0', latency => 3, units => [ "SSE" ], - mode => "mode_E", + mode => $mode_xmm +}, + +xPzero => { + irn_flags => "R", + reg_req => { out => [ "xmm" ] }, + emit => '. pxor %D0, %D0', + latency => 3, + units => [ "SSE" ], + mode => $mode_xmm +}, + +# produces all 1 bits +xAllOnes => { + irn_flags => "R", + reg_req => { out => [ "xmm" ] }, + emit => '. pcmpeqb %D0, %D0', + latency => 3, + units => [ "SSE" ], + mode => $mode_xmm +}, + +# integer shift left, dword +xPslld => { + irn_flags => "R", + reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] }, + emit => '. pslld %SI1, %D0', + latency => 3, + units => [ "SSE" ], + mode => $mode_xmm +}, + +# integer shift left, qword +xPsllq => { + irn_flags => "R", + reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] }, + emit => '. psllq %SI1, %D0', + latency => 3, + units => [ "SSE" ], + mode => $mode_xmm +}, + +# integer shift right, dword +xPsrld => { + irn_flags => "R", + reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] }, + emit => '. psrld %SI1, %D0', + latency => 1, + units => [ "SSE" ], + mode => $mode_xmm +}, + +# mov from integer to SSE register +xMovd => { + irn_flags => "R", + reg_req => { in => [ "gp" ], out => [ "xmm" ] }, + emit => '. movd %S0, %D0', + latency => 1, + units => [ "SSE" ], + mode => $mode_xmm }, # commutative operations xAdd => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "source,binary", emit => '. add%XXM %binop', latency => 4, units => [ "SSE" ], - mode => "mode_E", + mode => $mode_xmm }, xMul => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "source,binary", emit => '. mul%XXM %binop', latency => 4, units => [ "SSE" ], - mode => "mode_E", + mode => $mode_xmm }, xMax => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "source,binary", emit => '. max%XXM %binop', latency => 2, units => [ "SSE" ], - mode => "mode_E", + mode => $mode_xmm }, xMin => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "source,binary", emit => '. min%XXM %binop', latency => 2, units => [ "SSE" ], - mode => "mode_E", + mode => $mode_xmm }, xAnd => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "source,binary", emit => '. andp%XSD %binop', latency => 3, units => [ "SSE" ], - mode => "mode_E", + mode => $mode_xmm }, xOr => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "source,binary", emit => '. orp%XSD %binop', + latency => 3, units => [ "SSE" ], - mode => "mode_E", + mode => $mode_xmm }, xXor => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "source,binary", emit => '. xorp%XSD %binop', latency => 3, units => [ "SSE" ], - mode => "mode_E", + mode => $mode_xmm }, # not commutative operations xAndNot => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5" ] }, ins => [ "base", "index", "mem", "left", "right" ], am => "source,binary", emit => '. andnp%XSD %binop', latency => 3, units => [ "SSE" ], - mode => "mode_E", + mode => $mode_xmm }, xSub => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] }, - ins => [ "base", "index", "mem", "left", "right" ], + ins => [ "base", "index", "mem", "minuend", "subtrahend" ], am => "source,binary", emit => '. sub%XXM %binop', latency => 4, units => [ "SSE" ], - mode => "mode_E", + mode => $mode_xmm }, xDiv => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5", "none" ] }, - ins => [ "base", "index", "mem", "left", "right" ], + ins => [ "base", "index", "mem", "dividend", "divisor" ], am => "source,binary", outs => [ "res", "M" ], emit => '. div%XXM %binop', @@ -1397,6 +1666,7 @@ xDiv => { Ucomi => { irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "eflags" ] }, ins => [ "base", "index", "mem", "left", "right" ], outs => [ "flags" ], @@ -1415,12 +1685,12 @@ Ucomi => { xLoad => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] }, + reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none", "none" ] }, ins => [ "base", "index", "mem" ], + outs => [ "res", "M", "X_exc" ], emit => '. mov%XXM %AM, %D0', attr => "ir_mode *load_mode", init_attr => "attr->ls_mode = load_mode;", - outs => [ "res", "M" ], latency => 0, units => [ "SSE" ], }, @@ -1428,8 +1698,9 @@ xLoad => { xStore => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "xmm" ] }, + reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "none", "none" ] }, ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], emit => '. mov%XXM %S3, %AM', latency => 0, units => [ "SSE" ], @@ -1449,6 +1720,7 @@ xStoreSimple => { CvtSI2SS => { op_flags => "L|F", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] }, ins => [ "base", "index", "mem", "val" ], am => "source,unary", @@ -1460,6 +1732,7 @@ CvtSI2SS => { CvtSI2SD => { op_flags => "L|F", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] }, ins => [ "base", "index", "mem", "val" ], am => "source,unary", @@ -1470,36 +1743,43 @@ CvtSI2SD => { }, -l_X87toSSE => { +l_LLtoFloat => { op_flags => "L|F", cmp_attr => "return 1;", - arity => 3, + ins => [ "val_high", "val_low" ], }, -l_SSEtoX87 => { +l_FloattoLL => { op_flags => "L|F", cmp_attr => "return 1;", - arity => 3, + ins => [ "val" ], + outs => [ "res_high", "res_low" ], }, # CopyB CopyB => { - op_flags => "F|H", - state => "pinned", - reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] }, - outs => [ "DST", "SRC", "CNT", "M" ], - units => [ "GP" ], + op_flags => "F|H", + state => "pinned", + reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] }, + outs => [ "DST", "SRC", "CNT", "M" ], + attr_type => "ia32_copyb_attr_t", + attr => "unsigned size", + units => [ "GP" ], + latency => 3, # we don't care about this flag, so no need to mark this node # modified_flags => [ "DF" ] }, CopyB_i => { - op_flags => "F|H", - state => "pinned", - reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] }, - outs => [ "DST", "SRC", "M" ], - units => [ "GP" ], + op_flags => "F|H", + state => "pinned", + reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] }, + outs => [ "DST", "SRC", "M" ], + attr_type => "ia32_copyb_attr_t", + attr => "unsigned size", + units => [ "GP" ], + latency => 3, # we don't care about this flag, so no need to mark this node # modified_flags => [ "DF" ] }, @@ -1512,6 +1792,7 @@ Conv_I2I => { ins => [ "base", "index", "mem", "val" ], am => "source,unary", units => [ "GP" ], + latency => 1, attr => "ir_mode *smaller_mode", init_attr => "attr->ls_mode = smaller_mode;", mode => $mode_gp, @@ -1523,36 +1804,40 @@ Conv_I2I8Bit => { ins => [ "base", "index", "mem", "val" ], am => "source,unary", units => [ "GP" ], + latency => 1, attr => "ir_mode *smaller_mode", init_attr => "attr->ls_mode = smaller_mode;", mode => $mode_gp, }, Conv_I2FP => { - reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm", "none" ] }, - ins => [ "base", "index", "mem", "val" ], - am => "source,unary", - latency => 10, - units => [ "SSE" ], - mode => "mode_E", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + am => "source,unary", + latency => 10, + units => [ "SSE" ], + mode => $mode_xmm, }, Conv_FP2I => { - reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "gp", "none" ] }, - ins => [ "base", "index", "mem", "val" ], - am => "source,unary", - latency => 10, - units => [ "SSE" ], - mode => $mode_gp, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "gp", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + am => "source,unary", + latency => 10, + units => [ "SSE" ], + mode => $mode_gp, }, Conv_FP2FP => { - reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "xmm", "none" ] }, - ins => [ "base", "index", "mem", "val" ], - am => "source,unary", - latency => 8, - units => [ "SSE" ], - mode => "mode_E", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "xmm", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + am => "source,unary", + latency => 8, + units => [ "SSE" ], + mode => $mode_xmm, }, #----------------------------------------------------------# @@ -1569,11 +1854,12 @@ Conv_FP2FP => { # |_| |_|\___/ \__,_|\___||___/ # #----------------------------------------------------------# -# spilling disabled for all float nodes for now, because the fpcw handler -# runs before spilling and we might end up with wrong fpcw then +# rematerialisation disabled for all float nodes for now, because the fpcw +# handler runs before spilling and we might end up with wrong fpcw then vfadd => { # irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] }, ins => [ "base", "index", "mem", "left", "right", "fpcw" ], am => "source,binary", @@ -1585,6 +1871,7 @@ vfadd => { vfmul => { # irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] }, ins => [ "base", "index", "mem", "left", "right", "fpcw" ], am => "source,binary", @@ -1596,8 +1883,9 @@ vfmul => { vfsub => { # irn_flags => "R", + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] }, - ins => [ "base", "index", "mem", "left", "right", "fpcw" ], + ins => [ "base", "index", "mem", "minuend", "subtrahend", "fpcw" ], am => "source,binary", latency => 4, units => [ "VFP" ], @@ -1606,8 +1894,9 @@ vfsub => { }, vfdiv => { + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp", "none" ] }, - ins => [ "base", "index", "mem", "left", "right", "fpcw" ], + ins => [ "base", "index", "mem", "dividend", "divisor", "fpcw" ], am => "source,binary", outs => [ "res", "M" ], latency => 20, @@ -1647,11 +1936,12 @@ vfchs => { # virtual Load and Store vfld => { + irn_flags => "R", op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] }, + reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none", "none" ] }, ins => [ "base", "index", "mem" ], - outs => [ "res", "M" ], + outs => [ "res", "M", "X_exc" ], attr => "ir_mode *load_mode", init_attr => "attr->attr.ls_mode = load_mode;", latency => 2, @@ -1660,10 +1950,12 @@ vfld => { }, vfst => { + irn_flags => "R", op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "vfp" ] }, + reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "none", "none" ] }, ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], attr => "ir_mode *store_mode", init_attr => "attr->attr.ls_mode = store_mode;", latency => 2, @@ -1684,12 +1976,6 @@ vfild => { attr_type => "ia32_x87_attr_t", }, -l_vfild => { - cmp_attr => "return 1;", - outs => [ "res", "M" ], - arity => 2, -}, - vfist => { state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none", "vfp", "fpcw" ] }, @@ -1700,11 +1986,15 @@ vfist => { attr_type => "ia32_x87_attr_t", }, -l_vfist => { - cmp_attr => "return 1;", +# SSE3 fisttp instruction +vfisttp => { state => "exc_pinned", - arity => 3, - mode => "mode_M", + reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "in_r4", "none" ]}, + ins => [ "base", "index", "mem", "val" ], + outs => [ "res", "M" ], + latency => 4, + units => [ "VFP" ], + attr_type => "ia32_x87_attr_t", }, @@ -1822,6 +2112,7 @@ Sahf => { ins => [ "val" ], outs => [ "flags" ], emit => '. sahf', + latency => 1, units => [ "GP" ], mode => $mode_flags, }, @@ -1838,130 +2129,143 @@ Sahf => { # are swapped, we work this around in the emitter... fadd => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fadd%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, faddp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. faddp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fmul => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fmul%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fmulp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fmulp%XM %x87_binop',, + latency => 4, attr_type => "ia32_x87_attr_t", }, fsub => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fsub%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fsubp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, # see note about gas bugs emit => '. fsubrp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fsubr => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", irn_flags => "R", reg_req => { }, emit => '. fsubr%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fsubrp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", irn_flags => "R", reg_req => { }, # see note about gas bugs emit => '. fsubp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fprem => { - op_flags => "R", rd_constructor => "NONE", reg_req => { }, emit => '. fprem1', + latency => 20, attr_type => "ia32_x87_attr_t", }, # this node is just here, to keep the simulator running # we can omit this when a fprem simulation function exists fpremp => { - op_flags => "R", rd_constructor => "NONE", reg_req => { }, - emit => '. fprem1', + emit => '. fprem1\n'. + '. fstp %X0', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdiv => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fdiv%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdivp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, # see note about gas bugs emit => '. fdivrp%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdivr => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fdivr%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdivrp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, # see note about gas bugs emit => '. fdivp%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fabs => { - op_flags => "R", rd_constructor => "NONE", reg_req => { }, emit => '. fabs', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1970,6 +2274,7 @@ fchs => { rd_constructor => "NONE", reg_req => { }, emit => '. fchs', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1982,6 +2287,7 @@ fld => { reg_req => { }, emit => '. fld%XM %AM', attr_type => "ia32_x87_attr_t", + latency => 2, }, fst => { @@ -1992,6 +2298,7 @@ fst => { emit => '. fst%XM %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, fstp => { @@ -2002,36 +2309,49 @@ fstp => { emit => '. fstp%XM %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, # Conversions fild => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fild%M %AM', attr_type => "ia32_x87_attr_t", + latency => 2, }, fist => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fist%M %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, fistp => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fistp%M %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, +}, + +# SSE3 firsttp instruction +fisttp => { + state => "exc_pinned", + rd_constructor => "NONE", + reg_req => { }, + emit => '. fisttp%M %AM', + mode => "mode_M", + attr_type => "ia32_x87_attr_t", + latency => 2, }, # constants @@ -2042,6 +2362,7 @@ fldz => { reg_req => { out => [ "vfp" ] }, emit => '. fldz', attr_type => "ia32_x87_attr_t", + latency => 2, }, fld1 => { @@ -2050,6 +2371,7 @@ fld1 => { reg_req => { out => [ "vfp" ] }, emit => '. fld1', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldpi => { @@ -2058,6 +2380,7 @@ fldpi => { reg_req => { out => [ "vfp" ] }, emit => '. fldpi', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldln2 => { @@ -2066,6 +2389,7 @@ fldln2 => { reg_req => { out => [ "vfp" ] }, emit => '. fldln2', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldlg2 => { @@ -2074,6 +2398,7 @@ fldlg2 => { reg_req => { out => [ "vfp" ] }, emit => '. fldlg2', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldl2t => { @@ -2082,6 +2407,7 @@ fldl2t => { reg_req => { out => [ "vfp" ] }, emit => '. fldll2t', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldl2e => { @@ -2090,6 +2416,7 @@ fldl2e => { reg_req => { out => [ "vfp" ] }, emit => '. fldl2e', attr_type => "ia32_x87_attr_t", + latency => 2, }, # fxch, fpush, fpop @@ -2103,6 +2430,7 @@ fxch => { emit => '. fxch %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, fpush => { @@ -2112,14 +2440,15 @@ fpush => { emit => '. fld %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, fpushCopy => { - op_flags => "R", reg_req => { in => [ "vfp"], out => [ "vfp" ] }, cmp_attr => "return 1;", emit => '. fld %X0', attr_type => "ia32_x87_attr_t", + latency => 1, }, fpop => { @@ -2129,6 +2458,7 @@ fpop => { emit => '. fstp %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, ffreep => { @@ -2138,6 +2468,7 @@ ffreep => { emit => '. ffreep %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, emms => { @@ -2147,6 +2478,7 @@ emms => { emit => '. emms', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 3, }, femms => { @@ -2156,6 +2488,7 @@ femms => { emit => '. femms', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 3, }, # compare @@ -2163,41 +2496,47 @@ femms => { FucomFnstsw => { reg_req => { }, emit => ". fucom %X1\n". - ". fnstsw", + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, FucompFnstsw => { reg_req => { }, emit => ". fucomp %X1\n". - ". fnstsw", + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, FucomppFnstsw => { reg_req => { }, emit => ". fucompp\n". - ". fnstsw", + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, Fucomi => { reg_req => { }, emit => '. fucomi %X1', attr_type => "ia32_x87_attr_t", + latency => 1, }, Fucompi => { reg_req => { }, emit => '. fucompi %X1', attr_type => "ia32_x87_attr_t", + latency => 1, }, FtstFnstsw => { reg_req => { }, emit => ". ftst\n". - ". fnstsw", + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, @@ -2220,6 +2559,7 @@ xxLoad => { emit => '. movdqu %D0, %AM', outs => [ "res", "M" ], units => [ "SSE" ], + latency => 1, }, xxStore => { @@ -2229,6 +2569,7 @@ xxStore => { ins => [ "base", "index", "mem", "val" ], emit => '. movdqu %binop', units => [ "SSE" ], + latency => 1, mode => "mode_M", }, @@ -2241,3 +2582,28 @@ unless ($return = do $my_script_name) { warn "couldn't do $my_script_name: $!" unless defined $return; warn "couldn't run $my_script_name" unless $return; } + +# Transform some attributes +foreach my $op (keys(%nodes)) { + my $node = $nodes{$op}; + my $op_attr_init = $node->{op_attr_init}; + + if(defined($op_attr_init)) { + $op_attr_init .= "\n\t"; + } else { + $op_attr_init = ""; + } + + if(!defined($node->{latency})) { + if($op =~ m/^l_/) { + $node->{latency} = 0; + } else { + die("Latency missing for op $op"); + } + } + $op_attr_init .= "attr->latency = ".$node->{latency} . ";"; + + $node->{op_attr_init} = $op_attr_init; +} + +print "";