X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=f3fe10800f96affe1199f573d989a29c4d709a89;hb=379fd05b0fb269dd9b9105810de1ce565b18e446;hp=9cc0454fe439cc451b6c940f1186906961dc134b;hpb=f56ec028e3585aa134de4c4119a52b9a88de56fe;p=libfirm diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index 9cc0454fe..f3fe10800 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -32,7 +32,6 @@ $arch = "ia32"; # attr => "attitional attribute arguments for constructor" # init_attr => "emit attribute initialization template" # rd_constructor => "c source code which constructs an ir_node" -# latency => "latency of this operation (can be float)" # attr_type => "name of the attribute struct", # }, # @@ -96,8 +95,6 @@ $arch = "ia32"; # # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3 # -# latency: the latency of the operation, default is 1 -# # register types: # 0 - no special type @@ -110,10 +107,10 @@ $arch = "ia32"; # NOTE: Last entry of each class is the largest Firm-Mode a register can hold %reg_classes = ( gp => [ - { name => "eax", type => 1 }, { name => "edx", type => 1 }, - { name => "ebx", type => 2 }, { name => "ecx", type => 1 }, + { name => "eax", type => 1 }, + { name => "ebx", type => 2 }, { name => "esi", type => 2 }, { name => "edi", type => 2 }, { name => "ebp", type => 2 }, @@ -131,7 +128,7 @@ $arch = "ia32"; { name => "mm5", type => 4 }, { name => "mm6", type => 4 }, { name => "mm7", type => 4 }, - { mode => "mode_E" } + { mode => "mode_E", flags => "manual_ra" } ], xmm => [ { name => "xmm0", type => 1 }, @@ -168,72 +165,18 @@ $arch = "ia32"; { name => "st5", realname => "st(5)", type => 4 }, { name => "st6", realname => "st(6)", type => 4 }, { name => "st7", realname => "st(7)", type => 4 }, - { mode => "mode_E" } + { mode => "mode_E", flags => "manual_ra" } ], fp_cw => [ # the floating point control word - { name => "fpcw", type => 4 | 32}, - { mode => "mode_fpcw" } + { name => "fpcw", type => 4|32 }, + { mode => "mode_fpcw", flags => "manual_ra|state" } ], flags => [ - { name => "eflags", type => 4 }, - { mode => "mode_Iu" } - ], - fp_sw => [ - { name => "fpsw", type => 4 }, - { mode => "mode_Hu" } + { name => "eflags", type => 0 }, + { mode => "mode_Iu", flags => "manual_ra" } ], ); # %reg_classes -%flags = ( - CF => { reg => "eflags", bit => 0 }, - PF => { reg => "eflags", bit => 2 }, - AF => { reg => "eflags", bit => 4 }, - ZF => { reg => "eflags", bit => 6 }, - SF => { reg => "eflags", bit => 7 }, - TF => { reg => "eflags", bit => 8 }, - IF => { reg => "eflags", bit => 9 }, - DF => { reg => "eflags", bit => 10 }, - OF => { reg => "eflags", bit => 11 }, - IOPL0 => { reg => "eflags", bit => 12 }, - IOPL1 => { reg => "eflags", bit => 13 }, - NT => { reg => "eflags", bit => 14 }, - RF => { reg => "eflags", bit => 16 }, - VM => { reg => "eflags", bit => 17 }, - AC => { reg => "eflags", bit => 18 }, - VIF => { reg => "eflags", bit => 19 }, - VIP => { reg => "eflags", bit => 20 }, - ID => { reg => "eflags", bit => 21 }, - - FP_IE => { reg => "fpsw", bit => 0 }, - FP_DE => { reg => "fpsw", bit => 1 }, - FP_ZE => { reg => "fpsw", bit => 2 }, - FP_OE => { reg => "fpsw", bit => 3 }, - FP_UE => { reg => "fpsw", bit => 4 }, - FP_PE => { reg => "fpsw", bit => 5 }, - FP_SF => { reg => "fpsw", bit => 6 }, - FP_ES => { reg => "fpsw", bit => 7 }, - FP_C0 => { reg => "fpsw", bit => 8 }, - FP_C1 => { reg => "fpsw", bit => 9 }, - FP_C2 => { reg => "fpsw", bit => 10 }, - FP_TOP0 => { reg => "fpsw", bit => 11 }, - FP_TOP1 => { reg => "fpsw", bit => 12 }, - FP_TOP2 => { reg => "fpsw", bit => 13 }, - FP_C3 => { reg => "fpsw", bit => 14 }, - FP_B => { reg => "fpsw", bit => 15 }, - - FP_IM => { reg => "fpcw", bit => 0 }, - FP_DM => { reg => "fpcw", bit => 1 }, - FP_ZM => { reg => "fpcw", bit => 2 }, - FP_OM => { reg => "fpcw", bit => 3 }, - FP_UM => { reg => "fpcw", bit => 4 }, - FP_PM => { reg => "fpcw", bit => 5 }, - FP_PC0 => { reg => "fpcw", bit => 8 }, - FP_PC1 => { reg => "fpcw", bit => 9 }, - FP_RC0 => { reg => "fpcw", bit => 10 }, - FP_RC1 => { reg => "fpcw", bit => 11 }, - FP_X => { reg => "fpcw", bit => 12 } -); # %flags - %cpu = ( GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ], SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ], @@ -247,33 +190,35 @@ $arch = "ia32"; ); # vliw %emit_templates = ( - S0 => "${arch}_emit_source_register(env, node, 0);", - S1 => "${arch}_emit_source_register(env, node, 1);", - S2 => "${arch}_emit_source_register(env, node, 2);", - S3 => "${arch}_emit_source_register(env, node, 3);", - S4 => "${arch}_emit_source_register(env, node, 4);", - S5 => "${arch}_emit_source_register(env, node, 5);", - D0 => "${arch}_emit_dest_register(env, node, 0);", - D1 => "${arch}_emit_dest_register(env, node, 1);", - D2 => "${arch}_emit_dest_register(env, node, 2);", - D3 => "${arch}_emit_dest_register(env, node, 3);", - D4 => "${arch}_emit_dest_register(env, node, 4);", - D5 => "${arch}_emit_dest_register(env, node, 5);", - X0 => "${arch}_emit_x87_name(env, node, 0);", - X1 => "${arch}_emit_x87_name(env, node, 1);", - X2 => "${arch}_emit_x87_name(env, node, 2);", - C => "${arch}_emit_immediate(env, node);", - SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));", + S0 => "${arch}_emit_source_register(node, 0);", + S1 => "${arch}_emit_source_register(node, 1);", + S2 => "${arch}_emit_source_register(node, 2);", + S3 => "${arch}_emit_source_register(node, 3);", + SB1 => "${arch}_emit_8bit_source_register_or_immediate(node, 1);", + SB2 => "${arch}_emit_8bit_source_register_or_immediate(node, 2);", + SB3 => "${arch}_emit_8bit_source_register_or_immediate(node, 3);", + SI3 => "${arch}_emit_source_register_or_immediate(node, 3);", + D0 => "${arch}_emit_dest_register(node, 0);", + D1 => "${arch}_emit_dest_register(node, 1);", + DB0 => "${arch}_emit_8bit_dest_register(node, 0);", + X0 => "${arch}_emit_x87_register(node, 0);", + X1 => "${arch}_emit_x87_register(node, 1);", + SE => "${arch}_emit_extend_suffix(get_ia32_ls_mode(node));", ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n - ia32_emit_mode_suffix(env, node);", - M => "${arch}_emit_mode_suffix(env, node);", - XM => "${arch}_emit_x87_mode_suffix(env, node);", - XXM => "${arch}_emit_xmm_mode_suffix(env, node);", - XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);", - AM => "${arch}_emit_am(env, node);", - unop => "${arch}_emit_unop(env, node);", - binop => "${arch}_emit_binop(env, node);", - x87_binop => "${arch}_emit_x87_binop(env, node);", + ia32_emit_mode_suffix(node);", + M => "${arch}_emit_mode_suffix(node);", + XM => "${arch}_emit_x87_mode_suffix(node);", + XXM => "${arch}_emit_xmm_mode_suffix(node);", + XSD => "${arch}_emit_xmm_mode_suffix_s(node);", + AM => "${arch}_emit_am(node);", + unop3 => "${arch}_emit_unop(node, 3);", + unop4 => "${arch}_emit_unop(node, 4);", + unop5 => "${arch}_emit_unop(node, 5);", + DAM0 => "${arch}_emit_am_or_dest_register(node, 0);", + binop => "${arch}_emit_binop(node);", + x87_binop => "${arch}_emit_x87_binop(node);", + CMP0 => "${arch}_emit_cmp_suffix_node(node, 0);", + CMP3 => "${arch}_emit_cmp_suffix_node(node, 3);", ); #--------------------------------------------------# @@ -287,23 +232,79 @@ $arch = "ia32"; # |_| # #--------------------------------------------------# -$default_attr_type = "ia32_attr_t"; +$default_op_attr_type = "ia32_op_attr_t"; +$default_attr_type = "ia32_attr_t"; +$default_copy_attr = "ia32_copy_attr"; + +sub ia32_custom_init_attr { + my $node = shift; + my $name = shift; + my $res = ""; + + if(defined($node->{modified_flags})) { + $res .= "\tset_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);\n"; + } + if(defined($node->{am})) { + my $am = $node->{am}; + if($am eq "full,binary") { + $res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_binary);"; + } elsif($am eq "full,unary") { + $res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_unary);"; + } elsif($am eq "source,unary") { + $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_unary);"; + } elsif($am eq "source,binary") { + $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_binary);"; + } elsif($am eq "dest,unary") { + $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);"; + } elsif($am eq "dest,binary") { + $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);"; + } elsif($am eq "dest,ternary") { + $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_ternary);"; + } elsif($am eq "source,ternary") { + $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_ternary);"; + } elsif($am eq "none") { + # nothing to do + } else { + die("Invalid address mode '$am' specified on op $name"); + } + if($am ne "none") { + if($node->{state} ne "exc_pinned" + and $node->{state} ne "pinned") { + die("AM nodes must have pinned or AM pinned state ($name)"); + } + } + } + return $res; +} +$custom_init_attr_func = \&ia32_custom_init_attr; %init_attr = ( - ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", + ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", ia32_x87_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_ia32_x87_attributes(res);", ia32_asm_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_ia32_x87_attributes(res);". - "\tinit_ia32_asm_attributes(res);" + "\tinit_ia32_asm_attributes(res);", + ia32_immediate_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". + "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);", + ia32_copyb_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". + "\tinit_ia32_copyb_attributes(res, size);", + ia32_condcode_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". + "\tinit_ia32_condcode_attributes(res, pnc);", ); %compare_attr = ( - ia32_attr_t => "ia32_compare_nodes_attr", - ia32_x87_attr_t => "ia32_compare_x87_attr", - ia32_asm_attr_t => "ia32_compare_asm_attr", + ia32_attr_t => "ia32_compare_nodes_attr", + ia32_x87_attr_t => "ia32_compare_x87_attr", + ia32_asm_attr_t => "ia32_compare_asm_attr", + ia32_immediate_attr_t => "ia32_compare_immediate_attr", + ia32_copyb_attr_t => "ia32_compare_copyb_attr", + ia32_condcode_attr_t => "ia32_compare_condcode_attr", ); %operands = ( @@ -311,6 +312,7 @@ $default_attr_type = "ia32_attr_t"; $mode_xmm = "mode_E"; $mode_gp = "mode_Iu"; +$mode_flags = "mode_Iu"; $mode_fpcw = "mode_fpcw"; $status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ]; $fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM", @@ -323,6 +325,9 @@ Immediate => { op_flags => "c", irn_flags => "I", reg_req => { out => [ "gp_NOREG" ] }, + attr => "ir_entity *symconst, int symconst_sign, long offset", + attr_type => "ia32_immediate_attr_t", + latency => 0, mode => $mode_gp, }, @@ -331,6 +336,22 @@ Asm => { arity => "variable", out_arity => "variable", attr_type => "ia32_asm_attr_t", + attr => "ident *asm_text, const ia32_asm_reg_t *register_map", + init_attr => "attr->asm_text = asm_text;\n". + "\tattr->register_map = register_map;\n", + latency => 10, + modified_flags => 1, +}, + +ProduceVal => { + op_flags => "c", + irn_flags => "R", + reg_req => { out => [ "gp" ] }, + emit => "", + units => [ ], + latency => 0, + mode => $mode_gp, + cmp_attr => "return 1;", }, #-----------------------------------------------------------------# @@ -346,66 +367,80 @@ Asm => { # commutative operations -# NOTE: -# All nodes supporting Addressmode have 5 INs: -# 1 - base r1 == NoReg in case of no AM or no base -# 2 - index r2 == NoReg in case of no AM or no index -# 3 - op1 r3 == always present -# 4 - op2 r4 == NoReg in case of immediate operation -# 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load - Add => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - ins => [ "base", "index", "left", "right", "mem" ], + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "res", "flags", "M" ], emit => '. add%M %binop', + am => "full,binary", units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, -Adc => { - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. adc%M %binop', +AddMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "val" ], + emit => ". add%M %SI3, %AM", units => [ "GP" ], - mode => $mode_gp, + latency => 1, + mode => "mode_M", modified_flags => $status_flags }, -Add64Bit => { +AddMem8Bit => { irn_flags => "R", - arity => 4, - reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] }, - emit => ' -. movl %S0, %D0 -. movl %S1, %D1 -. addl %S2, %D0 -. adcl %S3, %D1 -', - outs => [ "low_res", "high_res" ], + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "val" ], + emit => ". add%M %SB3, %AM", + units => [ "GP" ], + latency => 1, + mode => "mode_M", + modified_flags => $status_flags +}, + +Adc => { + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, + ins => [ "base", "index", "mem", "left", "right", "eflags" ], + outs => [ "res", "flags", "M" ], + emit => '. adc%M %binop', + am => "full,binary", units => [ "GP" ], + latency => 1, + mode => $mode_gp, modified_flags => $status_flags }, l_Add => { op_flags => "C", - irn_flags => "R", - cmp_attr => "return 1;", - arity => 2, + reg_req => { in => [ "none", "none" ], out => [ "none" ] }, + ins => [ "left", "right" ], }, l_Adc => { - op_flags => "C", - cmp_attr => "return 1;", - arity => 2, + reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] }, + ins => [ "left", "right", "eflags" ], }, Mul => { # we should not rematrialize this node. It produces 2 results and has # very strict constrains - reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] }, - emit => '. mul%M %unop', - outs => [ "EAX", "EDX", "M" ], + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], + out => [ "eax", "edx", "none" ] }, + ins => [ "base", "index", "mem", "val_high", "val_low" ], + emit => '. mul%M %unop4', + outs => [ "res_low", "res_high", "M" ], + am => "source,binary", latency => 10, units => [ "GP" ], modified_flags => $status_flags @@ -422,8 +457,14 @@ l_Mul => { IMul => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. imul%M %binop', + state => "exc_pinned", + # TODO: adjust out requirements for the 3 operand form + # (no need for should_be_same then) + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "res", "flags", "M" ], + am => "source,binary", latency => 5, units => [ "GP" ], mode => $mode_gp, @@ -432,9 +473,13 @@ IMul => { IMul1OP => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] }, - emit => '. imul%M %unop', - outs => [ "EAX", "EDX", "M" ], + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], + out => [ "eax", "edx", "none" ] }, + ins => [ "base", "index", "mem", "val_high", "val_low" ], + emit => '. imul%M %unop4', + outs => [ "res_low", "res_high", "M" ], + am => "source,binary", latency => 5, units => [ "GP" ], modified_flags => $status_flags @@ -443,40 +488,125 @@ IMul1OP => { l_IMul => { op_flags => "C", cmp_attr => "return 1;", + outs => [ "res_low", "res_high", "M" ], arity => 2 }, And => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "res", "flags", "M" ], + op_modes => "commutative | am | immediate | mode_neutral", + am => "full,binary", emit => '. and%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, +AndMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "val" ], + emit => '. and%M %SI3, %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", + modified_flags => $status_flags +}, + +AndMem8Bit => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "val" ], + emit => '. and%M %SB3, %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", + modified_flags => $status_flags +}, + Or => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "res", "flags", "M" ], + am => "full,binary", emit => '. or%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, +OrMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "val" ], + emit => '. or%M %SI3, %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", + modified_flags => $status_flags +}, + +OrMem8Bit => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "val" ], + emit => '. or%M %SB3, %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", + modified_flags => $status_flags +}, + Xor => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "res", "flags", "M" ], + am => "full,binary", emit => '. xor%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, -l_Xor => { - op_flags => "C", - cmp_attr => "return 1;", - arity => 2, +XorMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "val" ], + emit => '. xor%M %SI3, %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", + modified_flags => $status_flags +}, + +XorMem8Bit => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "val" ], + emit => '. xor%M %SB3, %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", modified_flags => $status_flags }, @@ -484,55 +614,76 @@ l_Xor => { Sub => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4", "flags", "none" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "res", "flags", "M" ], + am => "full,binary", emit => '. sub%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, -Sbb => { - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] }, - emit => '. sbb%M %binop', +SubMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "val" ], + emit => '. sub%M %SI3, %AM', units => [ "GP" ], - mode => $mode_gp, + latency => 1, + mode => 'mode_M', modified_flags => $status_flags }, -Sub64Bit => { +SubMem8Bit => { irn_flags => "R", - arity => 4, - reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] }, - emit => ' -. movl %S0, %D0 -. movl %S1, %D1 -. subl %S2, %D0 -. sbbl %S3, %D1 -', - outs => [ "low_res", "high_res" ], + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "val" ], + emit => '. sub%M %SB3, %AM', units => [ "GP" ], + latency => 1, + mode => 'mode_M', + modified_flags => $status_flags +}, + +Sbb => { + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], + out => [ "in_r4 !in_r5", "flags", "none" ] }, + ins => [ "base", "index", "mem", "left", "right", "eflags" ], + outs => [ "res", "flags", "M" ], + am => "full,binary", + emit => '. sbb%M %binop', + units => [ "GP" ], + latency => 1, + mode => $mode_gp, modified_flags => $status_flags }, l_Sub => { - irn_flags => "R", - cmp_attr => "return 1;", - arity => 2, + reg_req => { in => [ "none", "none" ], out => [ "none" ] }, + ins => [ "left", "right" ], }, l_Sbb => { - cmp_attr => "return 1;", - arity => 2, + reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] }, + ins => [ "left", "right", "eflags" ], }, IDiv => { op_flags => "F|L", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] }, - attr => "ia32_op_flavour_t dm_flav", - init_attr => "attr->data.op_flav = dm_flav;", - emit => ". idiv%M %unop", - outs => [ "div_res", "mod_res", "M" ], + reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], + out => [ "eax", "flags", "none", "edx", "none" ] }, + ins => [ "base", "index", "mem", "left_low", "left_high", "right" ], + outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ], + am => "source,ternary", + emit => ". idiv%M %unop5", latency => 25, units => [ "GP" ], modified_flags => $status_flags @@ -541,11 +692,12 @@ IDiv => { Div => { op_flags => "F|L", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] }, - attr => "ia32_op_flavour_t dm_flav", - init_attr => "attr->data.op_flav = dm_flav;", - emit => ". div%M %unop", - outs => [ "div_res", "mod_res", "M" ], + reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], + out => [ "eax", "flags", "none", "edx", "none" ] }, + ins => [ "base", "index", "mem", "left_low", "left_high", "right" ], + outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ], + am => "source,ternary", + emit => ". div%M %unop5", latency => 25, units => [ "GP" ], modified_flags => $status_flags @@ -553,50 +705,42 @@ Div => { Shl => { irn_flags => "R", - # "in_r3" would be enough as out requirement, but the register allocator - # does strange things then and doesn't respect the constraint for in4 - # if the same value is attached to in3 and in4 (if you have "i << i" in C) - reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] }, - ins => [ "base", "index", "left", "right", "mem" ], - emit => '. shl%M %binop', + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, + ins => [ "val", "count" ], + outs => [ "res", "flags" ], + emit => '. shl %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, -l_Shl => { - cmp_attr => "return 1;", - arity => 2 +ShlMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "count" ], + emit => '. shl%M %SB3, %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", + modified_flags => $status_flags +}, + +l_ShlDep => { + cmp_attr => "return 1;", + ins => [ "val", "count", "dep" ], + arity => 3 }, ShlD => { irn_flags => "R", - # Out requirements is: different from all in - # This is because, out must be different from LowPart and ShiftCount. - # We could say "!ecx !in_r4" but it can occur, that all values live through - # this Shift and the only value dying is the ShiftCount. Then there would be - # a register missing, as result must not be ecx and all other registers are - # occupied. What we should write is "!in_r4 !in_r5", but this is not - # supported (and probably never will). So we create artificial interferences - # of the result with all inputs, so the spiller can always assure a free - # register. - reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] }, - emit => -' -if (get_ia32_immop_type(node) == ia32_ImmNone) { - if (get_ia32_op_type(node) == ia32_AddrModeD) { - . shld%M %%cl, %S3, %AM - } else { - . shld%M %%cl, %S3, %S2 - } -} else { - if (get_ia32_op_type(node) == ia32_AddrModeD) { - . shld%M %C, %S3, %AM - } else { - . shld%M %C, %S3, %S2 - } -} -', + reg_req => { in => [ "gp", "gp", "ecx" ], + out => [ "in_r1 !in_r2 !in_r3", "flags" ] }, + ins => [ "val_high", "val_low", "count" ], + outs => [ "res", "flags" ], + emit => ". shld%M %SB2, %S1, %D0", latency => 6, units => [ "GP" ], mode => $mode_gp, @@ -605,49 +749,48 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { l_ShlD => { cmp_attr => "return 1;", + ins => [ "val_high", "val_low", "count" ], arity => 3, }, Shr => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] }, - emit => '. shr%M %binop', + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, + ins => [ "val", "count" ], + outs => [ "res", "flags" ], + emit => '. shr %SB1, %S0', units => [ "GP" ], mode => $mode_gp, + latency => 1, modified_flags => $status_flags }, -l_Shr => { +ShrMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "count" ], + emit => '. shr%M %SB3, %AM', + units => [ "GP" ], + mode => "mode_M", + latency => 1, + modified_flags => $status_flags +}, + +l_ShrDep => { cmp_attr => "return 1;", - arity => 2 + ins => [ "val", "count", "dep" ], + arity => 3 }, ShrD => { irn_flags => "R", - # Out requirements is: different from all in - # This is because, out must be different from LowPart and ShiftCount. - # We could say "!ecx !in_r4" but it can occur, that all values live through - # this Shift and the only value dying is the ShiftCount. Then there would be a - # register missing, as result must not be ecx and all other registers are - # occupied. What we should write is "!in_r4 !in_r5", but this is not supported - # (and probably never will). So we create artificial interferences of the result - # with all inputs, so the spiller can always assure a free register. - reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] }, - emit => ' -if (get_ia32_immop_type(node) == ia32_ImmNone) { - if (get_ia32_op_type(node) == ia32_AddrModeD) { - . shrd%M %%cl, %S3, %AM - } else { - . shrd%M %%cl, %S3, %S2 - } -} else { - if (get_ia32_op_type(node) == ia32_AddrModeD) { - . shrd%M %C, %S3, %AM - } else { - . shrd%M %C, %S3, %S2 - } -} -', + reg_req => { in => [ "gp", "gp", "ecx" ], + out => [ "in_r1 !in_r2 !in_r3", "flags" ] }, + ins => [ "val_high", "val_low", "count" ], + outs => [ "res", "flags" ], + emit => ". shrd%M %SB2, %S1, %D0", latency => 6, units => [ "GP" ], mode => $mode_gp, @@ -656,131 +799,343 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { l_ShrD => { cmp_attr => "return 1;", - arity => 3 + arity => 3, + ins => [ "val_high", "val_low", "count" ], }, Sar => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] }, - emit => '. sar%M %binop', + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, + ins => [ "val", "count" ], + outs => [ "res", "flags" ], + emit => '. sar %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, -l_Sar => { +SarMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "count" ], + emit => '. sar%M %SB3, %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", + modified_flags => $status_flags +}, + +l_SarDep => { cmp_attr => "return 1;", - arity => 2 + ins => [ "val", "count", "dep" ], + arity => 3 }, Ror => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] }, - emit => '. ror%M %binop', + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, + ins => [ "val", "count" ], + outs => [ "res", "flags" ], + emit => '. ror %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, +RorMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "count" ], + emit => '. ror%M %SB3, %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", + modified_flags => $status_flags +}, + Rol => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] }, - emit => '. rol%M %binop', + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, + ins => [ "val", "count" ], + outs => [ "res", "flags" ], + emit => '. rol %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, +RolMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "count" ], + emit => '. rol%M %SB3, %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", + modified_flags => $status_flags +}, + # unary operations Neg => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. neg%M %unop', + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, + emit => '. neg %S0', + ins => [ "val" ], + outs => [ "res", "flags" ], units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, +NegMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, + ins => [ "base", "index", "mem" ], + emit => '. neg%M %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", + modified_flags => $status_flags +}, + Minus64Bit => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] }, - emit => ' -. movl %S0, %D0 -. movl %S0, %D1 -. subl %S1, %D0 -. sbbl %S2, %D1 -', + reg_req => { in => [ "gp", "gp" ], out => [ "in_r1", "gp" ] }, outs => [ "low_res", "high_res" ], units => [ "GP" ], + latency => 3, modified_flags => $status_flags }, -l_Neg => { - cmp_attr => "return 1;", - arity => 1, -}, - Inc => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. inc%M %unop', + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, + outs => [ "res", "flags" ], + emit => '. inc %S0', units => [ "GP" ], mode => $mode_gp, + latency => 1, + modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] +}, + +IncMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, + ins => [ "base", "index", "mem" ], + emit => '. inc%M %AM', + units => [ "GP" ], + mode => "mode_M", + latency => 1, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] }, Dec => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. dec%M %unop', + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, + outs => [ "res", "flags" ], + emit => '. dec %S0', units => [ "GP" ], mode => $mode_gp, + latency => 1, + modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] +}, + +DecMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, + ins => [ "base", "index", "mem" ], + emit => '. dec%M %AM', + units => [ "GP" ], + mode => "mode_M", + latency => 1, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] }, Not => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] }, - emit => '. not%M %unop', + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, + ins => [ "val" ], + outs => [ "res", "flags" ], + emit => '. not %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, - modified_flags => [] + # no flags modified +}, + +NotMem => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] }, + ins => [ "base", "index", "mem" ], + emit => '. not%M %AM', + units => [ "GP" ], + latency => 1, + mode => "mode_M", + # no flags modified +}, + +Cmc => { + reg_req => { in => [ "flags" ], out => [ "flags" ] }, + emit => '.cmc', + units => [ "GP" ], + latency => 1, + mode => $mode_flags, + modified_flags => $status_flags +}, + +Stc => { + reg_req => { out => [ "flags" ] }, + emit => '.stc', + units => [ "GP" ], + latency => 1, + mode => $mode_flags, + modified_flags => $status_flags }, # other operations -CondJmp => { - state => "pinned", - op_flags => "L|X|Y", - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none"] }, - outs => [ "false", "true" ], - latency => 3, - units => [ "BRANCH" ], +Cmp => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "eflags" ], + am => "source,binary", + emit => '. cmp%M %binop', + attr => "int ins_permuted, int cmp_unsigned", + init_attr => "attr->data.ins_permuted = ins_permuted;\n". + "\tattr->data.cmp_unsigned = cmp_unsigned;\n", + latency => 1, + units => [ "GP" ], + mode => $mode_flags, + modified_flags => $status_flags }, -TestJmp => { - state => "pinned", - op_flags => "L|X|Y", - reg_req => { in => [ "gp", "gp" ], out => [ "none", "none" ] }, - outs => [ "false", "true" ], - latency => 3, - units => [ "BRANCH" ], +Cmp8Bit => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "eflags" ], + am => "source,binary", + emit => '. cmpb %binop', + attr => "int ins_permuted, int cmp_unsigned", + init_attr => "attr->data.ins_permuted = ins_permuted;\n". + "\tattr->data.cmp_unsigned = cmp_unsigned;\n", + latency => 1, + units => [ "GP" ], + mode => $mode_flags, + modified_flags => $status_flags }, -CJmpAM => { - state => "pinned", - op_flags => "L|X|Y", - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] }, - outs => [ "false", "true" ], - units => [ "BRANCH" ], +Test => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "eflags" ], + am => "source,binary", + emit => '. test%M %binop', + attr => "int ins_permuted, int cmp_unsigned", + init_attr => "attr->data.ins_permuted = ins_permuted;\n". + "\tattr->data.cmp_unsigned = cmp_unsigned;\n", + latency => 1, + units => [ "GP" ], + mode => $mode_flags, + modified_flags => $status_flags +}, + +Test8Bit => { + irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "eflags" ], + am => "source,binary", + emit => '. testb %binop', + attr => "int ins_permuted, int cmp_unsigned", + init_attr => "attr->data.ins_permuted = ins_permuted;\n". + "\tattr->data.cmp_unsigned = cmp_unsigned;\n", + latency => 1, + units => [ "GP" ], + mode => $mode_flags, + modified_flags => $status_flags }, -CJmp => { +Set => { + #irn_flags => "R", + reg_req => { in => [ "eflags" ], out => [ "eax ebx ecx edx" ] }, + ins => [ "eflags" ], + attr_type => "ia32_condcode_attr_t", + attr => "pn_Cmp pnc, int ins_permuted", + init_attr => "attr->attr.data.ins_permuted = ins_permuted;\n". + "\tset_ia32_ls_mode(res, mode_Bu);\n", + emit => '. set%CMP0 %DB0', + latency => 1, + units => [ "GP" ], + mode => $mode_gp, +}, + +SetMem => { + #irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eflags" ], out => [ "none" ] }, + ins => [ "base", "index", "mem","eflags" ], + attr_type => "ia32_condcode_attr_t", + attr => "pn_Cmp pnc, int ins_permuted", + init_attr => "attr->attr.data.ins_permuted = ins_permuted;\n". + "\tset_ia32_ls_mode(res, mode_Bu);\n", + emit => '. set%CMP3 %AM', + latency => 1, + units => [ "GP" ], + mode => 'mode_M', +}, + +CMov => { + #irn_flags => "R", + # (note: leave the false,true order intact to make it compatible with other + # ia32_binary ops) + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "eflags" ], out => [ "in_r4 in_r5" ] }, + ins => [ "base", "index", "mem", "val_false", "val_true", "eflags" ], + am => "source,binary", + attr_type => "ia32_condcode_attr_t", + attr => "int ins_permuted, pn_Cmp pnc", + init_attr => "attr->attr.data.ins_permuted = ins_permuted;", + latency => 1, + units => [ "GP" ], + mode => $mode_gp, +}, + +Jcc => { state => "pinned", op_flags => "L|X|Y", - reg_req => { in => [ "gp", "gp" ] }, + reg_req => { in => [ "eflags" ], out => [ "none", "none" ] }, + ins => [ "eflags" ], + outs => [ "false", "true" ], + attr_type => "ia32_condcode_attr_t", + attr => "pn_Cmp pnc", + latency => 2, units => [ "BRANCH" ], }, @@ -788,8 +1143,24 @@ SwitchJmp => { state => "pinned", op_flags => "L|X|Y", reg_req => { in => [ "gp" ], out => [ "none" ] }, + mode => "mode_T", + attr_type => "ia32_condcode_attr_t", + attr => "pn_Cmp pnc", latency => 3, units => [ "BRANCH" ], + modified_flags => $status_flags, +}, + +IJmp => { + state => "pinned", + op_flags => "X", + reg_req => { in => [ "gp", "gp", "none", "gp" ] }, + ins => [ "base", "index", "mem", "target" ], + am => "source,unary", + emit => '. jmp *%unop3', + latency => 1, + units => [ "BRANCH" ], + mode => "mode_X", }, Const => { @@ -797,6 +1168,9 @@ Const => { irn_flags => "R", reg_req => { out => [ "gp" ] }, units => [ "GP" ], + attr => "ir_entity *symconst, int symconst_sign, long offset", + attr_type => "ia32_immediate_attr_t", + latency => 1, mode => $mode_gp, }, @@ -807,6 +1181,7 @@ Unknown_GP => { reg_req => { out => [ "gp_UKNWN" ] }, units => [], emit => "", + latency => 0, mode => $mode_gp }, @@ -818,6 +1193,7 @@ Unknown_VFP => { units => [], emit => "", mode => "mode_E", + latency => 0, attr_type => "ia32_x87_attr_t", }, @@ -828,6 +1204,7 @@ Unknown_XMM => { reg_req => { out => [ "xmm_UKNWN" ] }, units => [], emit => "", + latency => 0, mode => "mode_E" }, @@ -838,6 +1215,7 @@ NoReg_GP => { reg_req => { out => [ "gp_NOREG" ] }, units => [], emit => "", + latency => 0, mode => $mode_gp }, @@ -849,6 +1227,7 @@ NoReg_VFP => { units => [], emit => "", mode => "mode_E", + latency => 0, attr_type => "ia32_x87_attr_t", }, @@ -859,6 +1238,7 @@ NoReg_XMM => { reg_req => { out => [ "xmm_NOREG" ] }, units => [], emit => "", + latency => 0, mode => "mode_E" }, @@ -875,8 +1255,9 @@ ChangeCW => { FldCW => { op_flags => "L|F", - state => "exc_pinned", + state => "pinned", reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] }, + ins => [ "base", "index", "mem" ], latency => 5, emit => ". fldcw %AM", mode => $mode_fpcw, @@ -886,32 +1267,48 @@ FldCW => { FnstCW => { op_flags => "L|F", - state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] }, + state => "pinned", + reg_req => { in => [ "gp", "gp", "none", "fp_cw" ], out => [ "none" ] }, + ins => [ "base", "index", "mem", "fpcw" ], latency => 5, emit => ". fnstcw %AM", mode => "mode_M", units => [ "GP" ], }, +FnstCWNOP => { + op_flags => "L|F", + state => "pinned", + reg_req => { in => [ "fp_cw" ], out => [ "none" ] }, + ins => [ "fpcw" ], + latency => 0, + emit => "", + mode => "mode_M", +}, + Cltd => { - # we should not rematrialize this node. It produces 2 results and has - # very strict constrains - reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] }, + # we should not rematrialize this node. It has very strict constraints. + reg_req => { in => [ "eax", "edx" ], out => [ "edx" ] }, + ins => [ "val", "globbered" ], emit => '. cltd', - outs => [ "EAX", "EDX" ], + latency => 1, + mode => $mode_gp, units => [ "GP" ], }, # Load / Store +# +# Note that we add additional latency values depending on address mode, so a +# lateny of 0 for load is correct Load => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] }, - latency => 3, + reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none", "none" ] }, + ins => [ "base", "index", "mem" ], + outs => [ "res", "M", "X_exc" ], + latency => 0, emit => ". mov%SE%ME%.l %AM, %D0", - outs => [ "res", "M" ], units => [ "GP" ], }, @@ -933,9 +1330,11 @@ l_Store => { Store => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] }, - emit => '. mov%M %binop', - latency => 3, + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], + emit => '. mov%M %SI3, %AM', + latency => 2, units => [ "GP" ], mode => "mode_M", }, @@ -943,39 +1342,48 @@ Store => { Store8Bit => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] }, - emit => '. mov%M %binop', - latency => 3, + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], + emit => '. mov%M %SB3, %AM', + latency => 2, units => [ "GP" ], mode => "mode_M", }, Lea => { irn_flags => "R", - reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] }, + reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] }, + ins => [ "base", "index" ], emit => '. leal %AM, %D0', latency => 2, units => [ "GP" ], mode => $mode_gp, - modified_flags => [], +# lea doesn't modify the flags, but setting this seems advantageous since it +# increases chances that the Lea is transformed back to an Add + modified_flags => 1, }, Push => { - reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] }, - emit => '. push%M %unop', + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "esp", "none" ] }, + ins => [ "base", "index", "mem", "val", "stack" ], + emit => '. push%M %unop4', outs => [ "stack:I|S", "M" ], - latency => 3, + am => "source,binary", + latency => 2, units => [ "GP" ], - modified_flags => [], }, Pop => { - reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] }, - emit => '. pop%M %unop', - outs => [ "stack:I|S", "res", "M" ], - latency => 4, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "esp" ], out => [ "gp", "none", "none", "esp" ] }, + emit => '. pop%M %DAM0', + outs => [ "res", "M", "unused", "stack:I|S" ], + ins => [ "base", "index", "mem", "stack" ], + am => "dest,unary", + latency => 3, # Pop is more expensive than Push on Athlon units => [ "GP" ], - modified_flags => [], }, Enter => { @@ -996,18 +1404,27 @@ Leave => { AddSP => { irn_flags => "I", - reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] }, + state => "pinned", + reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "in_r4", "none" ] }, + ins => [ "base", "index", "mem", "stack", "size" ], + am => "source,binary", emit => '. addl %binop', - outs => [ "stack:S", "M" ], + latency => 1, + outs => [ "stack:I|S", "M" ], units => [ "GP" ], modified_flags => $status_flags }, SubSP => { - irn_flags => "I", - reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] }, - emit => '. subl %binop', - outs => [ "stack:S", "M" ], +#irn_flags => "I", + state => "pinned", + reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "in_r4", "gp", "none" ] }, + ins => [ "base", "index", "mem", "stack", "size" ], + am => "source,binary", + emit => ". subl %binop\n". + ". movl %%esp, %D1", + latency => 2, + outs => [ "stack:I|S", "addr", "M" ], units => [ "GP" ], modified_flags => $status_flags }, @@ -1016,17 +1433,7 @@ LdTls => { irn_flags => "R", reg_req => { out => [ "gp" ] }, units => [ "GP" ], -}, - -# the int instruction -int => { - reg_req => { in => [ "none" ], out => [ "none" ] }, - mode => "mode_M", - attr => "tarval *tv", - init_attr => "\tset_ia32_Immop_tarval(res, tv);", - emit => '. int %C', - units => [ "GP" ], - cmp_attr => "return 1;", + latency => 1, }, @@ -1039,11 +1446,23 @@ int => { # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # #-----------------------------------------------------------------------------# +xZero => { + irn_flags => "R", + reg_req => { out => [ "xmm" ] }, + emit => '. xorp%XSD %D0, %D0', + latency => 3, + units => [ "SSE" ], + mode => "mode_E", +}, + # commutative operations xAdd => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + am => "source,binary", emit => '. add%XXM %binop', latency => 4, units => [ "SSE" ], @@ -1052,7 +1471,10 @@ xAdd => { xMul => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + am => "source,binary", emit => '. mul%XXM %binop', latency => 4, units => [ "SSE" ], @@ -1061,7 +1483,10 @@ xMul => { xMax => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + am => "source,binary", emit => '. max%XXM %binop', latency => 2, units => [ "SSE" ], @@ -1070,7 +1495,10 @@ xMax => { xMin => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + am => "source,binary", emit => '. min%XXM %binop', latency => 2, units => [ "SSE" ], @@ -1079,7 +1507,10 @@ xMin => { xAnd => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + am => "source,binary", emit => '. andp%XSD %binop', latency => 3, units => [ "SSE" ], @@ -1088,15 +1519,22 @@ xAnd => { xOr => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + am => "source,binary", emit => '. orp%XSD %binop', + latency => 3, units => [ "SSE" ], mode => "mode_E", }, xXor => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + am => "source,binary", emit => '. xorp%XSD %binop', latency => 3, units => [ "SSE" ], @@ -1107,7 +1545,10 @@ xXor => { xAndNot => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + am => "source,binary", emit => '. andnp%XSD %binop', latency => 3, units => [ "SSE" ], @@ -1116,7 +1557,10 @@ xAndNot => { xSub => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + am => "source,binary", emit => '. sub%XXM %binop', latency => 4, units => [ "SSE" ], @@ -1125,7 +1569,10 @@ xSub => { xDiv => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4", "none" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5", "none" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + am => "source,binary", outs => [ "res", "M" ], emit => '. div%XXM %binop', latency => 16, @@ -1134,31 +1581,20 @@ xDiv => { # other operations -xCmp => { +Ucomi => { irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "eflags" ] }, + ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "flags" ], + am => "source,binary", + attr => "int ins_permuted", + init_attr => "attr->data.ins_permuted = ins_permuted;", + emit => ' .ucomi%XXM %binop', latency => 3, units => [ "SSE" ], - mode => "mode_E", -}, - -xCondJmp => { - state => "pinned", - op_flags => "L|X|Y", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] }, - outs => [ "false", "true" ], - latency => 5, - units => [ "SSE" ], -}, - -xConst => { - op_flags => "c", - irn_flags => "R", - reg_req => { out => [ "xmm" ] }, - emit => '. mov%XXM %C, %D0', - latency => 2, - units => [ "SSE" ], - mode => "mode_E", + mode => $mode_flags, + modified_flags => 1, }, # Load / Store @@ -1166,19 +1602,24 @@ xConst => { xLoad => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] }, + reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none", "none" ] }, + ins => [ "base", "index", "mem" ], + outs => [ "res", "M", "X_exc" ], emit => '. mov%XXM %AM, %D0', - outs => [ "res", "M" ], - latency => 2, + attr => "ir_mode *load_mode", + init_attr => "attr->ls_mode = load_mode;", + latency => 0, units => [ "SSE" ], }, xStore => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "xmm", "none" ] }, - emit => '. mov%XXM %binop', - latency => 2, + reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "none", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], + emit => '. mov%XXM %S3, %AM', + latency => 0, units => [ "SSE" ], mode => "mode_M", }, @@ -1186,18 +1627,21 @@ xStore => { xStoreSimple => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "xmm", "none" ] }, - ins => [ "base", "index", "val", "mem" ], - emit => '. mov%XXM %S2, %AM', - latency => 2, + reg_req => { in => [ "gp", "gp", "none", "xmm" ] }, + ins => [ "base", "index", "mem", "val" ], + emit => '. mov%XXM %S3, %AM', + latency => 0, units => [ "SSE" ], mode => "mode_M", }, CvtSI2SS => { op_flags => "L|F", - reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] }, - emit => '. cvtsi2ss %D0, %AM', + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] }, + ins => [ "base", "index", "mem", "val" ], + am => "source,unary", + emit => '. cvtsi2ss %unop3, %D0', latency => 2, units => [ "SSE" ], mode => $mode_xmm @@ -1205,181 +1649,112 @@ CvtSI2SS => { CvtSI2SD => { op_flags => "L|F", - reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] }, - emit => '. cvtsi2sd %unop', - latency => 2, - units => [ "SSE" ], - mode => $mode_xmm -}, - - -l_X87toSSE => { - op_flags => "L|F", - cmp_attr => "return 1;", - arity => 3, -}, - -l_SSEtoX87 => { - op_flags => "L|F", - cmp_attr => "return 1;", - arity => 3, -}, - -GetST0 => { - op_flags => "L|F", - irn_flags => "I", - state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none" ] }, - emit => '. fstp%XM %AM', - latency => 4, - units => [ "SSE" ], - mode => "mode_M", -}, - -SetST0 => { - op_flags => "L|F", - irn_flags => "I", - state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none" ], out => [ "vf0", "none" ] }, - ins => [ "base", "index", "mem" ], - emit => '. fld%XM %AM', - outs => [ "res", "M" ], + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] }, + ins => [ "base", "index", "mem", "val" ], + am => "source,unary", + emit => '. cvtsi2sd %unop3, %D0', latency => 2, - units => [ "SSE" ], -}, - -# CopyB - -CopyB => { - op_flags => "F|H", - state => "pinned", - reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] }, - outs => [ "DST", "SRC", "CNT", "M" ], - units => [ "GP" ], - modified_flags => [ "DF" ] -}, - -CopyB_i => { - op_flags => "F|H", - state => "pinned", - reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] }, - outs => [ "DST", "SRC", "M" ], - units => [ "GP" ], - modified_flags => [ "DF" ] -}, - -# Conversions - -Conv_I2I => { - reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] }, - units => [ "GP" ], - ins => [ "base", "index", "val", "mem" ], - mode => $mode_gp, - modified_flags => $status_flags -}, - -Conv_I2I8Bit => { - reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] }, - ins => [ "base", "index", "val", "mem" ], - units => [ "GP" ], - mode => $mode_gp, - modified_flags => $status_flags -}, - -Conv_I2FP => { - reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] }, - latency => 10, - units => [ "SSE" ], - mode => "mode_E", -}, - -Conv_FP2I => { - reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] }, - latency => 10, units => [ "SSE" ], - mode => $mode_gp, + mode => $mode_xmm }, -Conv_FP2FP => { - reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] }, - latency => 8, - units => [ "SSE" ], - mode => "mode_E", + +l_LLtoFloat => { + op_flags => "L|F", + cmp_attr => "return 1;", + ins => [ "val_high", "val_low" ], }, -CmpCMov => { - irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] }, - latency => 2, - units => [ "GP" ], - mode => $mode_gp, +l_FloattoLL => { + op_flags => "L|F", + cmp_attr => "return 1;", + ins => [ "val" ], + outs => [ "res_high", "res_low" ], }, -PsiCondCMov => { - irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp" ], out => [ "in_r3" ] }, - latency => 2, +# CopyB + +CopyB => { + op_flags => "F|H", + state => "pinned", + reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] }, + outs => [ "DST", "SRC", "CNT", "M" ], + attr_type => "ia32_copyb_attr_t", + attr => "unsigned size", units => [ "GP" ], - mode => $mode_gp, + latency => 3, +# we don't care about this flag, so no need to mark this node +# modified_flags => [ "DF" ] }, -xCmpCMov => { - irn_flags => "R", - reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] }, - latency => 5, - units => [ "SSE" ], - mode => $mode_gp, +CopyB_i => { + op_flags => "F|H", + state => "pinned", + reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] }, + outs => [ "DST", "SRC", "M" ], + attr_type => "ia32_copyb_attr_t", + attr => "unsigned size", + units => [ "GP" ], + latency => 3, +# we don't care about this flag, so no need to mark this node +# modified_flags => [ "DF" ] }, -vfCmpCMov => { - irn_flags => "R", - reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] }, - latency => 10, - units => [ "VFP" ], - mode => $mode_gp, - attr_type => "ia32_x87_attr_t", -}, +# Conversions -CmpSet => { - irn_flags => "R", - reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] }, - latency => 2, +Conv_I2I => { + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "gp", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + am => "source,unary", units => [ "GP" ], + latency => 1, + attr => "ir_mode *smaller_mode", + init_attr => "attr->ls_mode = smaller_mode;", mode => $mode_gp, }, -PsiCondSet => { - irn_flags => "R", - reg_req => { in => [ "gp" ], out => [ "eax ebx ecx edx" ] }, - latency => 2, +Conv_I2I8Bit => { + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "gp", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + am => "source,unary", units => [ "GP" ], + latency => 1, + attr => "ir_mode *smaller_mode", + init_attr => "attr->ls_mode = smaller_mode;", mode => $mode_gp, }, -xCmpSet => { - irn_flags => "R", - reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] }, - latency => 5, +Conv_I2FP => { + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + am => "source,unary", + latency => 10, units => [ "SSE" ], - mode => $mode_gp, + mode => "mode_E", }, -vfCmpSet => { - irn_flags => "R", - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] }, +Conv_FP2I => { + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "gp", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + am => "source,unary", latency => 10, - units => [ "VFP" ], + units => [ "SSE" ], mode => $mode_gp, - attr_type => "ia32_x87_attr_t", }, -vfCMov => { - irn_flags => "R", - reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] }, - latency => 10, - units => [ "VFP" ], +Conv_FP2FP => { + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "xmm", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + am => "source,unary", + latency => 8, + units => [ "SSE" ], mode => "mode_E", - attr_type => "ia32_x87_attr_t", }, #----------------------------------------------------------# @@ -1396,9 +1771,15 @@ vfCMov => { # |_| |_|\___/ \__,_|\___||___/ # #----------------------------------------------------------# +# rematerialisation disabled for all float nodes for now, because the fpcw +# handler runs before spilling and we might end up with wrong fpcw then + vfadd => { - irn_flags => "R", - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] }, +# irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] }, + ins => [ "base", "index", "mem", "left", "right", "fpcw" ], + am => "source,binary", latency => 4, units => [ "VFP" ], mode => "mode_E", @@ -1406,64 +1787,53 @@ vfadd => { }, vfmul => { - irn_flags => "R", - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] }, +# irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] }, + ins => [ "base", "index", "mem", "left", "right", "fpcw" ], + am => "source,binary", latency => 4, units => [ "VFP" ], mode => "mode_E", attr_type => "ia32_x87_attr_t", }, -l_vfmul => { - op_flags => "C", - cmp_attr => "return 1;", - arity => 2, -}, - vfsub => { - irn_flags => "R", - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] }, +# irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] }, + ins => [ "base", "index", "mem", "left", "right", "fpcw" ], + am => "source,binary", latency => 4, units => [ "VFP" ], mode => "mode_E", attr_type => "ia32_x87_attr_t", }, -l_vfsub => { - cmp_attr => "return 1;", - arity => 2, -}, - vfdiv => { - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp", "none" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp", "none" ] }, + ins => [ "base", "index", "mem", "left", "right", "fpcw" ], + am => "source,binary", outs => [ "res", "M" ], latency => 20, units => [ "VFP" ], attr_type => "ia32_x87_attr_t", }, -l_vfdiv => { - cmp_attr => "return 1;", - outs => [ "res", "M" ], - arity => 2, -}, - vfprem => { - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] }, + reg_req => { in => [ "vfp", "vfp", "fpcw" ], out => [ "vfp" ] }, + ins => [ "left", "right", "fpcw" ], latency => 20, units => [ "VFP" ], mode => "mode_E", attr_type => "ia32_x87_attr_t", }, -l_vfprem => { - cmp_attr => "return 1;", - arity => 2, -}, - vfabs => { irn_flags => "R", reg_req => { in => [ "vfp"], out => [ "vfp" ] }, + ins => [ "value" ], latency => 2, units => [ "VFP" ], mode => "mode_E", @@ -1473,55 +1843,38 @@ vfabs => { vfchs => { irn_flags => "R", reg_req => { in => [ "vfp"], out => [ "vfp" ] }, + ins => [ "value" ], latency => 2, units => [ "VFP" ], mode => "mode_E", attr_type => "ia32_x87_attr_t", }, -vfsin => { - irn_flags => "R", - reg_req => { in => [ "vfp"], out => [ "vfp" ] }, - latency => 150, - units => [ "VFP" ], - mode => "mode_E", - attr_type => "ia32_x87_attr_t", -}, - -vfcos => { - irn_flags => "R", - reg_req => { in => [ "vfp"], out => [ "vfp" ] }, - latency => 150, - units => [ "VFP" ], - mode => "mode_E", - attr_type => "ia32_x87_attr_t", -}, - -vfsqrt => { - irn_flags => "R", - reg_req => { in => [ "vfp"], out => [ "vfp" ] }, - latency => 30, - units => [ "VFP" ], - mode => "mode_E", - attr_type => "ia32_x87_attr_t", -}, - # virtual Load and Store vfld => { + irn_flags => "R", op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] }, - outs => [ "res", "M" ], + reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none", "none" ] }, + ins => [ "base", "index", "mem" ], + outs => [ "res", "M", "X_exc" ], + attr => "ir_mode *load_mode", + init_attr => "attr->attr.ls_mode = load_mode;", latency => 2, units => [ "VFP" ], attr_type => "ia32_x87_attr_t", }, vfst => { + irn_flags => "R", op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "vfp", "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "none", "none" ] }, + ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], + attr => "ir_mode *store_mode", + init_attr => "attr->attr.ls_mode = store_mode;", latency => 2, units => [ "VFP" ], mode => "mode_M", @@ -1531,8 +1884,10 @@ vfst => { # Conversions vfild => { + state => "exc_pinned", reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] }, outs => [ "res", "M" ], + ins => [ "base", "index", "mem" ], latency => 4, units => [ "VFP" ], attr_type => "ia32_x87_attr_t", @@ -1545,7 +1900,9 @@ l_vfild => { }, vfist => { - reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] }, + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "vfp", "fpcw" ] }, + ins => [ "base", "index", "mem", "val", "fpcw" ], latency => 4, units => [ "VFP" ], mode => "mode_M", @@ -1554,6 +1911,7 @@ vfist => { l_vfist => { cmp_attr => "return 1;", + state => "exc_pinned", arity => 3, mode => "mode_M", }, @@ -1624,26 +1982,58 @@ vfldl2e => { attr_type => "ia32_x87_attr_t", }, -vfConst => { - op_flags => "c", - irn_flags => "R", - reg_req => { out => [ "vfp" ] }, +# other + +vFucomFnstsw => { +# we can't allow to rematerialize this node so we don't have +# accidently produce Phi(Fucom, Fucom(ins_permuted)) +# irn_flags => "R", + reg_req => { in => [ "vfp", "vfp" ], out => [ "eax" ] }, + ins => [ "left", "right" ], + outs => [ "flags" ], + attr => "int ins_permuted", + init_attr => "attr->attr.data.ins_permuted = ins_permuted;", latency => 3, units => [ "VFP" ], - mode => "mode_E", attr_type => "ia32_x87_attr_t", + mode => $mode_gp }, -# other +vFucomi => { + irn_flags => "R", + reg_req => { in => [ "vfp", "vfp" ], out => [ "eflags" ] }, + ins => [ "left", "right" ], + outs => [ "flags" ], + attr => "int ins_permuted", + init_attr => "attr->attr.data.ins_permuted = ins_permuted;", + latency => 3, + units => [ "VFP" ], + attr_type => "ia32_x87_attr_t", + mode => $mode_gp +}, -vfCondJmp => { - state => "pinned", - op_flags => "L|X|Y", - reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] }, - outs => [ "false", "true", "temp_reg_eax" ], - latency => 10, +vFtstFnstsw => { +# irn_flags => "R", + reg_req => { in => [ "vfp" ], out => [ "eax" ] }, + ins => [ "left" ], + outs => [ "flags" ], + attr => "int ins_permuted", + init_attr => "attr->attr.data.ins_permuted = ins_permuted;", + latency => 3, units => [ "VFP" ], attr_type => "ia32_x87_attr_t", + mode => $mode_gp +}, + +Sahf => { + irn_flags => "R", + reg_req => { in => [ "eax" ], out => [ "eflags" ] }, + ins => [ "val" ], + outs => [ "flags" ], + emit => '. sahf', + latency => 1, + units => [ "GP" ], + mode => $mode_flags, }, #------------------------------------------------------------------------# @@ -1658,130 +2048,143 @@ vfCondJmp => { # are swapped, we work this around in the emitter... fadd => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fadd%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, faddp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, - emit => '. faddp %x87_binop', + emit => '. faddp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fmul => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fmul%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fmulp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, - emit => '. fmulp %x87_binop',, + emit => '. fmulp%XM %x87_binop',, + latency => 4, attr_type => "ia32_x87_attr_t", }, fsub => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fsub%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fsubp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, # see note about gas bugs - emit => '. fsubrp %x87_binop', + emit => '. fsubrp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fsubr => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", irn_flags => "R", reg_req => { }, emit => '. fsubr%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fsubrp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", irn_flags => "R", reg_req => { }, # see note about gas bugs - emit => '. fsubp %x87_binop', + emit => '. fsubp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fprem => { - op_flags => "R", rd_constructor => "NONE", reg_req => { }, emit => '. fprem1', + latency => 20, attr_type => "ia32_x87_attr_t", }, # this node is just here, to keep the simulator running # we can omit this when a fprem simulation function exists fpremp => { - op_flags => "R", rd_constructor => "NONE", reg_req => { }, - emit => '. fprem1', + emit => '. fprem1\n'. + '. fstp %X0', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdiv => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fdiv%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdivp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, # see note about gas bugs - emit => '. fdivrp %x87_binop', + emit => '. fdivrp%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdivr => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fdivr%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdivrp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, # see note about gas bugs - emit => '. fdivp %x87_binop', + emit => '. fdivp%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fabs => { - op_flags => "R", rd_constructor => "NONE", reg_req => { }, emit => '. fabs', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1790,30 +2193,7 @@ fchs => { rd_constructor => "NONE", reg_req => { }, emit => '. fchs', - attr_type => "ia32_x87_attr_t", -}, - -fsin => { - op_flags => "R", - rd_constructor => "NONE", - reg_req => { }, - emit => '. fsin', - attr_type => "ia32_x87_attr_t", -}, - -fcos => { - op_flags => "R", - rd_constructor => "NONE", - reg_req => { }, - emit => '. fcos', - attr_type => "ia32_x87_attr_t", -}, - -fsqrt => { - op_flags => "R", - rd_constructor => "NONE", - reg_req => { }, - emit => '. fsqrt $', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -1826,6 +2206,7 @@ fld => { reg_req => { }, emit => '. fld%XM %AM', attr_type => "ia32_x87_attr_t", + latency => 2, }, fst => { @@ -1836,6 +2217,7 @@ fst => { emit => '. fst%XM %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, fstp => { @@ -1846,92 +2228,103 @@ fstp => { emit => '. fstp%XM %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, # Conversions fild => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, - emit => '. fild%XM %AM', + emit => '. fild%M %AM', attr_type => "ia32_x87_attr_t", + latency => 2, }, fist => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, - emit => '. fist%XM %AM', + emit => '. fist%M %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, fistp => { - op_flags => "R", + state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, - emit => '. fistp%XM %AM', + emit => '. fistp%M %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, # constants fldz => { op_flags => "R|c|K", - irn_flags => "R", - reg_req => { }, + irn_flags => "R", + reg_req => { out => [ "vfp" ] }, emit => '. fldz', attr_type => "ia32_x87_attr_t", + latency => 2, }, fld1 => { op_flags => "R|c|K", - irn_flags => "R", - reg_req => { }, + irn_flags => "R", + reg_req => { out => [ "vfp" ] }, emit => '. fld1', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldpi => { op_flags => "R|c|K", - irn_flags => "R", - reg_req => { }, + irn_flags => "R", + reg_req => { out => [ "vfp" ] }, emit => '. fldpi', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldln2 => { op_flags => "R|c|K", - irn_flags => "R", - reg_req => { }, + irn_flags => "R", + reg_req => { out => [ "vfp" ] }, emit => '. fldln2', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldlg2 => { op_flags => "R|c|K", - irn_flags => "R", - reg_req => { }, + irn_flags => "R", + reg_req => { out => [ "vfp" ] }, emit => '. fldlg2', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldl2t => { op_flags => "R|c|K", - irn_flags => "R", - reg_req => { }, + irn_flags => "R", + reg_req => { out => [ "vfp" ] }, emit => '. fldll2t', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldl2e => { op_flags => "R|c|K", - irn_flags => "R", - reg_req => { }, + irn_flags => "R", + reg_req => { out => [ "vfp" ] }, emit => '. fldl2e', attr_type => "ia32_x87_attr_t", + latency => 2, }, # fxch, fpush, fpop @@ -1944,6 +2337,8 @@ fxch => { cmp_attr => "return 1;", emit => '. fxch %X0', attr_type => "ia32_x87_attr_t", + mode => "mode_ANY", + latency => 1, }, fpush => { @@ -1952,60 +2347,104 @@ fpush => { cmp_attr => "return 1;", emit => '. fld %X0', attr_type => "ia32_x87_attr_t", + mode => "mode_ANY", + latency => 1, }, fpushCopy => { - op_flags => "R", reg_req => { in => [ "vfp"], out => [ "vfp" ] }, cmp_attr => "return 1;", emit => '. fld %X0', attr_type => "ia32_x87_attr_t", + latency => 1, }, fpop => { - op_flags => "R|K", + op_flags => "K", reg_req => { }, cmp_attr => "return 1;", emit => '. fstp %X0', attr_type => "ia32_x87_attr_t", + mode => "mode_ANY", + latency => 1, +}, + +ffreep => { + op_flags => "K", + reg_req => { }, + cmp_attr => "return 1;", + emit => '. ffreep %X0', + attr_type => "ia32_x87_attr_t", + mode => "mode_ANY", + latency => 1, +}, + +emms => { + op_flags => "K", + reg_req => { }, + cmp_attr => "return 1;", + emit => '. emms', + attr_type => "ia32_x87_attr_t", + mode => "mode_ANY", + latency => 3, +}, + +femms => { + op_flags => "K", + reg_req => { }, + cmp_attr => "return 1;", + emit => '. femms', + attr_type => "ia32_x87_attr_t", + mode => "mode_ANY", + latency => 3, }, # compare -fcomJmp => { - op_flags => "L|X|Y", +FucomFnstsw => { reg_req => { }, + emit => ". fucom %X1\n". + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, -fcompJmp => { - op_flags => "L|X|Y", +FucompFnstsw => { reg_req => { }, + emit => ". fucomp %X1\n". + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, -fcomppJmp => { - op_flags => "L|X|Y", +FucomppFnstsw => { reg_req => { }, + emit => ". fucompp\n". + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, -fcomrJmp => { - op_flags => "L|X|Y", +Fucomi => { reg_req => { }, + emit => '. fucomi %X1', attr_type => "ia32_x87_attr_t", + latency => 1, }, -fcomrpJmp => { - op_flags => "L|X|Y", +Fucompi => { reg_req => { }, + emit => '. fucompi %X1', attr_type => "ia32_x87_attr_t", + latency => 1, }, -fcomrppJmp => { - op_flags => "L|X|Y", +FtstFnstsw => { reg_req => { }, + emit => ". ftst\n". + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, @@ -2028,14 +2467,17 @@ xxLoad => { emit => '. movdqu %D0, %AM', outs => [ "res", "M" ], units => [ "SSE" ], + latency => 1, }, xxStore => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "xmm", "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "xmm" ] }, + ins => [ "base", "index", "mem", "val" ], emit => '. movdqu %binop', units => [ "SSE" ], + latency => 1, mode => "mode_M", }, @@ -2048,3 +2490,28 @@ unless ($return = do $my_script_name) { warn "couldn't do $my_script_name: $!" unless defined $return; warn "couldn't run $my_script_name" unless $return; } + +# Transform some attributes +foreach my $op (keys(%nodes)) { + my $node = $nodes{$op}; + my $op_attr_init = $node->{op_attr_init}; + + if(defined($op_attr_init)) { + $op_attr_init .= "\n\t"; + } else { + $op_attr_init = ""; + } + + if(!defined($node->{latency})) { + if($op =~ m/^l_/) { + $node->{latency} = 0; + } else { + die("Latency missing for op $op"); + } + } + $op_attr_init .= "attr->latency = ".$node->{latency} . ";"; + + $node->{op_attr_init} = $op_attr_init; +} + +print "";