X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=dc0c49d8e41c5c6c1f9a6b28b54bef0bbae8a38d;hb=90f2e217df8deecb71f08af6bb28f9decd6795b0;hp=ce821aa6b30072df9d4ccd6d2d319acadb6f1dab;hpb=26707e47403f59f1fa8d1df66dde1a6856068524;p=libfirm

diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl
index ce821aa6b..dc0c49d8e 100644
--- a/ir/be/ia32/ia32_spec.pl
+++ b/ir/be/ia32/ia32_spec.pl
@@ -110,10 +110,10 @@ $arch = "ia32";
 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
 %reg_classes = (
 	gp => [
-		{ name => "eax", type => 1 },
 		{ name => "edx", type => 1 },
-		{ name => "ebx", type => 2 },
 		{ name => "ecx", type => 1 },
+		{ name => "eax", type => 1 },
+		{ name => "ebx", type => 2 },
 		{ name => "esi", type => 2 },
 		{ name => "edi", type => 2 },
 		{ name => "ebp", type => 2 },
@@ -131,7 +131,7 @@ $arch = "ia32";
 		{ name => "mm5", type => 4 },
 		{ name => "mm6", type => 4 },
 		{ name => "mm7", type => 4 },
-		{ mode => "mode_E" }
+		{ mode => "mode_E", flags => "manual_ra" }
 	],
 	xmm => [
 		{ name => "xmm0", type => 1 },
@@ -168,72 +168,18 @@ $arch = "ia32";
 		{ name => "st5", realname => "st(5)", type => 4 },
 		{ name => "st6", realname => "st(6)", type => 4 },
 		{ name => "st7", realname => "st(7)", type => 4 },
-		{ mode => "mode_E" }
+		{ mode => "mode_E", flags => "manual_ra" }
 	],
 	fp_cw => [	# the floating point control word
-		{ name => "fpcw", type => 4 | 32},
-		{ mode => "mode_fpcw" }
+		{ name => "fpcw", type => 4|32 },
+		{ mode => "mode_fpcw", flags => "manual_ra|state" }
 	],
 	flags => [
-		{ name => "eflags", type => 4 },
-		{ mode => "mode_Iu" }
-	],
-	fp_sw => [
-		{ name => "fpsw", type => 4 },
-		{ mode => "mode_Hu" }
+		{ name => "eflags", type => 0 },
+		{ mode => "mode_Iu", flags => "manual_ra" }
 	],
 ); # %reg_classes
 
-%flags = (
-	CF  => { reg => "eflags", bit => 0 },
-	PF  => { reg => "eflags", bit => 2 },
-	AF  => { reg => "eflags", bit => 4 },
-	ZF  => { reg => "eflags", bit => 6 },
-	SF  => { reg => "eflags", bit => 7 },
-	TF  => { reg => "eflags", bit => 8 },
-	IF  => { reg => "eflags", bit => 9 },
-	DF  => { reg => "eflags", bit => 10 },
-	OF  => { reg => "eflags", bit => 11 },
-	IOPL0 => { reg => "eflags", bit => 12 },
-	IOPL1 => { reg => "eflags", bit => 13 },
-	NT  => { reg => "eflags", bit => 14 },
-	RF  => { reg => "eflags", bit => 16 },
-	VM  => { reg => "eflags", bit => 17 },
-	AC  => { reg => "eflags", bit => 18 },
-	VIF => { reg => "eflags", bit => 19 },
-	VIP => { reg => "eflags", bit => 20 },
-	ID  => { reg => "eflags", bit => 21 },
-
-	FP_IE => { reg => "fpsw", bit => 0 },
-	FP_DE => { reg => "fpsw", bit => 1 },
-	FP_ZE => { reg => "fpsw", bit => 2 },
-	FP_OE => { reg => "fpsw", bit => 3 },
-	FP_UE => { reg => "fpsw", bit => 4 },
-	FP_PE => { reg => "fpsw", bit => 5 },
-	FP_SF => { reg => "fpsw", bit => 6 },
-	FP_ES => { reg => "fpsw", bit => 7 },
-	FP_C0 => { reg => "fpsw", bit => 8 },
-	FP_C1 => { reg => "fpsw", bit => 9 },
-	FP_C2 => { reg => "fpsw", bit => 10 },
-	FP_TOP0 => { reg => "fpsw", bit => 11 },
-	FP_TOP1 => { reg => "fpsw", bit => 12 },
-	FP_TOP2 => { reg => "fpsw", bit => 13 },
-	FP_C3 => { reg => "fpsw", bit => 14 },
-	FP_B  => { reg => "fpsw", bit => 15 },
-
-	FP_IM => { reg => "fpcw", bit => 0 },
-	FP_DM => { reg => "fpcw", bit => 1 },
-	FP_ZM => { reg => "fpcw", bit => 2 },
-	FP_OM => { reg => "fpcw", bit => 3 },
-	FP_UM => { reg => "fpcw", bit => 4 },
-	FP_PM => { reg => "fpcw", bit => 5 },
-	FP_PC0 => { reg => "fpcw", bit => 8 },
-	FP_PC1 => { reg => "fpcw", bit => 9 },
-	FP_RC0 => { reg => "fpcw", bit => 10 },
-	FP_RC1 => { reg => "fpcw", bit => 11 },
-	FP_X  => { reg => "fpcw", bit => 12 }
-); # %flags
-
 %cpu = (
 	GP     => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
 	SSE    => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
@@ -247,39 +193,49 @@ $arch = "ia32";
 ); # vliw
 
 %emit_templates = (
-	S0 => "${arch}_emit_source_register(env, node, 0);",
-	S1 => "${arch}_emit_source_register(env, node, 1);",
-	S2 => "${arch}_emit_source_register(env, node, 2);",
-	S3 => "${arch}_emit_source_register(env, node, 3);",
-	S4 => "${arch}_emit_source_register(env, node, 4);",
-	S5 => "${arch}_emit_source_register(env, node, 5);",
-	D0 => "${arch}_emit_dest_register(env, node, 0);",
-	D1 => "${arch}_emit_dest_register(env, node, 1);",
-	D2 => "${arch}_emit_dest_register(env, node, 2);",
-	D3 => "${arch}_emit_dest_register(env, node, 3);",
-	D4 => "${arch}_emit_dest_register(env, node, 4);",
-	D5 => "${arch}_emit_dest_register(env, node, 5);",
-	X0 => "${arch}_emit_x87_name(env, node, 0);",
-	X1 => "${arch}_emit_x87_name(env, node, 1);",
-	X2 => "${arch}_emit_x87_name(env, node, 2);",
-	C  => "${arch}_emit_immediate(env, node);",
-	SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
+	S0 => "${arch}_emit_source_register(node, 0);",
+	S1 => "${arch}_emit_source_register(node, 1);",
+	S2 => "${arch}_emit_source_register(node, 2);",
+	S3 => "${arch}_emit_source_register(node, 3);",
+	S4 => "${arch}_emit_source_register(node, 4);",
+	S5 => "${arch}_emit_source_register(node, 5);",
+	SB1 => "${arch}_emit_8bit_source_register_or_immediate(node, 1);",
+	SB2 => "${arch}_emit_8bit_source_register_or_immediate(node, 2);",
+	SB3 => "${arch}_emit_8bit_source_register_or_immediate(node, 3);",
+	SI0 => "${arch}_emit_source_register_or_immediate(node, 0);",
+	SI1 => "${arch}_emit_source_register_or_immediate(node, 1);",
+	SI2 => "${arch}_emit_source_register_or_immediate(node, 2);",
+	SI3 => "${arch}_emit_source_register_or_immediate(node, 3);",
+	D0 => "${arch}_emit_dest_register(node, 0);",
+	D1 => "${arch}_emit_dest_register(node, 1);",
+	D2 => "${arch}_emit_dest_register(node, 2);",
+	D3 => "${arch}_emit_dest_register(node, 3);",
+	D4 => "${arch}_emit_dest_register(node, 4);",
+	D5 => "${arch}_emit_dest_register(node, 5);",
+	DB0 => "${arch}_emit_8bit_dest_register(node, 0);",
+	X0 => "${arch}_emit_x87_register(node, 0);",
+	X1 => "${arch}_emit_x87_register(node, 1);",
+	X2 => "${arch}_emit_x87_register(node, 2);",
+	SE => "${arch}_emit_extend_suffix(get_ia32_ls_mode(node));",
 	ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
-	           ia32_emit_mode_suffix(env, node);",
-	M  => "${arch}_emit_mode_suffix(env, node);",
-	XM => "${arch}_emit_x87_mode_suffix(env, node);",
-	XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
-	XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
-	AM => "${arch}_emit_am(env, node);",
-	unop0 => "${arch}_emit_unop(env, node, 0);",
-	unop1 => "${arch}_emit_unop(env, node, 1);",
-	unop2 => "${arch}_emit_unop(env, node, 2);",
-	unop3 => "${arch}_emit_unop(env, node, 3);",
-	unop4 => "${arch}_emit_unop(env, node, 4);",
-	DAM0  => "${arch}_emit_am_or_dest_register(env, node, 0);",
-	DAM1  => "${arch}_emit_am_or_dest_register(env, node, 0);",
-	binop => "${arch}_emit_binop(env, node);",
-	x87_binop => "${arch}_emit_x87_binop(env, node);",
+	           ia32_emit_mode_suffix(node);",
+	M  => "${arch}_emit_mode_suffix(node);",
+	XM => "${arch}_emit_x87_mode_suffix(node);",
+	XXM => "${arch}_emit_xmm_mode_suffix(node);",
+	XSD => "${arch}_emit_xmm_mode_suffix_s(node);",
+	AM => "${arch}_emit_am(node);",
+	unop0 => "${arch}_emit_unop(node, 0);",
+	unop1 => "${arch}_emit_unop(node, 1);",
+	unop2 => "${arch}_emit_unop(node, 2);",
+	unop3 => "${arch}_emit_unop(node, 3);",
+	unop4 => "${arch}_emit_unop(node, 4);",
+	unop5 => "${arch}_emit_unop(node, 5);",
+	DAM0  => "${arch}_emit_am_or_dest_register(node, 0);",
+	DAM1  => "${arch}_emit_am_or_dest_register(node, 1);",
+	binop => "${arch}_emit_binop(node, 1);",
+	binop_nores => "${arch}_emit_binop(node, 0);",
+	x87_binop => "${arch}_emit_x87_binop(node);",
+	CMP0  => "${arch}_emit_cmp_suffix_node(node, 0);",
 );
 
 #--------------------------------------------------#
@@ -296,6 +252,39 @@ $arch = "ia32";
 $default_attr_type = "ia32_attr_t";
 $default_copy_attr = "ia32_copy_attr";
 
+sub ia32_custom_init_attr {
+	my $node = shift;
+	my $name = shift;
+	my $res = "";
+	if(defined($node->{modified_flags})) {
+		$res .= "\tset_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);\n";
+	}
+	if(defined($node->{am})) {
+		my $am = $node->{am};
+		if($am eq "full,binary") {
+			$res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_binary);";
+		} elsif($am eq "full,unary") {
+			$res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_unary);";
+		} elsif($am eq "source,binary") {
+			$res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_binary);";
+		} elsif($am eq "dest,unary") {
+			$res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);";
+		} elsif($am eq "dest,binary") {
+			$res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);";
+		} elsif($am eq "dest,ternary") {
+			$res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_ternary);";
+		} elsif($am eq "source,ternary") {
+			$res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_ternary);";
+		} elsif($am eq "none") {
+			# nothing to do
+		} else {
+			die("Invalid address mode '$am' specified on op $name");
+		}
+	}
+	return $res;
+}
+$custom_init_attr_func = \&ia32_custom_init_attr;
+
 %init_attr = (
 	ia32_attr_t     => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);",
 	ia32_x87_attr_t =>
@@ -322,6 +311,7 @@ $default_copy_attr = "ia32_copy_attr";
 
 $mode_xmm     = "mode_E";
 $mode_gp      = "mode_Iu";
+$mode_flags   = "mode_Iu";
 $mode_fpcw    = "mode_fpcw";
 $status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
 $fpcw_flags   = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
@@ -372,67 +362,66 @@ ProduceVal => {
 
 # commutative operations
 
-# NOTE:
-# All nodes supporting Addressmode have 5 INs:
-# 1 - base    r1 == NoReg in case of no AM or no base
-# 2 - index   r2 == NoReg in case of no AM or no index
-# 3 - op1     r3 == always present
-# 4 - op2     r4 == NoReg in case of immediate operation
-# 5 - mem     NoMem in case of no AM otherwise it takes the mem from the Load
-
 Add => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
-	ins       => [ "base", "index", "left", "right", "mem" ],
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5", "none", "flags" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	emit      => '. add%M %binop',
+	am        => "full,binary",
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
-Adc => {
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
-	emit      => '. adc%M %binop',
+AddMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => ". add%M %SI3, %AM",
 	units     => [ "GP" ],
-	mode      => $mode_gp,
+	mode      => "mode_M",
 	modified_flags => $status_flags
 },
 
-Add64Bit => {
+AddMem8Bit => {
 	irn_flags => "R",
-	arity     => 4,
-	reg_req   => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
-	emit      => '
-. movl %S0, %D0
-. movl %S1, %D1
-. addl %S2, %D0
-. adcl %S3, %D1
-',
-	outs      => [ "low_res", "high_res" ],
+	reg_req   => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => ". add%M %SB3, %AM",
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
+Adc => {
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right", "eflags" ],
+	emit      => '. adc%M %binop',
+	am        => "full,binary",
 	units     => [ "GP" ],
+	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
 l_Add => {
 	op_flags  => "C",
-	irn_flags => "R",
-	cmp_attr  => "return 1;",
-	arity     => 2,
+	reg_req   => { in => [ "none", "none" ], out => [ "none" ] },
+	ins       => [ "left", "right" ],
 },
 
 l_Adc => {
-	op_flags  => "C",
-	cmp_attr  => "return 1;",
-	arity     => 2,
+	reg_req   => { in => [ "none", "none", "none" ], out => [ "none" ] },
+	ins       => [ "left", "right", "eflags" ],
 },
 
 Mul => {
 	# we should not rematrialize this node. It produces 2 results and has
 	# very strict constrains
-	reg_req   => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
-	emit      => '. mul%M %unop3',
+	reg_req   => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] },
+	ins       => [ "base", "index", "mem", "val_high", "val_low" ],
+	emit      => '. mul%M %unop4',
 	outs      => [ "EAX", "EDX", "M" ],
-	ins       => [ "base", "index", "val_high", "val_low", "mem" ],
+	am        => "source,binary",
 	latency   => 10,
 	units     => [ "GP" ],
 	modified_flags => $status_flags
@@ -449,8 +438,10 @@ l_Mul => {
 
 IMul => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	emit      => '. imul%M %binop',
+	am        => "source,binary",
 	latency   => 5,
 	units     => [ "GP" ],
 	mode      => $mode_gp,
@@ -459,52 +450,115 @@ IMul => {
 
 IMul1OP => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
-	emit      => '. imul%M %unop3',
+	reg_req   => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] },
+	ins       => [ "base", "index", "mem", "val_high", "val_low" ],
+	emit      => '. imul%M %unop4',
 	outs      => [ "EAX", "EDX", "M" ],
-	ins       => [ "base", "index", "val_high", "val_low", "mem" ],
+	am        => "source,binary",
 	latency   => 5,
 	units     => [ "GP" ],
 	modified_flags => $status_flags
 },
 
 l_IMul => {
+	# we should not rematrialize this node. It produces 2 results and has
+	# very strict constrains
 	op_flags  => "C",
 	cmp_attr  => "return 1;",
+	outs      => [ "EAX", "EDX", "M" ],
 	arity     => 2
 },
 
 And => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
+	am        => "full,binary",
 	emit      => '. and%M %binop',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
+AndMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => '. and%M %SI3, %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
+AndMem8Bit => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none",  "eax ebx ecx edx" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => '. and%M %SB3, %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
 Or => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
+	am        => "full,binary",
 	emit      => '. or%M %binop',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
+OrMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => '. or%M %SI3, %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
+OrMem8Bit => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => '. or%M %SB3, %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
 Xor => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
+	am        => "full,binary",
 	emit      => '. xor%M %binop',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
-l_Xor => {
-	op_flags  => "C",
-	cmp_attr  => "return 1;",
-	arity     => 2,
+XorMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => '. xor%M %SI3, %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
+XorMem8Bit => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => '. xor%M %SB3, %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
 	modified_flags => $status_flags
 },
 
@@ -512,55 +566,65 @@ l_Xor => {
 
 Sub => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4", "none", "flags" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
+	am        => "full,binary",
 	emit      => '. sub%M %binop',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
-Sbb => {
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
-	emit      => '. sbb%M %binop',
+SubMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => '. sub%M %SI3, %AM',
 	units     => [ "GP" ],
-	mode      => $mode_gp,
+	mode      => 'mode_M',
 	modified_flags => $status_flags
 },
 
-Sub64Bit => {
+SubMem8Bit => {
 	irn_flags => "R",
-	arity     => 4,
-	reg_req   => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
-	emit      => '
-. movl %S0, %D0
-. movl %S1, %D1
-. subl %S2, %D0
-. sbbl %S3, %D1
-',
-	outs      => [ "low_res", "high_res" ],
+	reg_req   => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => '. sub%M %SB3, %AM',
 	units     => [ "GP" ],
+	mode      => 'mode_M',
+	modified_flags => $status_flags
+},
+
+Sbb => {
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 !in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right", "eflags" ],
+	am        => "full,binary",
+	emit      => '. sbb%M %binop',
+	units     => [ "GP" ],
+	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
 l_Sub => {
-	irn_flags => "R",
-	cmp_attr  => "return 1;",
-	arity     => 2,
+	reg_req   => { in => [ "none", "none" ], out => [ "none" ] },
+	ins       => [ "left", "right" ],
 },
 
 l_Sbb => {
-	cmp_attr  => "return 1;",
-	arity     => 2,
+	reg_req   => { in => [ "none", "none", "none" ], out => [ "none" ] },
+	ins       => [ "left", "right", "eflags" ],
 },
 
 IDiv => {
 	op_flags  => "F|L",
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "edx", "none" ] },
+	ins       => [ "base", "index", "mem", "left_low", "left_high", "right" ],
+	outs      => [ "div_res", "mod_res", "M" ],
 	attr      => "ia32_op_flavour_t dm_flav",
+	am        => "source,ternary",
 	init_attr => "attr->data.op_flav = dm_flav;",
-	emit      => ". idiv%M %unop4",
-	outs      => [ "div_res", "mod_res", "M" ],
+	emit      => ". idiv%M %unop5",
 	latency   => 25,
 	units     => [ "GP" ],
 	modified_flags => $status_flags
@@ -569,11 +633,13 @@ IDiv => {
 Div => {
 	op_flags  => "F|L",
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "edx", "none" ] },
+	ins       => [ "base", "index", "mem", "left_low", "left_high", "right" ],
+	outs      => [ "div_res", "mod_res", "M" ],
 	attr      => "ia32_op_flavour_t dm_flav",
+	am        => "source,ternary",
 	init_attr => "attr->data.op_flav = dm_flav;",
-	emit      => ". div%M %unop4",
-	outs      => [ "div_res", "mod_res", "M" ],
+	emit      => ". div%M %unop5",
 	latency   => 25,
 	units     => [ "GP" ],
 	modified_flags => $status_flags
@@ -581,50 +647,49 @@ Div => {
 
 Shl => {
 	irn_flags => "R",
-	# "in_r3" would be enough as out requirement, but the register allocator
-	# does strange things then and doesn't respect the constraint for in4
-	# if the same value is attached to in3 and in4 (if you have "i << i" in C)
-	reg_req   => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
-	ins       => [ "base", "index", "left", "right", "mem" ],
-	emit      => '. shl%M %binop',
+	reg_req   => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+	ins       => [ "left", "right" ],
+	am        => "dest,binary",
+	emit      => '. shl %SB1, %S0',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
-l_Shl => {
+ShlMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "count" ],
+	emit      => '. shl%M %SB3, %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
+l_ShlDep => {
 	cmp_attr  => "return 1;",
-	arity     => 2
+	# value, cnt, dependency
+	arity     => 3
 },
 
 ShlD => {
-	irn_flags => "R",
+	# FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shl
+	#
 	# Out requirements is: different from all in
 	# This is because, out must be different from LowPart and ShiftCount.
 	# We could say "!ecx !in_r4" but it can occur, that all values live through
-	# this Shift and the only value dying is the ShiftCount. Then there would be
-	# a register missing, as result must not be ecx and all other registers are
-	# occupied. What we should write is "!in_r4 !in_r5", but this is not
-	# supported (and probably never will). So we create artificial interferences
-	# of the result with all inputs, so the spiller can always assure a free
-	# register.
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
-	emit      =>
-'
-if (get_ia32_immop_type(node) == ia32_ImmNone) {
-	if (get_ia32_op_type(node) == ia32_AddrModeD) {
-		. shld%M %%cl, %S3, %AM
-	} else {
-		. shld%M %%cl, %S3, %S2
-	}
-} else {
-	if (get_ia32_op_type(node) == ia32_AddrModeD) {
-		. shld%M %C, %S3, %AM
-	} else {
-		. shld%M %C, %S3, %S2
-	}
-}
-',
+	# this Shift and the only value dying is the ShiftCount. Then there would be a
+	# register missing, as result must not be ecx and all other registers are
+	# occupied. What we should write is "!in_r4 !in_r5", but this is not supported
+	# (and probably never will). So we create artificial interferences of the result
+	# with all inputs, so the spiller can always assure a free register.
+	# reg_req   => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "ecx" ], out => [ "in_r1 !in_r3" ] },
+	ins       => [ "left_high", "left_low", "right" ],
+	am        => "dest,ternary",
+	emit      => '. shld%M %SB2, %S1, %S0',
 	latency   => 6,
 	units     => [ "GP" ],
 	mode      => $mode_gp,
@@ -638,20 +703,34 @@ l_ShlD => {
 
 Shr => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
-	emit      => '. shr%M %binop',
+	reg_req   => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+	ins       => [ "val", "count" ],
+	am        => "dest,binary",
+	emit      => '. shr %SB1, %S0',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
-l_Shr => {
+ShrMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "count" ],
+	emit      => '. shr%M %SB3, %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
+l_ShrDep => {
 	cmp_attr  => "return 1;",
-	arity     => 2
+	# value, cnt, dependency
+	arity     => 3
 },
 
 ShrD => {
-	irn_flags => "R",
+	# FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shr
+	#
 	# Out requirements is: different from all in
 	# This is because, out must be different from LowPart and ShiftCount.
 	# We could say "!ecx !in_r4" but it can occur, that all values live through
@@ -660,22 +739,13 @@ ShrD => {
 	# occupied. What we should write is "!in_r4 !in_r5", but this is not supported
 	# (and probably never will). So we create artificial interferences of the result
 	# with all inputs, so the spiller can always assure a free register.
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
-	emit      => '
-if (get_ia32_immop_type(node) == ia32_ImmNone) {
-	if (get_ia32_op_type(node) == ia32_AddrModeD) {
-		. shrd%M %%cl, %S3, %AM
-	} else {
-		. shrd%M %%cl, %S3, %S2
-	}
-} else {
-	if (get_ia32_op_type(node) == ia32_AddrModeD) {
-		. shrd%M %C, %S3, %AM
-	} else {
-		. shrd%M %C, %S3, %S2
-	}
-}
-',
+	# reg_req   => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "ecx" ], out => [ "in_r1 !in_r3" ] },
+	ins       => [ "left_high", "left_low", "right" ],
+	am        => "dest,ternary",
+	emit      => '. shrd%M %SB2, %S1, %S0',
 	latency   => 6,
 	units     => [ "GP" ],
 	mode      => $mode_gp,
@@ -689,57 +759,105 @@ l_ShrD => {
 
 Sar => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
-	emit      => '. sar%M %binop',
+	reg_req   => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+	ins       => [ "val", "count" ],
+	am        => "dest,binary",
+	emit      => '. sar %SB1, %S0',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
+SarMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "count" ],
+	emit      => '. sar%M %SB3, %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
 l_Sar => {
 	cmp_attr  => "return 1;",
+	# value, cnt
 	arity     => 2
 },
 
+l_SarDep => {
+	cmp_attr  => "return 1;",
+	# value, cnt, dependency
+	arity     => 3
+},
+
 Ror => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
-	emit      => '. ror%M %binop',
+	reg_req   => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+	ins       => [ "val", "count" ],
+	am        => "dest,binary",
+	emit      => '. ror %SB1, %S0',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
+RorMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "count" ],
+	emit      => '. ror%M %SB3, %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
 Rol => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
-	emit      => '. rol%M %binop',
+	reg_req   => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+	ins       => [ "val", "count" ],
+	am        => "dest,binary",
+	emit      => '. rol %SB1, %S0',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
+RolMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "count" ],
+	emit      => '. rol%M %SB3, %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
 # unary operations
 
 Neg => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
-	emit      => '. neg%M %unop2',
-	ins       => [ "base", "index", "val", "mem" ],
+	reg_req   => { in => [ "gp" ], out => [ "in_r1" ] },
+	emit      => '. neg %S0',
+	ins       => [ "val" ],
+	am        => "dest,unary",
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => $status_flags
 },
 
+NegMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem" ],
+	emit      => '. neg%M %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => $status_flags
+},
+
 Minus64Bit => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
-	emit      => '
-. movl %S0, %D0
-. movl %S0, %D1
-. subl %S1, %D0
-. sbbl %S2, %D1
-',
+	reg_req   => { in => [ "gp", "gp" ], out => [ "in_r1", "gp" ] },
 	outs      => [ "low_res", "high_res" ],
 	units     => [ "GP" ],
 	modified_flags => $status_flags
@@ -753,57 +871,165 @@ l_Neg => {
 
 Inc => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
-	emit      => '. inc%M %unop2',
+	reg_req   => { in => [ "gp" ], out => [ "in_r1" ] },
+	am        => "dest,unary",
+	emit      => '. inc %S0',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
 },
 
+IncMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem" ],
+	emit      => '. inc%M %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+},
+
 Dec => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
-	emit      => '. dec%M %unop2',
+	reg_req   => { in => [ "gp" ], out => [ "in_r1" ] },
+	am        => "dest,unary",
+	emit      => '. dec %S0',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
 	modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
 },
 
+DecMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem" ],
+	emit      => '. dec%M %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
+	modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+},
+
 Not => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
-	ins       => [ "base", "index", "val", "mem" ],
-	emit      => '. not%M %unop2',
+	reg_req   => { in => [ "gp" ], out => [ "in_r1" ] },
+	ins       => [ "val" ],
+	am        => "dest,unary",
+	emit      => '. not %S0',
 	units     => [ "GP" ],
 	mode      => $mode_gp,
-	modified_flags => []
+},
+
+NotMem => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem" ],
+	emit      => '. not%M %AM',
+	units     => [ "GP" ],
+	mode      => "mode_M",
 },
 
 # other operations
 
-CondJmp => {
-	state     => "pinned",
-	op_flags  => "L|X|Y",
-	reg_req   => { in  => [ "gp", "gp", "gp", "gp", "none" ],
-	               out => [ "none", "none"] },
-	ins       => [ "base", "index", "left", "right", "mem" ],
-	outs      => [ "false", "true" ],
-	attr      => "long pnc",
-	init_attr => "attr->pn_code = pnc;",
-	latency   => 3,
-	units     => [ "BRANCH" ],
+Cmp => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
+	outs      => [ "eflags" ],
+	am        => "source,binary",
+	emit      => '. cmp%M %binop_nores',
+	attr      => "int flipped, int cmp_unsigned",
+	init_attr => "attr->data.cmp_flipped = flipped;\n".
+	             "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+	latency   => 1,
+	units     => [ "GP" ],
+	mode      => $mode_flags,
+	modified_flags => $status_flags
+},
+
+Cmp8Bit => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
+	outs      => [ "eflags" ],
+	am        => "source,binary",
+	emit      => '. cmpb %binop_nores',
+	attr      => "int flipped, int cmp_unsigned",
+	init_attr => "attr->data.cmp_flipped = flipped;\n".
+	             "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+	latency   => 1,
+	units     => [ "GP" ],
+	mode      => $mode_flags,
+	modified_flags => $status_flags
+},
+
+Test => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
+	outs      => [ "eflags" ],
+	am        => "source,binary",
+	emit      => '. test%M %binop_nores',
+	attr      => "int flipped, int cmp_unsigned",
+	init_attr => "attr->data.cmp_flipped = flipped;\n".
+	             "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+	latency   => 1,
+	units     => [ "GP" ],
+	mode      => $mode_flags,
+	modified_flags => $status_flags
+},
+
+Test8Bit => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
+	outs      => [ "eflags" ],
+	am        => "source,binary",
+	emit      => '. testb %binop_nores',
+	attr      => "int flipped, int cmp_unsigned",
+	init_attr => "attr->data.cmp_flipped = flipped;\n".
+	             "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+	latency   => 1,
+	units     => [ "GP" ],
+	mode      => $mode_flags,
+	modified_flags => $status_flags
+},
+
+Set => {
+	#irn_flags => "R",
+	reg_req   => { in => [ "eflags" ], out => [ "eax ebx ecx edx" ] },
+	ins       => [ "eflags" ],
+	am        => "dest,unary",
+	attr      => "pn_Cmp pnc",
+	init_attr => "attr->pn_code = pnc;\nset_ia32_ls_mode(res, mode_Bu);\n",
+	emit      => '. set%CMP0 %DB0',
+	latency   => 1,
+	units     => [ "GP" ],
+	mode      => $mode_gp,
 },
 
-TestJmp => {
+CMov => {
+	#irn_flags => "R",
+	# (note: leave the false,true order intact to make it compatible with other
+	#  ia32_binary ops)
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "gp", "eflags" ], out => [ "in_r4" ] },
+	ins       => [ "base", "index", "mem", "val_false", "val_true", "eflags" ],
+	am        => "source,binary",
+	attr      => "pn_Cmp pn_code",
+	init_attr => "attr->pn_code = pn_code;",
+	latency   => 1,
+	units     => [ "GP" ],
+	mode      => $mode_gp,
+},
+
+Jcc => {
 	state     => "pinned",
 	op_flags  => "L|X|Y",
-	reg_req   => { in  => [ "gp", "gp", "gp", "gp", "none" ],
-	               out => [ "none", "none" ] },
-	ins       => [ "base", "index", "left", "right", "mem" ],
+	reg_req   => { in  => [ "eflags" ], out => [ "none", "none" ] },
+	ins       => [ "eflags" ],
 	outs      => [ "false", "true" ],
-	attr      => "long pnc",
+	attr      => "pn_Cmp pnc",
 	init_attr => "attr->pn_code = pnc;",
-	latency   => 3,
+	latency   => 2,
 	units     => [ "BRANCH" ],
 },
 
@@ -814,17 +1040,16 @@ SwitchJmp => {
 	latency   => 3,
 	units     => [ "BRANCH" ],
 	mode      => "mode_T",
+	modified_flags => $status_flags
 },
 
 IJmp => {
 	state     => "pinned",
 	op_flags  => "X",
-	reg_req   => { in => [ "gp", "gp", "gp", "none" ] },
-	ins       => [ "base", "index", "val", "mem" ],
-	emit      => '. jmp *%unop2',
+	reg_req   => { in => [ "gp" ] },
+	emit      => '. jmp *%S0',
 	units     => [ "BRANCH" ],
 	mode      => "mode_X",
-	modified_flags => []
 },
 
 Const => {
@@ -832,7 +1057,11 @@ Const => {
 	irn_flags => "R",
 	reg_req   => { out => [ "gp" ] },
 	units     => [ "GP" ],
+	attr      => "ir_entity *symconst, int symconst_sign, long offset",
+	attr_type => "ia32_immediate_attr_t",
 	mode      => $mode_gp,
+# depends on the const and is set in ia32_transform
+# modified_flags => $status_flags
 },
 
 Unknown_GP => {
@@ -912,6 +1141,7 @@ FldCW => {
 	op_flags  => "L|F",
 	state     => "pinned",
 	reg_req   => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
+	ins       => [ "base", "index", "mem" ],
 	latency   => 5,
 	emit      => ". fldcw %AM",
 	mode      => $mode_fpcw,
@@ -922,7 +1152,8 @@ FldCW => {
 FnstCW => {
 	op_flags  => "L|F",
 	state     => "pinned",
-	reg_req   => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "fp_cw" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "fpcw" ],
 	latency   => 5,
 	emit      => ". fnstcw %AM",
 	mode      => "mode_M",
@@ -930,8 +1161,7 @@ FnstCW => {
 },
 
 Cltd => {
-	# we should not rematrialize this node. It produces 2 results and has
-	# very strict constrains
+	# we should not rematrialize this node. It has very strict constraints.
 	reg_req   => { in => [ "eax", "edx" ], out => [ "edx" ] },
 	ins       => [ "val", "globbered" ],
 	emit      => '. cltd',
@@ -973,9 +1203,9 @@ l_Store => {
 Store => {
 	op_flags  => "L|F",
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
-	ins       => [ "base", "index", "val", "mem" ],
-	emit      => '. mov%M %binop',
+	reg_req   => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => '. mov%M %SI3, %AM',
 	latency   => 2,
 	units     => [ "GP" ],
 	mode      => "mode_M",
@@ -984,8 +1214,9 @@ Store => {
 Store8Bit => {
 	op_flags  => "L|F",
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
-	emit      => '. mov%M %binop',
+	reg_req   => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit      => '. mov%M %SB3, %AM',
 	latency   => 2,
 	units     => [ "GP" ],
 	mode      => "mode_M",
@@ -994,31 +1225,34 @@ Store8Bit => {
 Lea => {
 	irn_flags => "R",
 	reg_req   => { in => [ "gp", "gp" ], out => [ "gp" ] },
+	ins       => [ "base", "index" ],
 	emit      => '. leal %AM, %D0',
 	latency   => 2,
 	units     => [ "GP" ],
 	mode      => $mode_gp,
-	modified_flags => [],
+# well this isn't true for Lea, but we often transform Lea back to Add, Inc
+# or Dec, so we set the flag
+	modified_flags => 1,
 },
 
 Push => {
-	reg_req   => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
-	emit      => '. push%M %unop2',
-	ins       => [ "base", "index", "val", "stack", "mem" ],
+	reg_req   => { in => [ "gp", "gp", "none", "gp", "esp" ], out => [ "esp", "none" ] },
+	ins       => [ "base", "index", "mem", "val", "stack" ],
+	emit      => '. push%M %unop3',
 	outs      => [ "stack:I|S", "M" ],
+	am        => "source,binary",
 	latency   => 2,
 	units     => [ "GP" ],
-	modified_flags => [],
 },
 
 Pop => {
-	reg_req   => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "esp" ], out => [ "esp", "gp", "none" ] },
 	emit      => '. pop%M %DAM1',
 	outs      => [ "stack:I|S", "res", "M" ],
-	ins       => [ "base", "index", "stack", "mem" ],
+	ins       => [ "base", "index", "mem", "stack" ],
+	am        => "dest,unary",
 	latency   => 3, # Pop is more expensive than Push on Athlon
 	units     => [ "GP" ],
-	modified_flags => [],
 },
 
 Enter => {
@@ -1039,7 +1273,10 @@ Leave => {
 
 AddSP => {
 	irn_flags => "I",
-	reg_req   => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
+	state     => "pinned",
+	reg_req   => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "in_r4", "none" ] },
+	ins       => [ "base", "index", "mem", "stack", "size" ],
+	am        => "source,binary",
 	emit      => '. addl %binop',
 	outs      => [ "stack:S", "M" ],
 	units     => [ "GP" ],
@@ -1048,7 +1285,10 @@ AddSP => {
 
 SubSP => {
 #irn_flags => "I",
-	reg_req   => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "gp", "none" ] },
+	state     => "pinned",
+	reg_req   => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "in_r4", "gp", "none" ] },
+	ins       => [ "base", "index", "mem", "stack", "size" ],
+	am        => "source,binary",
 	emit      => ". subl %binop\n".
 	             ". movl %%esp, %D1",
 	outs      => [ "stack:I|S", "addr", "M" ],
@@ -1064,11 +1304,9 @@ LdTls => {
 
 # the int instruction
 int => {
-	reg_req   => { in => [ "none" ], out => [ "none" ] },
+	reg_req   => { in => [ "gp" ], out => [ "none" ] },
 	mode      => "mode_M",
-	attr      => "tarval *tv",
-	init_attr => "\tset_ia32_Immop_tarval(res, tv);",
-	emit      => '. int %C',
+	emit      => '. int %SI0',
 	units     => [ "GP" ],
 	cmp_attr  => "return 1;",
 },
@@ -1083,11 +1321,21 @@ int => {
 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
 #-----------------------------------------------------------------------------#
 
+xZero => {
+	irn_flags => "R",
+	reg_req   => { out => [ "xmm" ] },
+	emit      => '. xorp%XSD %D1, %D1',
+	latency   => 3,
+	units     => [ "SSE" ],
+	mode      => "mode_E",
+},
+
 # commutative operations
 
 xAdd => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	emit      => '. add%XXM %binop',
 	latency   => 4,
 	units     => [ "SSE" ],
@@ -1096,7 +1344,8 @@ xAdd => {
 
 xMul => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	emit      => '. mul%XXM %binop',
 	latency   => 4,
 	units     => [ "SSE" ],
@@ -1105,7 +1354,8 @@ xMul => {
 
 xMax => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	emit      => '. max%XXM %binop',
 	latency   => 2,
 	units     => [ "SSE" ],
@@ -1114,7 +1364,8 @@ xMax => {
 
 xMin => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	emit      => '. min%XXM %binop',
 	latency   => 2,
 	units     => [ "SSE" ],
@@ -1123,7 +1374,8 @@ xMin => {
 
 xAnd => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	emit      => '. andp%XSD %binop',
 	latency   => 3,
 	units     => [ "SSE" ],
@@ -1132,7 +1384,8 @@ xAnd => {
 
 xOr => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	emit      => '. orp%XSD %binop',
 	units     => [ "SSE" ],
 	mode      => "mode_E",
@@ -1140,7 +1393,8 @@ xOr => {
 
 xXor => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	emit      => '. xorp%XSD %binop',
 	latency   => 3,
 	units     => [ "SSE" ],
@@ -1151,7 +1405,8 @@ xXor => {
 
 xAndNot => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	emit      => '. andnp%XSD %binop',
 	latency   => 3,
 	units     => [ "SSE" ],
@@ -1160,7 +1415,8 @@ xAndNot => {
 
 xSub => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	emit      => '. sub%XXM %binop',
 	latency   => 4,
 	units     => [ "SSE" ],
@@ -1169,7 +1425,8 @@ xSub => {
 
 xDiv => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4", "none" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5", "none" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
 	outs      => [ "res", "M" ],
 	emit      => '. div%XXM %binop',
 	latency   => 16,
@@ -1178,34 +1435,19 @@ xDiv => {
 
 # other operations
 
-xCmp => {
+Ucomi => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "eflags" ] },
+	ins       => [ "base", "index", "mem", "left", "right" ],
+	outs      => [ "flags" ],
+	am        => "source,binary",
+	attr      => "int flipped",
+	init_attr => "attr->data.cmp_flipped = flipped;",
+	emit      => ' .ucomi%XXM %binop_nores',
 	latency   => 3,
 	units     => [ "SSE" ],
-	mode      => "mode_E",
-},
-
-xCondJmp => {
-	state     => "pinned",
-	op_flags  => "L|X|Y",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
-	ins       => [ "base", "index", "left", "right", "mem" ],
-	outs      => [ "false", "true" ],
-	attr      => "long pnc",
-	init_attr => "attr->pn_code = pnc;",
-	latency   => 5,
-	units     => [ "SSE" ],
-},
-
-xConst => {
-	op_flags  => "c",
-	irn_flags => "R",
-	reg_req   => { out => [ "xmm" ] },
-	emit      => '. mov%XXM %C, %D0',
-	latency   => 2,
-	units     => [ "SSE" ],
-	mode      => "mode_E",
+	mode      => $mode_flags,
+	modified_flags => 1,
 },
 
 # Load / Store
@@ -1214,18 +1456,22 @@ xLoad => {
 	op_flags  => "L|F",
 	state     => "exc_pinned",
 	reg_req   => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
+	ins       => [ "base", "index", "mem" ],
 	emit      => '. mov%XXM %AM, %D0',
+	attr      => "ir_mode *load_mode",
+	init_attr => "attr->ls_mode = load_mode;",
 	outs      => [ "res", "M" ],
-	latency   => 2,
+	latency   => 0,
 	units     => [ "SSE" ],
 },
 
 xStore => {
 	op_flags => "L|F",
 	state    => "exc_pinned",
-	reg_req  => { in => [ "gp", "gp", "xmm", "none" ] },
-	emit     => '. mov%XXM %binop',
-	latency  => 2,
+	reg_req  => { in => [ "gp", "gp", "none", "xmm" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	emit     => '. mov%XXM %S3, %AM',
+	latency  => 0,
 	units    => [ "SSE" ],
 	mode     => "mode_M",
 },
@@ -1233,17 +1479,18 @@ xStore => {
 xStoreSimple => {
 	op_flags => "L|F",
 	state    => "exc_pinned",
-	reg_req  => { in => [ "gp", "gp", "xmm", "none" ] },
-	ins      => [ "base", "index", "val", "mem" ],
-	emit     => '. mov%XXM %S2, %AM',
-	latency  => 2,
+	reg_req  => { in => [ "gp", "gp", "none", "xmm" ] },
+	ins      => [ "base", "index", "mem", "val" ],
+	emit     => '. mov%XXM %S3, %AM',
+	latency  => 0,
 	units    => [ "SSE" ],
 	mode     => "mode_M",
 },
 
 CvtSI2SS => {
 	op_flags => "L|F",
-	reg_req  => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
+	reg_req  => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] },
+	ins      => [ "base", "index", "mem", "val" ],
 	emit     => '. cvtsi2ss %D0, %AM',
 	latency  => 2,
 	units    => [ "SSE" ],
@@ -1252,8 +1499,9 @@ CvtSI2SS => {
 
 CvtSI2SD => {
 	op_flags => "L|F",
-	reg_req  => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
-	emit     => '. cvtsi2sd %unop2',
+	reg_req  => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] },
+	ins      => [ "base", "index", "mem", "val" ],
+	emit     => '. cvtsi2sd %unop3',
 	latency  => 2,
 	units    => [ "SSE" ],
 	mode     => $mode_xmm
@@ -1280,7 +1528,8 @@ CopyB => {
 	reg_req  => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
 	outs     => [ "DST", "SRC", "CNT", "M" ],
 	units    => [ "GP" ],
-	modified_flags => [ "DF" ]
+# we don't care about this flag, so no need to mark this node
+#	modified_flags => [ "DF" ]
 },
 
 CopyB_i => {
@@ -1289,135 +1538,56 @@ CopyB_i => {
 	reg_req  => { in => [ "edi", "esi", "none" ], out => [  "edi", "esi", "none" ] },
 	outs     => [ "DST", "SRC", "M" ],
 	units    => [ "GP" ],
-	modified_flags => [ "DF" ]
+# we don't care about this flag, so no need to mark this node
+#	modified_flags => [ "DF" ]
 },
 
 # Conversions
 
 Conv_I2I => {
-	reg_req  => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
-	units    => [ "GP" ],
-	ins      => [ "base", "index", "val", "mem" ],
-	mode     => $mode_gp,
-	modified_flags => $status_flags
+	state     => "exc_pinned",
+	reg_req   => { in => [ "gp", "gp", "none", "gp" ], out => [ "gp", "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	units     => [ "GP" ],
+	attr      => "ir_mode *smaller_mode",
+	init_attr => "attr->ls_mode = smaller_mode;",
+	mode      => $mode_gp,
 },
 
 Conv_I2I8Bit => {
-	reg_req  => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
-	ins      => [ "base", "index", "val", "mem" ],
-	units    => [ "GP" ],
-	mode     => $mode_gp,
-	modified_flags => $status_flags
+	state     => "exc_pinned",
+	reg_req   => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "gp", "none" ] },
+	ins       => [ "base", "index", "mem", "val" ],
+	units     => [ "GP" ],
+	attr      => "ir_mode *smaller_mode",
+	init_attr => "attr->ls_mode = smaller_mode;",
+	mode      => $mode_gp,
 },
 
 Conv_I2FP => {
-	reg_req  => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] },
+	reg_req  => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm", "none" ] },
+	ins      => [ "base", "index", "mem", "val" ],
 	latency  => 10,
 	units    => [ "SSE" ],
 	mode     => "mode_E",
 },
 
 Conv_FP2I => {
-	reg_req  => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
+	reg_req  => { in => [ "gp", "gp", "none", "xmm" ], out => [ "gp", "none" ] },
+	ins      => [ "base", "index", "mem", "val" ],
 	latency  => 10,
 	units    => [ "SSE" ],
 	mode     => $mode_gp,
 },
 
 Conv_FP2FP => {
-	reg_req  => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
+	reg_req  => { in => [ "gp", "gp", "none", "xmm" ], out => [ "xmm", "none" ] },
+	ins      => [ "base", "index", "mem", "val" ],
 	latency  => 8,
 	units    => [ "SSE" ],
 	mode     => "mode_E",
 },
 
-CmpCMov => {
-	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ], out => [ "in_r7" ] },
-	ins       => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true", "val_false" ],
-	attr      => "pn_Cmp pn_code",
-	init_attr => "attr->pn_code = pn_code;",
-	latency   => 2,
-	units     => [ "GP" ],
-	mode      => $mode_gp,
-},
-
-TestCMov => {
-	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ], out => [ "in_r7" ] },
-	ins       => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true", "val_false" ],
-	attr      => "pn_Cmp pn_code",
-	init_attr => "attr->pn_code = pn_code;",
-	latency   => 2,
-	units     => [ "GP" ],
-	mode      => $mode_gp,
-},
-
-xCmpCMov => {
-	irn_flags => "R",
-	reg_req   => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
-	latency   => 5,
-	units     => [ "SSE" ],
-	mode      => $mode_gp,
-},
-
-vfCmpCMov => {
-	irn_flags => "R",
-	reg_req   => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
-	latency   => 10,
-	units     => [ "VFP" ],
-	mode      => $mode_gp,
-	attr_type => "ia32_x87_attr_t",
-},
-
-CmpSet => {
-	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
-	ins       => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
-	attr      => "pn_Cmp pn_code",
-	init_attr => "attr->pn_code = pn_code;",
-	latency   => 2,
-	units     => [ "GP" ],
-	mode      => $mode_gp,
-},
-
-TestSet => {
-	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
-	ins       => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
-	attr      => "pn_Cmp pn_code",
-	init_attr => "attr->pn_code = pn_code;",
-	latency   => 2,
-	units     => [ "GP" ],
-	mode      => $mode_gp,
-},
-
-xCmpSet => {
-	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
-	latency   => 5,
-	units     => [ "SSE" ],
-	mode      => $mode_gp,
-},
-
-vfCmpSet => {
-	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
-	latency   => 10,
-	units     => [ "VFP" ],
-	mode      => $mode_gp,
-	attr_type => "ia32_x87_attr_t",
-},
-
-vfCMov => {
-	irn_flags => "R",
-	reg_req   => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
-	latency   => 10,
-	units     => [ "VFP" ],
-	mode      => "mode_E",
-	attr_type => "ia32_x87_attr_t",
-},
-
 #----------------------------------------------------------#
 #        _      _               _    __ _             _    #
 #       (_)    | |             | |  / _| |           | |   #
@@ -1434,8 +1604,8 @@ vfCMov => {
 
 vfadd => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
-	ins       => [ "base", "index", "left", "right", "mem", "fpcw" ],
+	reg_req   => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+	ins       => [ "base", "index", "mem", "left", "right", "fpcw" ],
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => "mode_E",
@@ -1444,8 +1614,8 @@ vfadd => {
 
 vfmul => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
-	ins       => [ "base", "index", "left", "right", "mem", "fpcw" ],
+	reg_req   => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+	ins       => [ "base", "index", "mem", "left", "right", "fpcw" ],
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => "mode_E",
@@ -1460,8 +1630,8 @@ l_vfmul => {
 
 vfsub => {
 	irn_flags => "R",
-	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
-	ins       => [ "base", "index", "left", "right", "mem", "fpcw" ],
+	reg_req   => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+	ins       => [ "base", "index", "mem", "left", "right", "fpcw" ],
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => "mode_E",
@@ -1474,8 +1644,8 @@ l_vfsub => {
 },
 
 vfdiv => {
-	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp", "none" ] },
-	ins       => [ "base", "index", "left", "right", "mem", "fpcw" ],
+	reg_req   => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp", "none" ] },
+	ins       => [ "base", "index", "mem", "left", "right", "fpcw" ],
 	outs      => [ "res", "M" ],
 	latency   => 20,
 	units     => [ "VFP" ],
@@ -1489,8 +1659,8 @@ l_vfdiv => {
 },
 
 vfprem => {
-	reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
-	ins       => [ "base", "index", "left", "right", "mem", "fpcw" ],
+	reg_req   => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+	ins       => [ "base", "index", "mem", "left", "right", "fpcw" ],
 	latency   => 20,
 	units     => [ "VFP" ],
 	mode      => "mode_E",
@@ -1530,8 +1700,8 @@ vfld => {
 	reg_req   => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
 	ins       => [ "base", "index", "mem" ],
 	outs      => [ "res", "M" ],
-	attr      => "ir_mode *store_mode",
-	init_attr => "attr->attr.ls_mode = store_mode;",
+	attr      => "ir_mode *load_mode",
+	init_attr => "attr->attr.ls_mode = load_mode;",
 	latency   => 2,
 	units     => [ "VFP" ],
 	attr_type => "ia32_x87_attr_t",
@@ -1540,8 +1710,8 @@ vfld => {
 vfst => {
 	op_flags  => "L|F",
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "vfp", "none" ] },
-	ins       => [ "base", "index", "val", "mem" ],
+	reg_req   => { in => [ "gp", "gp", "none", "vfp" ] },
+	ins       => [ "base", "index", "mem", "val" ],
 	attr      => "ir_mode *store_mode",
 	init_attr => "attr->attr.ls_mode = store_mode;",
 	latency   => 2,
@@ -1570,8 +1740,8 @@ l_vfild => {
 
 vfist => {
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
-	ins       => [ "base", "index", "val", "fpcw", "mem" ],
+	reg_req   => { in => [ "gp", "gp", "none", "vfp", "fpcw" ] },
+	ins       => [ "base", "index", "mem", "val", "fpcw" ],
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => "mode_M",
@@ -1651,29 +1821,32 @@ vfldl2e => {
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfConst => {
-	op_flags  => "c",
-	irn_flags => "R",
-	reg_req   => { out => [ "vfp" ] },
-	latency   => 3,
-	units     => [ "VFP" ],
-	mode      => "mode_E",
-	attr_type => "ia32_x87_attr_t",
-},
-
 # other
 
-vfCondJmp => {
-	state     => "pinned",
-	op_flags  => "L|X|Y",
-	reg_req   => { in => [ "vfp", "vfp" ], out => [ "none", "none", "eax" ] },
+vFucomFnstsw => {
+# we can't allow to rematerialize this node so we don't have
+#  accidently produce Phi(Fucom, Fucom(flipped))
+#	irn_flags => "R",
+	reg_req   => { in => [ "vfp", "vfp" ], out => [ "eax" ] },
 	ins       => [ "left", "right" ],
-	outs      => [ "false", "true", "temp_reg_eax" ],
-	attr      => "long pnc",
-	init_attr => "attr->attr.pn_code = pnc;",
-	latency   => 10,
+	outs      => [ "flags" ],
+	am        => "source,binary",
+	attr      => "int flipped",
+	init_attr => "attr->attr.data.cmp_flipped = flipped;",
+	latency   => 3,
 	units     => [ "VFP" ],
 	attr_type => "ia32_x87_attr_t",
+	mode      => $mode_gp
+},
+
+Sahf => {
+	irn_flags => "R",
+	reg_req   => { in => [ "eax" ], out => [ "eflags" ] },
+	ins       => [ "val" ],
+	outs      => [ "flags" ],
+	emit      => '. sahf',
+	units     => [ "GP" ],
+	mode      => $mode_flags,
 },
 
 #------------------------------------------------------------------------#
@@ -1860,7 +2033,7 @@ fild => {
 	op_flags  => "R",
 	rd_constructor => "NONE",
 	reg_req   => { },
-	emit      => '. fild%XM %AM',
+	emit      => '. fild%M %AM',
 	attr_type => "ia32_x87_attr_t",
 },
 
@@ -1869,7 +2042,7 @@ fist => {
 	state     => "exc_pinned",
 	rd_constructor => "NONE",
 	reg_req   => { },
-	emit      => '. fist%XM %AM',
+	emit      => '. fist%M %AM',
 	mode      => "mode_M",
 	attr_type => "ia32_x87_attr_t",
 },
@@ -1879,7 +2052,7 @@ fistp => {
 	state     => "exc_pinned",
 	rd_constructor => "NONE",
 	reg_req   => { },
-	emit      => '. fistp%XM %AM',
+	emit      => '. fistp%M %AM',
 	mode      => "mode_M",
 	attr_type => "ia32_x87_attr_t",
 },
@@ -1971,48 +2144,60 @@ fpushCopy => {
 },
 
 fpop => {
-	op_flags  => "R|K",
+	op_flags  => "K",
 	reg_req   => { },
 	cmp_attr  => "return 1;",
 	emit      => '. fstp %X0',
 	attr_type => "ia32_x87_attr_t",
 },
 
-# compare
-
-fcomJmp => {
-	op_flags  => "L|X|Y",
+ffreep => {
+	op_flags  => "K",
 	reg_req   => { },
+	cmp_attr  => "return 1;",
+	emit      => '. ffreep %X0',
 	attr_type => "ia32_x87_attr_t",
 },
 
-fcompJmp => {
-	op_flags  => "L|X|Y",
+emms => {
+	op_flags  => "K",
 	reg_req   => { },
+	cmp_attr  => "return 1;",
+	emit      => '. emms',
 	attr_type => "ia32_x87_attr_t",
 },
 
-fcomppJmp => {
-	op_flags  => "L|X|Y",
+femms => {
+	op_flags  => "K",
 	reg_req   => { },
+	cmp_attr  => "return 1;",
+	emit      => '. femms',
 	attr_type => "ia32_x87_attr_t",
 },
 
-fcomrJmp => {
-	op_flags  => "L|X|Y",
+# compare
+
+FucomFnstsw => {
+	op_flags  => "R",
 	reg_req   => { },
+	emit      => ". fucom %X1\n".
+	             ". fnstsw",
 	attr_type => "ia32_x87_attr_t",
 },
 
-fcomrpJmp => {
-	op_flags  => "L|X|Y",
+FucompFnstsw => {
+	op_flags  => "R",
 	reg_req   => { },
+	emit      => ". fucomp %X1\n".
+	             ". fnstsw",
 	attr_type => "ia32_x87_attr_t",
 },
 
-fcomrppJmp => {
-	op_flags  => "L|X|Y",
+FucomppFnstsw => {
+	op_flags  => "R",
 	reg_req   => { },
+	emit      => ". fucompp\n".
+	             ". fnstsw",
 	attr_type => "ia32_x87_attr_t",
 },
 
@@ -2041,7 +2226,8 @@ xxLoad => {
 xxStore => {
 	op_flags => "L|F",
 	state    => "exc_pinned",
-	reg_req  => { in => [ "gp", "gp", "xmm", "none" ] },
+	reg_req  => { in => [ "gp", "gp", "none", "xmm" ] },
+	ins      => [ "base", "index", "mem", "val" ],
 	emit     => '. movdqu %binop',
 	units    => [ "SSE" ],
 	mode     => "mode_M",