X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=bd89dbd5340cfe6d6338c9b13840c28a8e854c57;hb=506bcd96022448ff34d1ba875d2bae787799186d;hp=e3309944c2a4caf1e56c3e97302e5bae7056ba5d;hpb=323267da3fcfb2a3029b19e17008645055d86590;p=libfirm diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index e3309944c..bd89dbd53 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -5,8 +5,9 @@ # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...) $arch = "ia32"; -# this string marks the beginning of a comment in emit -$comment_string = "/*"; +# this strings mark the beginning and the end of a comment in emit +$comment_string = "/*"; +$comment_string_end = "*/"; # the number of additional opcodes you want to register #$additional_opcodes = 0; @@ -104,82 +105,81 @@ $comment_string = "/*"; # 1 - caller save (register must be saved by the caller of a function) # 2 - callee save (register must be saved by the called function) # 4 - ignore (do not assign this register) +# 8 - emitter can choose an arbitrary register of this class +# 16 - the register is a virtual one # NOTE: Last entry of each class is the largest Firm-Mode a register can hold %reg_classes = ( - "gp" => [ - { "name" => "eax", "type" => 1 }, - { "name" => "edx", "type" => 1 }, - { "name" => "ebx", "type" => 2 }, - { "name" => "ecx", "type" => 1 }, - { "name" => "esi", "type" => 2 }, - { "name" => "edi", "type" => 2 }, -# { "name" => "r11", "type" => 1 }, -# { "name" => "r12", "type" => 1 }, -# { "name" => "r13", "type" => 1 }, -# { "name" => "r14", "type" => 1 }, -# { "name" => "r15", "type" => 1 }, -# { "name" => "r16", "type" => 1 }, -# { "name" => "r17", "type" => 1 }, -# { "name" => "r18", "type" => 1 }, -# { "name" => "r19", "type" => 1 }, -# { "name" => "r20", "type" => 1 }, -# { "name" => "r21", "type" => 1 }, -# { "name" => "r22", "type" => 1 }, -# { "name" => "r23", "type" => 1 }, -# { "name" => "r24", "type" => 1 }, -# { "name" => "r25", "type" => 1 }, -# { "name" => "r26", "type" => 1 }, -# { "name" => "r27", "type" => 1 }, -# { "name" => "r28", "type" => 1 }, -# { "name" => "r29", "type" => 1 }, -# { "name" => "r30", "type" => 1 }, -# { "name" => "r31", "type" => 1 }, -# { "name" => "r32", "type" => 1 }, - { "name" => "ebp", "type" => 2 }, - { "name" => "esp", "type" => 4 }, - { "name" => "gp_NOREG", "type" => 2 | 4 }, # we need a dummy register for NoReg nodes - { "name" => "gp_UKNWN", "type" => 2 | 4 | 8 }, # we need a dummy register for Unknown nodes - { "mode" => "mode_P" } - ], - "xmm" => [ - { "name" => "xmm0", "type" => 1 }, - { "name" => "xmm1", "type" => 1 }, - { "name" => "xmm2", "type" => 1 }, - { "name" => "xmm3", "type" => 1 }, - { "name" => "xmm4", "type" => 1 }, - { "name" => "xmm5", "type" => 1 }, - { "name" => "xmm6", "type" => 1 }, - { "name" => "xmm7", "type" => 1 }, - { "name" => "xmm_NOREG", "type" => 2 | 4 }, # we need a dummy register for NoReg nodes - { "name" => "xmm_UKNWN", "type" => 2 | 4 | 8 }, # we need a dummy register for Unknown nodes - { "mode" => "mode_D" } - ], - "vfp" => [ - { "name" => "vf0", "type" => 1 }, - { "name" => "vf1", "type" => 1 }, - { "name" => "vf2", "type" => 1 }, - { "name" => "vf3", "type" => 1 }, - { "name" => "vf4", "type" => 1 }, - { "name" => "vf5", "type" => 1 }, - { "name" => "vf6", "type" => 1 }, - { "name" => "vf7", "type" => 1 }, - { "name" => "vfp_NOREG", "type" => 2 | 4 }, # we need a dummy register for NoReg nodes - { "name" => "vfp_UKNWN", "type" => 2 | 4 | 8 }, # we need a dummy register for Unknown nodes - { "mode" => "mode_E" } - ], - "st" => [ - { "name" => "st0", "type" => 1 }, - { "name" => "st1", "type" => 1 }, - { "name" => "st2", "type" => 1 }, - { "name" => "st3", "type" => 1 }, - { "name" => "st4", "type" => 1 }, - { "name" => "st5", "type" => 1 }, - { "name" => "st6", "type" => 1 }, - { "name" => "st7", "type" => 1 }, - { "mode" => "mode_E" } - ] + "gp" => [ + { "name" => "eax", "type" => 1 }, + { "name" => "edx", "type" => 1 }, + { "name" => "ebx", "type" => 2 }, + { "name" => "ecx", "type" => 1 }, + { "name" => "esi", "type" => 2 }, + { "name" => "edi", "type" => 2 }, + { "name" => "ebp", "type" => 2 }, + { "name" => "esp", "type" => 4 }, + { "name" => "gp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes + { "name" => "gp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes + { "mode" => "mode_P" } + ], + "xmm" => [ + { "name" => "xmm0", "type" => 1 }, + { "name" => "xmm1", "type" => 1 }, + { "name" => "xmm2", "type" => 1 }, + { "name" => "xmm3", "type" => 1 }, + { "name" => "xmm4", "type" => 1 }, + { "name" => "xmm5", "type" => 1 }, + { "name" => "xmm6", "type" => 1 }, + { "name" => "xmm7", "type" => 1 }, + { "name" => "xmm_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes + { "name" => "xmm_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes + { "mode" => "mode_D" } + ], + "vfp" => [ + { "name" => "vf0", "type" => 1 | 16 }, + { "name" => "vf1", "type" => 1 | 16 }, + { "name" => "vf2", "type" => 1 | 16 }, + { "name" => "vf3", "type" => 1 | 16 }, + { "name" => "vf4", "type" => 1 | 16 }, + { "name" => "vf5", "type" => 1 | 16 }, + { "name" => "vf6", "type" => 1 | 16 }, + { "name" => "vf7", "type" => 1 | 16 }, + { "name" => "vfp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes + { "name" => "vfp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes + { "mode" => "mode_E" } + ], + "st" => [ + { "name" => "st0", "type" => 1 }, + { "name" => "st1", "type" => 1 }, + { "name" => "st2", "type" => 1 }, + { "name" => "st3", "type" => 1 }, + { "name" => "st4", "type" => 1 }, + { "name" => "st5", "type" => 1 }, + { "name" => "st6", "type" => 1 }, + { "name" => "st7", "type" => 1 }, + { "mode" => "mode_E" } + ], + "fp_cw" => [ # the floating point control word + { "name" => "fpcw", "type" => 0 }, + { "mode" => "mode_Hu" }, + ], ); # %reg_classes +%cpu = ( + "ALU" => [ 1, "ALU1", "ALU2", "ALU3", "ALU4" ], + "MUL" => [ 1, "MUL1", "MUL2" ], + "SSE" => [ 1, "SSE1", "SSE2" ], + "FPU" => [ 1, "FPU1" ], + "MEM" => [ 1, "MEM1", "MEM2" ], + "BRANCH" => [ 1, "BRANCH1", "BRANCH2" ], + "DUMMY" => [ 1, "DUMMY1", "DUMMY2", "DUMMY3", "DUMMY4" ] +); # %cpu + +%vliw = ( + "bundle_size" => 3, + "bundels_per_cycle" => 2 +); # vliw + #--------------------------------------------------# # _ # # (_) # @@ -191,6 +191,8 @@ $comment_string = "/*"; # |_| # #--------------------------------------------------# +$default_cmp_attr = "return ia32_compare_immop_attr(attr_a, attr_b);"; + %operands = ( ); @@ -220,31 +222,44 @@ $comment_string = "/*"; "Add" => { "irn_flags" => "R", "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU", "MEM" ], }, "AddC" => { "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU", "MEM" ], +}, + +"Add64Bit" => { + "irn_flags" => "R", + "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry", + "arity" => 4, + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] }, + "emit" => ' +. mov %D1, %S1 /* mov a_l into assigned l_res register */ +. mov %D2, %S2 /* mov a_h into assigned h_res register */ +. add %D1, %S3 /* a_l + b_l */ +. adc %D2, %S4 /* a_h + b_h + carry */ +', + "outs" => [ "low_res", "high_res" ], + "units" => [ "ALU", "MEM" ], }, "l_Add" => { "op_flags" => "C", "irn_flags" => "R", - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b", "arity" => 2, }, "l_AddC" => { "op_flags" => "C", - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry", "arity" => 2, }, @@ -253,18 +268,18 @@ $comment_string = "/*"; # we should not rematrialize this node. It produces 2 results and has # very strict constrains "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] }, "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */', "outs" => [ "EAX", "EDX", "M" ], "latency" => 10, + "units" => [ "MUL" ], }, "l_MulS" => { # we should not rematrialize this node. It produces 2 results and has # very strict constrains "op_flags" => "C", - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b", "outs" => [ "EAX", "EDX", "M" ], "arity" => 2 @@ -273,16 +288,15 @@ $comment_string = "/*"; "Mul" => { "irn_flags" => "R", "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */', - "outs" => [ "res", "M" ], "latency" => 5, + "units" => [ "MUL" ], }, "l_Mul" => { "op_flags" => "C", - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b", "arity" => 2 }, @@ -292,43 +306,40 @@ $comment_string = "/*"; # we should not rematrialize this node. It produces 2 results and has # very strict constrains "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] }, "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */', "outs" => [ "EAX", "EDX", "M" ], "latency" => 5, + "units" => [ "MUL" ], }, "And" => { "irn_flags" => "R", "comment" => "construct And: And(a, b) = And(b, a) = a AND b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU" ], }, "Or" => { "irn_flags" => "R", "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU" ], }, "Eor" => { "irn_flags" => "R", "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU" ], }, "l_Eor" => { "op_flags" => "C", - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b", "arity" => 2 }, @@ -347,6 +358,7 @@ $comment_string = "/*"; } ', "latency" => 2, + "units" => [ "ALU" ], }, "Min" => { @@ -363,6 +375,7 @@ $comment_string = "/*"; } ', "latency" => 2, + "units" => [ "ALU" ], }, # not commutative operations @@ -370,29 +383,42 @@ $comment_string = "/*"; "Sub" => { "irn_flags" => "R", "comment" => "construct Sub: Sub(a, b) = a - b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU" ], }, "SubC" => { "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] }, "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU" ], +}, + +"Sub64Bit" => { + "irn_flags" => "R", + "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow", + "arity" => 4, + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] }, + "emit" => ' +. mov %D1, %S1 /* mov a_l into assigned l_res register */ +. mov %D2, %S2 /* mov a_h into assigned h_res register */ +. sub %D1, %S3 /* a_l - b_l */ +. sbb %D2, %S4 /* a_h - b_h - borrow */ +', + "outs" => [ "low_res", "high_res" ], + "units" => [ "ALU" ], }, "l_Sub" => { "irn_flags" => "R", - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered Sub: Sub(a, b) = a - b", "arity" => 2, }, "l_SubC" => { - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry", "arity" => 2, }, @@ -414,19 +440,19 @@ $comment_string = "/*"; ', "outs" => [ "div_res", "mod_res", "M" ], "latency" => 25, + "units" => [ "ALU" ], }, "Shl" => { "irn_flags" => "R", "comment" => "construct Shl: Shl(a, b) = a << b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU1", "SSE1" ], }, "l_Shl" => { - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered Shl: Shl(a, b) = a << b", "arity" => 2 }, @@ -434,8 +460,15 @@ $comment_string = "/*"; "ShlD" => { "irn_flags" => "R", "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] }, + # Out requirements is: different from all in + # This is because, out must be different from LowPart and ShiftCount. + # We could say "!ecx !in_r4" but it can occur, that all values live through + # this Shift and the only value dying is the ShiftCount. Then there would be a + # register missing, as result must not be ecx and all other registers are + # occupied. What we should write is "!in_r4 !in_r5", but this is not supported + # (and probably never will). So we create artificial interferences of the result + # with all inputs, so the spiller can always assure a free register. + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] }, "emit" => ' if (get_ia32_immop_type(n) == ia32_ImmNone) { @@ -455,12 +488,12 @@ else { } } ', - "outs" => [ "res", "M" ], "latency" => 6, + "units" => [ "ALU1", "SSE1" ], }, "l_ShlD" => { - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)", "arity" => 3 }, @@ -468,14 +501,13 @@ else { "Shr" => { "irn_flags" => "R", "comment" => "construct Shr: Shr(a, b) = a >> b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU1", "SSE1" ], }, "l_Shr" => { - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered Shr: Shr(a, b) = a << b", "arity" => 2 }, @@ -483,8 +515,15 @@ else { "ShrD" => { "irn_flags" => "R", "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] }, + # Out requirements is: different from all in + # This is because, out must be different from LowPart and ShiftCount. + # We could say "!ecx !in_r4" but it can occur, that all values live through + # this Shift and the only value dying is the ShiftCount. Then there would be a + # register missing, as result must not be ecx and all other registers are + # occupied. What we should write is "!in_r4 !in_r5", but this is not supported + # (and probably never will). So we create artificial interferences of the result + # with all inputs, so the spiller can always assure a free register. + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] }, "emit" => ' if (get_ia32_immop_type(n) == ia32_ImmNone) { @@ -504,12 +543,12 @@ else { } } ', - "outs" => [ "res", "M" ], "latency" => 6, + "units" => [ "ALU1", "SSE1" ], }, "l_ShrD" => { - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)", "arity" => 3 }, @@ -517,14 +556,13 @@ else { "Shrs" => { "irn_flags" => "R", "comment" => "construct Shrs: Shrs(a, b) = a >> b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU1", "SSE1" ], }, "l_Shrs" => { - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered Shrs: Shrs(a, b) = a << b", "arity" => 2 }, @@ -532,19 +570,17 @@ else { "RotR" => { "irn_flags" => "R", "comment" => "construct RotR: RotR(a, b) = a ROTR b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU1", "SSE1" ], }, "RotL" => { "irn_flags" => "R", "comment" => "construct RotL: RotL(a, b) = a ROTL b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "ALU1", "SSE1" ], }, # unary operations @@ -552,14 +588,29 @@ else { "Minus" => { "irn_flags" => "R", "comment" => "construct Minus: Minus(a) = -a", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */', - "outs" => [ "res", "M" ], + "units" => [ "ALU" ], +}, + +"Minus64Bit" => { + "irn_flags" => "R", + "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow", + "arity" => 4, + "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] }, + "emit" => ' +. mov %D1, %S1 /* l_res */ +. mov %D2, %S1 /* h_res */ +. sub %D1, %S2 /* 0 - a_l -> low_res */ +. sbb %D2, %S3 /* 0 - a_h - borrow -> high_res */ +', + "outs" => [ "low_res", "high_res" ], + "units" => [ "ALU" ], }, + "l_Minus" => { - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered Minus: Minus(a) = -a", "arity" => 1, }, @@ -567,28 +618,25 @@ else { "Inc" => { "irn_flags" => "R", "comment" => "construct Increment: Inc(a) = a++", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */', - "outs" => [ "res", "M" ], + "units" => [ "ALU" ], }, "Dec" => { "irn_flags" => "R", "comment" => "construct Decrement: Dec(a) = a--", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */', - "outs" => [ "res", "M" ], + "units" => [ "ALU" ], }, "Not" => { "irn_flags" => "R", "comment" => "construct Not: Not(a) = !a", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */', - "outs" => [ "res", "M" ], + "units" => [ "ALU" ], }, # other operations @@ -596,50 +644,81 @@ else { "CondJmp" => { "op_flags" => "L|X|Y", "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] }, "outs" => [ "false", "true" ], "latency" => 3, + "units" => [ "BRANCH" ], }, "TestJmp" => { "op_flags" => "L|X|Y", "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL", "reg_req" => { "in" => [ "gp", "gp" ] }, - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "outs" => [ "false", "true" ], "latency" => 3, + "units" => [ "BRANCH" ], }, "CJmpAM" => { "op_flags" => "L|X|Y", "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] }, "outs" => [ "false", "true" ], + "units" => [ "BRANCH" ], }, "CJmp" => { "op_flags" => "L|X|Y", "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp" ] }, + "units" => [ "BRANCH" ], }, "SwitchJmp" => { "op_flags" => "L|X|Y", "comment" => "construct switch", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] }, "latency" => 3, + "units" => [ "BRANCH" ], }, "Const" => { "op_flags" => "c", "irn_flags" => "R", "comment" => "represents an integer constant", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] }, + "reg_req" => { "out" => [ "gp" ] }, + "units" => [ "ALU" ], +}, + +"ChangeCW" => { + "irn_flags" => "R", + "comment" => "change floating point control word", + "reg_req" => { "out" => [ "fp_cw" ] }, + "mode" => "mode_Hu", + "latency" => 3, + "units" => [ "ALU" ], +}, + +"FldCW" => { + "op_flags" => "L|F", + "state" => "exc_pinned", + "comment" => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg", + "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp_cw" ] }, + "latency" => 5, + "emit" => ". fldcw %ia32_emit_am /* FldCW(%A1) -> %D1 */", + "mode" => "mode_Hu", + "units" => [ "MEM" ], +}, + +"FstCW" => { + "op_flags" => "L|F", + "state" => "exc_pinned", + "comment" => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg", + "reg_req" => { "in" => [ "gp", "gp", "fp_cw", "none" ] }, + "latency" => 5, + "emit" => ". fstcw %ia32_emit_am /* FstCW(%A3) -> %A1 */", + "mode" => "mode_M", + "units" => [ "MEM" ], }, "Cdq" => { @@ -649,6 +728,7 @@ else { "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] }, "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */', "outs" => [ "EAX", "EDX" ], + "units" => [ "ALU" ], }, # Load / Store @@ -657,7 +737,6 @@ else { "op_flags" => "L|F", "state" => "exc_pinned", "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] }, "latency" => 3, "emit" => @@ -669,11 +748,12 @@ else { } ', "outs" => [ "res", "M" ], + "units" => [ "MEM" ], }, "l_Load" => { "op_flags" => "L|F", - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg", "outs" => [ "res", "M" ], "arity" => 2, @@ -681,42 +761,42 @@ else { "l_Store" => { "op_flags" => "L|F", - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "state" => "exc_pinned", "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val", "arity" => 3, - "outs" => [ "M" ], + "mode" => "mode_M", }, "Store" => { "op_flags" => "L|F", "state" => "exc_pinned", "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] }, "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */', - "outs" => [ "M" ], "latency" => 3, + "units" => [ "MEM" ], + "mode" => "mode_M", }, "Store8Bit" => { "op_flags" => "L|F", "state" => "exc_pinned", "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx gp_NOREG", "none" ] }, + "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] }, "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */', - "outs" => [ "M" ], "latency" => 3, + "units" => [ "MEM" ], + "mode" => "mode_M", }, "Lea" => { "irn_flags" => "R", "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] }, "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */', "latency" => 2, + "units" => [ "ALU" ], }, "Push" => { @@ -725,6 +805,7 @@ else { "emit" => '. push %ia32_emit_unop /* PUSH(%A1) */', "outs" => [ "stack:I|S", "M" ], "latency" => 3, + "units" => [ "MEM" ], }, "Pop" => { @@ -734,6 +815,7 @@ else { "emit" => '. pop %ia32_emit_unop /* POP(%A1) */', "outs" => [ "res", "stack:I|S", "M" ], "latency" => 4, + "units" => [ "MEM" ], }, "Enter" => { @@ -742,6 +824,7 @@ else { "emit" => '. enter /* Enter */', "outs" => [ "frame:I", "stack:I|S", "M" ], "latency" => 15, + "units" => [ "MEM" ], }, "Leave" => { @@ -750,6 +833,7 @@ else { "emit" => '. leave /* Leave */', "outs" => [ "frame:I", "stack:I|S", "M" ], "latency" => 3, + "units" => [ "MEM" ], }, "AddSP" => { @@ -757,6 +841,7 @@ else { "comment" => "allocate space on stack", "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] }, "outs" => [ "stack:S", "M" ], + "units" => [ "ALU" ], }, "SubSP" => { @@ -764,12 +849,14 @@ else { "comment" => "free space on stack", "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] }, "outs" => [ "stack:S", "M" ], + "units" => [ "ALU" ], }, "LdTls" => { "irn_flags" => "R", "comment" => "get the TLS base address", "reg_req" => { "out" => [ "gp" ] }, + "units" => [ "MEM" ], }, @@ -788,70 +875,63 @@ else { "xAdd" => { "irn_flags" => "R", "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], "latency" => 4, + "units" => [ "SSE" ], }, "xMul" => { "irn_flags" => "R", "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], "latency" => 4, + "units" => [ "SSE" ], }, "xMax" => { "irn_flags" => "R", "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], "latency" => 2, + "units" => [ "SSE" ], }, "xMin" => { "irn_flags" => "R", "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], "latency" => 2, + "units" => [ "SSE" ], }, "xAnd" => { "irn_flags" => "R", "comment" => "construct SSE And: And(a, b) = a AND b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], "latency" => 3, + "units" => [ "SSE" ], }, "xOr" => { "irn_flags" => "R", "comment" => "construct SSE Or: Or(a, b) = a OR b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], + "units" => [ "SSE" ], }, "xEor" => { "irn_flags" => "R", "comment" => "construct SSE Eor: Eor(a, b) = a XOR b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], "latency" => 3, + "units" => [ "SSE" ], }, # not commutative operations @@ -859,31 +939,29 @@ else { "xAndNot" => { "irn_flags" => "R", "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] }, "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */', - "outs" => [ "res", "M" ], "latency" => 3, + "units" => [ "SSE" ], }, "xSub" => { "irn_flags" => "R", "comment" => "construct SSE Sub: Sub(a, b) = a - b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */', - "outs" => [ "res", "M" ], "latency" => 4, + "units" => [ "SSE" ], }, "xDiv" => { "irn_flags" => "R", "comment" => "construct SSE Div: Div(a, b) = a / b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] }, - "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */', "outs" => [ "res", "M" ], + "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */', "latency" => 16, + "units" => [ "SSE" ], }, # other operations @@ -892,27 +970,27 @@ else { "irn_flags" => "R", "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] }, - "outs" => [ "res", "M" ], "latency" => 3, + "units" => [ "SSE" ], }, "xCondJmp" => { "op_flags" => "L|X|Y", "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] }, "outs" => [ "false", "true" ], "latency" => 5, + "units" => [ "SSE" ], }, "xConst" => { "op_flags" => "c", "irn_flags" => "R", "comment" => "represents a SSE constant", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] }, + "reg_req" => { "out" => [ "xmm" ] }, "emit" => '. movs%M %D1, %C /* Load fConst into register */', "latency" => 2, + "units" => [ "SSE" ], }, # Load / Store @@ -921,46 +999,46 @@ else { "op_flags" => "L|F", "state" => "exc_pinned", "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] }, "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */', "outs" => [ "res", "M" ], "latency" => 2, + "units" => [ "SSE" ], }, "xStore" => { "op_flags" => "L|F", "state" => "exc_pinned", "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] }, "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */', - "outs" => [ "M" ], - "latency" => 2, + "latency" => 2, + "units" => [ "MEM" ], + "mode" => "mode_M", }, "xStoreSimple" => { "op_flags" => "L|F", "state" => "exc_pinned", "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "xmm", "none" ] }, "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */', - "outs" => [ "M" ], - "latency" => 2, + "latency" => 2, + "units" => [ "MEM" ], + "mode" => "mode_M", }, "l_X87toSSE" => { "op_flags" => "L|F", "comment" => "construct: transfer a value from x87 FPU into a SSE register", - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "arity" => 3, }, "l_SSEtoX87" => { "op_flags" => "L|F", "comment" => "construct: transfer a value from SSE register to x87 FPU", - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "arity" => 3, }, @@ -969,11 +1047,11 @@ else { "irn_flags" => "I", "state" => "exc_pinned", "comment" => "store ST0 onto stack", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "none" ] }, + "reg_req" => { "in" => [ "gp", "gp", "none" ] }, "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */', - "outs" => [ "M" ], "latency" => 4, + "units" => [ "MEM" ], + "mode" => "mode_M", }, "SetST0" => { @@ -981,11 +1059,11 @@ else { "irn_flags" => "I", "state" => "exc_pinned", "comment" => "load ST0 from stack", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] }, "emit" => '. fld %ia32_emit_am /* load ST0 from stack */', "outs" => [ "res", "M" ], "latency" => 2, + "units" => [ "MEM" ], }, # CopyB @@ -996,55 +1074,51 @@ else { "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)", "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] }, "outs" => [ "DST", "SRC", "CNT", "M" ], + "units" => [ "MEM" ], }, "CopyB_i" => { "op_flags" => "F|H", "state" => "pinned", "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] }, "outs" => [ "DST", "SRC", "M" ], + "units" => [ "MEM" ], }, # Conversions "Conv_I2I" => { "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] }, - "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", "comment" => "construct Conv Int -> Int", - "outs" => [ "res", "M" ], + "units" => [ "ALU" ], }, "Conv_I2I8Bit" => { "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] }, - "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", "comment" => "construct Conv Int -> Int", - "outs" => [ "res", "M" ], + "units" => [ "ALU" ], }, "Conv_I2FP" => { "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] }, - "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", "comment" => "construct Conv Int -> Floating Point", - "outs" => [ "res", "M" ], "latency" => 10, + "units" => [ "SSE" ], }, "Conv_FP2I" => { "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] }, - "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", "comment" => "construct Conv Floating Point -> Int", - "outs" => [ "res", "M" ], "latency" => 10, + "units" => [ "SSE" ], }, "Conv_FP2FP" => { "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] }, - "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", "comment" => "construct Conv Floating Point -> Floating Point", - "outs" => [ "res", "M" ], "latency" => 8, + "units" => [ "SSE" ], }, "CmpCMov" => { @@ -1052,6 +1126,7 @@ else { "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }, "latency" => 2, + "units" => [ "ALU" ], }, "PsiCondCMov" => { @@ -1059,6 +1134,7 @@ else { "comment" => "check if Psi condition tree evaluates to true and move result accordingly", "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] }, "latency" => 2, + "units" => [ "ALU" ], }, "xCmpCMov" => { @@ -1066,6 +1142,7 @@ else { "comment" => "construct Conditional Move: SSE Compare + int CMov ", "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }, "latency" => 5, + "units" => [ "SSE" ], }, "vfCmpCMov" => { @@ -1073,14 +1150,15 @@ else { "comment" => "construct Conditional Move: x87 Compare + int CMov", "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }, "latency" => 10, + "units" => [ "FPU" ], }, "CmpSet" => { "irn_flags" => "R", "comment" => "construct Set: Set(sel) == sel ? 1 : 0", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] }, - "outs" => [ "res", "M" ], "latency" => 2, + "units" => [ "ALU" ], }, "PsiCondSet" => { @@ -1088,22 +1166,23 @@ else { "comment" => "check if Psi condition tree evaluates to true and set result accordingly", "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] }, "latency" => 2, + "units" => [ "ALU" ], }, "xCmpSet" => { "irn_flags" => "R", "comment" => "construct Set: SSE Compare + int Set", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] }, - "outs" => [ "res", "M" ], "latency" => 5, + "units" => [ "SSE" ], }, "vfCmpSet" => { "irn_flags" => "R", "comment" => "construct Set: x87 Compare + int Set", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] }, - "outs" => [ "res", "M" ], "latency" => 10, + "units" => [ "FPU" ], }, "vfCMov" => { @@ -1111,6 +1190,7 @@ else { "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b", "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }, "latency" => 10, + "units" => [ "FPU" ], }, #----------------------------------------------------------# @@ -1130,24 +1210,22 @@ else { "vfadd" => { "irn_flags" => "R", "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, - "outs" => [ "res", "M" ], "latency" => 4, + "units" => [ "FPU" ], }, "vfmul" => { "irn_flags" => "R", "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, - "outs" => [ "res", "M" ], "latency" => 4, + "units" => [ "FPU" ], }, "l_vfmul" => { "op_flags" => "C", - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b", "arity" => 2, }, @@ -1155,37 +1233,50 @@ else { "vfsub" => { "irn_flags" => "R", "comment" => "virtual fp Sub: Sub(a, b) = a - b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, - "outs" => [ "res", "M" ], "latency" => 4, + "units" => [ "FPU" ], }, "l_vfsub" => { - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b", "arity" => 2, }, "vfdiv" => { "comment" => "virtual fp Div: Div(a, b) = a / b", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, "outs" => [ "res", "M" ], "latency" => 20, + "units" => [ "FPU" ], }, "l_vfdiv" => { - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "lowered virtual fp Div: Div(a, b) = a / b", "arity" => 2, }, +"vfprem" => { + "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)", + "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, + "latency" => 20, + "units" => [ "FPU" ], +}, + +"l_vfprem" => { + "cmp_attr" => "return 1;", + "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)", + "arity" => 2, +}, + "vfabs" => { "irn_flags" => "R", "comment" => "virtual fp Abs: Abs(a) = |a|", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, "latency" => 2, + "units" => [ "FPU" ], }, "vfchs" => { @@ -1193,6 +1284,7 @@ else { "comment" => "virtual fp Chs: Chs(a) = -a", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, "latency" => 2, + "units" => [ "FPU" ], }, "vfsin" => { @@ -1200,6 +1292,7 @@ else { "comment" => "virtual fp Sin: Sin(a) = sin(a)", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, "latency" => 150, + "units" => [ "FPU" ], }, "vfcos" => { @@ -1207,6 +1300,7 @@ else { "comment" => "virtual fp Cos: Cos(a) = cos(a)", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, "latency" => 150, + "units" => [ "FPU" ], }, "vfsqrt" => { @@ -1214,6 +1308,7 @@ else { "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, "latency" => 30, + "units" => [ "FPU" ], }, # virtual Load and Store @@ -1222,34 +1317,34 @@ else { "op_flags" => "L|F", "state" => "exc_pinned", "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] }, "outs" => [ "res", "M" ], "latency" => 2, + "units" => [ "FPU" ], }, "vfst" => { "op_flags" => "L|F", "state" => "exc_pinned", "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] }, - "outs" => [ "M" ], "latency" => 2, + "units" => [ "FPU" ], + "mode" => "mode_M", }, # Conversions "vfild" => { "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] }, "outs" => [ "res", "M" ], "latency" => 4, + "units" => [ "FPU" ], }, "l_vfild" => { - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg", "outs" => [ "res", "M" ], "arity" => 2, @@ -1257,17 +1352,17 @@ else { "vfist" => { "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] }, - "outs" => [ "M" ], "latency" => 4, + "units" => [ "FPU" ], + "mode" => "mode_M", }, "l_vfist" => { - "cmp_attr" => " return 1;\n", + "cmp_attr" => "return 1;", "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val", - "outs" => [ "M" ], "arity" => 3, + "mode" => "mode_M", }, @@ -1278,6 +1373,7 @@ else { "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg", "reg_req" => { "out" => [ "vfp" ] }, "latency" => 4, + "units" => [ "FPU" ], }, "vfld1" => { @@ -1285,6 +1381,7 @@ else { "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg", "reg_req" => { "out" => [ "vfp" ] }, "latency" => 4, + "units" => [ "FPU" ], }, "vfldpi" => { @@ -1292,6 +1389,7 @@ else { "comment" => "virtual fp Load pi: Ld pi -> reg", "reg_req" => { "out" => [ "vfp" ] }, "latency" => 4, + "units" => [ "FPU" ], }, "vfldln2" => { @@ -1299,6 +1397,7 @@ else { "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg", "reg_req" => { "out" => [ "vfp" ] }, "latency" => 4, + "units" => [ "FPU" ], }, "vfldlg2" => { @@ -1306,6 +1405,7 @@ else { "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg", "reg_req" => { "out" => [ "vfp" ] }, "latency" => 4, + "units" => [ "FPU" ], }, "vfldl2t" => { @@ -1313,6 +1413,7 @@ else { "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg", "reg_req" => { "out" => [ "vfp" ] }, "latency" => 4, + "units" => [ "FPU" ], }, "vfldl2e" => { @@ -1320,6 +1421,7 @@ else { "comment" => "virtual fp Load ld e: Ld ld e -> reg", "reg_req" => { "out" => [ "vfp" ] }, "latency" => 4, + "units" => [ "FPU" ], }, "vfConst" => { @@ -1327,9 +1429,9 @@ else { "irn_flags" => "R", "init_attr" => " set_ia32_ls_mode(res, mode);", "comment" => "represents a virtual floating point constant", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] }, + "reg_req" => { "out" => [ "vfp" ] }, "latency" => 3, + "units" => [ "FPU" ], }, # other @@ -1337,10 +1439,10 @@ else { "vfCondJmp" => { "op_flags" => "L|X|Y", "comment" => "represents a virtual floating point compare", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] }, "outs" => [ "false", "true", "temp_reg_eax" ], "latency" => 10, + "units" => [ "FPU" ], }, #------------------------------------------------------------------------# @@ -1417,6 +1519,24 @@ else { "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */', }, +"fprem" => { + "op_flags" => "R", + "rd_constructor" => "NONE", + "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)", + "reg_req" => { }, + "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 */', +}, + +# this node is just here, to keep the simulator running +# we can omit this when a fprem simulation function exists +"fpremp" => { + "op_flags" => "R", + "rd_constructor" => "NONE", + "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)", + "reg_req" => { }, + "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 WITH POP */', +}, + "fdiv" => { "op_flags" => "R", "rd_constructor" => "NONE", @@ -1507,6 +1627,7 @@ else { "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val", "reg_req" => { }, "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */', + "mode" => "mode_M", }, "fstp" => { @@ -1516,6 +1637,7 @@ else { "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val", "reg_req" => { }, "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */', + "mode" => "mode_M", }, # Conversions @@ -1534,6 +1656,7 @@ else { "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val", "reg_req" => { }, "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */', + "mode" => "mode_M", }, "fistp" => { @@ -1542,6 +1665,7 @@ else { "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val", "reg_req" => { }, "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */', + "mode" => "mode_M", }, # constants @@ -1550,7 +1674,7 @@ else { "op_flags" => "R|c", "irn_flags" => "R", "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg", - "reg_req" => { }, + "reg_req" => { "out" => [ "vfp" ] }, "emit" => '. fldz /* x87 0.0 -> %D1 */', }, @@ -1558,7 +1682,7 @@ else { "op_flags" => "R|c", "irn_flags" => "R", "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg", - "reg_req" => { }, + "reg_req" => { "out" => [ "vfp" ] }, "emit" => '. fld1 /* x87 1.0 -> %D1 */', }, @@ -1566,7 +1690,7 @@ else { "op_flags" => "R|c", "irn_flags" => "R", "comment" => "x87 fp Load pi: Ld pi -> reg", - "reg_req" => { }, + "reg_req" => { "out" => [ "vfp" ] }, "emit" => '. fldpi /* x87 pi -> %D1 */', }, @@ -1574,7 +1698,7 @@ else { "op_flags" => "R|c", "irn_flags" => "R", "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg", - "reg_req" => { }, + "reg_req" => { "out" => [ "vfp" ] }, "emit" => '. fldln2 /* x87 ln(2) -> %D1 */', }, @@ -1582,7 +1706,7 @@ else { "op_flags" => "R|c", "irn_flags" => "R", "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg", - "reg_req" => { }, + "reg_req" => { "out" => [ "vfp" ] }, "emit" => '. fldlg2 /* x87 log(2) -> %D1 */', }, @@ -1590,7 +1714,7 @@ else { "op_flags" => "R|c", "irn_flags" => "R", "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg", - "reg_req" => { }, + "reg_req" => { "out" => [ "vfp" ] }, "emit" => '. fldll2t /* x87 ld(10) -> %D1 */', }, @@ -1598,7 +1722,7 @@ else { "op_flags" => "R|c", "irn_flags" => "R", "comment" => "x87 fp Load ld e: Ld ld e -> reg", - "reg_req" => { }, + "reg_req" => { "out" => [ "vfp" ] }, "emit" => '. fldl2e /* x87 ld(e) -> %D1 */', }, @@ -1607,35 +1731,43 @@ else { "irn_flags" => "R", "rd_constructor" => "NONE", "comment" => "represents a x87 constant", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "out" => [ "st" ] }, + "reg_req" => { "out" => [ "vfp" ] }, "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */', }, # fxch, fpush, fpop # Note that it is NEVER allowed to do CSE on these nodes +# Moreover, note the virtual register requierements! "fxch" => { "op_flags" => "R|K", "comment" => "x87 stack exchange", - "reg_req" => { "in" => [ "st"], "out" => [ "st" ] }, - "cmp_attr" => " return 1;\n", + "reg_req" => { }, + "cmp_attr" => "return 1;", "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */', }, "fpush" => { + "op_flags" => "R|K", + "comment" => "x87 stack push", + "reg_req" => {}, + "cmp_attr" => "return 1;", + "emit" => '. fld %X1 /* x87 push %X1 */', +}, + +"fpushCopy" => { "op_flags" => "R", "comment" => "x87 stack push", - "reg_req" => { "in" => [ "st"], "out" => [ "st" ] }, - "cmp_attr" => " return 1;\n", + "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, + "cmp_attr" => "return 1;", "emit" => '. fld %X1 /* x87 push %X1 */', }, "fpop" => { "op_flags" => "R|K", "comment" => "x87 stack pop", - "reg_req" => { "out" => [ "st" ] }, - "cmp_attr" => " return 1;\n", + "reg_req" => { }, + "cmp_attr" => "return 1;", "emit" => '. fstp %X1 /* x87 pop %X1 */', }, @@ -1644,42 +1776,36 @@ else { "fcomJmp" => { "op_flags" => "L|X|Y", "comment" => "floating point compare", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { }, }, "fcompJmp" => { "op_flags" => "L|X|Y", "comment" => "floating point compare and pop", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { }, }, "fcomppJmp" => { "op_flags" => "L|X|Y", "comment" => "floating point compare and pop twice", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { }, }, "fcomrJmp" => { "op_flags" => "L|X|Y", "comment" => "floating point compare reverse", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { }, }, "fcomrpJmp" => { "op_flags" => "L|X|Y", "comment" => "floating point compare reverse and pop", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { }, }, "fcomrppJmp" => { "op_flags" => "L|X|Y", "comment" => "floating point compare reverse and pop twice", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { }, },