X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=a996025fbe24f8db5fae0dc3483b2a4e4620584d;hb=a61c3426415a95aea3e7ba1444d97782c471e681;hp=27ad5cd5a312dbb8236f4a669ae0a89404fcc106;hpb=1752786900095fecb07aa28fa6eeb75e0e3f8d1a;p=libfirm

diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl
index 27ad5cd5a..a996025fb 100644
--- a/ir/be/ia32/ia32_spec.pl
+++ b/ir/be/ia32/ia32_spec.pl
@@ -69,6 +69,9 @@ $comment_string = "/*";
 #        for i = 1 .. arity: ir_node *op_i
 #        ir_mode *mode
 #
+# outs:  if a node defines more than one output, the names of the projections
+#        nodes having outs having automatically the mode mode_T
+#
 # comment: OPTIONAL comment for the node constructor
 #
 # rd_constructor: for every operation there will be a
@@ -101,6 +104,28 @@ $comment_string = "/*";
             { "name" => "ecx", "type" => 1 },
             { "name" => "esi", "type" => 2 },
             { "name" => "edi", "type" => 2 },
+#            { "name" => "r11", "type" => 1 },
+#            { "name" => "r12", "type" => 1 },
+#            { "name" => "r13", "type" => 1 },
+#            { "name" => "r14", "type" => 1 },
+#            { "name" => "r15", "type" => 1 },
+#            { "name" => "r16", "type" => 1 },
+#            { "name" => "r17", "type" => 1 },
+#            { "name" => "r18", "type" => 1 },
+#            { "name" => "r19", "type" => 1 },
+#            { "name" => "r20", "type" => 1 },
+#            { "name" => "r21", "type" => 1 },
+#            { "name" => "r22", "type" => 1 },
+#            { "name" => "r23", "type" => 1 },
+#            { "name" => "r24", "type" => 1 },
+#            { "name" => "r25", "type" => 1 },
+#            { "name" => "r26", "type" => 1 },
+#            { "name" => "r27", "type" => 1 },
+#            { "name" => "r28", "type" => 1 },
+#            { "name" => "r29", "type" => 1 },
+#            { "name" => "r30", "type" => 1 },
+#            { "name" => "r31", "type" => 1 },
+#            { "name" => "r32", "type" => 1 },
             { "name" => "ebp", "type" => 2 },
             { "name" => "esp", "type" => 4 },
             { "name" => "gp_NOREG", "type" => 6 },  # we need a dummy register for NoReg nodes
@@ -142,8 +167,6 @@ $comment_string = "/*";
             { "name" => "st5", "type" => 1 },
             { "name" => "st6", "type" => 1 },
             { "name" => "st7", "type" => 1 },
-            { "name" => "st_NOREG", "type" => 6 },  # we need a dummy register for NoReg nodes
-            { "name" => "st_UKNWN", "type" => 6 },  # we need a dummy register for Unknown nodes
 			{ "mode" => "mode_E" }
           ]
 ); # %reg_classes
@@ -159,6 +182,9 @@ $comment_string = "/*";
 #                                      |_|         #
 #--------------------------------------------------#
 
+%operands = (
+);
+
 %nodes = (
 
 #-----------------------------------------------------------------#
@@ -187,15 +213,59 @@ $comment_string = "/*";
   "comment"   => "construct Add: Add(a, b) = Add(b, a) = a + b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
+  "emit"      => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
+},
+
+"AddC" => {
+  "comment"   => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+  "emit"      => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
+},
+
+"l_Add" => {
+  "op_flags"  => "C",
+  "irn_flags" => "R",
+  "comment"   => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
+  "arity"     => 2,
+},
+
+"l_AddC" => {
+  "op_flags"  => "C",
+  "comment"   => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
+  "arity"     => 2,
+},
+
+"MulS" => {
+  "comment"   => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
+  "emit"      => '. mul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
+  "outs"      => [ "EAX", "EDX", "M" ],
+},
+
+"l_MulS" => {
+  "op_flags"  => "C",
+  "comment"   => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
+  "outs"      => [ "EAX", "EDX", "M" ],
+  "arity"     => 2
 },
 
 "Mul" => {
-  "irn_flags" => "A",
+  "irn_flags" => "R",
   "comment"   => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */'
+  "emit"      => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
+  "outs"      => [ "res", "M" ],
+},
+
+"l_Mul" => {
+  "op_flags"  => "C",
+  "comment"   => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
+  "arity"     => 2
 },
 
 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
@@ -203,7 +273,8 @@ $comment_string = "/*";
   "comment"   => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
-  "emit"      => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */'
+  "emit"      => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */',
+  "outs"      => [ "EAX", "EDX", "M" ],
 },
 
 "And" => {
@@ -211,7 +282,8 @@ $comment_string = "/*";
   "comment"   => "construct And: And(a, b) = And(b, a) = a AND b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */'
+  "emit"      => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 "Or" => {
@@ -219,7 +291,8 @@ $comment_string = "/*";
   "comment"   => "construct Or: Or(a, b) = Or(b, a) = a OR b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */'
+  "emit"      => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 "Eor" => {
@@ -227,7 +300,14 @@ $comment_string = "/*";
   "comment"   => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */'
+  "emit"      => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
+  "outs"      => [ "res", "M" ],
+},
+
+"l_Eor" => {
+  "op_flags"  => "C",
+  "comment"   => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
+  "arity"     => 2
 },
 
 "Max" => {
@@ -260,16 +340,6 @@ $comment_string = "/*";
 '
 },
 
-"CMov" => {
-  "irn_flags" => "R",
-  "comment"   => "construct Mux: Mux(sel, a, b) == sel ? a : b",
-  "reg_req"   => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
-  "emit"      =>
-'. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */
-. cmovne %D1, %S3 /* sel == true -> return %S3 */
-'
-},
-
 # not commutative operations
 
 "Sub" => {
@@ -277,7 +347,27 @@ $comment_string = "/*";
   "comment"   => "construct Sub: Sub(a, b) = a - b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */'
+  "emit"      => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
+},
+
+"SubC" => {
+  "comment"   => "construct Sub with Carry: SubC(a, b) = a - b - carry",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+  "emit"      => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
+},
+
+"l_Sub" => {
+  "irn_flags" => "R",
+  "comment"   => "construct lowered Sub: Sub(a, b) = a - b",
+  "arity"     => 2,
+},
+
+"l_SubC" => {
+  "comment"   => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
+  "arity"     => 2,
 },
 
 "DivMod" => {
@@ -294,7 +384,8 @@ $comment_string = "/*";
   else {
 4.  div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
   }
-'
+',
+  "outs"      => [ "div_res", "mod_res", "M" ],
 },
 
 "Shl" => {
@@ -302,7 +393,45 @@ $comment_string = "/*";
   "comment"   => "construct Shl: Shl(a, b) = a << b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
-  "emit"      => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */'
+  "emit"      => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
+  "outs"      => [ "res", "M" ],
+},
+
+"l_Shl" => {
+  "comment"   => "construct lowered Shl: Shl(a, b) = a << b",
+  "arity"     => 2
+},
+
+"ShlD" => {
+  "irn_flags" => "R",
+  "comment"   => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
+  "emit"      =>
+'
+if (get_ia32_immop_type(n) == ia32_ImmNone) {
+  if (get_ia32_op_type(n) == ia32_AddrModeD) {
+4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
+  }
+  else {
+4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
+  }
+}
+else {
+  if (get_ia32_op_type(n) == ia32_AddrModeD) {
+4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
+  }
+  else {
+4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
+  }
+}
+',
+  "outs"      => [ "res", "M" ],
+},
+
+"l_ShlD" => {
+  "comment"   => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
+  "arity"     => 3
 },
 
 "Shr" => {
@@ -310,7 +439,45 @@ $comment_string = "/*";
   "comment"   => "construct Shr: Shr(a, b) = a >> b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
-  "emit"      => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */'
+  "emit"      => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
+  "outs"      => [ "res", "M" ],
+},
+
+"l_Shr" => {
+  "comment"   => "construct lowered Shr: Shr(a, b) = a << b",
+  "arity"     => 2
+},
+
+"ShrD" => {
+  "irn_flags" => "R",
+  "comment"   => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r5" ] },
+  "emit"      =>
+'
+if (get_ia32_immop_type(n) == ia32_ImmNone) {
+  if (get_ia32_op_type(n) == ia32_AddrModeD) {
+4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
+  }
+  else {
+4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
+  }
+}
+else {
+  if (get_ia32_op_type(n) == ia32_AddrModeD) {
+4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
+  }
+  else {
+4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
+  }
+}
+',
+  "outs"      => [ "res", "M" ],
+},
+
+"l_ShrD" => {
+  "comment"   => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
+  "arity"     => 3
 },
 
 "Shrs" => {
@@ -318,7 +485,13 @@ $comment_string = "/*";
   "comment"   => "construct Shrs: Shrs(a, b) = a >> b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
-  "emit"      => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */'
+  "emit"      => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
+  "outs"      => [ "res", "M" ],
+},
+
+"l_Shrs" => {
+  "comment"   => "construct lowered Shrs: Shrs(a, b) = a << b",
+  "arity"     => 2
 },
 
 "RotR" => {
@@ -326,7 +499,8 @@ $comment_string = "/*";
   "comment"     => "construct RotR: RotR(a, b) = a ROTR b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"     => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
-  "emit"        => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */'
+  "emit"        => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 "RotL" => {
@@ -334,7 +508,8 @@ $comment_string = "/*";
   "comment"   => "construct RotL: RotL(a, b) = a ROTL b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
-  "emit"      => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */'
+  "emit"      => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 # unary operations
@@ -344,7 +519,13 @@ $comment_string = "/*";
   "comment"   => "construct Minus: Minus(a) = -a",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */'
+  "emit"      => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
+  "outs"      => [ "res", "M" ],
+},
+
+"l_Minus" => {
+  "comment"   => "construct lowered Minus: Minus(a) = -a",
+  "arity"     => 1,
 },
 
 "Inc" => {
@@ -352,7 +533,8 @@ $comment_string = "/*";
   "comment"   => "construct Increment: Inc(a) = a++",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */'
+  "emit"      => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
+  "outs"      => [ "res", "M" ],
 },
 
 "Dec" => {
@@ -360,7 +542,8 @@ $comment_string = "/*";
   "comment"   => "construct Decrement: Dec(a) = a--",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */'
+  "emit"      => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
+  "outs"      => [ "res", "M" ],
 },
 
 "Not" => {
@@ -368,7 +551,8 @@ $comment_string = "/*";
   "comment"   => "construct Not: Not(a) = !a",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */'
+  "emit"      => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
+  "outs"      => [ "res", "M" ],
 },
 
 # other operations
@@ -378,6 +562,7 @@ $comment_string = "/*";
   "comment"   => "construct conditional jump: CMP A, B && JMPxx LABEL",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
+  "outs"      => [ "false", "true" ],
 },
 
 "TestJmp" => {
@@ -385,6 +570,7 @@ $comment_string = "/*";
   "comment"   => "construct conditional jump: TEST A, B && JMPxx LABEL",
   "reg_req"  => { "in" => [ "gp", "gp" ] },
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "outs"      => [ "false", "true" ],
 },
 
 "CJmpAM" => {
@@ -392,6 +578,7 @@ $comment_string = "/*";
   "comment"   => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
+  "outs"      => [ "false", "true" ],
 },
 
 "CJmp" => {
@@ -413,14 +600,15 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "comment"   => "represents an integer constant",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
-  "reg_req"   => { "out" => [ "gp" ] },
+  "reg_req"   => { "in" => [ "none" ], "out" => [ "gp" ] },
 },
 
 "Cdq" => {
   "irn_flags" => "R",
   "comment"   => "construct CDQ: sign extend EAX -> EDX:EAX",
   "reg_req"   => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
-  "emit"      => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */'
+  "emit"      => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
+  "outs"      => [ "EAX", "EDX" ],
 },
 
 # Load / Store
@@ -439,7 +627,8 @@ $comment_string = "/*";
   else {
 4.   mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
   }
-'
+',
+  "outs"      => [ "res", "M" ],
 },
 
 "Store" => {
@@ -448,7 +637,8 @@ $comment_string = "/*";
   "comment"   => "construct Store: Store(ptr, val, mem) = ST ptr,val",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "gp", "none" ] },
-  "emit"      => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
+  "emit"      => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
+  "outs"      => [ "M" ],
 },
 
 "Store8Bit" => {
@@ -457,7 +647,8 @@ $comment_string = "/*";
   "comment"   => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
-  "emit"      => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
+  "emit"      => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
+  "outs"      => [ "M" ],
 },
 
 "Lea" => {
@@ -470,26 +661,41 @@ $comment_string = "/*";
 
 "Push" => {
   "comment"   => "push a gp register on the stack",
-  "reg_req"   => { "in" => [ "esp", "gp", "none" ], "out" => [ "gp" ] },
-  "emit"      => '. push %S2 /* Push(%A2) */'
+  "reg_req"   => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] },
+  "emit"      => '
+if (get_ia32_id_cnst(n)) {
+	if (get_ia32_immop_type(n) == ia32_ImmConst) {
+. push %C /* Push(%A2) */
+	} else {
+. push OFFSET FLAT:%C /* Push(%A2) */
+	}
+}
+else {
+. push %S2 /* Push(%A2) */
+}
+',
+  "outs"      => [ "stack", "M" ],
 },
 
 "Pop" => {
   "comment"   => "pop a gp register from the stack",
   "reg_req"   => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
-  "emit"      => '. pop %D1 /* Pop -> %D1 */'
+  "emit"      => '. pop %D1 /* Pop -> %D1 */',
+  "outs"      => [ "res", "stack", "M" ],
 },
 
 "Enter" => {
   "comment"   => "create stack frame",
   "reg_req"   => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
-  "emit"      => '. enter /* Enter */'
+  "emit"      => '. enter /* Enter */',
+  "outs"      => [ "frame", "stack", "M" ],
 },
 
 "Leave" => {
   "comment"   => "destroy stack frame",
   "reg_req"   => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
-  "emit"      => '. leave /* Leave */'
+  "emit"      => '. leave /* Leave */',
+  "outs"      => [ "frame", "stack", "M" ],
 },
 
 #-----------------------------------------------------------------------------#
@@ -508,7 +714,8 @@ $comment_string = "/*";
   "comment"   => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
+  "emit"      => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 "xMul" => {
@@ -516,7 +723,8 @@ $comment_string = "/*";
   "comment"   => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
+  "emit"      => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 "xMax" => {
@@ -524,7 +732,8 @@ $comment_string = "/*";
   "comment"   => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
+  "emit"      => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 "xMin" => {
@@ -532,7 +741,8 @@ $comment_string = "/*";
   "comment"   => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
+  "emit"      => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 "xAnd" => {
@@ -540,7 +750,8 @@ $comment_string = "/*";
   "comment"   => "construct SSE And: And(a, b) = a AND b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
+  "emit"      => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 "xOr" => {
@@ -548,7 +759,8 @@ $comment_string = "/*";
   "comment"   => "construct SSE Or: Or(a, b) = a OR b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
+  "emit"      => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 "xEor" => {
@@ -556,17 +768,28 @@ $comment_string = "/*";
   "comment"   => "construct SSE Eor: Eor(a, b) = a XOR b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
+  "emit"      => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 # not commutative operations
 
+"xAndNot" => {
+  "irn_flags" => "R",
+  "comment"   => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
+  "emit"      => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
+  "outs"      => [ "res", "M" ],
+},
+
 "xSub" => {
   "irn_flags" => "R",
   "comment"   => "construct SSE Sub: Sub(a, b) = a - b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
-  "emit"      => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */'
+  "emit"      => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 "xDiv" => {
@@ -574,16 +797,25 @@ $comment_string = "/*";
   "comment"   => "construct SSE Div: Div(a, b) = a / b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
-  "emit"      => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */'
+  "emit"      => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 # other operations
 
+"xCmp" => {
+  "irn_flags" => "R",
+  "comment"   => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
+  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
+  "outs"      => [ "res", "M" ],
+},
+
 "xCondJmp" => {
   "op_flags"  => "L|X|Y",
   "comment"   => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
+  "outs"      => [ "false", "true" ],
 },
 
 "xConst" => {
@@ -591,8 +823,8 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "comment"   => "represents a SSE constant",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
-  "reg_req"   => { "out" => [ "xmm" ] },
-  "emit"      => '. mov%M %D1, %C /* Load fConst into register */',
+  "reg_req"   => { "in" => [ "none" ], "out" => [ "xmm" ] },
+  "emit"      => '. movs%M %D1, %C /* Load fConst into register */',
 },
 
 # Load / Store
@@ -604,7 +836,8 @@ $comment_string = "/*";
   "comment"   => "construct SSE Load: Load(ptr, mem) = LD ptr",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
-  "emit"      => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
+  "emit"      => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
+  "outs"      => [ "res", "M" ],
 },
 
 "xStore" => {
@@ -613,7 +846,8 @@ $comment_string = "/*";
   "comment"  => "construct Store: Store(ptr, val, mem) = ST ptr,val",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"  => { "in" => [ "gp", "gp", "xmm", "none" ] },
-  "emit"     => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */'
+  "emit"     => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
+  "outs"      => [ "M" ],
 },
 
 # CopyB
@@ -638,31 +872,93 @@ $comment_string = "/*";
 "Conv_I2I" => {
   "reg_req"  => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
   "cmp_attr"  => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
-  "comment"  => "construct Conv Int -> Int"
+  "comment"  => "construct Conv Int -> Int",
+  "outs"      => [ "res", "M" ],
 },
 
 "Conv_I2I8Bit" => {
   "reg_req"  => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
   "cmp_attr"  => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
-  "comment"  => "construct Conv Int -> Int"
+  "comment"  => "construct Conv Int -> Int",
+  "outs"      => [ "res", "M" ],
 },
 
 "Conv_I2FP" => {
   "reg_req"  => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
   "cmp_attr"  => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
-  "comment"  => "construct Conv Int -> Floating Point"
+  "comment"  => "construct Conv Int -> Floating Point",
+  "outs"      => [ "res", "M" ],
 },
 
 "Conv_FP2I" => {
   "reg_req"  => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
   "cmp_attr"  => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
-  "comment"  => "construct Conv Floating Point -> Int"
+  "comment"  => "construct Conv Floating Point -> Int",
+  "outs"      => [ "res", "M" ],
 },
 
 "Conv_FP2FP" => {
   "reg_req"  => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
   "cmp_attr"  => "  return ia32_compare_conv_attr(attr_a, attr_b);\n",
   "comment"  => "construct Conv Floating Point -> Floating Point",
+  "outs"      => [ "res", "M" ],
+},
+
+"CmpCMov" => {
+  "irn_flags" => "R",
+  "comment"   => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
+  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }
+},
+
+"PsiCondCMov" => {
+  "irn_flags" => "R",
+  "comment"   => "check if Psi condition tree evaluates to true and move result accordingly",
+  "reg_req"   => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] }
+},
+
+"xCmpCMov" => {
+  "irn_flags" => "R",
+  "comment"   => "construct Conditional Move: SSE Compare + int CMov ",
+  "reg_req"   => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }
+},
+
+"vfCmpCMov" => {
+  "irn_flags" => "R",
+  "comment"   => "construct Conditional Move: x87 Compare + int CMov",
+  "reg_req"   => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }
+},
+
+"CmpSet" => {
+  "irn_flags" => "R",
+  "comment"   => "construct Set: Set(sel) == sel ? 1 : 0",
+  "reg_req"   => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
+  "outs"      => [ "res", "M" ],
+},
+
+"PsiCondSet" => {
+  "irn_flags" => "R",
+  "comment"   => "check if Psi condition tree evaluates to true and set result accordingly",
+  "reg_req"   => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
+},
+
+"xCmpSet" => {
+  "irn_flags" => "R",
+  "comment"   => "construct Set: SSE Compare + int Set",
+  "reg_req"   => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
+  "outs"      => [ "res", "M" ],
+},
+
+"vfCmpSet" => {
+  "irn_flags" => "R",
+  "comment"   => "construct Set: x87 Compare + int Set",
+  "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
+  "outs"      => [ "res", "M" ],
+},
+
+"vfCMov" => {
+  "irn_flags" => "R",
+  "comment"   => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
+  "reg_req"   => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }
 },
 
 #----------------------------------------------------------#
@@ -684,6 +980,7 @@ $comment_string = "/*";
   "comment"   => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+  "outs"      => [ "res", "M" ],
 },
 
 "vfmul" => {
@@ -691,6 +988,7 @@ $comment_string = "/*";
   "comment"   => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+  "outs"      => [ "res", "M" ],
 },
 
 "vfsub" => {
@@ -698,12 +996,14 @@ $comment_string = "/*";
   "comment"   => "virtual fp Sub: Sub(a, b) = a - b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+  "outs"      => [ "res", "M" ],
 },
 
 "vfdiv" => {
   "comment"   => "virtual fp Div: Div(a, b) = a / b",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
+  "outs"      => [ "res", "M" ],
 },
 
 "vfabs" => {
@@ -744,7 +1044,8 @@ $comment_string = "/*";
   "state"     => "exc_pinned",
   "comment"   => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
-  "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
+  "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
+  "outs"      => [ "res", "M" ],
 },
 
 "vfst" => {
@@ -753,6 +1054,7 @@ $comment_string = "/*";
   "comment"   => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "none" ] },
+  "outs"      => [ "M" ],
 },
 
 # Conversions
@@ -761,13 +1063,15 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "comment"   => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
-  "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
+  "reg_req"   => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
+  "outs"      => [ "res", "M" ],
 },
 
 "vfist" => {
   "comment"   => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "in" => [ "gp", "gp", "vfp", "none" ] },
+  "outs"      => [ "M" ],
 },
 
 # constants
@@ -817,9 +1121,20 @@ $comment_string = "/*";
 "vfConst" => {
   "op_flags"  => "c",
   "irn_flags" => "R",
+  "init_attr" => "  set_ia32_ls_mode(res, mode);",
   "comment"   => "represents a virtual floating point constant",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
-  "reg_req"   => { "out" => [ "vfp" ] },
+  "reg_req"   => { "in" => [ "none" ], "out" => [ "vfp" ] },
+},
+
+# other
+
+"vfCondJmp" => {
+  "op_flags"  => "L|X|Y",
+  "comment"   => "represents a virtual floating point compare",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
+  "outs"      => [ "false", "true", "temp_reg_eax" ],
 },
 
 #------------------------------------------------------------------------#
@@ -835,7 +1150,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 Add: Add(a, b) = Add(b, a) = a + b",
   "reg_req"   => { },
-  "emit"      => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
+  "emit"      => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
 },
 
 "faddp" => {
@@ -843,7 +1158,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 Add: Add(a, b) = Add(b, a) = a + b",
   "reg_req"   => { },
-  "emit"      => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
+  "emit"      => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */',
 },
 
 "fmul" => {
@@ -851,7 +1166,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
   "reg_req"   => { },
-  "emit"      => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */'
+  "emit"      => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',
 },
 
 "fmulp" => {
@@ -859,7 +1174,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
   "reg_req"   => { },
-  "emit"      => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */'
+  "emit"      => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',,
 },
 
 "fsub" => {
@@ -867,7 +1182,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Sub: Sub(a, b) = a - b",
   "reg_req"   => { },
-  "emit"      => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */'
+  "emit"      => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
 },
 
 "fsubp" => {
@@ -875,7 +1190,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Sub: Sub(a, b) = a - b",
   "reg_req"   => { },
-  "emit"      => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */'
+  "emit"      => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */',
 },
 
 "fsubr" => {
@@ -884,7 +1199,7 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "comment"   => "x87 fp SubR: SubR(a, b) = b - a",
   "reg_req"   => { },
-  "emit"      => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
+  "emit"      => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
 },
 
 "fsubrp" => {
@@ -893,7 +1208,7 @@ $comment_string = "/*";
   "irn_flags" => "R",
   "comment"   => "x87 fp SubR: SubR(a, b) = b - a",
   "reg_req"   => { },
-  "emit"      => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
+  "emit"      => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */',
 },
 
 "fdiv" => {
@@ -901,7 +1216,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Div: Div(a, b) = a / b",
   "reg_req"   => { },
-  "emit"      => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
+  "emit"      => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
 },
 
 "fdivp" => {
@@ -909,7 +1224,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Div: Div(a, b) = a / b",
   "reg_req"   => { },
-  "emit"      => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
+  "emit"      => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */',
 },
 
 "fdivr" => {
@@ -917,7 +1232,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp DivR: DivR(a, b) = b / a",
   "reg_req"   => { },
-  "emit"      => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
+  "emit"      => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
 },
 
 "fdivrp" => {
@@ -925,7 +1240,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp DivR: DivR(a, b) = b / a",
   "reg_req"   => { },
-  "emit"      => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
+  "emit"      => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */',
 },
 
 "fabs" => {
@@ -933,7 +1248,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Abs: Abs(a) = |a|",
   "reg_req"   => { },
-  "emit"      => '. fabs /* x87 fabs(%S1) -> %D1 */'
+  "emit"      => '. fabs /* x87 fabs(%S1) -> %D1 */',
 },
 
 "fchs" => {
@@ -941,7 +1256,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Chs: Chs(a) = -a",
   "reg_req"   => { },
-  "emit"      => '. fchs /* x87 fchs(%S1) -> %D1 */'
+  "emit"      => '. fchs /* x87 fchs(%S1) -> %D1 */',
 },
 
 "fsin" => {
@@ -949,7 +1264,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Sin: Sin(a) = sin(a)",
   "reg_req"   => { },
-  "emit"      => '. fsin /* x87 sin(%S1) -> %D1 */'
+  "emit"      => '. fsin /* x87 sin(%S1) -> %D1 */',
 },
 
 "fcos" => {
@@ -957,7 +1272,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Cos: Cos(a) = cos(a)",
   "reg_req"   => { },
-  "emit"      => '. fcos /* x87 cos(%S1) -> %D1 */'
+  "emit"      => '. fcos /* x87 cos(%S1) -> %D1 */',
 },
 
 "fsqrt" => {
@@ -965,7 +1280,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
   "reg_req"   => { },
-  "emit"      => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */'
+  "emit"      => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */',
 },
 
 # x87 Load and Store
@@ -976,7 +1291,7 @@ $comment_string = "/*";
   "state"     => "exc_pinned",
   "comment"   => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
   "reg_req"   => { },
-  "emit"      => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */'
+  "emit"      => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
 },
 
 "fst" => {
@@ -985,7 +1300,7 @@ $comment_string = "/*";
   "state"     => "exc_pinned",
   "comment"   => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
   "reg_req"   => { },
-  "emit"      => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */'
+  "emit"      => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
 },
 
 "fstp" => {
@@ -994,7 +1309,7 @@ $comment_string = "/*";
   "state"     => "exc_pinned",
   "comment"   => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
   "reg_req"   => { },
-  "emit"      => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */'
+  "emit"      => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
 },
 
 # Conversions
@@ -1002,9 +1317,10 @@ $comment_string = "/*";
 "fild" => {
   "op_flags"  => "R",
   "irn_flags" => "R",
+  "rd_constructor" => "NONE",
   "comment"   => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
   "reg_req"   => { },
-  "emit"      => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */'
+  "emit"      => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
 },
 
 "fist" => {
@@ -1012,7 +1328,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
   "reg_req"   => { },
-  "emit"      => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */'
+  "emit"      => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
 },
 
 "fistp" => {
@@ -1020,7 +1336,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
   "reg_req"   => { },
-  "emit"      => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */'
+  "emit"      => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
 },
 
 # constants
@@ -1030,7 +1346,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load 0.0: Ld 0.0 -> reg",
   "reg_req"   => { },
-  "emit"      => '. fldz /* x87 0.0 -> %D1 */'
+  "emit"      => '. fldz /* x87 0.0 -> %D1 */',
 },
 
 "fld1" => {
@@ -1038,7 +1354,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load 1.0: Ld 1.0 -> reg",
   "reg_req"   => { },
-  "emit"      => '. fld1 /* x87 1.0 -> %D1 */'
+  "emit"      => '. fld1 /* x87 1.0 -> %D1 */',
 },
 
 "fldpi" => {
@@ -1046,7 +1362,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load pi: Ld pi -> reg",
   "reg_req"   => { },
-  "emit"      => '. fldpi /* x87 pi -> %D1 */'
+  "emit"      => '. fldpi /* x87 pi -> %D1 */',
 },
 
 "fldln2" => {
@@ -1054,7 +1370,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load ln 2: Ld ln 2 -> reg",
   "reg_req"   => { },
-  "emit"      => '. fldln2 /* x87 ln(2) -> %D1 */'
+  "emit"      => '. fldln2 /* x87 ln(2) -> %D1 */',
 },
 
 "fldlg2" => {
@@ -1062,7 +1378,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load lg 2: Ld lg 2 -> reg",
   "reg_req"   => { },
-  "emit"      => '. fldlg2 /* x87 log(2) -> %D1 */'
+  "emit"      => '. fldlg2 /* x87 log(2) -> %D1 */',
 },
 
 "fldl2t" => {
@@ -1070,7 +1386,7 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load ld 10: Ld ld 10 -> reg",
   "reg_req"   => { },
-  "emit"      => '. fldll2t /* x87 ld(10) -> %D1 */'
+  "emit"      => '. fldll2t /* x87 ld(10) -> %D1 */',
 },
 
 "fldl2e" => {
@@ -1078,20 +1394,20 @@ $comment_string = "/*";
   "rd_constructor" => "NONE",
   "comment"   => "x87 fp Load ld e: Ld ld e -> reg",
   "reg_req"   => { },
-  "emit"      => '. fldl2e /* x87 ld(e) -> %D1 */'
+  "emit"      => '. fldl2e /* x87 ld(e) -> %D1 */',
 },
 
 "fldConst" => {
-  "op_flags"  => "R",
-  "op_flags"  => "c",
+  "op_flags"  => "R|c",
   "irn_flags" => "R",
+  "rd_constructor" => "NONE",
   "comment"   => "represents a x87 constant",
   "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
   "reg_req"   => { "out" => [ "st" ] },
-  "emit"      => '. fld%M %C /* Load fConst into register -> %D1 */',
+  "emit"      => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
 },
 
-# fxch, fpush
+# fxch, fpush, fpop
 # Note that it is NEVER allowed to do CSE on these nodes
 
 "fxch" => {
@@ -1110,4 +1426,56 @@ $comment_string = "/*";
   "emit"      => '. fld %X1 /* x87 push %X1 */',
 },
 
+"fpop" => {
+  "op_flags"  => "R|K",
+  "comment"   => "x87 stack pop",
+  "reg_req"   => { "in" => [ "st"], "out" => [ "st" ] },
+  "cmp_attr"  => "  return 1;\n",
+  "emit"      => '. fstp %X1 /* x87 pop %X1 */',
+},
+
+# compare
+
+"fcomJmp" => {
+  "op_flags"  => "L|X|Y",
+  "comment"   => "floating point compare",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { },
+},
+
+"fcompJmp" => {
+  "op_flags"  => "L|X|Y",
+  "comment"   => "floating point compare and pop",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { },
+},
+
+"fcomppJmp" => {
+  "op_flags"  => "L|X|Y",
+  "comment"   => "floating point compare and pop twice",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { },
+},
+
+"fcomrJmp" => {
+  "op_flags"  => "L|X|Y",
+  "comment"   => "floating point compare reverse",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { },
+},
+
+"fcomrpJmp" => {
+  "op_flags"  => "L|X|Y",
+  "comment"   => "floating point compare reverse and pop",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { },
+},
+
+"fcomrppJmp" => {
+  "op_flags"  => "L|X|Y",
+  "comment"   => "floating point compare reverse and pop twice",
+  "cmp_attr"  => "  return ia32_compare_immop_attr(attr_a, attr_b);\n",
+  "reg_req"   => { },
+},
+
 ); # end of %nodes