X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=93c507063c87b50ef7265d9d3eb5ec67d78a2dfb;hb=fa4ec191e159484f0fcbea2ef044deaa2ab2d293;hp=9bb8eaad9f19079563d876b047a29a246382da82;hpb=308688bf5bef393cf8b6ba31caf2e7c7e18bade3;p=libfirm diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index 9bb8eaad9..93c507063 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -9,7 +9,7 @@ $arch = "ia32"; $comment_string = "/*"; # the number of additional opcodes you want to register -$additional_opcodes = 0; +#$additional_opcodes = 0; # The node description is done as a perl hash initializer with the # following structure: @@ -126,7 +126,7 @@ $additional_opcodes = 0; { "name" => "vf4", "type" => 1 }, { "name" => "vf5", "type" => 1 }, { "name" => "vf6", "type" => 1 }, - { "name" => "vf7", "type" => 4 }, + { "name" => "vf7", "type" => 1 }, { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes { "mode" => "mode_E" } ], @@ -199,7 +199,7 @@ $additional_opcodes = 0; "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] }, - "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */' + "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */' }, "And" => { @@ -462,7 +462,8 @@ $additional_opcodes = 0; "state" => "exc_pinned", "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] } + "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] }, + "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */' }, "Lea" => { @@ -473,14 +474,14 @@ $additional_opcodes = 0; "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */' }, -#--------------------------------------------------------# -# __ _ _ _ # -# / _| | | | | | # -# | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ # -# | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| # -# | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ # -# |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # -#--------------------------------------------------------# +#-----------------------------------------------------------------------------# +# _____ _____ ______ __ _ _ _ # +# / ____/ ____| ____| / _| | | | | | # +# | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ # +# \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| # +# ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ # +# |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # +#-----------------------------------------------------------------------------# # commutative operations @@ -646,16 +647,19 @@ $additional_opcodes = 0; "comment" => "construct Conv Floating Point -> Floating Point", }, -#--------------------------------------------------------# -# __ _ _ _ # -# / _| | | | | | # -# | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ # -# | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| # -# | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ # -# |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # -#--------------------------------------------------------# - -# virtual float nodes +#----------------------------------------------------------# +# _ _ _ __ _ _ # +# (_) | | | | / _| | | | # +# __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ # +# \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| # +# \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ # +# \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| # +# | | # +# _ __ ___ __| | ___ ___ # +# | '_ \ / _ \ / _` |/ _ \/ __| # +# | | | | (_) | (_| | __/\__ \ # +# |_| |_|\___/ \__,_|\___||___/ # +#----------------------------------------------------------# "vfadd" => { "irn_flags" => "R", @@ -678,25 +682,12 @@ $additional_opcodes = 0; "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, }, -"vfsubr" => { - "irn_flags" => "R", - "comment" => "virtual fp SubR: SubR(a, b) = b - a", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, -}, - "vfdiv" => { "comment" => "virtual fp Div: Div(a, b) = a / b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, }, -"vfdivr" => { - "comment" => "virtual fp DivR: DivR(a, b) = b / a", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, -}, - "vfabs" => { "irn_flags" => "R", "comment" => "virtual fp Abs: Abs(a) = |a|", @@ -813,273 +804,291 @@ $additional_opcodes = 0; "reg_req" => { "out" => [ "vfp" ] }, }, -#--------------------------------------------------------# -# __ _ _ _ # -# / _| | | | | | # -# | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ # -# | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| # -# | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ # -# |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # -#--------------------------------------------------------# - -# x87 float nodes +#------------------------------------------------------------------------# +# ___ _____ __ _ _ _ # +# __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ # +# \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| # +# > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ # +# /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # +#------------------------------------------------------------------------# "fadd" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b", "reg_req" => { }, -# "emit" => '. fadd %ia32_emit_binop /* x87 fadd(%A1, %A2) -> %D1 */' - "emit" => '. fadd %X1, %X2 /* x87 fadd(%X1, %X2) -> %X3 */' + "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */' }, "faddp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b", "reg_req" => { }, -# "emit" => '. faddp %ia32_emit_binop /* x87 fadd(%A1, %A2) -> %D1 */' - "emit" => '. faddp %X1, %X2 /* x87 fadd(%X1, %X2) -> %X3 and pop */' + "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */' }, "fmul" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b", "reg_req" => { }, -# "emit" => '. fmul %ia32_emit_binop /* x87 fmul(%A1, %A2) -> %D1 */' - "emit" => '. fmul %X1, %X2 /* x87 fmul(%X1, %X2) -> %X3 */' + "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */' }, "fmulp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b", "reg_req" => { }, -# "emit" => '. fmulp %ia32_emit_binop /* x87 fmul(%A1, %A2) -> %D1 */' - "emit" => '. fmulp %X1, %X2 /* x87 fmul(%X1, %X2) -> %X3 and pop */' + "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */' }, "fsub" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Sub: Sub(a, b) = a - b", "reg_req" => { }, -# "emit" => '. fsub %ia32_emit_binop /* x87 fsub(%A1, %A2) -> %D1 */' - "emit" => '. fsub %X1, %X2 /* x87 fsub(%X1, %X2) -> %X3 */' + "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */' }, "fsubp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Sub: Sub(a, b) = a - b", "reg_req" => { }, -# "emit" => '. fsubp %ia32_emit_binop /* x87 fsub(%A1, %A2) -> %D1 */' - "emit" => '. fsubp %X1, %X2 /* x87 fsub(%X1, %X2) -> %X3 and pop */' + "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */' }, "fsubr" => { + "op_flags" => "R", "rd_constructor" => "NONE", "irn_flags" => "R", "comment" => "x87 fp SubR: SubR(a, b) = b - a", "reg_req" => { }, -# "emit" => '. fsubr %ia32_emit_binop /* x87 fsubr(%A1, %A2) -> %D1 */' - "emit" => '. fsubr %X1, %X2 /* x87 fsubr(%X1, %X2) -> %X3 */' + "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */' }, "fsubrp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "irn_flags" => "R", "comment" => "x87 fp SubR: SubR(a, b) = b - a", "reg_req" => { }, -# "emit" => '. fsubrp %ia32_emit_binop /* x87 fsubr(%A1, %A2) -> %D1 */' - "emit" => '. fsubrp %X1, %X2 /* x87 fsubr(%X1, %X2) -> %X3 and pop */' + "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */' }, "fdiv" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Div: Div(a, b) = a / b", "reg_req" => { }, -# "emit" => '. fdiv %ia32_emit_binop /* x87 fdiv(%A1, %A2) -> %D1 */' - "emit" => '. fdiv %X1, %X2 /* x87 fdiv(%X1, %X2) -> %X3 */' + "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */' }, "fdivp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Div: Div(a, b) = a / b", "reg_req" => { }, -# "emit" => '. fdivp %ia32_emit_binop /* x87 fdiv(%A1, %A2) -> %D1 */' - "emit" => '. fdivp %X1, %X2 /* x87 fdiv(%X1, %X2) -> %X3 and pop */' + "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */' }, "fdivr" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp DivR: DivR(a, b) = b / a", "reg_req" => { }, -# "emit" => '. fdivr %ia32_emit_binop /* x87 fdivr(%A1, %A2) -> %D1 */' - "emit" => '. fdivr %X1, %X2 /* x87 fdivr(%X1, %X2) -> %X3 */' + "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */' }, "fdivrp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp DivR: DivR(a, b) = b / a", "reg_req" => { }, -# "emit" => '. fdivrp %ia32_emit_binop /* x87 fdivr(%A1, %A2) -> %D1 */' - "emit" => '. fdivrp %X1, %X2 /* x87 fdivr(%X1, %X2) -> %X3 and pop */' + "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */' }, "fabs" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Abs: Abs(a) = |a|", "reg_req" => { }, - "emit" => '. fabs %X1 /* x87 fabs(%X1) -> %X3 */' + "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */' }, "fchs" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Chs: Chs(a) = -a", "reg_req" => { }, - "emit" => '. fchs %X1 /* x87 fchs(%X1) -> %X3 */' + "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */' }, "fsin" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Sin: Sin(a) = sin(a)", "reg_req" => { }, - "emit" => '. fsin %X1 /* x87 sin(%X1) -> %X3 */' + "emit" => '. fsin /* x87 sin(%S1) -> %D1 */' }, "fcos" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Cos: Cos(a) = cos(a)", "reg_req" => { }, - "emit" => '. fcos %X1 /* x87 cos(%X1) -> %X3 */' + "emit" => '. fcos /* x87 cos(%S1) -> %D1 */' }, "fsqrt" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5", "reg_req" => { }, - "emit" => '. fsqrt %X1 $ /* x87 sqrt(%X1) -> %X3 */' + "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */' }, # x87 Load and Store "fld" => { "rd_constructor" => "NONE", - "op_flags" => "L|F", + "op_flags" => "R|L|F", "state" => "exc_pinned", "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg", "reg_req" => { }, - "emit" => '. fld %X3, %ia32_emit_am /* Load((%A1)) -> %X3 */' + "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */' }, "fst" => { "rd_constructor" => "NONE", - "op_flags" => "L|F", + "op_flags" => "R|L|F", "state" => "exc_pinned", "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val", "reg_req" => { }, - "emit" => '. fst %ia32_emit_binop /* Store(%X3) -> (%A1) */' + "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */' }, "fstp" => { "rd_constructor" => "NONE", - "op_flags" => "L|F", + "op_flags" => "R|L|F", "state" => "exc_pinned", "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val", "reg_req" => { }, - "emit" => '. fstp %ia32_emit_binop /* Store(%X3) -> (%A1) and pop */' + "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */' }, # Conversions "fild" => { + "op_flags" => "R", "irn_flags" => "R", "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg", "reg_req" => { }, - "emit" => '. fild %X3, %ia32_emit_am /* integer Load((%A1)) -> %X3 */' + "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */' }, "fist" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val", "reg_req" => { }, - "emit" => '. fist %ia32_emit_binop /* integer Store(%X3) -> (%A1) */' + "emit" => '. fist %ia32_emit_binop /* integer Store(%A3) -> (%A1) */' }, "fistp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val", "reg_req" => { }, - "emit" => '. fistp %ia32_emit_binop /* integer Store(%X3) -> (%A1) and pop */' + "emit" => '. fistp %ia32_emit_binop /* integer Store(%A3) -> (%A1) and pop */' }, # constants "fldz" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg", "reg_req" => { }, - "emit" => '. fldz %X3 /* x87 0.0 -> %X3 */' + "emit" => '. fldz /* x87 0.0 -> %D1 */' }, "fld1" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg", "reg_req" => { }, - "emit" => '. fld1 %X3 /* x87 1.0 -> %X3 */' + "emit" => '. fld1 /* x87 1.0 -> %D1 */' }, "fldpi" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load pi: Ld pi -> reg", "reg_req" => { }, - "emit" => '. fldpi %X3 /* x87 pi -> %X3 */' + "emit" => '. fldpi /* x87 pi -> %D1 */' }, "fldln2" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg", "reg_req" => { }, - "emit" => '. fldln2 %X3 /* x87 ln(2) -> %X3 */' + "emit" => '. fldln2 /* x87 ln(2) -> %D1 */' }, "fldlg2" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg", "reg_req" => { }, - "emit" => '. fldlg2 %X3 /* x87 log(2) -> %X3 */' + "emit" => '. fldlg2 /* x87 log(2) -> %D1 */' }, "fldl2t" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg", "reg_req" => { }, - "emit" => '. fldll2t %X3 /* x87 ld(10) -> %X3 */' + "emit" => '. fldll2t /* x87 ld(10) -> %D1 */' }, "fldl2e" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Load ld e: Ld ld e -> reg", "reg_req" => { }, - "emit" => '. fldl2e %X3 /* x87 ld(e) -> %X3 */' + "emit" => '. fldl2e /* x87 ld(e) -> %D1 */' }, "fldConst" => { + "op_flags" => "R", "op_flags" => "c", "irn_flags" => "R", "comment" => "represents a x87 constant", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "out" => [ "st" ] }, - "emit" => '. fld%M %C /* Load fConst into register -> %X3 */', + "emit" => '. fld%M %C /* Load fConst into register -> %D1 */', }, # fxch, fpush +# Note that it is NEVER allowed to do CSE on these nodes "fxch" => { + "op_flags" => "R|K", "comment" => "x87 stack exchange", "reg_req" => { "in" => [ "st"], "out" => [ "st" ] }, - "emit" => '. fxch %X1, %X3 /* x87 swap %X1, %X3 */', + "cmp_attr" => " return 1;\n", + "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */', }, "fpush" => { + "op_flags" => "R", "comment" => "x87 stack push", "reg_req" => { "in" => [ "st"], "out" => [ "st" ] }, + "cmp_attr" => " return 1;\n", "emit" => '. fld %X1 /* x87 push %X1 */', },