X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=84c2425bf2c12aaf89208d62401819e09be66d43;hb=7e8388fa7996ff182d3aa4e0cdd41b27bed4982f;hp=043bb0079c27eadac608b63c2e4d82ee1f6d8660;hpb=91ec71cfb8e6242aee2b0f727e01a18085f27551;p=libfirm diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index 043bb0079..84c2425bf 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -32,7 +32,6 @@ $arch = "ia32"; # attr => "attitional attribute arguments for constructor" # init_attr => "emit attribute initialization template" # rd_constructor => "c source code which constructs an ir_node" -# latency => "latency of this operation (can be float)" # attr_type => "name of the attribute struct", # }, # @@ -96,8 +95,6 @@ $arch = "ia32"; # # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3 # -# latency: the latency of the operation, default is 1 -# # register types: # 0 - no special type @@ -200,6 +197,7 @@ $arch = "ia32"; SB1 => "${arch}_emit_8bit_source_register_or_immediate(node, 1);", SB2 => "${arch}_emit_8bit_source_register_or_immediate(node, 2);", SB3 => "${arch}_emit_8bit_source_register_or_immediate(node, 3);", + SI1 => "${arch}_emit_source_register_or_immediate(node, 1);", SI3 => "${arch}_emit_source_register_or_immediate(node, 3);", D0 => "${arch}_emit_dest_register(node, 0);", D1 => "${arch}_emit_dest_register(node, 1);", @@ -217,10 +215,10 @@ $arch = "ia32"; unop3 => "${arch}_emit_unop(node, 3);", unop4 => "${arch}_emit_unop(node, 4);", unop5 => "${arch}_emit_unop(node, 5);", - DAM1 => "${arch}_emit_am_or_dest_register(node, 1);", binop => "${arch}_emit_binop(node);", x87_binop => "${arch}_emit_x87_binop(node);", CMP0 => "${arch}_emit_cmp_suffix_node(node, 0);", + CMP3 => "${arch}_emit_cmp_suffix_node(node, 3);", ); #--------------------------------------------------# @@ -234,32 +232,24 @@ $arch = "ia32"; # |_| # #--------------------------------------------------# -$default_attr_type = "ia32_attr_t"; -$default_copy_attr = "ia32_copy_attr"; +$default_op_attr_type = "ia32_op_attr_t"; +$default_attr_type = "ia32_attr_t"; +$default_copy_attr = "ia32_copy_attr"; sub ia32_custom_init_attr { my $node = shift; my $name = shift; my $res = ""; + if(defined($node->{modified_flags})) { $res .= "\tset_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);\n"; } if(defined($node->{am})) { my $am = $node->{am}; - if($am eq "full,binary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_binary);"; - } elsif($am eq "full,unary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_unary);"; - } elsif($am eq "source,unary") { + if($am eq "source,unary") { $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_unary);"; } elsif($am eq "source,binary") { $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_binary);"; - } elsif($am eq "dest,unary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);"; - } elsif($am eq "dest,binary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);"; - } elsif($am eq "dest,ternary") { - $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_ternary);"; } elsif($am eq "source,ternary") { $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_ternary);"; } elsif($am eq "none") { @@ -279,17 +269,23 @@ sub ia32_custom_init_attr { $custom_init_attr_func = \&ia32_custom_init_attr; %init_attr = ( - ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);", + ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);", ia32_x87_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_ia32_x87_attributes(res);", ia32_asm_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". "\tinit_ia32_x87_attributes(res);". "\tinit_ia32_asm_attributes(res);", ia32_immediate_attr_t => - "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n". - "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);" + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". + "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);", + ia32_copyb_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". + "\tinit_ia32_copyb_attributes(res, size);", + ia32_condcode_attr_t => + "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n". + "\tinit_ia32_condcode_attributes(res, pnc);", ); %compare_attr = ( @@ -297,6 +293,8 @@ $custom_init_attr_func = \&ia32_custom_init_attr; ia32_x87_attr_t => "ia32_compare_x87_attr", ia32_asm_attr_t => "ia32_compare_asm_attr", ia32_immediate_attr_t => "ia32_compare_immediate_attr", + ia32_copyb_attr_t => "ia32_compare_copyb_attr", + ia32_condcode_attr_t => "ia32_compare_condcode_attr", ); %operands = ( @@ -362,11 +360,14 @@ ProduceVal => { Add => { irn_flags => "R", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5", "none", "flags" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], + outs => [ "res", "flags", "M" ], emit => '. add%M %binop', - am => "full,binary", + am => "source,binary", units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -378,6 +379,7 @@ AddMem => { ins => [ "base", "index", "mem", "val" ], emit => ". add%M %SI3, %AM", units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -389,17 +391,21 @@ AddMem8Bit => { ins => [ "base", "index", "mem", "val" ], emit => ". add%M %SB3, %AM", units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, Adc => { state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 in_r5" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right", "eflags" ], + outs => [ "res", "flags", "M" ], emit => '. adc%M %binop', - am => "full,binary", + am => "source,binary", units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -419,10 +425,11 @@ Mul => { # we should not rematrialize this node. It produces 2 results and has # very strict constrains state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], + out => [ "eax", "edx", "none" ] }, ins => [ "base", "index", "mem", "val_high", "val_low" ], emit => '. mul%M %unop4', - outs => [ "EAX", "EDX", "M" ], + outs => [ "res_low", "res_high", "M" ], am => "source,binary", latency => 10, units => [ "GP" ], @@ -441,9 +448,12 @@ l_Mul => { IMul => { irn_flags => "R", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, + # TODO: adjust out requirements for the 3 operand form + # (no need for should_be_same then) + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], - emit => '. imul%M %binop', + outs => [ "res", "flags", "M" ], am => "source,binary", latency => 5, units => [ "GP" ], @@ -454,10 +464,11 @@ IMul => { IMul1OP => { irn_flags => "R", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], + out => [ "eax", "edx", "none" ] }, ins => [ "base", "index", "mem", "val_high", "val_low" ], emit => '. imul%M %unop4', - outs => [ "EAX", "EDX", "M" ], + outs => [ "res_low", "res_high", "M" ], am => "source,binary", latency => 5, units => [ "GP" ], @@ -465,22 +476,24 @@ IMul1OP => { }, l_IMul => { - # we should not rematrialize this node. It produces 2 results and has - # very strict constrains op_flags => "C", cmp_attr => "return 1;", - outs => [ "EAX", "EDX", "M" ], + outs => [ "res_low", "res_high", "M" ], arity => 2 }, And => { irn_flags => "R", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], - am => "full,binary", + outs => [ "res", "flags", "M" ], + op_modes => "commutative | am | immediate | mode_neutral", + am => "source,binary", emit => '. and%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -492,6 +505,7 @@ AndMem => { ins => [ "base", "index", "mem", "val" ], emit => '. and%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -503,6 +517,7 @@ AndMem8Bit => { ins => [ "base", "index", "mem", "val" ], emit => '. and%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -510,11 +525,14 @@ AndMem8Bit => { Or => { irn_flags => "R", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], - am => "full,binary", + outs => [ "res", "flags", "M" ], + am => "source,binary", emit => '. or%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -526,6 +544,7 @@ OrMem => { ins => [ "base", "index", "mem", "val" ], emit => '. or%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -537,6 +556,7 @@ OrMem8Bit => { ins => [ "base", "index", "mem", "val" ], emit => '. or%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -544,11 +564,14 @@ OrMem8Bit => { Xor => { irn_flags => "R", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4 in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], - am => "full,binary", + outs => [ "res", "flags", "M" ], + am => "source,binary", emit => '. xor%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -560,6 +583,7 @@ XorMem => { ins => [ "base", "index", "mem", "val" ], emit => '. xor%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -571,6 +595,7 @@ XorMem8Bit => { ins => [ "base", "index", "mem", "val" ], emit => '. xor%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -580,11 +605,14 @@ XorMem8Bit => { Sub => { irn_flags => "R", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4", "none", "flags" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], + out => [ "in_r4", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right" ], - am => "full,binary", + outs => [ "res", "flags", "M" ], + am => "source,binary", emit => '. sub%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -596,6 +624,7 @@ SubMem => { ins => [ "base", "index", "mem", "val" ], emit => '. sub%M %SI3, %AM', units => [ "GP" ], + latency => 1, mode => 'mode_M', modified_flags => $status_flags }, @@ -607,17 +636,21 @@ SubMem8Bit => { ins => [ "base", "index", "mem", "val" ], emit => '. sub%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => 'mode_M', modified_flags => $status_flags }, Sbb => { state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 !in_r5" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], + out => [ "in_r4 !in_r5", "flags", "none" ] }, ins => [ "base", "index", "mem", "left", "right", "eflags" ], - am => "full,binary", + outs => [ "res", "flags", "M" ], + am => "source,binary", emit => '. sbb%M %binop', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -635,9 +668,10 @@ l_Sbb => { IDiv => { op_flags => "F|L", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "edx", "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], + out => [ "eax", "flags", "none", "edx", "none" ] }, ins => [ "base", "index", "mem", "left_low", "left_high", "right" ], - outs => [ "div_res", "mod_res", "M" ], + outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ], am => "source,ternary", emit => ". idiv%M %unop5", latency => 25, @@ -648,9 +682,10 @@ IDiv => { Div => { op_flags => "F|L", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "edx", "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], + out => [ "eax", "flags", "none", "edx", "none" ] }, ins => [ "base", "index", "mem", "left_low", "left_high", "right" ], - outs => [ "div_res", "mod_res", "M" ], + outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ], am => "source,ternary", emit => ". div%M %unop5", latency => 25, @@ -660,10 +695,13 @@ Div => { Shl => { irn_flags => "R", - reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] }, - ins => [ "left", "right" ], + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, + ins => [ "val", "count" ], + outs => [ "res", "flags" ], emit => '. shl %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -675,23 +713,24 @@ ShlMem => { ins => [ "base", "index", "mem", "count" ], emit => '. shl%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, l_ShlDep => { - cmp_attr => "return 1;", - # value, cnt, dependency - arity => 3 + cmp_attr => "return 1;", + ins => [ "val", "count", "dep" ], + arity => 3 }, ShlD => { irn_flags => "R", - # see ShrD about the strange out constraint - reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "!in" ] }, - ins => [ "left_high", "left_low", "right" ], - emit => ". shld%M %SB2, %S1, %S0\n". - ". movl %S0, %D0", + reg_req => { in => [ "gp", "gp", "ecx" ], + out => [ "in_r1 !in_r2 !in_r3", "flags" ] }, + ins => [ "val_high", "val_low", "count" ], + outs => [ "res", "flags" ], + emit => ". shld%M %SB2, %S1, %D0", latency => 6, units => [ "GP" ], mode => $mode_gp, @@ -700,16 +739,20 @@ ShlD => { l_ShlD => { cmp_attr => "return 1;", + ins => [ "val_high", "val_low", "count" ], arity => 3, }, Shr => { irn_flags => "R", - reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] }, + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, ins => [ "val", "count" ], + outs => [ "res", "flags" ], emit => '. shr %SB1, %S0', units => [ "GP" ], mode => $mode_gp, + latency => 1, modified_flags => $status_flags }, @@ -721,35 +764,23 @@ ShrMem => { emit => '. shr%M %SB3, %AM', units => [ "GP" ], mode => "mode_M", + latency => 1, modified_flags => $status_flags }, l_ShrDep => { cmp_attr => "return 1;", - # value, cnt, dependency + ins => [ "val", "count", "dep" ], arity => 3 }, ShrD => { - # What's going on with the out constraint here? We would like to write - # "in_r2" and be done. However in firm we only support should_be_same - # constraints at the moment. Which means they could be non-fullfilled in - # some cases. Now when all values happen to live through the node, out - # is ecx and in_r2 not ecx, then we're screwed. Because in this case we - # need a 4th Register. - # - # The best solution for this is extending the register allocator to support - # must_be_same constraints which create a copy when the in_r2 value - # lives through (this ensures that we have the 4th register in the cases - # when we need it and can always fix the situation). - # - # For now I'm doing this ultra ugly !in hack which allocates 4 registers - # and creates an extra mov - irn_flags => "R", - reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "!in" ] }, - ins => [ "left_high", "left_low", "right" ], - emit => ". shrd%M %SB2, %S1, %S0\n". - ". movl %S0, %D0", + irn_flags => "R", + reg_req => { in => [ "gp", "gp", "ecx" ], + out => [ "in_r1 !in_r2 !in_r3", "flags" ] }, + ins => [ "val_high", "val_low", "count" ], + outs => [ "res", "flags" ], + emit => ". shrd%M %SB2, %S1, %D0", latency => 6, units => [ "GP" ], mode => $mode_gp, @@ -758,15 +789,19 @@ ShrD => { l_ShrD => { cmp_attr => "return 1;", - arity => 3 + arity => 3, + ins => [ "val_high", "val_low", "count" ], }, Sar => { irn_flags => "R", - reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] }, + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, ins => [ "val", "count" ], + outs => [ "res", "flags" ], emit => '. sar %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -778,22 +813,26 @@ SarMem => { ins => [ "base", "index", "mem", "count" ], emit => '. sar%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, l_SarDep => { cmp_attr => "return 1;", - # value, cnt, dependency + ins => [ "val", "count", "dep" ], arity => 3 }, Ror => { irn_flags => "R", - reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] }, + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, ins => [ "val", "count" ], + outs => [ "res", "flags" ], emit => '. ror %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -805,16 +844,20 @@ RorMem => { ins => [ "base", "index", "mem", "count" ], emit => '. ror%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, Rol => { irn_flags => "R", - reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] }, + reg_req => { in => [ "gp", "ecx" ], + out => [ "in_r1 !in_r2", "flags" ] }, ins => [ "val", "count" ], + outs => [ "res", "flags" ], emit => '. rol %SB1, %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -826,6 +869,7 @@ RolMem => { ins => [ "base", "index", "mem", "count" ], emit => '. rol%M %SB3, %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -834,10 +878,13 @@ RolMem => { Neg => { irn_flags => "R", - reg_req => { in => [ "gp" ], out => [ "in_r1" ] }, + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, emit => '. neg %S0', ins => [ "val" ], + outs => [ "res", "flags" ], units => [ "GP" ], + latency => 1, mode => $mode_gp, modified_flags => $status_flags }, @@ -849,6 +896,7 @@ NegMem => { ins => [ "base", "index", "mem" ], emit => '. neg%M %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", modified_flags => $status_flags }, @@ -858,21 +906,20 @@ Minus64Bit => { reg_req => { in => [ "gp", "gp" ], out => [ "in_r1", "gp" ] }, outs => [ "low_res", "high_res" ], units => [ "GP" ], + latency => 3, modified_flags => $status_flags }, -l_Neg => { - cmp_attr => "return 1;", - arity => 1, -}, - Inc => { irn_flags => "R", - reg_req => { in => [ "gp" ], out => [ "in_r1" ] }, + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, + outs => [ "res", "flags" ], emit => '. inc %S0', units => [ "GP" ], mode => $mode_gp, + latency => 1, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] }, @@ -884,15 +931,19 @@ IncMem => { emit => '. inc%M %AM', units => [ "GP" ], mode => "mode_M", + latency => 1, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] }, Dec => { irn_flags => "R", - reg_req => { in => [ "gp" ], out => [ "in_r1" ] }, + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, + outs => [ "res", "flags" ], emit => '. dec %S0', units => [ "GP" ], mode => $mode_gp, + latency => 1, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] }, @@ -904,16 +955,21 @@ DecMem => { emit => '. dec%M %AM', units => [ "GP" ], mode => "mode_M", + latency => 1, modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ] }, Not => { irn_flags => "R", - reg_req => { in => [ "gp" ], out => [ "in_r1" ] }, + reg_req => { in => [ "gp" ], + out => [ "in_r1", "flags" ] }, ins => [ "val" ], + outs => [ "res", "flags" ], emit => '. not %S0', units => [ "GP" ], + latency => 1, mode => $mode_gp, + # no flags modified }, NotMem => { @@ -923,7 +979,27 @@ NotMem => { ins => [ "base", "index", "mem" ], emit => '. not%M %AM', units => [ "GP" ], + latency => 1, mode => "mode_M", + # no flags modified +}, + +Cmc => { + reg_req => { in => [ "flags" ], out => [ "flags" ] }, + emit => '.cmc', + units => [ "GP" ], + latency => 1, + mode => $mode_flags, + modified_flags => $status_flags +}, + +Stc => { + reg_req => { out => [ "flags" ] }, + emit => '.stc', + units => [ "GP" ], + latency => 1, + mode => $mode_flags, + modified_flags => $status_flags }, # other operations @@ -1000,9 +1076,9 @@ Set => { #irn_flags => "R", reg_req => { in => [ "eflags" ], out => [ "eax ebx ecx edx" ] }, ins => [ "eflags" ], + attr_type => "ia32_condcode_attr_t", attr => "pn_Cmp pnc, int ins_permuted", - init_attr => "attr->pn_code = pnc;\n". - "attr->data.ins_permuted = ins_permuted;\n". + init_attr => "attr->attr.data.ins_permuted = ins_permuted;\n". "\tset_ia32_ls_mode(res, mode_Bu);\n", emit => '. set%CMP0 %DB0', latency => 1, @@ -1010,6 +1086,21 @@ Set => { mode => $mode_gp, }, +SetMem => { + #irn_flags => "R", + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "eflags" ], out => [ "none" ] }, + ins => [ "base", "index", "mem","eflags" ], + attr_type => "ia32_condcode_attr_t", + attr => "pn_Cmp pnc, int ins_permuted", + init_attr => "attr->attr.data.ins_permuted = ins_permuted;\n". + "\tset_ia32_ls_mode(res, mode_Bu);\n", + emit => '. set%CMP3 %AM', + latency => 1, + units => [ "GP" ], + mode => 'mode_M', +}, + CMov => { #irn_flags => "R", # (note: leave the false,true order intact to make it compatible with other @@ -1018,9 +1109,9 @@ CMov => { reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "eflags" ], out => [ "in_r4 in_r5" ] }, ins => [ "base", "index", "mem", "val_false", "val_true", "eflags" ], am => "source,binary", - attr => "int ins_permuted, pn_Cmp pn_code", - init_attr => "attr->pn_code = pn_code;\n". - "attr->data.ins_permuted = ins_permuted;", + attr_type => "ia32_condcode_attr_t", + attr => "int ins_permuted, pn_Cmp pnc", + init_attr => "attr->attr.data.ins_permuted = ins_permuted;", latency => 1, units => [ "GP" ], mode => $mode_gp, @@ -1032,8 +1123,8 @@ Jcc => { reg_req => { in => [ "eflags" ], out => [ "none", "none" ] }, ins => [ "eflags" ], outs => [ "false", "true" ], + attr_type => "ia32_condcode_attr_t", attr => "pn_Cmp pnc", - init_attr => "attr->pn_code = pnc;", latency => 2, units => [ "BRANCH" ], }, @@ -1042,17 +1133,22 @@ SwitchJmp => { state => "pinned", op_flags => "L|X|Y", reg_req => { in => [ "gp" ], out => [ "none" ] }, + mode => "mode_T", + attr_type => "ia32_condcode_attr_t", + attr => "pn_Cmp pnc", latency => 3, units => [ "BRANCH" ], - mode => "mode_T", - modified_flags => $status_flags + modified_flags => $status_flags, }, IJmp => { state => "pinned", op_flags => "X", - reg_req => { in => [ "gp" ] }, - emit => '. jmp *%S0', + reg_req => { in => [ "gp", "gp", "none", "gp" ] }, + ins => [ "base", "index", "mem", "target" ], + am => "source,unary", + emit => '. jmp *%unop3', + latency => 1, units => [ "BRANCH" ], mode => "mode_X", }, @@ -1064,9 +1160,17 @@ Const => { units => [ "GP" ], attr => "ir_entity *symconst, int symconst_sign, long offset", attr_type => "ia32_immediate_attr_t", + latency => 1, mode => $mode_gp, -# depends on the const and is set in ia32_transform -# modified_flags => $status_flags +}, + +GetEIP => { + op_flags => "c", + reg_req => { out => [ "gp" ] }, + units => [ "GP" ], + latency => 5, + mode => $mode_gp, + modified_flags => $status_flags, }, Unknown_GP => { @@ -1076,6 +1180,7 @@ Unknown_GP => { reg_req => { out => [ "gp_UKNWN" ] }, units => [], emit => "", + latency => 0, mode => $mode_gp }, @@ -1087,6 +1192,7 @@ Unknown_VFP => { units => [], emit => "", mode => "mode_E", + latency => 0, attr_type => "ia32_x87_attr_t", }, @@ -1097,6 +1203,7 @@ Unknown_XMM => { reg_req => { out => [ "xmm_UKNWN" ] }, units => [], emit => "", + latency => 0, mode => "mode_E" }, @@ -1107,6 +1214,7 @@ NoReg_GP => { reg_req => { out => [ "gp_NOREG" ] }, units => [], emit => "", + latency => 0, mode => $mode_gp }, @@ -1118,6 +1226,7 @@ NoReg_VFP => { units => [], emit => "", mode => "mode_E", + latency => 0, attr_type => "ia32_x87_attr_t", }, @@ -1128,6 +1237,7 @@ NoReg_XMM => { reg_req => { out => [ "xmm_NOREG" ] }, units => [], emit => "", + latency => 0, mode => "mode_E" }, @@ -1165,11 +1275,22 @@ FnstCW => { units => [ "GP" ], }, +FnstCWNOP => { + op_flags => "L|F", + state => "pinned", + reg_req => { in => [ "fp_cw" ], out => [ "none" ] }, + ins => [ "fpcw" ], + latency => 0, + emit => "", + mode => "mode_M", +}, + Cltd => { # we should not rematrialize this node. It has very strict constraints. reg_req => { in => [ "eax", "edx" ], out => [ "edx" ] }, ins => [ "val", "globbered" ], emit => '. cltd', + latency => 1, mode => $mode_gp, units => [ "GP" ], }, @@ -1182,9 +1303,9 @@ Cltd => { Load => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] }, + reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none", "none" ] }, ins => [ "base", "index", "mem" ], - outs => [ "res", "M" ], + outs => [ "res", "M", "X_exc" ], latency => 0, emit => ". mov%SE%ME%.l %AM, %D0", units => [ "GP" ], @@ -1208,8 +1329,9 @@ l_Store => { Store => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none", "none" ] }, ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], emit => '. mov%M %SI3, %AM', latency => 2, units => [ "GP" ], @@ -1219,8 +1341,9 @@ Store => { Store8Bit => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none" ] }, + reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none", "none" ] }, ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], emit => '. mov%M %SB3, %AM', latency => 2, units => [ "GP" ], @@ -1235,16 +1358,16 @@ Lea => { latency => 2, units => [ "GP" ], mode => $mode_gp, -# well this isn't true for Lea, but we often transform Lea back to Add, Inc -# or Dec, so we set the flag +# lea doesn't modify the flags, but setting this seems advantageous since it +# increases chances that the Lea is transformed back to an Add modified_flags => 1, }, Push => { state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "esp", "none" ] }, + reg_req => { in => [ "gp", "gp", "none", "gp", "esp" ], out => [ "esp", "none" ] }, ins => [ "base", "index", "mem", "val", "stack" ], - emit => '. push%M %unop4', + emit => '. push%M %unop3', outs => [ "stack:I|S", "M" ], am => "source,binary", latency => 2, @@ -1253,11 +1376,20 @@ Push => { Pop => { state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "esp" ], out => [ "esp", "gp", "none" ] }, - emit => '. pop%M %DAM1', - outs => [ "stack:I|S", "res", "M" ], + reg_req => { in => [ "none", "esp" ], out => [ "gp", "none", "none", "esp" ] }, + ins => [ "mem", "stack" ], + outs => [ "res", "M", "unused", "stack:I|S" ], + emit => '. pop%M %D0', + latency => 3, # Pop is more expensive than Push on Athlon + units => [ "GP" ], +}, + +PopMem => { + state => "exc_pinned", + reg_req => { in => [ "gp", "gp", "none", "esp" ], out => [ "none", "none", "none", "esp" ] }, ins => [ "base", "index", "mem", "stack" ], - am => "dest,unary", + outs => [ "unused0", "M", "unused1", "stack:I|S" ], + emit => '. pop%M %AM', latency => 3, # Pop is more expensive than Push on Athlon units => [ "GP" ], }, @@ -1285,7 +1417,8 @@ AddSP => { ins => [ "base", "index", "mem", "stack", "size" ], am => "source,binary", emit => '. addl %binop', - outs => [ "stack:S", "M" ], + latency => 1, + outs => [ "stack:I|S", "M" ], units => [ "GP" ], modified_flags => $status_flags }, @@ -1298,15 +1431,25 @@ SubSP => { am => "source,binary", emit => ". subl %binop\n". ". movl %%esp, %D1", + latency => 2, outs => [ "stack:I|S", "addr", "M" ], units => [ "GP" ], modified_flags => $status_flags }, +RepPrefix => { + op_flags => "K", + state => "pinned", + mode => "mode_M", + emit => ". rep", + latency => 0, +}, + LdTls => { irn_flags => "R", reg_req => { out => [ "gp" ] }, units => [ "GP" ], + latency => 1, }, @@ -1319,6 +1462,7 @@ LdTls => { # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # #-----------------------------------------------------------------------------# +# produces a 0/+0.0 xZero => { irn_flags => "R", reg_req => { out => [ "xmm" ] }, @@ -1328,6 +1472,56 @@ xZero => { mode => "mode_E", }, +# produces all 1 bits +xAllOnes => { + irn_flags => "R", + reg_req => { out => [ "xmm" ] }, + emit => '. pcmpeqb %D0, %D0', + latency => 3, + units => [ "SSE" ], + mode => "mode_E", +}, + +# integer shift left, dword +xPslld => { + irn_flags => "R", + reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] }, + emit => '. pslld %SI1, %D0', + units => [ "SSE" ], + mode => "mode_E", + latency => 3, +}, + +# integer shift left, qword +xPsllq => { + irn_flags => "R", + reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] }, + emit => '. psllq %SI1, %D0', + units => [ "SSE" ], + mode => "mode_E", + latency => 3, +}, + +# integer shift right, dword +xPsrld => { + irn_flags => "R", + reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] }, + emit => '. psrld %SI1, %D0', + units => [ "SSE" ], + mode => "mode_E", + latency => 1, +}, + +# mov from integer to SSE register +xMovd => { + irn_flags => "R", + reg_req => { in => [ "gp" ], out => [ "xmm" ] }, + emit => '. movd %S0, %D0', + units => [ "SSE" ], + mode => "mode_E", + latency => 1, +}, + # commutative operations xAdd => { @@ -1397,6 +1591,7 @@ xOr => { ins => [ "base", "index", "mem", "left", "right" ], am => "source,binary", emit => '. orp%XSD %binop', + latency => 3, units => [ "SSE" ], mode => "mode_E", }, @@ -1474,12 +1669,12 @@ Ucomi => { xLoad => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] }, + reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none", "none" ] }, ins => [ "base", "index", "mem" ], + outs => [ "res", "M", "X_exc" ], emit => '. mov%XXM %AM, %D0', attr => "ir_mode *load_mode", init_attr => "attr->ls_mode = load_mode;", - outs => [ "res", "M" ], latency => 0, units => [ "SSE" ], }, @@ -1487,8 +1682,9 @@ xLoad => { xStore => { op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "xmm" ] }, + reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "none", "none" ] }, ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], emit => '. mov%XXM %S3, %AM', latency => 0, units => [ "SSE" ], @@ -1531,36 +1727,43 @@ CvtSI2SD => { }, -l_X87toSSE => { +l_LLtoFloat => { op_flags => "L|F", cmp_attr => "return 1;", - arity => 3, + ins => [ "val_high", "val_low" ], }, -l_SSEtoX87 => { +l_FloattoLL => { op_flags => "L|F", cmp_attr => "return 1;", - arity => 3, + ins => [ "val" ], + outs => [ "res_high", "res_low" ], }, # CopyB CopyB => { - op_flags => "F|H", - state => "pinned", - reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] }, - outs => [ "DST", "SRC", "CNT", "M" ], - units => [ "GP" ], + op_flags => "F|H", + state => "pinned", + reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] }, + outs => [ "DST", "SRC", "CNT", "M" ], + attr_type => "ia32_copyb_attr_t", + attr => "unsigned size", + units => [ "GP" ], + latency => 3, # we don't care about this flag, so no need to mark this node # modified_flags => [ "DF" ] }, CopyB_i => { - op_flags => "F|H", - state => "pinned", - reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] }, - outs => [ "DST", "SRC", "M" ], - units => [ "GP" ], + op_flags => "F|H", + state => "pinned", + reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] }, + outs => [ "DST", "SRC", "M" ], + attr_type => "ia32_copyb_attr_t", + attr => "unsigned size", + units => [ "GP" ], + latency => 3, # we don't care about this flag, so no need to mark this node # modified_flags => [ "DF" ] }, @@ -1573,6 +1776,7 @@ Conv_I2I => { ins => [ "base", "index", "mem", "val" ], am => "source,unary", units => [ "GP" ], + latency => 1, attr => "ir_mode *smaller_mode", init_attr => "attr->ls_mode = smaller_mode;", mode => $mode_gp, @@ -1584,6 +1788,7 @@ Conv_I2I8Bit => { ins => [ "base", "index", "mem", "val" ], am => "source,unary", units => [ "GP" ], + latency => 1, attr => "ir_mode *smaller_mode", init_attr => "attr->ls_mode = smaller_mode;", mode => $mode_gp, @@ -1633,8 +1838,8 @@ Conv_FP2FP => { # |_| |_|\___/ \__,_|\___||___/ # #----------------------------------------------------------# -# spilling disabled for all float nodes for now, because the fpcw handler -# runs before spilling and we might end up with wrong fpcw then +# rematerialisation disabled for all float nodes for now, because the fpcw +# handler runs before spilling and we might end up with wrong fpcw then vfadd => { # irn_flags => "R", @@ -1715,11 +1920,12 @@ vfchs => { # virtual Load and Store vfld => { + irn_flags => "R", op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] }, + reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none", "none" ] }, ins => [ "base", "index", "mem" ], - outs => [ "res", "M" ], + outs => [ "res", "M", "X_exc" ], attr => "ir_mode *load_mode", init_attr => "attr->attr.ls_mode = load_mode;", latency => 2, @@ -1728,10 +1934,12 @@ vfld => { }, vfst => { + irn_flags => "R", op_flags => "L|F", state => "exc_pinned", - reg_req => { in => [ "gp", "gp", "none", "vfp" ] }, + reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "none", "none" ] }, ins => [ "base", "index", "mem", "val" ], + outs => [ "M", "X_exc" ], attr => "ir_mode *store_mode", init_attr => "attr->attr.ls_mode = store_mode;", latency => 2, @@ -1890,6 +2098,7 @@ Sahf => { ins => [ "val" ], outs => [ "flags" ], emit => '. sahf', + latency => 1, units => [ "GP" ], mode => $mode_flags, }, @@ -1906,142 +2115,143 @@ Sahf => { # are swapped, we work this around in the emitter... fadd => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fadd%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, faddp => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. faddp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fmul => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fmul%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fmulp => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fmulp%XM %x87_binop',, + latency => 4, attr_type => "ia32_x87_attr_t", }, fsub => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fsub%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fsubp => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, # see note about gas bugs emit => '. fsubrp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fsubr => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", irn_flags => "R", reg_req => { }, emit => '. fsubr%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fsubrp => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", irn_flags => "R", reg_req => { }, # see note about gas bugs emit => '. fsubp%XM %x87_binop', + latency => 4, attr_type => "ia32_x87_attr_t", }, fprem => { - op_flags => "R", rd_constructor => "NONE", reg_req => { }, emit => '. fprem1', + latency => 20, attr_type => "ia32_x87_attr_t", }, # this node is just here, to keep the simulator running # we can omit this when a fprem simulation function exists fpremp => { - op_flags => "R", rd_constructor => "NONE", reg_req => { }, - emit => '. fprem1', + emit => '. fprem1\n'. + '. fstp %X0', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdiv => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fdiv%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdivp => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, # see note about gas bugs emit => '. fdivrp%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdivr => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fdivr%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fdivrp => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, # see note about gas bugs emit => '. fdivp%XM %x87_binop', + latency => 20, attr_type => "ia32_x87_attr_t", }, fabs => { - op_flags => "R", rd_constructor => "NONE", reg_req => { }, emit => '. fabs', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -2050,6 +2260,7 @@ fchs => { rd_constructor => "NONE", reg_req => { }, emit => '. fchs', + latency => 4, attr_type => "ia32_x87_attr_t", }, @@ -2062,6 +2273,7 @@ fld => { reg_req => { }, emit => '. fld%XM %AM', attr_type => "ia32_x87_attr_t", + latency => 2, }, fst => { @@ -2072,6 +2284,7 @@ fst => { emit => '. fst%XM %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, fstp => { @@ -2082,37 +2295,38 @@ fstp => { emit => '. fstp%XM %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, # Conversions fild => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fild%M %AM', attr_type => "ia32_x87_attr_t", + latency => 2, }, fist => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fist%M %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, fistp => { - op_flags => "R", state => "exc_pinned", rd_constructor => "NONE", reg_req => { }, emit => '. fistp%M %AM', mode => "mode_M", attr_type => "ia32_x87_attr_t", + latency => 2, }, # constants @@ -2123,6 +2337,7 @@ fldz => { reg_req => { out => [ "vfp" ] }, emit => '. fldz', attr_type => "ia32_x87_attr_t", + latency => 2, }, fld1 => { @@ -2131,6 +2346,7 @@ fld1 => { reg_req => { out => [ "vfp" ] }, emit => '. fld1', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldpi => { @@ -2139,6 +2355,7 @@ fldpi => { reg_req => { out => [ "vfp" ] }, emit => '. fldpi', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldln2 => { @@ -2147,6 +2364,7 @@ fldln2 => { reg_req => { out => [ "vfp" ] }, emit => '. fldln2', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldlg2 => { @@ -2155,6 +2373,7 @@ fldlg2 => { reg_req => { out => [ "vfp" ] }, emit => '. fldlg2', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldl2t => { @@ -2163,6 +2382,7 @@ fldl2t => { reg_req => { out => [ "vfp" ] }, emit => '. fldll2t', attr_type => "ia32_x87_attr_t", + latency => 2, }, fldl2e => { @@ -2171,6 +2391,7 @@ fldl2e => { reg_req => { out => [ "vfp" ] }, emit => '. fldl2e', attr_type => "ia32_x87_attr_t", + latency => 2, }, # fxch, fpush, fpop @@ -2184,6 +2405,7 @@ fxch => { emit => '. fxch %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, fpush => { @@ -2193,14 +2415,15 @@ fpush => { emit => '. fld %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, fpushCopy => { - op_flags => "R", reg_req => { in => [ "vfp"], out => [ "vfp" ] }, cmp_attr => "return 1;", emit => '. fld %X0', attr_type => "ia32_x87_attr_t", + latency => 1, }, fpop => { @@ -2210,6 +2433,7 @@ fpop => { emit => '. fstp %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, ffreep => { @@ -2219,6 +2443,7 @@ ffreep => { emit => '. ffreep %X0', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 1, }, emms => { @@ -2228,6 +2453,7 @@ emms => { emit => '. emms', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 3, }, femms => { @@ -2237,6 +2463,7 @@ femms => { emit => '. femms', attr_type => "ia32_x87_attr_t", mode => "mode_ANY", + latency => 3, }, # compare @@ -2244,41 +2471,47 @@ femms => { FucomFnstsw => { reg_req => { }, emit => ". fucom %X1\n". - ". fnstsw", + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, FucompFnstsw => { reg_req => { }, emit => ". fucomp %X1\n". - ". fnstsw", + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, FucomppFnstsw => { reg_req => { }, emit => ". fucompp\n". - ". fnstsw", + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, Fucomi => { reg_req => { }, emit => '. fucomi %X1', attr_type => "ia32_x87_attr_t", + latency => 1, }, Fucompi => { reg_req => { }, emit => '. fucompi %X1', attr_type => "ia32_x87_attr_t", + latency => 1, }, FtstFnstsw => { reg_req => { }, emit => ". ftst\n". - ". fnstsw", + ". fnstsw %%ax", attr_type => "ia32_x87_attr_t", + latency => 2, }, @@ -2301,6 +2534,7 @@ xxLoad => { emit => '. movdqu %D0, %AM', outs => [ "res", "M" ], units => [ "SSE" ], + latency => 1, }, xxStore => { @@ -2310,6 +2544,7 @@ xxStore => { ins => [ "base", "index", "mem", "val" ], emit => '. movdqu %binop', units => [ "SSE" ], + latency => 1, mode => "mode_M", }, @@ -2322,3 +2557,28 @@ unless ($return = do $my_script_name) { warn "couldn't do $my_script_name: $!" unless defined $return; warn "couldn't run $my_script_name" unless $return; } + +# Transform some attributes +foreach my $op (keys(%nodes)) { + my $node = $nodes{$op}; + my $op_attr_init = $node->{op_attr_init}; + + if(defined($op_attr_init)) { + $op_attr_init .= "\n\t"; + } else { + $op_attr_init = ""; + } + + if(!defined($node->{latency})) { + if($op =~ m/^l_/) { + $node->{latency} = 0; + } else { + die("Latency missing for op $op"); + } + } + $op_attr_init .= "attr->latency = ".$node->{latency} . ";"; + + $node->{op_attr_init} = $op_attr_init; +} + +print "";