X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=709e1dbe57235bc976b4692be2e3e7bd81a0c804;hb=435d56a4e04e517c9dfb3e25bcad1ac44f9de2d2;hp=a4c7a72911e2d8d522fdb8e34f6686734ebd078d;hpb=c11262873a64779c78b8eee6118a1b0659d0f043;p=libfirm

diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl
index a4c7a7291..709e1dbe5 100644
--- a/ir/be/ia32/ia32_spec.pl
+++ b/ir/be/ia32/ia32_spec.pl
@@ -197,19 +197,22 @@ $arch = "ia32";
 	S1 => "${arch}_emit_source_register(node, 1);",
 	S2 => "${arch}_emit_source_register(node, 2);",
 	S3 => "${arch}_emit_source_register(node, 3);",
+	SB0 => "${arch}_emit_8bit_source_register_or_immediate(node, 0);",
 	SB1 => "${arch}_emit_8bit_source_register_or_immediate(node, 1);",
 	SB2 => "${arch}_emit_8bit_source_register_or_immediate(node, 2);",
 	SB3 => "${arch}_emit_8bit_source_register_or_immediate(node, 3);",
+	SH0 => "${arch}_emit_8bit_high_source_register(node, 0);",
+	SS0 => "${arch}_emit_16bit_source_register_or_immediate(node, 0);",
+	SI0 => "${arch}_emit_source_register_or_immediate(node, 0);",
 	SI1 => "${arch}_emit_source_register_or_immediate(node, 1);",
 	SI3 => "${arch}_emit_source_register_or_immediate(node, 3);",
 	D0 => "${arch}_emit_dest_register(node, 0);",
 	D1 => "${arch}_emit_dest_register(node, 1);",
+	DS0 => "${arch}_emit_dest_register_size(node, 0);",
 	DB0 => "${arch}_emit_8bit_dest_register(node, 0);",
 	X0 => "${arch}_emit_x87_register(node, 0);",
 	X1 => "${arch}_emit_x87_register(node, 1);",
-	SE => "${arch}_emit_extend_suffix(get_ia32_ls_mode(node));",
-	ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
-	           ia32_emit_mode_suffix(node);",
+	EX => "${arch}_emit_extend_suffix(node);",
 	M  => "${arch}_emit_mode_suffix(node);",
 	XM => "${arch}_emit_x87_mode_suffix(node);",
 	XXM => "${arch}_emit_xmm_mode_suffix(node);",
@@ -1337,7 +1340,7 @@ Load => {
 	ins       => [ "base", "index", "mem" ],
 	outs      => [ "res", "M", "X_exc" ],
 	latency   => 0,
-	emit      => ". mov%SE%ME%.l %AM, %D0",
+	emit      => ". mov%EX%.l %AM, %D0",
 	units     => [ "GP" ],
 },
 
@@ -1475,6 +1478,9 @@ LdTls => {
 	latency   => 1,
 },
 
+#
+# BT supports source address mode, but this is unused yet
+#
 Bt => {
 	irn_flags => "R",
 	state     => "exc_pinned",
@@ -1487,6 +1493,54 @@ Bt => {
 	modified_flags => $status_flags  # only CF is set, but the other flags are undefined
 },
 
+Bsf => {
+	irn_flags => "R",
+	state     => "exc_pinned",
+	reg_req   => { in => [ "gp", "gp", "none", "gp" ],
+	               out => [ "gp", "flags", "none" ] },
+	ins       => [ "base", "index", "mem", "operand" ],
+	outs      => [ "res", "flags", "M" ],
+	am        => "source,binary",
+	emit      => '. bsf%M %unop3, %D0',
+	units     => [ "GP" ],
+	latency   => 1,
+	mode      => $mode_gp,
+	modified_flags => $status_flags
+},
+
+Bsr => {
+	irn_flags => "R",
+	state     => "exc_pinned",
+	reg_req   => { in => [ "gp", "gp", "none", "gp" ],
+	               out => [ "gp", "flags", "none" ] },
+	ins       => [ "base", "index", "mem", "operand" ],
+	outs      => [ "res", "flags", "M" ],
+	am        => "source,binary",
+	emit      => '. bsr%M %unop3, %D0',
+	units     => [ "GP" ],
+	latency   => 1,
+	mode      => $mode_gp,
+	modified_flags => $status_flags
+},
+
+#
+# SSE4.2 or SSE4a popcnt instruction
+#
+Popcnt => {
+	irn_flags => "R",
+	state     => "exc_pinned",
+	reg_req   => { in => [ "gp", "gp", "none", "gp" ],
+	               out => [ "gp", "flags", "none" ] },
+	ins       => [ "base", "index", "mem", "operand" ],
+	outs      => [ "res", "flags", "M" ],
+	am        => "source,binary",
+	emit      => '. popcnt%M %unop3, %D0',
+	units     => [ "GP" ],
+	latency   => 1,
+	mode      => $mode_gp,
+	modified_flags => $status_flags
+},
+
 Call => {
 	state     => "exc_pinned",
 	reg_req   => {
@@ -1519,6 +1573,91 @@ ClimbFrame => {
 	mode      => $mode_gp
 },
 
+#
+# bswap
+#
+Bswap => {
+	irn_flags => "R",
+	reg_req   => { in => [ "gp" ],
+	               out => [ "in_r1" ] },
+	emit      => '. bswap%M %S0',
+	ins       => [ "val" ],
+	units     => [ "GP" ],
+	latency   => 1,
+	mode      => $mode_gp,
+},
+
+#
+# bswap16, use xchg here
+#
+Bswap16 => {
+	irn_flags => "R",
+	reg_req   => { in => [ "eax ebx ecx edx" ],
+	               out => [ "in_r1" ] },
+	emit      => '. xchg %SB0, %SH0',
+	ins       => [ "val" ],
+	units     => [ "GP" ],
+	latency   => 1,
+	mode      => $mode_gp,
+},
+
+#
+# BreakPoint
+#
+Breakpoint => {
+	state     => "pinned",
+	reg_req   => { in => [ "none" ], out => [ "none" ] },
+	ins       => [ "mem" ],
+	latency   => 0,
+	emit      => ". int3",
+	units     => [ "GP" ],
+	mode      => mode_M,
+},
+
+#
+# Undefined Instruction on ALL x86 CPU's
+#
+UD2 => {
+	state     => "pinned",
+	reg_req   => { in => [ "none" ], out => [ "none" ] },
+	ins       => [ "mem" ],
+	latency   => 0,
+	emit      => ". .value  0x0b0f",
+	units     => [ "GP" ],
+	mode      => mode_M,
+},
+
+#
+# outport
+#
+Outport => {
+	irn_flags => "R",
+	state     => "pinned",
+	reg_req   => { in => [ "edx", "eax", "none" ], out => [ "none" ] },
+	ins       => [ "port", "value", "mem" ],
+	emit      => '. out%M %SS0, %SI1',
+	units     => [ "GP" ],
+	latency   => 1,
+	mode      => mode_M,
+	modified_flags => $status_flags
+},
+
+#
+# inport
+#
+Inport => {
+	irn_flags => "R",
+	state     => "pinned",
+	reg_req   => { in => [ "edx", "none" ], out => [ "eax", "none" ] },
+	ins       => [ "port", "mem" ],
+	outs      => [ "res", "M" ],
+	emit      => '. in%M %DS0, %SS0',
+	units     => [ "GP" ],
+	latency   => 1,
+	mode      => mode_T,
+	modified_flags => $status_flags
+},
+
 #
 # Intel style prefetching
 #
@@ -1529,7 +1668,7 @@ Prefetch0 => {
 	ins       => [ "base", "index", "mem" ],
 	outs      => [ "M" ],
 	latency   => 0,
-	emit      => ". prefetch0 %AM",
+	emit      => ". prefetcht0 %AM",
 	units     => [ "GP" ],
 },
 
@@ -1540,7 +1679,7 @@ Prefetch1 => {
 	ins       => [ "base", "index", "mem" ],
 	outs      => [ "M" ],
 	latency   => 0,
-	emit      => ". prefetch1 %AM",
+	emit      => ". prefetcht1 %AM",
 	units     => [ "GP" ],
 },
 
@@ -1551,7 +1690,7 @@ Prefetch2 => {
 	ins       => [ "base", "index", "mem" ],
 	outs      => [ "M" ],
 	latency   => 0,
-	emit      => ". prefetch2 %AM",
+	emit      => ". prefetcht2 %AM",
 	units     => [ "GP" ],
 },