X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=582e78a719925ff86385cb16b0f5ae153f56fdfc;hb=1b8713c0eca7389d9db2a74302e206d718edc902;hp=c9cb278492a068ab86069d89e63e90e19e5ad826;hpb=a093f54a5ea7e62d4c8204b8327f30526e5dbee8;p=libfirm diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index c9cb27849..582e78a71 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -12,15 +12,17 @@ $arch = "ia32"; # %nodes = ( # # => { -# "op_flags" => "N|L|C|X|I|F|Y|H|c", -# "arity" => "0|1|2|3|variable|dynamic|all", -# "state" => "floats|pinned", -# "args" => [ -# { "type" => "type 1", "name" => "name 1" }, -# { "type" => "type 2", "name" => "name 2" }, -# ... -# ], -# "comment" => "any comment for constructor", +# "op_flags" => "N|L|C|X|I|F|Y|H|c|K", +# "irn_flags" => "R|N|I" +# "arity" => "0|1|2|3 ... |variable|dynamic|all", +# "state" => "floats|pinned", +# "args" => [ +# { "type" => "type 1", "name" => "name 1" }, +# { "type" => "type 2", "name" => "name 2" }, +# ... +# ], +# "comment" => "any comment for constructor", +# "emit" => "emit code with templates", # "rd_constructor" => "c source code which constructs an ir_node" # }, # @@ -28,6 +30,7 @@ $arch = "ia32"; # # ); # close the %nodes initializer +# op_flags: flags for the operation, OPTIONAL (default is "N") # the op_flags correspond to the firm irop_flags: # N irop_flag_none # L irop_flag_labeled @@ -38,8 +41,13 @@ $arch = "ia32"; # Y irop_flag_forking # H irop_flag_highlevel # c irop_flag_constlike +# K irop_flag_keep # -# op_flags: flags for the operation, OPTIONAL (default is "N") +# irn_flags: special node flags, OPTIONAL (default is 0) +# following irn_flags are supported: +# R rematerializeable +# N not spillable +# I ignore for register allocation # # state: state of the operation, OPTIONAL (default is "pinned") # @@ -65,13 +73,49 @@ $arch = "ia32"; # for i = 1 to arity # set in[i] = op_i # done -# res = new_ir_node(dbg, irg, block, op__, mode, in) -# res = optimize_node(res) -# IRN_VRFY_IRG(res, irg) +# res = new_ir_node(db, irg, block, op__, mode, arity, in) # return res # # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3 +# register types: +# 0 - no special type +# 1 - caller save (register must be saved by the caller of a function) +# 2 - callee save (register must be saved by the called function) +# 4 - ignore (do not assign this register) +# 8 - this is the stack pointer +# 16 - this is the base pointer +# NOTE: Make sure to list the registers returning the call-result before all other +# caller save registers and in the correct order, otherwise it will break +# the magic! +# Last entry of each class is the largest Firm-Mode a register can hold +%reg_classes = ( + "gp" => [ + { "name" => "eax", "type" => 1 }, + { "name" => "edx", "type" => 1 }, + { "name" => "ebx", "type" => 2 }, + { "name" => "ecx", "type" => 1 }, + { "name" => "esi", "type" => 2 }, + { "name" => "edi", "type" => 2 }, + { "name" => "ebp", "type" => 16 }, + { "name" => "esp", "type" => 8 }, + { "name" => "xxx", "type" => 4 }, # we need a dummy register for NoReg and Unknown nodes + { "mode" => "mode_P" } + ], + "fp" => [ + { "name" => "xmm0", "type" => 1 }, + { "name" => "xmm1", "type" => 1 }, + { "name" => "xmm2", "type" => 1 }, + { "name" => "xmm3", "type" => 1 }, + { "name" => "xmm4", "type" => 1 }, + { "name" => "xmm5", "type" => 1 }, + { "name" => "xmm6", "type" => 1 }, + { "name" => "xmm7", "type" => 1 }, + { "name" => "xxxx", "type" => 4 }, # we need a dummy register for NoReg and Unknown nodes + { "mode" => "mode_D" } + ] +); # %reg_classes + #--------------------------------------------------# # _ # # (_) # @@ -85,182 +129,493 @@ $arch = "ia32"; %nodes = ( -# arithmetic operations +#-----------------------------------------------------------------# +# _ _ _ # +# (_) | | | | # +# _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ # +# | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| # +# | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ # +# |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ # +# __/ | # +# |___/ # +#-----------------------------------------------------------------# # commutative operations -"Add" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b", -}, +# NOTE: +# All nodes supporting Addressmode have 5 INs: +# 1 - base r1 == NoReg in case of no AM or no base +# 2 - index r2 == NoReg in case of no AM or no index +# 3 - op1 r3 == always present +# 4 - op2 r4 == NoReg in case of immediate operation +# 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load -"Add_i" => { - "arity" => 1, - "comment" => "construct Add: Add(a, const) = Add(const, a) = a + const", - "rd_constructor" => "DEFAULT" +"Add" => { + "irn_flags" => "R", + "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. add %ia32_emit_binop\t\t\t/* Add(%A1, %A2) -> %D1 */' }, "Mul" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", + "irn_flags" => "A", + "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. imul %ia32_emit_binop\t\t\t/* Mul(%A1, %A2) -> %D1 */' }, -"Mul_i" => { - "state" => "pinned", - "arity" => 1, - "comment" => "construct Mul: Mul(a, const) = Mul(const, a) = a * const", +# Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX +"Mulh" => { + "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r2" ] }, + "emit" => '. imul %ia32_emit_unop\t\t\t/* Mulh(%A1, %A2) -> %D1 */ ' }, "And" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct And: And(a, b) = And(b, a) = a AND b", -}, - -"And_i" => { - "arity" => 1, - "comment" => "construct And: And(a, const) = And(const, a) = a AND const", + "irn_flags" => "R", + "comment" => "construct And: And(a, b) = And(b, a) = a AND b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. and %ia32_emit_binop\t\t\t/* And(%A1, %A2) -> %D1 */' }, "Or" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b", + "irn_flags" => "R", + "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. or %ia32_emit_binop\t\t\t/* Or(%A1, %A2) -> %D1 */' }, -"Or_i" => { - "arity" => 1, - "comment" => "construct Or: Or(a, const) = Or(const, a) = a OR const", +"Eor" => { + "irn_flags" => "R", + "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. xor %ia32_emit_binop\t\t\t/* Xor(%A1, %A2) -> %D1 */' }, -"Eor" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b", +"Max" => { + "irn_flags" => "R", + "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b", + "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] }, + "emit" => +'2. cmp %S1, %S2\t\t\t/* prepare Max (%S1 - %S2), (%A1, %A2) */ + if (mode_is_signed(get_irn_mode(n))) { +4. cmovl %D1, %S2\t\t\t/* %S1 is less %S2 */ + } + else { +4. cmovb %D1, %S2\t\t\t/* %S1 is below %S2 */ + } +' }, -"Eor_i" => { - "arity" => 1, - "comment" => "construct Eor: Eor(a, const) = Eor(const, a) = a EOR const", +"Min" => { + "irn_flags" => "R", + "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b", + "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] }, + "emit" => +'2. cmp %S1, %S2\t\t\t/* prepare Min (%S1 - %S2), (%A1, %A2) */ + if (mode_is_signed(get_irn_mode(n))) { +2. cmovg %D1, %S2\t\t\t/* %S1 is greater %S2 */ + } + else { +2. cmova %D1, %S2, %D1\t\t\t/* %S1 is above %S2 */ + } +' }, # not commutative operations "Sub" => { - "arity" => 2, - "comment" => "construct Sub: Sub(a, b) = a - b", + "irn_flags" => "R", + "comment" => "construct Sub: Sub(a, b) = a - b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. sub %ia32_emit_binop\t\t\t/* Sub(%A1, %A2) -> %D1 */' }, -"Sub_i" => { - "arity" => 1, - "comment" => "construct Sub: Sub(a, const) = a - const", +"DivMod" => { + "op_flags" => "F|L", + "state" => "exc_pinned", + "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] }, + "emit" => +' if (mode_is_signed(get_irn_mode(n))) { +4. idiv %S2\t\t\t/* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */ + } + else { +4. div %S2\t\t\t/* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */ + } +' }, -"Mod" => { - "arity" => 2, - "comment" => "construct Mod: Mod(a, b) = a % b", +"Shl" => { + "irn_flags" => "R", + "comment" => "construct Shl: Shl(a, b) = a << b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. shl %ia32_emit_binop\t\t\t/* Shl(%A1, %A2) -> %D1 */' }, -"Mod_i" => { - "arity" => 1, - "comment" => "construct Mod: Mod(a, const) = a % const", +"Shr" => { + "irn_flags" => "R", + "comment" => "construct Shr: Shr(a, b) = a >> b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. shr %ia32_emit_binop\t\t\t/* Shr(%A1, %A2) -> %D1 */' }, -"Shl" => { - "arity" => 2, - "comment" => "construct Shl: Shl(a, b) = a << b", +"Shrs" => { + "irn_flags" => "R", + "comment" => "construct Shrs: Shrs(a, b) = a >> b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. sar %ia32_emit_binop\t\t\t/* Shrs(%A1, %A2) -> %D1 */' }, -"Shl_i" => { - "arity" => 1, - "comment" => "construct Shl: Shl(a, const) = a << const", +"RotR" => { + "irn_flags" => "R", + "comment" => "construct RotR: RotR(a, b) = a ROTR b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. ror %ia32_emit_binop\t\t\t/* RotR(%A1, %A2) -> %D1 */' }, -"Shr" => { - "arity" => 2, - "comment" => "construct Shr: Shr(a, b) = a >> b", +"RotL" => { + "irn_flags" => "R", + "comment" => "construct RotL: RotL(a, b) = a ROTL b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. rol %ia32_emit_binop\t\t\t/* RotL(%A1, %A2) -> %D1 */' +}, + +# unary operations + +"Minus" => { + "irn_flags" => "R", + "comment" => "construct Minus: Minus(a) = -a", + "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. neg %ia32_emit_unop\t\t\t/* Neg(%A1) -> %D1, (%A1) */' }, -"Shr_i" => { +"Inc" => { + "irn_flags" => "R", + "comment" => "construct Increment: Inc(a) = a++", + "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. inc %ia32_emit_unop\t\t\t/* Inc(%S1) -> %D1, (%A1) */' +}, + +"Dec" => { + "irn_flags" => "R", + "comment" => "construct Decrement: Dec(a) = a--", + "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. dec %ia32_emit_unop\t\t\t/* Dec(%S1) -> %D1, (%A1) */' +}, + +"Not" => { + "irn_flags" => "R", + "comment" => "construct Not: Not(a) = !a", + "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. not %ia32_emit_unop\t\t\t/* Not(%S1) -> %D1, (%A1) */' +}, + +# other operations + +"Conv" => { "arity" => 1, - "comment" => "construct Shr: Shr(a, const) = a >> const", + "reg_req" => { "in" => [ "gp" ], "out" => [ "in_r1" ] }, + "comment" => "construct Conv: Conv(a) = (conv)a" }, -"Shrs" => { - "arity" => 2, - "comment" => "construct Shrs: Shrs(a, b) = a >> b", +"CondJmp" => { + "op_flags" => "L|X|Y", + "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] }, +}, + +"SwitchJmp" => { + "op_flags" => "L|X|Y", + "comment" => "construct switch", + "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "none" ] }, }, -"Shrs_i" => { +"Const" => { + "op_flags" => "c", + "irn_flags" => "R", + "comment" => "represents an integer constant", + "reg_req" => { "out" => [ "gp" ] }, + "emit" => '. mov %D1, %C\t\t\t/* Mov Const into register */', + "cmp_attr" => +' + if (attr_a->tp == attr_b->tp) { + if (attr_a->tp == ia32_SymConst) { + if (attr_a->sc == NULL || attr_b->sc == NULL) + return 1; + else + return strcmp(attr_a->sc, attr_b->sc); + } + else { + if (attr_a->tv == NULL || attr_b->tv == NULL) + return 1; + + if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq) + return 0; + else + return 1; + } + } + else + return 1; +' +}, + +"Cdq" => { + "irn_flags" => "R", + "comment" => "construct CDQ: sign extend EAX -> EDX:EAX", + "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] }, + "emit" => '. cdq\t\t\t/* sign extend EAX -> EDX:EAX, (%A1) */' +}, + +# Load / Store + +"Load" => { + "op_flags" => "L|F", + "irn_flags" => "R", + "state" => "exc_pinned", + "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg", + "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] }, + "emit" => '. mov %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */' +}, + +"Store" => { + "op_flags" => "L|F", + "state" => "exc_pinned", + "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val", + "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] }, + "emit" => '. mov %ia32_emit_am, %S3\t\t\t/* Store(%A2) -> (%A1) */' +}, + +"Lea" => { + "irn_flags" => "R", + "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8", + "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] }, + "emit" => '. lea %D1, %ia32_emit_am\t\t/* %D1 = %S1 + %S2 << %C + %O, (%A1, %A2) */' +}, + +"StackParam" => { "arity" => 1, - "comment" => "construct Shrs: Shrs(a, const) = a >> const", + "remat" => 1, + "comment" => "constructs a Stack Parameter to retrieve a parameter from Stack", + "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] }, + "cmp_attr" => +' + return (attr_a->pn_code != attr_b->pn_code); +' }, -"Rot" => { +"StackArg" => { "arity" => 2, - "comment" => "construct Rot: Rot(a, b) = a ROT b", + "comment" => "constructs a Stack Argument to pass an argument on Stack", + "reg_req" => { "in" => [ "none", "gp" ], "out" => [ "none" ] }, + "cmp_attr" => +' + return (attr_a->pn_code != attr_b->pn_code); +' }, -"Rot_i" => { - "arity" => 1, - "comment" => "construct Rot: Rot(a, const) = a ROT const", +#--------------------------------------------------------# +# __ _ _ _ # +# / _| | | | | | # +# | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ # +# | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| # +# | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ # +# |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # +#--------------------------------------------------------# + +# commutative operations + +"fAdd" => { + "irn_flags" => "R", + "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b", + "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. adds%M %ia32_emit_binop\t\t\t/* SSE Add(%A1, %A2) -> %D1 */' }, -"Minus" => { - "arity" => 1, - "comment" => "construct Minus: Minus(a) = -a", +"fMul" => { + "irn_flags" => "R", + "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b", + "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] }, + "emit" => '. muls%M %ia32_emit_binop\t\t\t/* SSE Mul(%A1, %A2) -> %D1 */' }, -"Inc" => { - "arity" => 1, - "comment" => "construct Increment: Inc(a) = a++", +"fMax" => { + "irn_flags" => "R", + "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b", + "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] }, + "emit" => '. maxs%M %ia32_emit_binop\t\t\t/* SSE Max(%A1, %A2) -> %D1 */' }, -"Dec" => { - "arity" => 1, - "comment" => "construct Decrement: Dec(a) = a--", +"fMin" => { + "irn_flags" => "R", + "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b", + "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] }, + "emit" => '. mins%M %ia32_emit_binop\t\t\t/* SSE Min(%A1, %A2) -> %D1 */' +}, + +"fAnd" => { + "irn_flags" => "R", + "comment" => "construct SSE And: And(a, b) = a AND b", + "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] }, + "emit" => '. andp%M %ia32_emit_binop\t\t\t/* SSE And(%A3, %A4) -> %D1 */' +}, + +"fOr" => { + "irn_flags" => "R", + "comment" => "construct SSE Or: Or(a, b) = a OR b", + "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] }, + "emit" => '. orp%M %ia32_emit_binop\t\t\t/* SSE Or(%A3, %A4) -> %D1 */' +}, + +"fEor" => { + "irn_flags" => "R", + "comment" => "construct SSE Eor: Eor(a, b) = a XOR b", + "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] }, + "emit" => '. xorp%M %ia32_emit_binop\t\t\t/* SSE Xor(%A3, %A4) -> %D1 */' +}, + +# not commutative operations + +"fSub" => { + "irn_flags" => "R", + "comment" => "construct SSE Sub: Sub(a, b) = a - b", + "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. subs%M %ia32_emit_binop\t\t\t/* SSE Sub(%A1, %A2) -> %D1 */' +}, + +"fDiv" => { + "irn_flags" => "R", + "comment" => "construct SSE Div: Div(a, b) = a / b", + "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] }, + "emit" => '. divs%M %ia32_emit_binop\t\t\t/* SSE Div(%A1, %A2) -> %D1 */' }, # other operations -"Conv" => { +"fConv" => { "arity" => 1, - "comment" => "construct Conv: Conv(a) = (conv)a", + "reg_req" => { "in" => [ "fp" ], "out" => [ "gp" ] }, + "comment" => "construct Conv: Conv(a) = (conv)a" }, -"Cmp" => { - "op_flags" => "C", - "arity" => 2, - "comment" => "construct Cmp: Cmp(a, b) = a CMP b", +"fCondJmp" => { + "op_flags" => "L|X|Y", + "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL", + "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "none", "none" ] }, }, -"Cmp_i" => { - "arity" => 1, - "comment" => "construct Cmp: Cmp(a, const) = Cmp(const, a) = a CMP const", +"fConst" => { + "op_flags" => "c", + "irn_flags" => "R", + "comment" => "represents a SSE constant", + "reg_req" => { "out" => [ "fp" ] }, + "emit" => '. mov%M %D1, %C\t\t\t/* Load fConst into register */', + "cmp_attr" => +' + if (attr_a->tp == attr_b->tp) { + if (attr_a->tp == ia32_SymConst) { + if (attr_a->sc == NULL || attr_b->sc == NULL) + return 1; + else + return strcmp(attr_a->sc, attr_b->sc); + } + else { + if (attr_a->tv == NULL || attr_b->tv == NULL) + return 1; + + if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq) + return 0; + else + return 1; + } + } + else + return 1; +' }, # Load / Store -"Load" => { - "arity" => 2, - "comment" => "construct Load: Load(mem-edge, ptr) = LD ptr", +"fLoad" => { + "op_flags" => "L|F", + "irn_flags" => "R", + "state" => "exc_pinned", + "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr", + "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp" ] }, + "emit" => '. movs%M %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */' }, -"Store" => { - "arity" => 3, - "comment" => "construct Store: Store(mem-edge, ptr, val) = ST ptr,val", +"fStore" => { + "op_flags" => "L|F", + "state" => "exc_pinned", + "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val", + "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ] }, + "emit" => '. movs%M %ia32_emit_am, %S3\t\t\t/* Store(%S3) -> (%A1) */' }, -"Lea" => { +"fStackParam" => { + "arity" => 1, + "remat" => 1, + "comment" => "constructs a Stack Parameter to retrieve a SSE parameter from Stack", + "reg_req" => { "in" => [ "none" ], "out" => [ "fp" ] }, + "cmp_attr" => +' + return (attr_a->pn_code != attr_b->pn_code); +' +}, + +"fStackArg" => { "arity" => 2, - "comment" => "construct Lea: Lea(a,b) = lea offs(a,b,const) | res = a + b * const + offs with const = 0,1,2,4,8", + "comment" => "constructs a Stack Argument to pass an argument on Stack", + "reg_req" => { "in" => [ "none", "fp" ], "out" => [ "none" ] }, + "cmp_attr" => +' + return (attr_a->pn_code != attr_b->pn_code); +' }, -"Lea_i" => { - "arity" => 1, - "comment" => "construct Lea: Lea(a) = lea offs(a) | res = a + offs", -} +# Call + +"Call" => { + "op_flags" => "L|F", + "state" => "mem_pinned", + "arity" => "variable", + "comment" => "construct Call: Call(...)", + "args" => [ + { "type" => "int", "name" => "n" }, + { "type" => "ir_node **", "name" => "in" } + ], + "rd_constructor" => +" if (!op_ia32_Call) assert(0); + return new_ir_node(db, irg, block, op_ia32_Call, mode_T, n, in); +" +}, + +# Return + +"Return" => { + "op_flags" => "L|X", + "state" => "pinned", + "arity" => "variable", + "comment" => "construct Return: Return(...)", + "args" => [ + { "type" => "int", "name" => "n" }, + { "type" => "ir_node **", "name" => "in" } + ], + "rd_constructor" => +" if (!op_ia32_Return) assert(0); + return new_ir_node(db, irg, block, op_ia32_Return, mode_X, n, in); +" +}, + +# M/Alloc + +"Alloca" => { + "op_flags" => "L|F", + "state" => "pinned", + "arity" => "2", + "comment" => "construct Alloca: allocate memory on Stack", + "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] } +}, ); # end of %nodes