X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=489e7f5e0a78923b7e0013ae4011b1a11ef85783;hb=ccc3b043755afa75de797214938d9246d9cf932a;hp=6d92b7d7f91bdfbbac87ceb7e8323ac9f39fb1a7;hpb=13dc182ad4f2a1e34735d19cba4bc5bd803e416a;p=libfirm diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index 6d92b7d7f..489e7f5e0 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -18,7 +18,7 @@ $comment_string = "/*"; # # => { # "op_flags" => "N|L|C|X|I|F|Y|H|c|K", -# "irn_flags" => "R|N|I" +# "irn_flags" => "R|N|I|S" # "arity" => "0|1|2|3 ... |variable|dynamic|any", # "state" => "floats|pinned|mem_pinned|exc_pinned", # "args" => [ @@ -33,6 +33,7 @@ $comment_string = "/*"; # "attr" => "attitional attribute arguments for constructor" # "init_attr" => "emit attribute initialization template" # "rd_constructor" => "c source code which constructs an ir_node" +# "latency" => "latency of this operation (can be float)" # }, # # ... # (all nodes you need to describe) @@ -57,6 +58,7 @@ $comment_string = "/*"; # R rematerializeable # N not spillable # I ignore for register allocation +# S modifies stack pointer # # state: state of the operation, OPTIONAL (default is "floats") # @@ -89,6 +91,9 @@ $comment_string = "/*"; # return res # # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3 +# +# latency: the latency of the operation, default is 1 +# # register types: # 0 - no special type @@ -104,6 +109,28 @@ $comment_string = "/*"; { "name" => "ecx", "type" => 1 }, { "name" => "esi", "type" => 2 }, { "name" => "edi", "type" => 2 }, +# { "name" => "r11", "type" => 1 }, +# { "name" => "r12", "type" => 1 }, +# { "name" => "r13", "type" => 1 }, +# { "name" => "r14", "type" => 1 }, +# { "name" => "r15", "type" => 1 }, +# { "name" => "r16", "type" => 1 }, +# { "name" => "r17", "type" => 1 }, +# { "name" => "r18", "type" => 1 }, +# { "name" => "r19", "type" => 1 }, +# { "name" => "r20", "type" => 1 }, +# { "name" => "r21", "type" => 1 }, +# { "name" => "r22", "type" => 1 }, +# { "name" => "r23", "type" => 1 }, +# { "name" => "r24", "type" => 1 }, +# { "name" => "r25", "type" => 1 }, +# { "name" => "r26", "type" => 1 }, +# { "name" => "r27", "type" => 1 }, +# { "name" => "r28", "type" => 1 }, +# { "name" => "r29", "type" => 1 }, +# { "name" => "r30", "type" => 1 }, +# { "name" => "r31", "type" => 1 }, +# { "name" => "r32", "type" => 1 }, { "name" => "ebp", "type" => 2 }, { "name" => "esp", "type" => 4 }, { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes @@ -191,10 +218,54 @@ $comment_string = "/*"; "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */', + "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], +}, + +"AddC" => { + "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, + "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */', "outs" => [ "res", "M" ], }, +"l_Add" => { + "op_flags" => "C", + "irn_flags" => "R", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b", + "arity" => 2, +}, + +"l_AddC" => { + "op_flags" => "C", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry", + "arity" => 2, +}, + +"MulS" => { + # we should not rematrialize this node. It produces 2 results and has + # very strict constrains + "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] }, + "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */', + "outs" => [ "EAX", "EDX", "M" ], + "latency" => 10, +}, + +"l_MulS" => { + # we should not rematrialize this node. It produces 2 results and has + # very strict constrains + "op_flags" => "C", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b", + "outs" => [ "EAX", "EDX", "M" ], + "arity" => 2 +}, + "Mul" => { "irn_flags" => "R", "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", @@ -202,15 +273,26 @@ $comment_string = "/*"; "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */', "outs" => [ "res", "M" ], + "latency" => 5, +}, + +"l_Mul" => { + "op_flags" => "C", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b", + "arity" => 2 }, # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX "Mulh" => { + # we should not rematrialize this node. It produces 2 results and has + # very strict constrains "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] }, - "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */', + "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] }, + "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */', "outs" => [ "EAX", "EDX", "M" ], + "latency" => 5, }, "And" => { @@ -240,6 +322,13 @@ $comment_string = "/*"; "outs" => [ "res", "M" ], }, +"l_Eor" => { + "op_flags" => "C", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b", + "arity" => 2 +}, + "Max" => { "irn_flags" => "R", "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b", @@ -252,7 +341,8 @@ $comment_string = "/*"; else { 4. cmovb %D1, %S2 /* %S1 is below %S2 */ } -' +', + "latency" => 2, }, "Min" => { @@ -267,17 +357,8 @@ $comment_string = "/*"; else { 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */ } -' -}, - -"CMov" => { - "irn_flags" => "R", - "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b", - "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] }, - "emit" => -'. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */ -. cmovne %D1, %S3 /* sel == true -> return %S3 */ -' +', + "latency" => 2, }, # not commutative operations @@ -287,19 +368,40 @@ $comment_string = "/*"; "comment" => "construct Sub: Sub(a, b) = a - b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */', + "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */', "outs" => [ "res", "M" ], }, +"SubC" => { + "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], +}, + +"l_Sub" => { + "irn_flags" => "R", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Sub: Sub(a, b) = a - b", + "arity" => 2, +}, + +"l_SubC" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry", + "arity" => 2, +}, + "DivMod" => { "op_flags" => "F|L", "state" => "exc_pinned", - "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] }, + "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] }, "attr" => "ia32_op_flavour_t dm_flav", "init_attr" => " attr->data.op_flav = dm_flav;", "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n", "emit" => -' if (mode_is_signed(get_irn_mode(n))) { +' if (mode_is_signed(get_ia32_res_mode(n))) { 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */ } else { @@ -307,35 +409,122 @@ $comment_string = "/*"; } ', "outs" => [ "div_res", "mod_res", "M" ], + "latency" => 25, }, "Shl" => { "irn_flags" => "R", "comment" => "construct Shl: Shl(a, b) = a << b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] }, "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */', "outs" => [ "res", "M" ], }, +"l_Shl" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Shl: Shl(a, b) = a << b", + "arity" => 2 +}, + +"ShlD" => { + "irn_flags" => "R", + "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] }, + "emit" => +' +if (get_ia32_immop_type(n) == ia32_ImmNone) { + if (get_ia32_op_type(n) == ia32_AddrModeD) { +4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */ + } + else { +4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */ + } +} +else { + if (get_ia32_op_type(n) == ia32_AddrModeD) { +4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */ + } + else { +4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */ + } +} +', + "outs" => [ "res", "M" ], + "latency" => 6, +}, + +"l_ShlD" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)", + "arity" => 3 +}, + "Shr" => { "irn_flags" => "R", "comment" => "construct Shr: Shr(a, b) = a >> b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] }, "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */', "outs" => [ "res", "M" ], }, +"l_Shr" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Shr: Shr(a, b) = a << b", + "arity" => 2 +}, + +"ShrD" => { + "irn_flags" => "R", + "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] }, + "emit" => +' +if (get_ia32_immop_type(n) == ia32_ImmNone) { + if (get_ia32_op_type(n) == ia32_AddrModeD) { +4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */ + } + else { +4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */ + } +} +else { + if (get_ia32_op_type(n) == ia32_AddrModeD) { +4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */ + } + else { +4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */ + } +} +', + "outs" => [ "res", "M" ], + "latency" => 6, +}, + +"l_ShrD" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)", + "arity" => 3 +}, + "Shrs" => { "irn_flags" => "R", "comment" => "construct Shrs: Shrs(a, b) = a >> b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] }, "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */', "outs" => [ "res", "M" ], }, +"l_Shrs" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Shrs: Shrs(a, b) = a << b", + "arity" => 2 +}, + "RotR" => { "irn_flags" => "R", "comment" => "construct RotR: RotR(a, b) = a ROTR b", @@ -365,6 +554,12 @@ $comment_string = "/*"; "outs" => [ "res", "M" ], }, +"l_Minus" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Minus: Minus(a) = -a", + "arity" => 1, +}, + "Inc" => { "irn_flags" => "R", "comment" => "construct Increment: Inc(a) = a++", @@ -400,6 +595,7 @@ $comment_string = "/*"; "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] }, "outs" => [ "false", "true" ], + "latency" => 3, }, "TestJmp" => { @@ -408,6 +604,7 @@ $comment_string = "/*"; "reg_req" => { "in" => [ "gp", "gp" ] }, "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "outs" => [ "false", "true" ], + "latency" => 3, }, "CJmpAM" => { @@ -430,6 +627,7 @@ $comment_string = "/*"; "comment" => "construct switch", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] }, + "latency" => 3, }, "Const" => { @@ -441,7 +639,8 @@ $comment_string = "/*"; }, "Cdq" => { - "irn_flags" => "R", + # we should not rematrialize this node. It produces 2 results and has + # very strict constrains "comment" => "construct CDQ: sign extend EAX -> EDX:EAX", "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] }, "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */', @@ -452,11 +651,11 @@ $comment_string = "/*"; "Load" => { "op_flags" => "L|F", - "irn_flags" => "R", "state" => "exc_pinned", "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] }, + "latency" => 3, "emit" => ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) { 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */ @@ -468,6 +667,23 @@ $comment_string = "/*"; "outs" => [ "res", "M" ], }, +"l_Load" => { + "op_flags" => "L|F", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg", + "outs" => [ "res", "M" ], + "arity" => 2, +}, + +"l_Store" => { + "op_flags" => "L|F", + "cmp_attr" => " return 1;\n", + "state" => "exc_pinned", + "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val", + "arity" => 3, + "outs" => [ "M" ], +}, + "Store" => { "op_flags" => "L|F", "state" => "exc_pinned", @@ -476,6 +692,7 @@ $comment_string = "/*"; "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] }, "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */', "outs" => [ "M" ], + "latency" => 3, }, "Store8Bit" => { @@ -483,9 +700,10 @@ $comment_string = "/*"; "state" => "exc_pinned", "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] }, + "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx gp_NOREG", "none" ] }, "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */', "outs" => [ "M" ], + "latency" => 3, }, "Lea" => { @@ -493,32 +711,26 @@ $comment_string = "/*"; "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] }, - "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */' + "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */', + "latency" => 2, }, "Push" => { - "comment" => "push a gp register on the stack", - "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] }, - "emit" => ' -if (get_ia32_id_cnst(n)) { - if (get_ia32_immop_type(n) == ia32_ImmConst) { -. push %C /* Push(%A2) */ - } else { -. push OFFSET FLAT:%C /* Push(%A2) */ - } -} -else { -. push %S2 /* Push(%A2) */ -} -', + # We don't set class modify_stack here (but we will do this on proj 0) + "comment" => "push on the stack", + "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp" ] }, + "emit" => '. push %ia32_emit_unop /* PUSH(%A1) */', "outs" => [ "stack", "M" ], + "latency" => 3, }, "Pop" => { + # We don't set class modify stack here (but we will do this on proj 1) "comment" => "pop a gp register from the stack", - "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] }, - "emit" => '. pop %D1 /* Pop -> %D1 */', + "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "gp", "esp" ] }, + "emit" => '. pop %ia32_emit_unop /* POP(%A1) */', "outs" => [ "res", "stack", "M" ], + "latency" => 4, }, "Enter" => { @@ -526,6 +738,7 @@ else { "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] }, "emit" => '. enter /* Enter */', "outs" => [ "frame", "stack", "M" ], + "latency" => 15, }, "Leave" => { @@ -533,8 +746,31 @@ else { "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] }, "emit" => '. leave /* Leave */', "outs" => [ "frame", "stack", "M" ], + "latency" => 3, +}, + +"AddSP" => { + "irn_flags" => "I", + "comment" => "allocate space on stack", + "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] }, + "outs" => [ "stack", "M" ], }, +"SubSP" => { + "irn_flags" => "I", + "comment" => "free space on stack", + "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] }, + "outs" => [ "stack", "M" ], +}, + +"LdTls" => { + "irn_flags" => "R", + "comment" => "get the TLS base address", + "reg_req" => { "out" => [ "gp" ] }, +}, + + + #-----------------------------------------------------------------------------# # _____ _____ ______ __ _ _ _ # # / ____/ ____| ____| / _| | | | | | # @@ -553,6 +789,7 @@ else { "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */', "outs" => [ "res", "M" ], + "latency" => 4, }, "xMul" => { @@ -562,6 +799,7 @@ else { "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */', "outs" => [ "res", "M" ], + "latency" => 4, }, "xMax" => { @@ -571,6 +809,7 @@ else { "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */', "outs" => [ "res", "M" ], + "latency" => 2, }, "xMin" => { @@ -580,6 +819,7 @@ else { "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */', "outs" => [ "res", "M" ], + "latency" => 2, }, "xAnd" => { @@ -589,6 +829,7 @@ else { "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */', "outs" => [ "res", "M" ], + "latency" => 3, }, "xOr" => { @@ -607,10 +848,21 @@ else { "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */', "outs" => [ "res", "M" ], + "latency" => 3, }, # not commutative operations +"xAndNot" => { + "irn_flags" => "R", + "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 3, +}, + "xSub" => { "irn_flags" => "R", "comment" => "construct SSE Sub: Sub(a, b) = a - b", @@ -618,6 +870,7 @@ else { "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */', "outs" => [ "res", "M" ], + "latency" => 4, }, "xDiv" => { @@ -627,16 +880,26 @@ else { "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] }, "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */', "outs" => [ "res", "M" ], + "latency" => 16, }, # other operations +"xCmp" => { + "irn_flags" => "R", + "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b", + "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "outs" => [ "res", "M" ], + "latency" => 3, +}, + "xCondJmp" => { "op_flags" => "L|X|Y", "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] }, "outs" => [ "false", "true" ], + "latency" => 5, }, "xConst" => { @@ -646,19 +909,20 @@ else { "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] }, "emit" => '. movs%M %D1, %C /* Load fConst into register */', + "latency" => 2, }, # Load / Store "xLoad" => { "op_flags" => "L|F", - "irn_flags" => "R", "state" => "exc_pinned", "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] }, "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */', "outs" => [ "res", "M" ], + "latency" => 2, }, "xStore" => { @@ -669,6 +933,56 @@ else { "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] }, "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */', "outs" => [ "M" ], + "latency" => 2, +}, + +"xStoreSimple" => { + "op_flags" => "L|F", + "state" => "exc_pinned", + "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "xmm", "none" ] }, + "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */', + "outs" => [ "M" ], + "latency" => 2, +}, + +"l_X87toSSE" => { + "op_flags" => "L|F", + "comment" => "construct: transfer a value from x87 FPU into a SSE register", + "cmp_attr" => " return 1;\n", + "arity" => 3, +}, + +"l_SSEtoX87" => { + "op_flags" => "L|F", + "comment" => "construct: transfer a value from SSE register to x87 FPU", + "cmp_attr" => " return 1;\n", + "arity" => 3, +}, + +"GetST0" => { + "op_flags" => "L|F", + "irn_flags" => "I", + "state" => "exc_pinned", + "comment" => "store ST0 onto stack", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "none" ] }, + "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */', + "outs" => [ "M" ], + "latency" => 4, +}, + +"SetST0" => { + "op_flags" => "L|F", + "irn_flags" => "I", + "state" => "exc_pinned", + "comment" => "load ST0 from stack", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] }, + "emit" => '. fld %ia32_emit_am /* load ST0 from stack */', + "outs" => [ "res", "M" ], + "latency" => 2, }, # CopyB @@ -677,52 +991,123 @@ else { "op_flags" => "F|H", "state" => "pinned", "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)", - "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] }, + "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] }, + "outs" => [ "DST", "SRC", "CNT", "M" ], }, "CopyB_i" => { "op_flags" => "F|H", "state" => "pinned", "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] }, + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] }, + "outs" => [ "DST", "SRC", "M" ], }, # Conversions "Conv_I2I" => { "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] }, - "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", + "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", "comment" => "construct Conv Int -> Int", - "outs" => [ "res", "M" ], + "outs" => [ "res", "M" ], }, "Conv_I2I8Bit" => { "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] }, - "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", + "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", "comment" => "construct Conv Int -> Int", - "outs" => [ "res", "M" ], + "outs" => [ "res", "M" ], }, "Conv_I2FP" => { "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] }, - "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", + "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", "comment" => "construct Conv Int -> Floating Point", - "outs" => [ "res", "M" ], + "outs" => [ "res", "M" ], + "latency" => 10, }, "Conv_FP2I" => { "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] }, - "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", + "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", "comment" => "construct Conv Floating Point -> Int", - "outs" => [ "res", "M" ], + "outs" => [ "res", "M" ], + "latency" => 10, }, "Conv_FP2FP" => { "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] }, - "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", + "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", "comment" => "construct Conv Floating Point -> Floating Point", + "outs" => [ "res", "M" ], + "latency" => 8, +}, + +"CmpCMov" => { + "irn_flags" => "R", + "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }, + "latency" => 2, +}, + +"PsiCondCMov" => { + "irn_flags" => "R", + "comment" => "check if Psi condition tree evaluates to true and move result accordingly", + "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] }, + "latency" => 2, +}, + +"xCmpCMov" => { + "irn_flags" => "R", + "comment" => "construct Conditional Move: SSE Compare + int CMov ", + "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }, + "latency" => 5, +}, + +"vfCmpCMov" => { + "irn_flags" => "R", + "comment" => "construct Conditional Move: x87 Compare + int CMov", + "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }, + "latency" => 10, +}, + +"CmpSet" => { + "irn_flags" => "R", + "comment" => "construct Set: Set(sel) == sel ? 1 : 0", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] }, + "outs" => [ "res", "M" ], + "latency" => 2, +}, + +"PsiCondSet" => { + "irn_flags" => "R", + "comment" => "check if Psi condition tree evaluates to true and set result accordingly", + "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] }, + "latency" => 2, +}, + +"xCmpSet" => { + "irn_flags" => "R", + "comment" => "construct Set: SSE Compare + int Set", + "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] }, + "outs" => [ "res", "M" ], + "latency" => 5, +}, + +"vfCmpSet" => { + "irn_flags" => "R", + "comment" => "construct Set: x87 Compare + int Set", + "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] }, "outs" => [ "res", "M" ], + "latency" => 10, +}, + +"vfCMov" => { + "irn_flags" => "R", + "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b", + "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }, + "latency" => 10, }, #----------------------------------------------------------# @@ -745,14 +1130,23 @@ else { "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, "outs" => [ "res", "M" ], + "latency" => 4, }, "vfmul" => { "irn_flags" => "R", - "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b", + "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, "outs" => [ "res", "M" ], + "latency" => 4, +}, + +"l_vfmul" => { + "op_flags" => "C", + "cmp_attr" => " return 1;\n", + "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b", + "arity" => 2, }, "vfsub" => { @@ -761,6 +1155,13 @@ else { "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, "outs" => [ "res", "M" ], + "latency" => 4, +}, + +"l_vfsub" => { + "cmp_attr" => " return 1;\n", + "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b", + "arity" => 2, }, "vfdiv" => { @@ -768,48 +1169,60 @@ else { "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, "outs" => [ "res", "M" ], + "latency" => 20, +}, + +"l_vfdiv" => { + "cmp_attr" => " return 1;\n", + "comment" => "lowered virtual fp Div: Div(a, b) = a / b", + "arity" => 2, }, "vfabs" => { "irn_flags" => "R", "comment" => "virtual fp Abs: Abs(a) = |a|", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, + "latency" => 2, }, "vfchs" => { "irn_flags" => "R", "comment" => "virtual fp Chs: Chs(a) = -a", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, + "latency" => 2, }, "vfsin" => { "irn_flags" => "R", "comment" => "virtual fp Sin: Sin(a) = sin(a)", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, + "latency" => 150, }, "vfcos" => { "irn_flags" => "R", "comment" => "virtual fp Cos: Cos(a) = cos(a)", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, + "latency" => 150, }, "vfsqrt" => { "irn_flags" => "R", "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, + "latency" => 30, }, # virtual Load and Store "vfld" => { "op_flags" => "L|F", - "irn_flags" => "R", "state" => "exc_pinned", "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] }, "outs" => [ "res", "M" ], + "latency" => 2, }, "vfst" => { @@ -819,16 +1232,24 @@ else { "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] }, "outs" => [ "M" ], + "latency" => 2, }, # Conversions "vfild" => { - "irn_flags" => "R", "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] }, "outs" => [ "res", "M" ], + "latency" => 4, +}, + +"l_vfild" => { + "cmp_attr" => " return 1;\n", + "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg", + "outs" => [ "res", "M" ], + "arity" => 2, }, "vfist" => { @@ -836,58 +1257,76 @@ else { "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] }, "outs" => [ "M" ], + "latency" => 4, +}, + +"l_vfist" => { + "cmp_attr" => " return 1;\n", + "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val", + "outs" => [ "M" ], + "arity" => 3, }, + # constants "vfldz" => { "irn_flags" => "R", "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfld1" => { "irn_flags" => "R", "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfldpi" => { "irn_flags" => "R", "comment" => "virtual fp Load pi: Ld pi -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfldln2" => { "irn_flags" => "R", "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfldlg2" => { "irn_flags" => "R", "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfldl2t" => { "irn_flags" => "R", "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfldl2e" => { "irn_flags" => "R", "comment" => "virtual fp Load ld e: Ld ld e -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfConst" => { "op_flags" => "c", "irn_flags" => "R", + "init_attr" => " set_ia32_ls_mode(res, mode);", "comment" => "represents a virtual floating point constant", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] }, + "latency" => 3, }, # other @@ -898,6 +1337,7 @@ else { "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] }, "outs" => [ "false", "true", "temp_reg_eax" ], + "latency" => 10, }, #------------------------------------------------------------------------# @@ -913,7 +1353,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b", "reg_req" => { }, - "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */', + "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */', }, "faddp" => { @@ -921,7 +1361,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b", "reg_req" => { }, - "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */', + "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */', }, "fmul" => { @@ -929,7 +1369,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b", "reg_req" => { }, - "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */', + "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */', }, "fmulp" => { @@ -937,7 +1377,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b", "reg_req" => { }, - "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */',, + "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',, }, "fsub" => { @@ -945,7 +1385,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp Sub: Sub(a, b) = a - b", "reg_req" => { }, - "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */', + "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */', }, "fsubp" => { @@ -953,7 +1393,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp Sub: Sub(a, b) = a - b", "reg_req" => { }, - "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */', + "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */', }, "fsubr" => { @@ -962,7 +1402,7 @@ else { "irn_flags" => "R", "comment" => "x87 fp SubR: SubR(a, b) = b - a", "reg_req" => { }, - "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */', + "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */', }, "fsubrp" => { @@ -971,7 +1411,7 @@ else { "irn_flags" => "R", "comment" => "x87 fp SubR: SubR(a, b) = b - a", "reg_req" => { }, - "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */', + "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */', }, "fdiv" => { @@ -979,7 +1419,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp Div: Div(a, b) = a / b", "reg_req" => { }, - "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */', + "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */', }, "fdivp" => { @@ -987,7 +1427,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp Div: Div(a, b) = a / b", "reg_req" => { }, - "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */', + "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */', }, "fdivr" => { @@ -995,7 +1435,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp DivR: DivR(a, b) = b / a", "reg_req" => { }, - "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */', + "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */', }, "fdivrp" => { @@ -1003,7 +1443,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp DivR: DivR(a, b) = b / a", "reg_req" => { }, - "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */', + "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */', }, "fabs" => { @@ -1011,7 +1451,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp Abs: Abs(a) = |a|", "reg_req" => { }, - "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */', + "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */', }, "fchs" => { @@ -1019,7 +1459,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp Chs: Chs(a) = -a", "reg_req" => { }, - "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */', + "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */', }, "fsin" => { @@ -1027,7 +1467,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp Sin: Sin(a) = sin(a)", "reg_req" => { }, - "emit" => '. fsin /* x87 sin(%S1) -> %D1 */', + "emit" => '. fsin /* x87 sin(%A1) -> %D1 */', }, "fcos" => { @@ -1035,7 +1475,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp Cos: Cos(a) = cos(a)", "reg_req" => { }, - "emit" => '. fcos /* x87 cos(%S1) -> %D1 */', + "emit" => '. fcos /* x87 cos(%A1) -> %D1 */', }, "fsqrt" => { @@ -1043,7 +1483,7 @@ else { "rd_constructor" => "NONE", "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5", "reg_req" => { }, - "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */', + "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */', }, # x87 Load and Store @@ -1079,7 +1519,7 @@ else { "fild" => { "op_flags" => "R", - "irn_flags" => "R", + "rd_constructor" => "NONE", "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg", "reg_req" => { }, "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */', @@ -1104,69 +1544,69 @@ else { # constants "fldz" => { - "op_flags" => "R", - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg", "reg_req" => { }, "emit" => '. fldz /* x87 0.0 -> %D1 */', }, "fld1" => { - "op_flags" => "R", - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg", "reg_req" => { }, "emit" => '. fld1 /* x87 1.0 -> %D1 */', }, "fldpi" => { - "op_flags" => "R", - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load pi: Ld pi -> reg", "reg_req" => { }, "emit" => '. fldpi /* x87 pi -> %D1 */', }, "fldln2" => { - "op_flags" => "R", - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg", "reg_req" => { }, "emit" => '. fldln2 /* x87 ln(2) -> %D1 */', }, "fldlg2" => { - "op_flags" => "R", - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg", "reg_req" => { }, "emit" => '. fldlg2 /* x87 log(2) -> %D1 */', }, "fldl2t" => { - "op_flags" => "R", - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg", "reg_req" => { }, "emit" => '. fldll2t /* x87 ld(10) -> %D1 */', }, "fldl2e" => { - "op_flags" => "R", - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load ld e: Ld ld e -> reg", "reg_req" => { }, "emit" => '. fldl2e /* x87 ld(e) -> %D1 */', }, "fldConst" => { - "op_flags" => "R", - "op_flags" => "c", + "op_flags" => "R|c", "irn_flags" => "R", + "rd_constructor" => "NONE", "comment" => "represents a x87 constant", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "out" => [ "st" ] }, - "emit" => '. fld%M %C /* Load fConst into register -> %D1 */', + "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */', }, # fxch, fpush, fpop @@ -1191,7 +1631,7 @@ else { "fpop" => { "op_flags" => "R|K", "comment" => "x87 stack pop", - "reg_req" => { "in" => [ "st"], "out" => [ "st" ] }, + "reg_req" => { "out" => [ "st" ] }, "cmp_attr" => " return 1;\n", "emit" => '. fstp %X1 /* x87 pop %X1 */', },