X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_spec.pl;h=0d32820d6ef70ff8b4f415a627e878c92efd7428;hb=08139f66b29d4e6ed0cd34312236d733cc903a34;hp=9bb8eaad9f19079563d876b047a29a246382da82;hpb=308688bf5bef393cf8b6ba31caf2e7c7e18bade3;p=libfirm diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl index 9bb8eaad9..0d32820d6 100644 --- a/ir/be/ia32/ia32_spec.pl +++ b/ir/be/ia32/ia32_spec.pl @@ -9,7 +9,7 @@ $arch = "ia32"; $comment_string = "/*"; # the number of additional opcodes you want to register -$additional_opcodes = 0; +#$additional_opcodes = 0; # The node description is done as a perl hash initializer with the # following structure: @@ -18,7 +18,7 @@ $additional_opcodes = 0; # # => { # "op_flags" => "N|L|C|X|I|F|Y|H|c|K", -# "irn_flags" => "R|N|I" +# "irn_flags" => "R|N|I|S" # "arity" => "0|1|2|3 ... |variable|dynamic|any", # "state" => "floats|pinned|mem_pinned|exc_pinned", # "args" => [ @@ -33,6 +33,7 @@ $additional_opcodes = 0; # "attr" => "attitional attribute arguments for constructor" # "init_attr" => "emit attribute initialization template" # "rd_constructor" => "c source code which constructs an ir_node" +# "latency" => "latency of this operation (can be float)" # }, # # ... # (all nodes you need to describe) @@ -57,6 +58,7 @@ $additional_opcodes = 0; # R rematerializeable # N not spillable # I ignore for register allocation +# S modifies stack pointer # # state: state of the operation, OPTIONAL (default is "floats") # @@ -69,6 +71,9 @@ $additional_opcodes = 0; # for i = 1 .. arity: ir_node *op_i # ir_mode *mode # +# outs: if a node defines more than one output, the names of the projections +# nodes having outs having automatically the mode mode_T +# # comment: OPTIONAL comment for the node constructor # # rd_constructor: for every operation there will be a @@ -86,6 +91,9 @@ $additional_opcodes = 0; # return res # # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3 +# +# latency: the latency of the operation, default is 1 +# # register types: # 0 - no special type @@ -101,9 +109,32 @@ $additional_opcodes = 0; { "name" => "ecx", "type" => 1 }, { "name" => "esi", "type" => 2 }, { "name" => "edi", "type" => 2 }, +# { "name" => "r11", "type" => 1 }, +# { "name" => "r12", "type" => 1 }, +# { "name" => "r13", "type" => 1 }, +# { "name" => "r14", "type" => 1 }, +# { "name" => "r15", "type" => 1 }, +# { "name" => "r16", "type" => 1 }, +# { "name" => "r17", "type" => 1 }, +# { "name" => "r18", "type" => 1 }, +# { "name" => "r19", "type" => 1 }, +# { "name" => "r20", "type" => 1 }, +# { "name" => "r21", "type" => 1 }, +# { "name" => "r22", "type" => 1 }, +# { "name" => "r23", "type" => 1 }, +# { "name" => "r24", "type" => 1 }, +# { "name" => "r25", "type" => 1 }, +# { "name" => "r26", "type" => 1 }, +# { "name" => "r27", "type" => 1 }, +# { "name" => "r28", "type" => 1 }, +# { "name" => "r29", "type" => 1 }, +# { "name" => "r30", "type" => 1 }, +# { "name" => "r31", "type" => 1 }, +# { "name" => "r32", "type" => 1 }, { "name" => "ebp", "type" => 2 }, { "name" => "esp", "type" => 4 }, - { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes + { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes + { "name" => "gp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes { "mode" => "mode_P" } ], "xmm" => [ @@ -115,7 +146,8 @@ $additional_opcodes = 0; { "name" => "xmm5", "type" => 1 }, { "name" => "xmm6", "type" => 1 }, { "name" => "xmm7", "type" => 1 }, - { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes + { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes + { "name" => "xmm_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes { "mode" => "mode_D" } ], "vfp" => [ @@ -126,8 +158,9 @@ $additional_opcodes = 0; { "name" => "vf4", "type" => 1 }, { "name" => "vf5", "type" => 1 }, { "name" => "vf6", "type" => 1 }, - { "name" => "vf7", "type" => 4 }, - { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes + { "name" => "vf7", "type" => 1 }, + { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg nodes + { "name" => "vfp_UKNWN", "type" => 6 }, # we need a dummy register for Unknown nodes { "mode" => "mode_E" } ], "st" => [ @@ -139,7 +172,6 @@ $additional_opcodes = 0; { "name" => "st5", "type" => 1 }, { "name" => "st6", "type" => 1 }, { "name" => "st7", "type" => 1 }, - { "name" => "st_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes { "mode" => "mode_E" } ] ); # %reg_classes @@ -155,6 +187,9 @@ $additional_opcodes = 0; # |_| # #--------------------------------------------------# +%operands = ( +); + %nodes = ( #-----------------------------------------------------------------# @@ -183,23 +218,75 @@ $additional_opcodes = 0; "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */', + "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], +}, + +"AddC" => { + "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, + "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], +}, + +"l_Add" => { + "op_flags" => "C", + "irn_flags" => "R", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b", + "arity" => 2, +}, + +"l_AddC" => { + "op_flags" => "C", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry", + "arity" => 2, +}, + +"MulS" => { + "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] }, + "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */', + "outs" => [ "EAX", "EDX", "M" ], + "latency" => 10, +}, + +"l_MulS" => { + "op_flags" => "C", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b", + "outs" => [ "EAX", "EDX", "M" ], + "arity" => 2 }, "Mul" => { - "irn_flags" => "A", + "irn_flags" => "R", "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */' + "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 5, +}, + +"l_Mul" => { + "op_flags" => "C", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b", + "arity" => 2 }, # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX "Mulh" => { "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] }, - "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */' + "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] }, + "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */', + "outs" => [ "EAX", "EDX", "M" ], + "latency" => 5, }, "And" => { @@ -207,7 +294,8 @@ $additional_opcodes = 0; "comment" => "construct And: And(a, b) = And(b, a) = a AND b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */' + "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */', + "outs" => [ "res", "M" ], }, "Or" => { @@ -215,7 +303,8 @@ $additional_opcodes = 0; "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */' + "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */', + "outs" => [ "res", "M" ], }, "Eor" => { @@ -223,7 +312,15 @@ $additional_opcodes = 0; "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */' + "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */', + "outs" => [ "res", "M" ], +}, + +"l_Eor" => { + "op_flags" => "C", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b", + "arity" => 2 }, "Max" => { @@ -238,7 +335,8 @@ $additional_opcodes = 0; else { 4. cmovb %D1, %S2 /* %S1 is below %S2 */ } -' +', + "latency" => 2, }, "Min" => { @@ -253,17 +351,8 @@ $additional_opcodes = 0; else { 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */ } -' -}, - -"CMov" => { - "irn_flags" => "R", - "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b", - "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] }, - "emit" => -'. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */ -. cmovne %D1, %S3 /* sel == true -> return %S3 */ -' +', + "latency" => 2, }, # not commutative operations @@ -273,21 +362,48 @@ $additional_opcodes = 0; "comment" => "construct Sub: Sub(a, b) = a - b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */' + "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], +}, + +"SubC" => { + "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], +}, + +"l_Sub" => { + "irn_flags" => "R", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Sub: Sub(a, b) = a - b", + "arity" => 2, +}, + +"l_SubC" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry", + "arity" => 2, }, "DivMod" => { - "op_flags" => "F|L", - "state" => "exc_pinned", - "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] }, - "emit" => -' if (mode_is_signed(get_irn_mode(n))) { + "op_flags" => "F|L", + "state" => "exc_pinned", + "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] }, + "attr" => "ia32_op_flavour_t dm_flav", + "init_attr" => " attr->data.op_flav = dm_flav;", + "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n", + "emit" => +' if (mode_is_signed(get_ia32_res_mode(n))) { 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */ } else { 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */ } -' +', + "outs" => [ "div_res", "mod_res", "M" ], + "latency" => 25, }, "Shl" => { @@ -295,7 +411,48 @@ $additional_opcodes = 0; "comment" => "construct Shl: Shl(a, b) = a << b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, - "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */' + "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */', + "outs" => [ "res", "M" ], +}, + +"l_Shl" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Shl: Shl(a, b) = a << b", + "arity" => 2 +}, + +"ShlD" => { + "irn_flags" => "R", + "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] }, + "emit" => +' +if (get_ia32_immop_type(n) == ia32_ImmNone) { + if (get_ia32_op_type(n) == ia32_AddrModeD) { +4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */ + } + else { +4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */ + } +} +else { + if (get_ia32_op_type(n) == ia32_AddrModeD) { +4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */ + } + else { +4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */ + } +} +', + "outs" => [ "res", "M" ], + "latency" => 6, +}, + +"l_ShlD" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)", + "arity" => 3 }, "Shr" => { @@ -303,7 +460,48 @@ $additional_opcodes = 0; "comment" => "construct Shr: Shr(a, b) = a >> b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, - "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */' + "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */', + "outs" => [ "res", "M" ], +}, + +"l_Shr" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Shr: Shr(a, b) = a << b", + "arity" => 2 +}, + +"ShrD" => { + "irn_flags" => "R", + "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!ecx in_r3 !in_r4" ] }, + "emit" => +' +if (get_ia32_immop_type(n) == ia32_ImmNone) { + if (get_ia32_op_type(n) == ia32_AddrModeD) { +4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */ + } + else { +4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */ + } +} +else { + if (get_ia32_op_type(n) == ia32_AddrModeD) { +4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */ + } + else { +4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */ + } +} +', + "outs" => [ "res", "M" ], + "latency" => 6, +}, + +"l_ShrD" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)", + "arity" => 3 }, "Shrs" => { @@ -311,7 +509,14 @@ $additional_opcodes = 0; "comment" => "construct Shrs: Shrs(a, b) = a >> b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, - "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */' + "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */', + "outs" => [ "res", "M" ], +}, + +"l_Shrs" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Shrs: Shrs(a, b) = a << b", + "arity" => 2 }, "RotR" => { @@ -319,7 +524,8 @@ $additional_opcodes = 0; "comment" => "construct RotR: RotR(a, b) = a ROTR b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, - "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */' + "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */', + "outs" => [ "res", "M" ], }, "RotL" => { @@ -327,7 +533,8 @@ $additional_opcodes = 0; "comment" => "construct RotL: RotL(a, b) = a ROTL b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] }, - "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */' + "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */', + "outs" => [ "res", "M" ], }, # unary operations @@ -337,7 +544,14 @@ $additional_opcodes = 0; "comment" => "construct Minus: Minus(a) = -a", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */' + "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */', + "outs" => [ "res", "M" ], +}, + +"l_Minus" => { + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Minus: Minus(a) = -a", + "arity" => 1, }, "Inc" => { @@ -345,7 +559,8 @@ $additional_opcodes = 0; "comment" => "construct Increment: Inc(a) = a++", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */' + "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */', + "outs" => [ "res", "M" ], }, "Dec" => { @@ -353,7 +568,8 @@ $additional_opcodes = 0; "comment" => "construct Decrement: Dec(a) = a--", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */' + "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */', + "outs" => [ "res", "M" ], }, "Not" => { @@ -361,7 +577,8 @@ $additional_opcodes = 0; "comment" => "construct Not: Not(a) = !a", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */' + "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */', + "outs" => [ "res", "M" ], }, # other operations @@ -371,6 +588,8 @@ $additional_opcodes = 0; "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] }, + "outs" => [ "false", "true" ], + "latency" => 3, }, "TestJmp" => { @@ -378,6 +597,8 @@ $additional_opcodes = 0; "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL", "reg_req" => { "in" => [ "gp", "gp" ] }, "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "outs" => [ "false", "true" ], + "latency" => 3, }, "CJmpAM" => { @@ -385,6 +606,7 @@ $additional_opcodes = 0; "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] }, + "outs" => [ "false", "true" ], }, "CJmp" => { @@ -399,6 +621,7 @@ $additional_opcodes = 0; "comment" => "construct switch", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] }, + "latency" => 3, }, "Const" => { @@ -406,38 +629,26 @@ $additional_opcodes = 0; "irn_flags" => "R", "comment" => "represents an integer constant", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "out" => [ "gp" ] }, - "emit" => -' if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) { -4. sub %D1, %D1 /* optimized mov 0 to register */ - } - else { - if (get_ia32_op_type(n) == ia32_SymConst) { -6. mov %D1, OFFSET FLAT:%C /* Move address of SymConst into register */ - } - else { -6. mov %D1, %C /* Mov Const into register */ - } - } -', + "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] }, }, "Cdq" => { "irn_flags" => "R", "comment" => "construct CDQ: sign extend EAX -> EDX:EAX", "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] }, - "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */' + "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */', + "outs" => [ "EAX", "EDX" ], }, # Load / Store "Load" => { "op_flags" => "L|F", - "irn_flags" => "R", "state" => "exc_pinned", "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] }, + "latency" => 3, "emit" => ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) { 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */ @@ -445,7 +656,25 @@ $additional_opcodes = 0; else { 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */ } -' +', + "outs" => [ "res", "M" ], +}, + +"l_Load" => { + "op_flags" => "L|F", + "cmp_attr" => " return 1;\n", + "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg", + "outs" => [ "res", "M" ], + "arity" => 2, +}, + +"l_Store" => { + "op_flags" => "L|F", + "cmp_attr" => " return 1;\n", + "state" => "exc_pinned", + "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val", + "arity" => 3, + "outs" => [ "M" ], }, "Store" => { @@ -454,7 +683,9 @@ $additional_opcodes = 0; "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] }, - "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */' + "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */', + "outs" => [ "M" ], + "latency" => 3, }, "Store8Bit" => { @@ -462,139 +693,303 @@ $additional_opcodes = 0; "state" => "exc_pinned", "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] } + "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] }, + "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */', + "outs" => [ "M" ], + "latency" => 3, }, "Lea" => { "irn_flags" => "R", "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] }, - "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */' + "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] }, + "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */', + "latency" => 2, +}, + +"Push" => { + # We don't set class modify_stack here (but we will do this on proj 0) + "comment" => "push a gp register on the stack", + "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "esp" ] }, + "emit" => ' +if (get_ia32_id_cnst(n)) { + if (get_ia32_immop_type(n) == ia32_ImmConst) { +4. push %C /* Push const on stack */ +} else { +4. push OFFSET FLAT:%C /* Push symconst on stack */ + } +} +else if (get_ia32_op_type(n) == ia32_Normal) { +2. push %S2 /* Push(%A2) */ +} +else { +2. push %ia32_emit_am /* Push memory to stack */ +}; +', + "outs" => [ "stack", "M" ], + "latency" => 3, +}, + +"Pop" => { + # We don't set class modify stack here (but we will do this on proj 1) + "comment" => "pop a gp register from the stack", + "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] }, + "emit" => ' +if (get_ia32_op_type(n) == ia32_Normal) { +2. pop %D1 /* Pop from stack into %D1 */ +} +else { +2. pop %ia32_emit_am /* Pop from stack into memory */ +} +', + "outs" => [ "res", "stack", "M" ], + "latency" => 4, +}, + +"Enter" => { + "comment" => "create stack frame", + "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] }, + "emit" => '. enter /* Enter */', + "outs" => [ "frame", "stack", "M" ], + "latency" => 15, +}, + +"Leave" => { + "comment" => "destroy stack frame", + "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] }, + "emit" => '. leave /* Leave */', + "outs" => [ "frame", "stack", "M" ], + "latency" => 3, +}, + +"AddSP" => { + "irn_flags" => "I", + "comment" => "allocate space on stack", + "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] }, + "outs" => [ "stack", "M" ], +}, + +"LdTls" => { + "irn_flags" => "R", + "comment" => "get the TLS base address", + "reg_req" => { "out" => [ "gp" ] }, }, -#--------------------------------------------------------# -# __ _ _ _ # -# / _| | | | | | # -# | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ # -# | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| # -# | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ # -# |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # -#--------------------------------------------------------# + + +#-----------------------------------------------------------------------------# +# _____ _____ ______ __ _ _ _ # +# / ____/ ____| ____| / _| | | | | | # +# | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ # +# \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| # +# ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ # +# |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # +#-----------------------------------------------------------------------------# # commutative operations -"fAdd" => { +"xAdd" => { "irn_flags" => "R", "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */' + "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 4, }, -"fMul" => { +"xMul" => { "irn_flags" => "R", "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */' + "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 4, }, -"fMax" => { +"xMax" => { "irn_flags" => "R", "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */' + "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 2, }, -"fMin" => { +"xMin" => { "irn_flags" => "R", "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */' + "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 2, }, -"fAnd" => { +"xAnd" => { "irn_flags" => "R", "comment" => "construct SSE And: And(a, b) = a AND b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */' + "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 3, }, -"fOr" => { +"xOr" => { "irn_flags" => "R", "comment" => "construct SSE Or: Or(a, b) = a OR b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */' + "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], }, -"fEor" => { +"xEor" => { "irn_flags" => "R", "comment" => "construct SSE Eor: Eor(a, b) = a XOR b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */' + "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 3, }, # not commutative operations -"fSub" => { +"xAndNot" => { + "irn_flags" => "R", + "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 3, +}, + +"xSub" => { "irn_flags" => "R", "comment" => "construct SSE Sub: Sub(a, b) = a - b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, - "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */' + "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 4, }, -"fDiv" => { +"xDiv" => { "irn_flags" => "R", "comment" => "construct SSE Div: Div(a, b) = a / b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] }, - "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */' + "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 16, }, # other operations -"fCondJmp" => { +"xCmp" => { + "irn_flags" => "R", + "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b", + "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] }, + "outs" => [ "res", "M" ], + "latency" => 3, +}, + +"xCondJmp" => { "op_flags" => "L|X|Y", "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] }, + "outs" => [ "false", "true" ], + "latency" => 5, }, -"fConst" => { +"xConst" => { "op_flags" => "c", "irn_flags" => "R", "comment" => "represents a SSE constant", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "out" => [ "xmm" ] }, - "emit" => '. mov%M %D1, %C /* Load fConst into register */', + "reg_req" => { "in" => [ "none" ], "out" => [ "xmm" ] }, + "emit" => '. movs%M %D1, %C /* Load fConst into register */', + "latency" => 2, }, # Load / Store -"fLoad" => { +"xLoad" => { "op_flags" => "L|F", - "irn_flags" => "R", "state" => "exc_pinned", "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] }, - "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */' + "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */', + "outs" => [ "res", "M" ], + "latency" => 2, }, -"fStore" => { +"xStore" => { "op_flags" => "L|F", "state" => "exc_pinned", "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] }, - "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */' + "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */', + "outs" => [ "M" ], + "latency" => 2, +}, + +"xStoreSimple" => { + "op_flags" => "L|F", + "state" => "exc_pinned", + "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "xmm", "none" ] }, + "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */', + "outs" => [ "M" ], + "latency" => 2, +}, + +"l_X87toSSE" => { + "op_flags" => "L|F", + "comment" => "construct: transfer a value from x87 FPU into a SSE register", + "cmp_attr" => " return 1;\n", + "arity" => 3, +}, + +"l_SSEtoX87" => { + "op_flags" => "L|F", + "comment" => "construct: transfer a value from SSE register to x87 FPU", + "cmp_attr" => " return 1;\n", + "arity" => 3, +}, + +"GetST0" => { + "op_flags" => "L|F", + "irn_flags" => "I", + "state" => "exc_pinned", + "comment" => "store ST0 onto stack", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "none" ] }, + "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */', + "outs" => [ "M" ], + "latency" => 4, +}, + +"SetST0" => { + "op_flags" => "L|F", + "irn_flags" => "I", + "state" => "exc_pinned", + "comment" => "load ST0 from stack", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "st0", "none" ] }, + "emit" => '. fld %ia32_emit_am /* load ST0 from stack */', + "outs" => [ "res", "M" ], + "latency" => 2, }, # CopyB @@ -603,72 +998,162 @@ $additional_opcodes = 0; "op_flags" => "F|H", "state" => "pinned", "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)", - "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] }, + "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] }, + "outs" => [ "DST", "SRC", "CNT", "M" ], }, "CopyB_i" => { "op_flags" => "F|H", "state" => "pinned", "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] }, + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] }, + "outs" => [ "DST", "SRC", "M" ], }, # Conversions "Conv_I2I" => { "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] }, - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "comment" => "construct Conv Int -> Int" + "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", + "comment" => "construct Conv Int -> Int", + "outs" => [ "res", "M" ], }, "Conv_I2I8Bit" => { "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] }, - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "comment" => "construct Conv Int -> Int" + "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", + "comment" => "construct Conv Int -> Int", + "outs" => [ "res", "M" ], }, "Conv_I2FP" => { "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] }, - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "comment" => "construct Conv Int -> Floating Point" + "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", + "comment" => "construct Conv Int -> Floating Point", + "outs" => [ "res", "M" ], + "latency" => 10, }, "Conv_FP2I" => { "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] }, - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "comment" => "construct Conv Floating Point -> Int" + "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", + "comment" => "construct Conv Floating Point -> Int", + "outs" => [ "res", "M" ], + "latency" => 10, }, "Conv_FP2FP" => { "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] }, - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n", "comment" => "construct Conv Floating Point -> Floating Point", + "outs" => [ "res", "M" ], + "latency" => 8, }, -#--------------------------------------------------------# -# __ _ _ _ # -# / _| | | | | | # -# | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ # -# | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| # -# | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ # -# |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # -#--------------------------------------------------------# +"CmpCMov" => { + "irn_flags" => "R", + "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] }, + "latency" => 2, +}, + +"PsiCondCMov" => { + "irn_flags" => "R", + "comment" => "check if Psi condition tree evaluates to true and move result accordingly", + "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] }, + "latency" => 2, +}, + +"xCmpCMov" => { + "irn_flags" => "R", + "comment" => "construct Conditional Move: SSE Compare + int CMov ", + "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] }, + "latency" => 5, +}, + +"vfCmpCMov" => { + "irn_flags" => "R", + "comment" => "construct Conditional Move: x87 Compare + int CMov", + "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] }, + "latency" => 10, +}, + +"CmpSet" => { + "irn_flags" => "R", + "comment" => "construct Set: Set(sel) == sel ? 1 : 0", + "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] }, + "outs" => [ "res", "M" ], + "latency" => 2, +}, + +"PsiCondSet" => { + "irn_flags" => "R", + "comment" => "check if Psi condition tree evaluates to true and set result accordingly", + "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] }, + "latency" => 2, +}, + +"xCmpSet" => { + "irn_flags" => "R", + "comment" => "construct Set: SSE Compare + int Set", + "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] }, + "outs" => [ "res", "M" ], + "latency" => 5, +}, -# virtual float nodes +"vfCmpSet" => { + "irn_flags" => "R", + "comment" => "construct Set: x87 Compare + int Set", + "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] }, + "outs" => [ "res", "M" ], + "latency" => 10, +}, + +"vfCMov" => { + "irn_flags" => "R", + "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b", + "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }, + "latency" => 10, +}, + +#----------------------------------------------------------# +# _ _ _ __ _ _ # +# (_) | | | | / _| | | | # +# __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ # +# \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| # +# \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ # +# \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| # +# | | # +# _ __ ___ __| | ___ ___ # +# | '_ \ / _ \ / _` |/ _ \/ __| # +# | | | | (_) | (_| | __/\__ \ # +# |_| |_|\___/ \__,_|\___||___/ # +#----------------------------------------------------------# "vfadd" => { "irn_flags" => "R", "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, + "outs" => [ "res", "M" ], + "latency" => 4, }, "vfmul" => { "irn_flags" => "R", - "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b", + "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, + "outs" => [ "res", "M" ], + "latency" => 4, +}, + +"l_vfmul" => { + "op_flags" => "C", + "cmp_attr" => " return 1;\n", + "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b", + "arity" => 2, }, "vfsub" => { @@ -676,66 +1161,75 @@ $additional_opcodes = 0; "comment" => "virtual fp Sub: Sub(a, b) = a - b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, + "outs" => [ "res", "M" ], + "latency" => 4, }, -"vfsubr" => { - "irn_flags" => "R", - "comment" => "virtual fp SubR: SubR(a, b) = b - a", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, +"l_vfsub" => { + "cmp_attr" => " return 1;\n", + "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b", + "arity" => 2, }, "vfdiv" => { "comment" => "virtual fp Div: Div(a, b) = a / b", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, + "outs" => [ "res", "M" ], + "latency" => 20, }, -"vfdivr" => { - "comment" => "virtual fp DivR: DivR(a, b) = b / a", - "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] }, +"l_vfdiv" => { + "cmp_attr" => " return 1;\n", + "comment" => "lowered virtual fp Div: Div(a, b) = a / b", + "arity" => 2, }, "vfabs" => { "irn_flags" => "R", "comment" => "virtual fp Abs: Abs(a) = |a|", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, + "latency" => 2, }, "vfchs" => { "irn_flags" => "R", "comment" => "virtual fp Chs: Chs(a) = -a", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, + "latency" => 2, }, "vfsin" => { "irn_flags" => "R", "comment" => "virtual fp Sin: Sin(a) = sin(a)", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, + "latency" => 150, }, "vfcos" => { "irn_flags" => "R", "comment" => "virtual fp Cos: Cos(a) = cos(a)", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, + "latency" => 150, }, "vfsqrt" => { "irn_flags" => "R", "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5", "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] }, + "latency" => 30, }, # virtual Load and Store "vfld" => { "op_flags" => "L|F", - "irn_flags" => "R", "state" => "exc_pinned", "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] }, + "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] }, + "outs" => [ "res", "M" ], + "latency" => 2, }, "vfst" => { @@ -744,343 +1238,453 @@ $additional_opcodes = 0; "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] }, + "outs" => [ "M" ], + "latency" => 2, }, # Conversions "vfild" => { - "irn_flags" => "R", "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] }, + "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] }, + "outs" => [ "res", "M" ], + "latency" => 4, +}, + +"l_vfild" => { + "cmp_attr" => " return 1;\n", + "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg", + "outs" => [ "res", "M" ], + "arity" => 2, }, "vfist" => { "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] }, + "outs" => [ "M" ], + "latency" => 4, }, +"l_vfist" => { + "cmp_attr" => " return 1;\n", + "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val", + "outs" => [ "M" ], + "arity" => 3, +}, + + # constants "vfldz" => { "irn_flags" => "R", "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfld1" => { "irn_flags" => "R", "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfldpi" => { "irn_flags" => "R", "comment" => "virtual fp Load pi: Ld pi -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfldln2" => { "irn_flags" => "R", "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfldlg2" => { "irn_flags" => "R", "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfldl2t" => { "irn_flags" => "R", "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfldl2e" => { "irn_flags" => "R", "comment" => "virtual fp Load ld e: Ld ld e -> reg", "reg_req" => { "out" => [ "vfp" ] }, + "latency" => 4, }, "vfConst" => { "op_flags" => "c", "irn_flags" => "R", + "init_attr" => " set_ia32_ls_mode(res, mode);", "comment" => "represents a virtual floating point constant", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", - "reg_req" => { "out" => [ "vfp" ] }, + "reg_req" => { "in" => [ "none" ], "out" => [ "vfp" ] }, + "latency" => 3, }, -#--------------------------------------------------------# -# __ _ _ _ # -# / _| | | | | | # -# | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ # -# | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| # -# | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ # -# |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # -#--------------------------------------------------------# +# other -# x87 float nodes +"vfCondJmp" => { + "op_flags" => "L|X|Y", + "comment" => "represents a virtual floating point compare", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] }, + "outs" => [ "false", "true", "temp_reg_eax" ], + "latency" => 10, +}, + +#------------------------------------------------------------------------# +# ___ _____ __ _ _ _ # +# __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ # +# \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| # +# > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ # +# /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ # +#------------------------------------------------------------------------# "fadd" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b", "reg_req" => { }, -# "emit" => '. fadd %ia32_emit_binop /* x87 fadd(%A1, %A2) -> %D1 */' - "emit" => '. fadd %X1, %X2 /* x87 fadd(%X1, %X2) -> %X3 */' + "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */', }, "faddp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b", "reg_req" => { }, -# "emit" => '. faddp %ia32_emit_binop /* x87 fadd(%A1, %A2) -> %D1 */' - "emit" => '. faddp %X1, %X2 /* x87 fadd(%X1, %X2) -> %X3 and pop */' + "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */', }, "fmul" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b", "reg_req" => { }, -# "emit" => '. fmul %ia32_emit_binop /* x87 fmul(%A1, %A2) -> %D1 */' - "emit" => '. fmul %X1, %X2 /* x87 fmul(%X1, %X2) -> %X3 */' + "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */', }, "fmulp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b", "reg_req" => { }, -# "emit" => '. fmulp %ia32_emit_binop /* x87 fmul(%A1, %A2) -> %D1 */' - "emit" => '. fmulp %X1, %X2 /* x87 fmul(%X1, %X2) -> %X3 and pop */' + "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',, }, "fsub" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Sub: Sub(a, b) = a - b", "reg_req" => { }, -# "emit" => '. fsub %ia32_emit_binop /* x87 fsub(%A1, %A2) -> %D1 */' - "emit" => '. fsub %X1, %X2 /* x87 fsub(%X1, %X2) -> %X3 */' + "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */', }, "fsubp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Sub: Sub(a, b) = a - b", "reg_req" => { }, -# "emit" => '. fsubp %ia32_emit_binop /* x87 fsub(%A1, %A2) -> %D1 */' - "emit" => '. fsubp %X1, %X2 /* x87 fsub(%X1, %X2) -> %X3 and pop */' + "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */', }, "fsubr" => { + "op_flags" => "R", "rd_constructor" => "NONE", "irn_flags" => "R", "comment" => "x87 fp SubR: SubR(a, b) = b - a", "reg_req" => { }, -# "emit" => '. fsubr %ia32_emit_binop /* x87 fsubr(%A1, %A2) -> %D1 */' - "emit" => '. fsubr %X1, %X2 /* x87 fsubr(%X1, %X2) -> %X3 */' + "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */', }, "fsubrp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "irn_flags" => "R", "comment" => "x87 fp SubR: SubR(a, b) = b - a", "reg_req" => { }, -# "emit" => '. fsubrp %ia32_emit_binop /* x87 fsubr(%A1, %A2) -> %D1 */' - "emit" => '. fsubrp %X1, %X2 /* x87 fsubr(%X1, %X2) -> %X3 and pop */' + "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */', }, "fdiv" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Div: Div(a, b) = a / b", "reg_req" => { }, -# "emit" => '. fdiv %ia32_emit_binop /* x87 fdiv(%A1, %A2) -> %D1 */' - "emit" => '. fdiv %X1, %X2 /* x87 fdiv(%X1, %X2) -> %X3 */' + "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */', }, "fdivp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Div: Div(a, b) = a / b", "reg_req" => { }, -# "emit" => '. fdivp %ia32_emit_binop /* x87 fdiv(%A1, %A2) -> %D1 */' - "emit" => '. fdivp %X1, %X2 /* x87 fdiv(%X1, %X2) -> %X3 and pop */' + "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */', }, "fdivr" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp DivR: DivR(a, b) = b / a", "reg_req" => { }, -# "emit" => '. fdivr %ia32_emit_binop /* x87 fdivr(%A1, %A2) -> %D1 */' - "emit" => '. fdivr %X1, %X2 /* x87 fdivr(%X1, %X2) -> %X3 */' + "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */', }, "fdivrp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp DivR: DivR(a, b) = b / a", "reg_req" => { }, -# "emit" => '. fdivrp %ia32_emit_binop /* x87 fdivr(%A1, %A2) -> %D1 */' - "emit" => '. fdivrp %X1, %X2 /* x87 fdivr(%X1, %X2) -> %X3 and pop */' + "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */', }, "fabs" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Abs: Abs(a) = |a|", "reg_req" => { }, - "emit" => '. fabs %X1 /* x87 fabs(%X1) -> %X3 */' + "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */', }, "fchs" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Chs: Chs(a) = -a", "reg_req" => { }, - "emit" => '. fchs %X1 /* x87 fchs(%X1) -> %X3 */' + "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */', }, "fsin" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Sin: Sin(a) = sin(a)", "reg_req" => { }, - "emit" => '. fsin %X1 /* x87 sin(%X1) -> %X3 */' + "emit" => '. fsin /* x87 sin(%A1) -> %D1 */', }, "fcos" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Cos: Cos(a) = cos(a)", "reg_req" => { }, - "emit" => '. fcos %X1 /* x87 cos(%X1) -> %X3 */' + "emit" => '. fcos /* x87 cos(%A1) -> %D1 */', }, "fsqrt" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5", "reg_req" => { }, - "emit" => '. fsqrt %X1 $ /* x87 sqrt(%X1) -> %X3 */' + "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */', }, # x87 Load and Store "fld" => { "rd_constructor" => "NONE", - "op_flags" => "L|F", + "op_flags" => "R|L|F", "state" => "exc_pinned", "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg", "reg_req" => { }, - "emit" => '. fld %X3, %ia32_emit_am /* Load((%A1)) -> %X3 */' + "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */', }, "fst" => { "rd_constructor" => "NONE", - "op_flags" => "L|F", + "op_flags" => "R|L|F", "state" => "exc_pinned", "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val", "reg_req" => { }, - "emit" => '. fst %ia32_emit_binop /* Store(%X3) -> (%A1) */' + "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */', }, "fstp" => { "rd_constructor" => "NONE", - "op_flags" => "L|F", + "op_flags" => "R|L|F", "state" => "exc_pinned", "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val", "reg_req" => { }, - "emit" => '. fstp %ia32_emit_binop /* Store(%X3) -> (%A1) and pop */' + "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */', }, # Conversions "fild" => { - "irn_flags" => "R", + "op_flags" => "R", + "rd_constructor" => "NONE", "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg", "reg_req" => { }, - "emit" => '. fild %X3, %ia32_emit_am /* integer Load((%A1)) -> %X3 */' + "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */', }, "fist" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val", "reg_req" => { }, - "emit" => '. fist %ia32_emit_binop /* integer Store(%X3) -> (%A1) */' + "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */', }, "fistp" => { + "op_flags" => "R", "rd_constructor" => "NONE", "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val", "reg_req" => { }, - "emit" => '. fistp %ia32_emit_binop /* integer Store(%X3) -> (%A1) and pop */' + "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */', }, # constants "fldz" => { - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg", "reg_req" => { }, - "emit" => '. fldz %X3 /* x87 0.0 -> %X3 */' + "emit" => '. fldz /* x87 0.0 -> %D1 */', }, "fld1" => { - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg", "reg_req" => { }, - "emit" => '. fld1 %X3 /* x87 1.0 -> %X3 */' + "emit" => '. fld1 /* x87 1.0 -> %D1 */', }, "fldpi" => { - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load pi: Ld pi -> reg", "reg_req" => { }, - "emit" => '. fldpi %X3 /* x87 pi -> %X3 */' + "emit" => '. fldpi /* x87 pi -> %D1 */', }, "fldln2" => { - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg", "reg_req" => { }, - "emit" => '. fldln2 %X3 /* x87 ln(2) -> %X3 */' + "emit" => '. fldln2 /* x87 ln(2) -> %D1 */', }, "fldlg2" => { - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg", "reg_req" => { }, - "emit" => '. fldlg2 %X3 /* x87 log(2) -> %X3 */' + "emit" => '. fldlg2 /* x87 log(2) -> %D1 */', }, "fldl2t" => { - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg", "reg_req" => { }, - "emit" => '. fldll2t %X3 /* x87 ld(10) -> %X3 */' + "emit" => '. fldll2t /* x87 ld(10) -> %D1 */', }, "fldl2e" => { - "rd_constructor" => "NONE", + "op_flags" => "R|c", + "irn_flags" => "R", "comment" => "x87 fp Load ld e: Ld ld e -> reg", "reg_req" => { }, - "emit" => '. fldl2e %X3 /* x87 ld(e) -> %X3 */' + "emit" => '. fldl2e /* x87 ld(e) -> %D1 */', }, "fldConst" => { - "op_flags" => "c", + "op_flags" => "R|c", "irn_flags" => "R", + "rd_constructor" => "NONE", "comment" => "represents a x87 constant", "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", "reg_req" => { "out" => [ "st" ] }, - "emit" => '. fld%M %C /* Load fConst into register -> %X3 */', + "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */', }, -# fxch, fpush +# fxch, fpush, fpop +# Note that it is NEVER allowed to do CSE on these nodes "fxch" => { + "op_flags" => "R|K", "comment" => "x87 stack exchange", "reg_req" => { "in" => [ "st"], "out" => [ "st" ] }, - "emit" => '. fxch %X1, %X3 /* x87 swap %X1, %X3 */', + "cmp_attr" => " return 1;\n", + "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */', }, "fpush" => { + "op_flags" => "R", "comment" => "x87 stack push", "reg_req" => { "in" => [ "st"], "out" => [ "st" ] }, + "cmp_attr" => " return 1;\n", "emit" => '. fld %X1 /* x87 push %X1 */', }, +"fpop" => { + "op_flags" => "R|K", + "comment" => "x87 stack pop", + "reg_req" => { "out" => [ "st" ] }, + "cmp_attr" => " return 1;\n", + "emit" => '. fstp %X1 /* x87 pop %X1 */', +}, + +# compare + +"fcomJmp" => { + "op_flags" => "L|X|Y", + "comment" => "floating point compare", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { }, +}, + +"fcompJmp" => { + "op_flags" => "L|X|Y", + "comment" => "floating point compare and pop", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { }, +}, + +"fcomppJmp" => { + "op_flags" => "L|X|Y", + "comment" => "floating point compare and pop twice", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { }, +}, + +"fcomrJmp" => { + "op_flags" => "L|X|Y", + "comment" => "floating point compare reverse", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { }, +}, + +"fcomrpJmp" => { + "op_flags" => "L|X|Y", + "comment" => "floating point compare reverse and pop", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { }, +}, + +"fcomrppJmp" => { + "op_flags" => "L|X|Y", + "comment" => "floating point compare reverse and pop twice", + "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n", + "reg_req" => { }, +}, + ); # end of %nodes