X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=fcfe4195d6435d8ea599d43d755976fbeae94594;hb=6cc3eb2c360735ef160acd81d396a9b149c51ea7;hp=43643acefca7d71553c8a84d138f1b883fdaee02;hpb=25787e66c8e7c13c5022e8e9b053eebfd5166923;p=libfirm diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c index 43643acef..fcfe4195d 100644 --- a/ir/be/ia32/ia32_optimize.c +++ b/ir/be/ia32/ia32_optimize.c @@ -6,10 +6,18 @@ #include "irprog_t.h" #include "ircons.h" #include "firm_types.h" +#include "iredges.h" +#include "tv.h" +#include "irgmod.h" + +#include "../benode_t.h" #include "ia32_new_nodes.h" #include "bearch_ia32_t.h" +#undef is_NoMem +#define is_NoMem(irn) (get_irn_op(irn) == op_NoMem) + /** * creates a unique ident by adding a number to a tag * @@ -157,7 +165,7 @@ void ia32_place_consts(ir_node *irn, void *env) { tenv.block = get_nodes_block(irn); tenv.cg = cg; tenv.irg = cg->irg; - tenv.mod = firm_dbg_register("ir.be.ia32.optimize"); + tenv.mod = cg->mod; /* Loop over all predecessors and check for Sym/Const nodes */ for (i = get_irn_arity(irn) - 1; i >= 0; --i) { @@ -191,3 +199,621 @@ void ia32_place_consts(ir_node *irn, void *env) { } } } + + +/****************************************************************** + * _ _ __ __ _ + * /\ | | | | | \/ | | | + * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___ + * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \ + * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/ + * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___| + * + ******************************************************************/ + +static int node_is_comm(const ir_node *irn) { + if (is_ia32_Add(irn) || + is_ia32_fAdd(irn) || + is_ia32_Mul(irn) || + is_ia32_Mulh(irn) || + is_ia32_fMul(irn) || + is_ia32_And(irn) || + is_ia32_fAnd(irn) || + is_ia32_Or(irn) || + is_ia32_fOr(irn) || + is_ia32_Eor(irn) || + is_ia32_fEor(irn) || + is_ia32_Min(irn) || + is_ia32_fMin(irn) || + is_ia32_Max(irn) || + is_ia32_fMax(irn)) + { + return 1; + } + + return 0; +} + +static int ia32_get_irn_n_edges(const ir_node *irn) { + const ir_edge_t *edge; + int cnt = 0; + + foreach_out_edge(irn, edge) { + cnt++; + } + + return cnt; +} + +/** + * Returns the first mode_M Proj connected to irn. + */ +static ir_node *get_mem_proj(const ir_node *irn) { + const ir_edge_t *edge; + ir_node *src; + + assert(get_irn_mode(irn) == mode_T && "expected mode_T node"); + + foreach_out_edge(irn, edge) { + src = get_edge_src_irn(edge); + + assert(is_Proj(src) && "Proj expected"); + + if (get_irn_mode(src) == mode_M) + return src; + } + + return NULL; +} + +/** + * Returns the Proj with number 0 connected to irn. + */ +static ir_node *get_res_proj(const ir_node *irn) { + const ir_edge_t *edge; + ir_node *src; + + assert(get_irn_mode(irn) == mode_T && "expected mode_T node"); + + foreach_out_edge(irn, edge) { + src = get_edge_src_irn(edge); + + assert(is_Proj(src) && "Proj expected"); + + if (get_Proj_proj(src) == 0) + return src; + } + + return NULL; +} + +/** + * Determines if pred is a Proj and if is_op_func returns true for it's predecessor. + * + * @param pred The node to be checked + * @param is_op_func The check-function + * @return 1 if conditions are fulfilled, 0 otherwise + */ +static int pred_is_specific_node(const ir_node *pred, int (*is_op_func)(const ir_node *n)) { + if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) { + return 1; + } + + return 0; +} + +/** + * Determines if pred is a Proj and if is_op_func returns true for it's predecessor + * and if the predecessor is in block bl. + * + * @param bl The block + * @param pred The node to be checked + * @param is_op_func The check-function + * @return 1 if conditions are fulfilled, 0 otherwise + */ +static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred, + int (*is_op_func)(const ir_node *n)) +{ + if (is_Proj(pred)) { + pred = get_Proj_pred(pred); + if ((bl == get_nodes_block(pred)) && is_op_func(pred)) { + return 1; + } + } + + return 0; +} + +/** + * Folds Add or Sub to LEA if possible + */ +static ir_node *fold_addr(ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) { + ir_graph *irg = get_irn_irg(irn); + ir_mode *mode = get_irn_mode(irn); + dbg_info *dbg = get_irn_dbg_info(irn); + ir_node *block = get_nodes_block(irn); + ir_node *res = irn; + char *offs = NULL; + char *offs_cnst = NULL; + char *offs_lea = NULL; + int scale = 0; + int isadd = 0; + int dolea = 0; + ir_node *left, *right, *temp; + ir_node *base, *index; + ia32_am_flavour_t am_flav; + + if (is_ia32_Add(irn)) + isadd = 1; + + left = get_irn_n(irn, 2); + right = get_irn_n(irn, 3); + + base = left; + index = noreg; + offs = NULL; + scale = 0; + am_flav = 0; + + /* "normalize" arguments in case of add with two operands */ + if (isadd && ! be_is_NoReg(right)) { + /* put LEA == ia32_am_O as right operand */ + if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) { + set_irn_n(irn, 2, right); + set_irn_n(irn, 3, left); + temp = left; + left = right; + right = temp; + } + + /* put LEA != ia32_am_O as left operand */ + if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) { + set_irn_n(irn, 2, right); + set_irn_n(irn, 3, left); + temp = left; + left = right; + right = temp; + } + + /* put SHL as left operand iff left is NOT a LEA */ + if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) { + set_irn_n(irn, 2, right); + set_irn_n(irn, 3, left); + temp = left; + left = right; + right = temp; + } + } + + /* check if operand is either const */ + if (get_ia32_cnst(irn)) { + DBG((mod, LEVEL_1, "\tfound op with imm")); + + offs_cnst = get_ia32_cnst(irn); + dolea = 1; + } + + /* determine the operand which needs to be checked */ + if (be_is_NoReg(right)) { + temp = left; + } + else { + temp = right; + } + + /* check if right operand is AMConst (LEA with ia32_am_O) */ + if (is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) { + DBG((mod, LEVEL_1, "\tgot op with LEA am_O")); + + offs_lea = get_ia32_am_offs(temp); + dolea = 1; + } + + if (isadd) { + /* default for add -> make right operand to index */ + index = right; + dolea = 1; + + DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index)); + + /* determine the operand which needs to be checked */ + temp = left; + if (is_ia32_Lea(left)) { + temp = right; + } + + /* check for SHL 1,2,3 */ + if (pred_is_specific_node(temp, is_ia32_Shl)) { + temp = get_Proj_pred(temp); + + if (get_ia32_Immop_tarval(temp)) { + scale = get_tarval_long(get_ia32_Immop_tarval(temp)); + + if (scale <= 3) { + scale = 1 << scale; + index = get_irn_n(temp, 2); + + DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index)); + } + } + } + + /* fix base */ + if (! be_is_NoReg(index)) { + /* if we have index, but left == right -> no base */ + if (left == right) { + base = noreg; + } + else if (! is_ia32_Lea(left) && (index != right)) { + /* index != right -> we found a good Shl */ + /* left != LEA -> this Shl was the left operand */ + /* -> base is right operand */ + base = right; + } + } + } + + /* Try to assimilate a LEA as left operand */ + if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) { + am_flav = get_ia32_am_flavour(left); + + /* If we have an Add with a real right operand (not NoReg) and */ + /* the LEA contains already an index calculation then we create */ + /* a new LEA. */ + if (isadd && !be_is_NoReg(index) && (am_flav & ia32_am_I)) { + DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n")); + } + else { + DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n")); + offs = get_ia32_am_offs(left); + base = get_irn_n(left, 0); + index = get_irn_n(left, 1); + scale = get_ia32_am_scale(left); + } + } + + /* ok, we can create a new LEA */ + if (dolea) { + res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is); + + /* add the old offset of a previous LEA */ + if (offs) { + add_ia32_am_offs(res, offs); + } + + /* add the new offset */ + if (isadd) { + if (offs_cnst) { + add_ia32_am_offs(res, offs_cnst); + } + if (offs_lea) { + add_ia32_am_offs(res, offs_lea); + } + } + else { + /* either lea_O-cnst, -cnst or -lea_O */ + if (offs_cnst) { + if (offs_lea) { + add_ia32_am_offs(res, offs_lea); + } + + sub_ia32_am_offs(res, offs_cnst); + } + else { + sub_ia32_am_offs(res, offs_lea); + } + } + + /* set scale */ + set_ia32_am_scale(res, scale); + + am_flav = ia32_am_N; + /* determine new am flavour */ + if (offs || offs_cnst || offs_lea) { + am_flav |= ia32_O; + } + if (! be_is_NoReg(base)) { + am_flav |= ia32_B; + } + if (! be_is_NoReg(index)) { + am_flav |= ia32_I; + } + if (scale > 0) { + am_flav |= ia32_S; + } + set_ia32_am_flavour(res, am_flav); + + set_ia32_op_type(res, ia32_AddrModeS); + + DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res))); + + /* get the result Proj of the Add/Sub */ + irn = get_res_proj(irn); + + assert(irn && "Couldn't find result proj"); + + /* exchange the old op with the new LEA */ + exchange(irn, res); + } + + return res; +} + +/** + * Optimizes a pattern around irn to address mode if possible. + */ +void ia32_optimize_am(ir_node *irn, void *env) { + ia32_code_gen_t *cg = env; + ir_graph *irg = cg->irg; + firm_dbg_module_t *mod = cg->mod; + ir_node *res = irn; + dbg_info *dbg; + ir_mode *mode; + ir_node *block, *noreg_gp, *noreg_fp; + ir_node *left, *right, *temp; + ir_node *store, *load, *mem_proj; + ir_node *succ, *addr_b, *addr_i; + int check_am_src = 0; + + if (! is_ia32_irn(irn)) + return; + + dbg = get_irn_dbg_info(irn); + mode = get_irn_mode(irn); + block = get_nodes_block(irn); + noreg_gp = ia32_new_NoReg_gp(cg); + noreg_fp = ia32_new_NoReg_fp(cg); + + DBG((mod, LEVEL_1, "checking for AM\n")); + + /* 1st part: check for address calculations and transform the into Lea */ + + /* Following cases can occur: */ + /* - Sub (l, imm) -> LEA [base - offset] */ + /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */ + /* - Add (l, imm) -> LEA [base + offset] */ + /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */ + /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */ + /* - Add (l, r) -> LEA [base + index * scale] */ + /* with scale > 1 iff l/r == shl (1,2,3) */ + + if (is_ia32_Sub(irn) || is_ia32_Add(irn)) { + left = get_irn_n(irn, 2); + right = get_irn_n(irn, 3); + + /* Do not try to create a LEA if one of the operands is a Load. */ + if (! pred_is_specific_nodeblock(block, left, is_ia32_Load) && + ! pred_is_specific_nodeblock(block, right, is_ia32_Load)) + { + res = fold_addr(irn, mod, noreg_gp); + } + } + + /* 2nd part: fold following patterns: */ + /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */ + /* - Store -> LEA into Store } it might be better to keep the LEA */ + /* - op -> Load into AMop with am_Source */ + /* conditions: */ + /* - op is am_Source capable AND */ + /* - the Load is only used by this op AND */ + /* - the Load is in the same block */ + /* - Store -> op -> Load into AMop with am_Dest */ + /* conditions: */ + /* - op is am_Dest capable AND */ + /* - the Store uses the same address as the Load AND */ + /* - the Load is only used by this op AND */ + /* - the Load and Store are in the same block AND */ + /* - nobody else uses the result of the op */ + + if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) { + /* 1st: check for Load/Store -> LEA */ + if (is_ia32_Ld(irn) || is_ia32_St(irn)) { + left = get_irn_n(irn, 0); + + if (is_ia32_Lea(left)) { + /* get the AM attributes from the LEA */ + add_ia32_am_offs(irn, get_ia32_am_offs(left)); + set_ia32_am_scale(irn, get_ia32_am_scale(left)); + set_ia32_am_flavour(irn, get_ia32_am_flavour(left)); + set_ia32_op_type(irn, get_ia32_op_type(left)); + + /* set base and index */ + set_irn_n(irn, 0, get_irn_n(left, 0)); + set_irn_n(irn, 1, get_irn_n(left, 1)); + } + } + /* check if at least one operand is a Load */ + else if (pred_is_specific_nodeblock(block, get_irn_n(irn, 2), is_ia32_Ld) || + pred_is_specific_nodeblock(block, get_irn_n(irn, 3), is_ia32_Ld)) + { + left = get_irn_n(irn, 2); + if (get_irn_arity(irn) == 4) { + /* it's an "unary" operation */ + right = left; + } + else { + right = get_irn_n(irn, 3); + } + + /* normalize commutative ops */ + if (node_is_comm(irn)) { + /* Assure that right operand is always a Load if there is one */ + /* because non-commutative ops can only use Dest AM if the right */ + /* operand is a load, so we only need to check right operand. */ + if (pred_is_specific_nodeblock(block, left, is_ia32_Ld)) + { + set_irn_n(irn, 2, right); + set_irn_n(irn, 3, left); + + temp = left; + left = right; + right = temp; + } + } + + /* check for Store -> op -> Load */ + + /* Store -> op -> Load optimization is only possible if supported by op */ + /* and if right operand is a Load */ + if ((get_ia32_am_support(irn) & ia32_am_Dest) && + pred_is_specific_nodeblock(block, right, is_ia32_Ld)) + { + + /* An address mode capable op always has a result Proj. */ + /* If this Proj is used by more than one other node, we don't need to */ + /* check further, otherwise we check for Store and remember the address, */ + /* the Store points to. */ + + succ = get_res_proj(irn); + assert(succ && "Couldn't find result proj"); + + addr_b = NULL; + addr_i = NULL; + store = NULL; + + /* now check for users and Store */ + if (ia32_get_irn_n_edges(succ) == 1) { + succ = get_edge_src_irn(get_irn_out_edge_first(succ)); + + if (is_ia32_fStore(succ) || is_ia32_Store(succ)) { + store = succ; + addr_b = get_irn_n(store, 0); + + /* Could be that the Store is connected to the address */ + /* calculating LEA while the Load is already transformed. */ + if (is_ia32_Lea(addr_b)) { + succ = addr_b; + addr_b = get_irn_n(succ, 0); + addr_i = get_irn_n(succ, 1); + } + else { + addr_i = noreg_gp; + } + } + } + + if (store) { + /* we found a Store as single user: Now check for Load */ + + /* Extra check for commutative ops with two Loads */ + /* -> put the interesting Load right */ + if (node_is_comm(irn) && + pred_is_specific_nodeblock(block, left, is_ia32_Ld)) + { + if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) && + (addr_i == get_irn_n(get_Proj_pred(left), 1))) + { + /* We exchange left and right, so it's easier to kill */ + /* the correct Load later and to handle unary operations. */ + set_irn_n(irn, 2, right); + set_irn_n(irn, 3, left); + + temp = left; + left = right; + right = temp; + } + } + + /* skip the Proj for easier access */ + load = get_Proj_pred(right); + + /* Compare Load and Store address */ + if ((addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1))) + { + /* Right Load is from same address, so we can */ + /* disconnect the Load and Store here */ + + /* set new base, index and attributes */ + set_irn_n(irn, 0, addr_b); + set_irn_n(irn, 1, addr_i); + add_ia32_am_offs(irn, get_ia32_am_offs(load)); + set_ia32_am_scale(irn, get_ia32_am_scale(load)); + set_ia32_am_flavour(irn, get_ia32_am_flavour(load)); + set_ia32_op_type(irn, ia32_AddrModeD); + + /* connect to Load memory and disconnect Load */ + if (get_irn_arity(irn) == 5) { + /* binary AMop */ + set_irn_n(irn, 4, get_irn_n(load, 2)); + set_irn_n(irn, 3, noreg_gp); + } + else { + /* unary AMop */ + set_irn_n(irn, 3, get_irn_n(load, 2)); + set_irn_n(irn, 2, noreg_gp); + } + + /* connect the memory Proj of the Store to the op */ + mem_proj = get_mem_proj(store); + set_Proj_pred(mem_proj, irn); + set_Proj_proj(mem_proj, 1); + } + } /* if (store) */ + else if (get_ia32_am_support(irn) & ia32_am_Source) { + /* There was no store, check if we still can optimize for source address mode */ + check_am_src = 1; + } + } /* if (support AM Dest) */ + else if (get_ia32_am_support(irn) & ia32_am_Source) { + /* op doesn't support am AM Dest -> check for AM Source */ + check_am_src = 1; + } + + /* normalize commutative ops */ + if (node_is_comm(irn)) { + /* Assure that left operand is always a Load if there is one */ + /* because non-commutative ops can only use Source AM if the */ + /* left operand is a Load, so we only need to check the left */ + /* operand afterwards. */ + if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) { + set_irn_n(irn, 2, right); + set_irn_n(irn, 3, left); + + temp = left; + left = right; + right = temp; + } + } + + /* optimize op -> Load iff Load is only used by this op */ + /* and left operand is a Load which only used by this irn */ + if (check_am_src && + pred_is_specific_nodeblock(block, left, is_ia32_Ld) && + (ia32_get_irn_n_edges(left) == 1)) + { + left = get_Proj_pred(left); + + addr_b = get_irn_n(left, 0); + addr_i = get_irn_n(left, 1); + + /* set new base, index and attributes */ + set_irn_n(irn, 0, addr_b); + set_irn_n(irn, 1, addr_i); + add_ia32_am_offs(irn, get_ia32_am_offs(left)); + set_ia32_am_scale(irn, get_ia32_am_scale(left)); + set_ia32_am_flavour(irn, get_ia32_am_flavour(left)); + set_ia32_op_type(irn, ia32_AddrModeS); + + /* connect to Load memory */ + if (get_irn_arity(irn) == 5) { + /* binary AMop */ + set_irn_n(irn, 4, get_irn_n(left, 2)); + } + else { + /* unary AMop */ + set_irn_n(irn, 3, get_irn_n(left, 2)); + } + + /* disconnect from Load */ + set_irn_n(irn, 2, noreg_gp); + + /* If Load has a memory Proj, connect it to the op */ + mem_proj = get_mem_proj(left); + if (mem_proj) { + set_Proj_pred(mem_proj, irn); + set_Proj_proj(mem_proj, 1); + } + } + } + } +}