X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=f3eba306a30258824acd2b7247e73d6c7c4dc0a2;hb=50b4ecceaf7e7d764244725e67912f97dcd3b577;hp=a66d20ff11914c3169b40e1eec304ff66b9dbc82;hpb=7a9a11e3be2aee776c3045e8c3c4742a0b6bbcbe;p=libfirm diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c index a66d20ff1..f3eba306a 100644 --- a/ir/be/ia32/ia32_optimize.c +++ b/ir/be/ia32/ia32_optimize.c @@ -34,15 +34,16 @@ #include "tv.h" #include "irgmod.h" #include "irgwalk.h" -#include "height.h" +#include "heights.h" #include "irbitset.h" #include "irprintf.h" +#include "irdump.h" #include "error.h" #include "../be_t.h" #include "../beabi.h" -#include "../benode_t.h" -#include "../besched_t.h" +#include "../benode.h" +#include "../besched.h" #include "../bepeephole.h" #include "ia32_new_nodes.h" @@ -57,8 +58,6 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) -static ia32_code_gen_t *cg; - static void copy_mark(const ir_node *old, ir_node *new) { if (is_ia32_is_reload(old)) @@ -145,6 +144,7 @@ check_shift_amount: static void peephole_ia32_Cmp(ir_node *const node) { ir_node *right; + ir_graph *irg; ia32_immediate_attr_t const *imm; dbg_info *dbgi; ir_node *block; @@ -171,8 +171,9 @@ static void peephole_ia32_Cmp(ir_node *const node) return; dbgi = get_irn_dbg_info(node); + irg = get_irn_irg(node); block = get_nodes_block(node); - noreg = ia32_new_NoReg_gp(cg); + noreg = ia32_new_NoReg_gp(irg); nomem = get_irg_no_mem(current_ir_graph); op = get_irn_n(node, n_ia32_Cmp_left); attr = get_irn_generic_attr(node); @@ -232,12 +233,8 @@ static void peephole_ia32_Test(ir_node *node) left = get_Proj_pred(left); } - /* happens rarely, but if it does code will panic' */ - if (is_ia32_Unknown_GP(left)) - return; - - /* walk schedule up and abort when we find left or some other node destroys - the flags */ + /* walk schedule up and abort when we find left or some other node + * destroys the flags */ schedpoint = node; for (;;) { schedpoint = sched_prev(schedpoint); @@ -254,7 +251,7 @@ static void peephole_ia32_Test(ir_node *node) ir_node *user = get_edge_src_irn(edge); int pnc = get_ia32_condcode(user); - if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) { + if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) { return; } } @@ -269,8 +266,8 @@ static void peephole_ia32_Test(ir_node *node) int pnc = get_ia32_condcode(user); switch (pnc) { - case pn_Cmp_Eq: pnc = pn_Cmp_Ge | ia32_pn_Cmp_unsigned; break; - case pn_Cmp_Lg: pnc = pn_Cmp_Lt | ia32_pn_Cmp_unsigned; break; + case pn_Cmp_Eq: pnc = ia32_pn_Cmp_not_carry; break; + case pn_Cmp_Lg: pnc = ia32_pn_Cmp_carry; break; default: panic("unexpected pn"); } set_ia32_condcode(user, pnc); @@ -286,8 +283,7 @@ static void peephole_ia32_Test(ir_node *node) /* If there are other users, reroute them to result proj */ if (get_irn_n_edges(left) != 2) { - ir_node *res = new_r_Proj(current_ir_graph, block, left, - mode_Iu, pn_ia32_res); + ir_node *res = new_r_Proj(left, mode_Iu, pn_ia32_res); edges_reroute(left, res, current_ir_graph); /* Reattach the result proj to left */ @@ -296,8 +292,7 @@ static void peephole_ia32_Test(ir_node *node) } flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode; - flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode, - pn_ia32_flags); + flags_proj = new_r_Proj(left, flags_mode, pn_ia32_flags); arch_set_irn_register(flags_proj, &ia32_flags_regs[REG_EFLAGS]); assert(get_irn_mode(node) != mode_T); @@ -356,7 +351,8 @@ static void peephole_ia32_Test(ir_node *node) * conditional jump or directly preceded by other jump instruction. * Can be avoided by placing a Rep prefix before the return. */ -static void peephole_ia32_Return(ir_node *node) { +static void peephole_ia32_Return(ir_node *node) +{ ir_node *block, *irn; if (!ia32_cg_config.use_pad_return) @@ -371,7 +367,7 @@ static void peephole_ia32_Return(ir_node *node) { /* the return node itself, ignore */ continue; case iro_Start: - case beo_RegParams: + case beo_Start: case beo_Barrier: /* ignore no code generated */ continue; @@ -482,13 +478,13 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) /* walk through the Stores and create Pushs for them */ block = get_nodes_block(irn); spmode = get_irn_mode(irn); - irg = cg->irg; + irg = get_irn_irg(irn); for (; i >= 0; --i) { const arch_register_t *spreg; ir_node *push; ir_node *val, *mem, *mem_proj; ir_node *store = stores[i]; - ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *noreg = ia32_new_NoReg_gp(irg); val = get_irn_n(store, n_ia32_unary_op); mem = get_irn_n(store, n_ia32_mem); @@ -503,11 +499,11 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) sched_add_after(skip_Proj(curr_sp), push); /* create stackpointer Proj */ - curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack); + curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack); arch_set_irn_register(curr_sp, spreg); /* create memory Proj */ - mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M); + mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M); /* use the memproj now */ be_peephole_exchange(store, mem_proj); @@ -529,6 +525,34 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) } #if 0 +/** + * Creates a Push instruction before the given schedule point. + * + * @param dbgi debug info + * @param block the block + * @param stack the previous stack value + * @param schedpoint the new node is added before this node + * @param reg the register to pop + * + * @return the new stack value + */ +static ir_node *create_push(dbg_info *dbgi, ir_node *block, + ir_node *stack, ir_node *schedpoint) +{ + const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + + ir_node *val = ia32_new_NoReg_gp(cg); + ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *nomem = new_NoMem(); + ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack); + sched_add_before(schedpoint, push); + + stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack); + arch_set_irn_register(stack, esp); + + return stack; +} + static void peephole_store_incsp(ir_node *store) { dbg_info *dbgi; @@ -617,7 +641,8 @@ static void peephole_store_incsp(ir_node *store) /** * Return true if a mode can be stored in the GP register set */ -static inline int mode_needs_gp_reg(ir_mode *mode) { +static inline int mode_needs_gp_reg(ir_mode *mode) +{ if (mode == mode_fpcw) return 0; if (get_mode_size_bits(mode) > 32) @@ -746,9 +771,9 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn) /* create a new IncSP if needed */ block = get_nodes_block(irn); - irg = cg->irg; + irg = get_irn_irg(irn); if (inc_ofs > 0) { - pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn)); + pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn)); sched_add_before(irn, pred_sp); } @@ -768,7 +793,7 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn) copy_mark(load, pop); /* create stackpointer Proj */ - pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack); + pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack); arch_set_irn_register(pred_sp, esp); sched_add_before(irn, pop); @@ -797,12 +822,12 @@ static const arch_register_t *get_free_gp_reg(void) { int i; - for(i = 0; i < N_ia32_gp_REGS; ++i) { + for (i = 0; i < N_ia32_gp_REGS; ++i) { const arch_register_t *reg = &ia32_gp_regs[i]; - if(arch_register_type_is(reg, ignore)) + if (arch_register_type_is(reg, ignore)) continue; - if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL) + if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL) return &ia32_gp_regs[i]; } @@ -813,7 +838,6 @@ static const arch_register_t *get_free_gp_reg(void) * Creates a Pop instruction before the given schedule point. * * @param dbgi debug info - * @param irg the graph * @param block the block * @param stack the previous stack value * @param schedpoint the new node is added before this node @@ -821,7 +845,7 @@ static const arch_register_t *get_free_gp_reg(void) * * @return the new stack value */ -static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block, +static ir_node *create_pop(dbg_info *dbgi, ir_node *block, ir_node *stack, ir_node *schedpoint, const arch_register_t *reg) { @@ -833,49 +857,20 @@ static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block, pop = new_bd_ia32_Pop(dbgi, block, new_NoMem(), stack); - stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack); + stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack); arch_set_irn_register(stack, esp); - val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res); + val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res); arch_set_irn_register(val, reg); sched_add_before(schedpoint, pop); in[0] = val; - keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in); + keep = be_new_Keep(block, 1, in); sched_add_before(schedpoint, keep); return stack; } -/** - * Creates a Push instruction before the given schedule point. - * - * @param dbgi debug info - * @param irg the graph - * @param block the block - * @param stack the previous stack value - * @param schedpoint the new node is added before this node - * @param reg the register to pop - * - * @return the new stack value - */ -static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block, - ir_node *stack, ir_node *schedpoint) -{ - const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; - - ir_node *val = ia32_new_Unknown_gp(cg); - ir_node *noreg = ia32_new_NoReg_gp(cg); - ir_node *nomem = get_irg_no_mem(irg); - ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack); - sched_add_before(schedpoint, push); - - stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack); - arch_set_irn_register(stack, esp); - - return stack; -} - /** * Optimize an IncSp by replacing it with Push/Pop. */ @@ -883,7 +878,6 @@ static void peephole_be_IncSP(ir_node *node) { const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; const arch_register_t *reg; - ir_graph *irg = current_ir_graph; dbg_info *dbgi; ir_node *block; ir_node *stack; @@ -919,19 +913,23 @@ static void peephole_be_IncSP(ir_node *node) block = get_nodes_block(node); stack = be_get_IncSP_pred(node); - stack = create_pop(dbgi, irg, block, stack, node, reg); + stack = create_pop(dbgi, block, stack, node, reg); if (offset == -8) { - stack = create_pop(dbgi, irg, block, stack, node, reg); + stack = create_pop(dbgi, block, stack, node, reg); } } else { dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); stack = be_get_IncSP_pred(node); - stack = create_push(dbgi, irg, block, stack, node); + stack = new_bd_ia32_PushEax(dbgi, block, stack); + arch_set_irn_register(stack, esp); + sched_add_before(node, stack); if (offset == +8) { - stack = create_push(dbgi, irg, block, stack, node); + stack = new_bd_ia32_PushEax(dbgi, block, stack); + arch_set_irn_register(stack, esp); + sched_add_before(node, stack); } } @@ -973,12 +971,12 @@ static void peephole_ia32_Const(ir_node *node) be_peephole_exchange(node, xor); } -static inline int is_noreg(ia32_code_gen_t *cg, const ir_node *node) +static inline int is_noreg(const ir_node *node) { - return node == cg->noreg_gp; + return is_ia32_NoReg_GP(node); } -static ir_node *create_immediate_from_int(int val) +ir_node *ia32_immediate_from_long(long val) { ir_graph *irg = current_ir_graph; ir_node *start_block = get_irg_start_block(irg); @@ -1026,6 +1024,7 @@ static int is_am_minus_one(const ir_node *node) */ static void peephole_ia32_Lea(ir_node *node) { + ir_graph *irg; ir_node *base; ir_node *index; const arch_register_t *base_reg; @@ -1044,26 +1043,26 @@ static void peephole_ia32_Lea(ir_node *node) assert(is_ia32_Lea(node)); /* we can only do this if it is allowed to clobber the flags */ - if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL) + if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL) return; base = get_irn_n(node, n_ia32_Lea_base); index = get_irn_n(node, n_ia32_Lea_index); - if(is_noreg(cg, base)) { + if (is_noreg(base)) { base = NULL; base_reg = NULL; } else { base_reg = arch_get_irn_register(base); } - if(is_noreg(cg, index)) { + if (is_noreg(index)) { index = NULL; index_reg = NULL; } else { index_reg = arch_get_irn_register(index); } - if(base == NULL && index == NULL) { + if (base == NULL && index == NULL) { /* we shouldn't construct these in the first place... */ #ifdef DEBUG_libfirm ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n"); @@ -1076,7 +1075,7 @@ static void peephole_ia32_Lea(ir_node *node) assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL); /* check if we have immediates values (frame entities should already be * expressed in the offsets) */ - if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) { + if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) { has_immediates = 1; } else { has_immediates = 0; @@ -1084,10 +1083,10 @@ static void peephole_ia32_Lea(ir_node *node) /* we can transform leas where the out register is the same as either the * base or index register back to an Add or Shl */ - if(out_reg == base_reg) { - if(index == NULL) { + if (out_reg == base_reg) { + if (index == NULL) { #ifdef DEBUG_libfirm - if(!has_immediates) { + if (!has_immediates) { ir_fprintf(stderr, "Optimisation warning: found lea which is " "just a copy\n"); } @@ -1095,29 +1094,29 @@ static void peephole_ia32_Lea(ir_node *node) op1 = base; goto make_add_immediate; } - if(scale == 0 && !has_immediates) { + if (scale == 0 && !has_immediates) { op1 = base; op2 = index; goto make_add; } /* can't create an add */ return; - } else if(out_reg == index_reg) { - if(base == NULL) { - if(has_immediates && scale == 0) { + } else if (out_reg == index_reg) { + if (base == NULL) { + if (has_immediates && scale == 0) { op1 = index; goto make_add_immediate; - } else if(!has_immediates && scale > 0) { + } else if (!has_immediates && scale > 0) { op1 = index; - op2 = create_immediate_from_int(scale); + op2 = ia32_immediate_from_long(scale); goto make_shl; - } else if(!has_immediates) { + } else if (!has_immediates) { #ifdef DEBUG_libfirm ir_fprintf(stderr, "Optimisation warning: found lea which is " "just a copy\n"); #endif } - } else if(scale == 0 && !has_immediates) { + } else if (scale == 0 && !has_immediates) { op1 = index; op2 = base; goto make_add; @@ -1130,15 +1129,15 @@ static void peephole_ia32_Lea(ir_node *node) } make_add_immediate: - if(ia32_cg_config.use_incdec) { - if(is_am_one(node)) { + if (ia32_cg_config.use_incdec) { + if (is_am_one(node)) { dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); res = new_bd_ia32_Inc(dbgi, block, op1); arch_set_irn_register(res, out_reg); goto exchange; } - if(is_am_minus_one(node)) { + if (is_am_minus_one(node)) { dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); res = new_bd_ia32_Dec(dbgi, block, op1); @@ -1151,7 +1150,8 @@ make_add_immediate: make_add: dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); - noreg = ia32_new_NoReg_gp(cg); + irg = get_irn_irg(node); + noreg = ia32_new_NoReg_gp(irg); nomem = new_NoMem(); res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2); arch_set_irn_register(res, out_reg); @@ -1161,7 +1161,8 @@ make_add: make_shl: dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); - noreg = ia32_new_NoReg_gp(cg); + irg = get_irn_irg(node); + noreg = ia32_new_NoReg_gp(irg); nomem = new_NoMem(); res = new_bd_ia32_Shl(dbgi, block, op1, op2); arch_set_irn_register(res, out_reg); @@ -1246,10 +1247,8 @@ static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) } /* Perform peephole-optimizations. */ -void ia32_peephole_optimization(ia32_code_gen_t *new_cg) +void ia32_peephole_optimization(ir_graph *irg) { - cg = new_cg; - /* register peephole optimisations */ clear_irp_opcodes_generic_func(); register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const); @@ -1267,7 +1266,7 @@ void ia32_peephole_optimization(ia32_code_gen_t *new_cg) if (ia32_cg_config.use_short_sex_eax) register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I); - be_peephole_opt(cg->birg); + be_peephole_opt(irg); } /** @@ -1277,7 +1276,7 @@ void ia32_peephole_optimization(ia32_code_gen_t *new_cg) */ static inline void try_kill(ir_node *node) { - if(get_irn_mode(node) == mode_T) { + if (get_irn_mode(node) == mode_T) { const ir_edge_t *edge, *next; foreach_out_edge_safe(node, edge, next) { ir_node *proj = get_edge_src_irn(edge); @@ -1285,7 +1284,7 @@ static inline void try_kill(ir_node *node) } } - if(get_irn_n_edges(node) != 0) + if (get_irn_n_edges(node) != 0) return; if (sched_is_scheduled(node)) { @@ -1302,32 +1301,32 @@ static void optimize_conv_store(ir_node *node) ir_mode *conv_mode; ir_mode *store_mode; - if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node)) + if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node)) return; assert(n_ia32_Store_val == n_ia32_Store8Bit_val); pred_proj = get_irn_n(node, n_ia32_Store_val); - if(is_Proj(pred_proj)) { + if (is_Proj(pred_proj)) { pred = get_Proj_pred(pred_proj); } else { pred = pred_proj; } - if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred)) + if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred)) return; - if(get_ia32_op_type(pred) != ia32_Normal) + if (get_ia32_op_type(pred) != ia32_Normal) return; /* the store only stores the lower bits, so we only need the conv * it it shrinks the mode */ conv_mode = get_ia32_ls_mode(pred); store_mode = get_ia32_ls_mode(node); - if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode)) + if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode)) return; set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val)); - if(get_irn_n_edges(pred_proj) == 0) { + if (get_irn_n_edges(pred_proj) == 0) { kill_node(pred_proj); - if(pred != pred_proj) + if (pred != pred_proj) kill_node(pred); } } @@ -1343,25 +1342,25 @@ static void optimize_load_conv(ir_node *node) assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val); pred = get_irn_n(node, n_ia32_Conv_I2I_val); - if(!is_Proj(pred)) + if (!is_Proj(pred)) return; predpred = get_Proj_pred(pred); - if(!is_ia32_Load(predpred)) + if (!is_ia32_Load(predpred)) return; /* the load is sign extending the upper bits, so we only need the conv * if it shrinks the mode */ load_mode = get_ia32_ls_mode(predpred); conv_mode = get_ia32_ls_mode(node); - if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode)) + if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode)) return; - if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) { + if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) { /* change the load if it has only 1 user */ - if(get_irn_n_edges(pred) == 1) { + if (get_irn_n_edges(pred) == 1) { ir_mode *newmode; - if(get_mode_sign(conv_mode)) { + if (get_mode_sign(conv_mode)) { newmode = find_signed_mode(load_mode); } else { newmode = find_unsigned_mode(load_mode); @@ -1390,12 +1389,12 @@ static void optimize_conv_conv(ir_node *node) assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val); pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val); - if(is_Proj(pred_proj)) + if (is_Proj(pred_proj)) pred = get_Proj_pred(pred_proj); else pred = pred_proj; - if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred)) + if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred)) return; /* we know that after a conv, the upper bits are sign extended @@ -1405,24 +1404,25 @@ static void optimize_conv_conv(ir_node *node) pred_mode = get_ia32_ls_mode(pred); pred_mode_bits = get_mode_size_bits(pred_mode); - if(conv_mode_bits == pred_mode_bits + if (conv_mode_bits == pred_mode_bits && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) { result_conv = pred_proj; - } else if(conv_mode_bits <= pred_mode_bits) { + } else if (conv_mode_bits <= pred_mode_bits) { /* if 2nd conv is smaller then first conv, then we can always take the * 2nd conv */ - if(get_irn_n_edges(pred_proj) == 1) { + if (get_irn_n_edges(pred_proj) == 1) { result_conv = pred_proj; set_ia32_ls_mode(pred, conv_mode); /* Argh:We must change the opcode to 8bit AND copy the register constraints */ if (get_mode_size_bits(conv_mode) == 8) { set_irn_op(pred, op_ia32_Conv_I2I8Bit); - set_ia32_in_req_all(pred, get_ia32_in_req_all(node)); + arch_set_in_register_reqs(pred, + arch_get_in_register_reqs(node)); } } else { /* we don't want to end up with 2 loads, so we better do nothing */ - if(get_irn_mode(pred) == mode_T) { + if (get_irn_mode(pred) == mode_T) { return; } @@ -1432,16 +1432,17 @@ static void optimize_conv_conv(ir_node *node) /* Argh:We must change the opcode to 8bit AND copy the register constraints */ if (get_mode_size_bits(conv_mode) == 8) { set_irn_op(result_conv, op_ia32_Conv_I2I8Bit); - set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node)); + arch_set_in_register_reqs(result_conv, + arch_get_in_register_reqs(node)); } } } else { /* if both convs have the same sign, then we can take the smaller one */ - if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) { + if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) { result_conv = pred_proj; } else { /* no optimisation possible if smaller conv is sign-extend */ - if(mode_is_signed(pred_mode)) { + if (mode_is_signed(pred_mode)) { return; } /* we can take the smaller conv if it is unsigned */ @@ -1455,9 +1456,9 @@ static void optimize_conv_conv(ir_node *node) /* kill the conv */ exchange(node, result_conv); - if(get_irn_n_edges(pred_proj) == 0) { + if (get_irn_n_edges(pred_proj) == 0) { kill_node(pred_proj); - if(pred != pred_proj) + if (pred != pred_proj) kill_node(pred); } optimize_conv_conv(result_conv); @@ -1475,12 +1476,9 @@ static void optimize_node(ir_node *node, void *env) /** * Performs conv and address mode optimization. */ -void ia32_optimize_graph(ia32_code_gen_t *cg) +void ia32_optimize_graph(ir_graph *irg) { - irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg); - - if (cg->dump) - be_dump(cg->irg, "-opt", dump_ir_block_graph_sched); + irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL); } void ia32_init_optimize(void)