X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=f19817e581cc7209ddc399ee695aa01707ab782b;hb=dc5eb2926b1ff88193b0ec00f3fbc8f969baaa4f;hp=9b9c308b4dda43eb06c66aae01a17d580682374d;hpb=83ae842bb35718cdc1498888014045f9da8a6769;p=libfirm diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c index 9b9c308b4..f19817e58 100644 --- a/ir/be/ia32/ia32_optimize.c +++ b/ir/be/ia32/ia32_optimize.c @@ -1,27 +1,12 @@ /* - * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. - * * This file is part of libFirm. - * - * This file may be distributed and/or modified under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation and appearing in the file LICENSE.GPL included in the - * packaging of this file. - * - * Licensees holding valid libFirm Professional Edition licenses may use - * this file in accordance with the libFirm Commercial License. - * Agreement provided with the Software. - * - * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE - * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. + * Copyright (C) 2012 University of Karlsruhe. */ /** * @file * @brief Implements several optimizations for IA32. * @author Matthias Braun, Christian Wuerdig - * @version $Id$ */ #include "config.h" @@ -34,16 +19,17 @@ #include "tv.h" #include "irgmod.h" #include "irgwalk.h" -#include "height.h" -#include "irbitset.h" +#include "heights.h" #include "irprintf.h" +#include "irdump.h" #include "error.h" +#include "firmstat_t.h" -#include "../be_t.h" -#include "../beabi.h" -#include "../benode_t.h" -#include "../besched_t.h" -#include "../bepeephole.h" +#include "be_t.h" +#include "beabi.h" +#include "benode.h" +#include "besched.h" +#include "bepeephole.h" #include "ia32_new_nodes.h" #include "ia32_optimize.h" @@ -52,36 +38,35 @@ #include "ia32_common_transform.h" #include "ia32_transform.h" #include "ia32_dbg_stat.h" -#include "ia32_util.h" #include "ia32_architecture.h" DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) -static ia32_code_gen_t *cg; - -static void copy_mark(const ir_node *old, ir_node *new) +static void copy_mark(const ir_node *old, ir_node *newn) { if (is_ia32_is_reload(old)) - set_ia32_is_reload(new); + set_ia32_is_reload(newn); if (is_ia32_is_spill(old)) - set_ia32_is_spill(new); + set_ia32_is_spill(newn); if (is_ia32_is_remat(old)) - set_ia32_is_remat(new); + set_ia32_is_remat(newn); } typedef enum produces_flag_t { produces_no_flag, - produces_flag_zero, - produces_flag_carry + produces_zero_sign, + produces_zero_in_carry } produces_flag_t; /** - * Return which usable flag the given node produces + * Return which usable flag the given node produces about the result. + * That is zero (ZF) and sign(SF). + * We do not check for carry (CF) or overflow (OF). * * @param node the node to check * @param pn the projection number of the used result */ -static produces_flag_t produces_test_flag(ir_node *node, int pn) +static produces_flag_t check_produces_zero_sign(ir_node *node, int pn) { ir_node *count; const ia32_immediate_attr_t *imm_attr; @@ -104,15 +89,15 @@ static produces_flag_t produces_test_flag(ir_node *node, int pn) case iro_ia32_ShlD: case iro_ia32_ShrD: - assert(n_ia32_ShlD_count == n_ia32_ShrD_count); + assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count); count = get_irn_n(node, n_ia32_ShlD_count); goto check_shift_amount; case iro_ia32_Shl: case iro_ia32_Shr: case iro_ia32_Sar: - assert(n_ia32_Shl_count == n_ia32_Shr_count - && n_ia32_Shl_count == n_ia32_Sar_count); + assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count + && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count); count = get_irn_n(node, n_ia32_Shl_count); check_shift_amount: /* when shift count is zero the flags are not affected, so we can only @@ -129,14 +114,13 @@ check_shift_amount: case iro_ia32_Mul: return pn == pn_ia32_Mul_res_high ? - produces_flag_carry : produces_no_flag; + produces_zero_in_carry : produces_no_flag; default: return produces_no_flag; } - return pn == pn_ia32_res ? - produces_flag_zero : produces_no_flag; + return pn == pn_ia32_res ? produces_zero_sign : produces_no_flag; } /** @@ -144,54 +128,35 @@ check_shift_amount: */ static void peephole_ia32_Cmp(ir_node *const node) { - ir_node *right; - ia32_immediate_attr_t const *imm; - dbg_info *dbgi; - ir_node *block; - ir_node *noreg; - ir_node *nomem; - ir_node *op; - ia32_attr_t const *attr; - int ins_permuted; - int cmp_unsigned; - ir_node *test; - arch_register_t const *reg; - ir_edge_t const *edge; - ir_edge_t const *tmp; - if (get_ia32_op_type(node) != ia32_Normal) return; - right = get_irn_n(node, n_ia32_Cmp_right); + ir_node *const right = get_irn_n(node, n_ia32_Cmp_right); if (!is_ia32_Immediate(right)) return; - imm = get_ia32_immediate_attr_const(right); + ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right); if (imm->symconst != NULL || imm->offset != 0) return; - dbgi = get_irn_dbg_info(node); - block = get_nodes_block(node); - noreg = ia32_new_NoReg_gp(cg); - nomem = get_irg_no_mem(current_ir_graph); - op = get_irn_n(node, n_ia32_Cmp_left); - attr = get_irn_generic_attr(node); - ins_permuted = attr->data.ins_permuted; - cmp_unsigned = attr->data.cmp_unsigned; - - if (is_ia32_Cmp(node)) { - test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem, - op, op, ins_permuted, cmp_unsigned); - } else { - test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem, - op, op, ins_permuted, cmp_unsigned); - } - set_ia32_ls_mode(test, get_ia32_ls_mode(node)); + dbg_info *const dbgi = get_irn_dbg_info(node); + ir_node *const block = get_nodes_block(node); + ir_graph *const irg = get_Block_irg(block); + ir_node *const noreg = ia32_new_NoReg_gp(irg); + ir_node *const nomem = get_irg_no_mem(irg); + ir_node *const op = get_irn_n(node, n_ia32_Cmp_left); + int const ins_permuted = get_ia32_attr(node)->data.ins_permuted; - reg = arch_irn_get_register(node, pn_ia32_Cmp_eflags); - arch_irn_set_register(test, pn_ia32_Test_eflags, reg); + ir_mode *const ls_mode = get_ia32_ls_mode(node); + ir_node *const test = get_mode_size_bits(ls_mode) == 8 + ? new_bd_ia32_Test_8bit(dbgi, block, noreg, noreg, nomem, op, op, ins_permuted) + : new_bd_ia32_Test (dbgi, block, noreg, noreg, nomem, op, op, ins_permuted); + set_ia32_ls_mode(test, ls_mode); - foreach_out_edge_safe(node, edge, tmp) { + arch_register_t const *const reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags); + arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg); + + foreach_out_edge_safe(node, edge) { ir_node *const user = get_edge_src_irn(edge); if (is_Proj(user)) @@ -213,35 +178,30 @@ static void peephole_ia32_Test(ir_node *node) ir_node *left = get_irn_n(node, n_ia32_Test_left); ir_node *right = get_irn_n(node, n_ia32_Test_right); - assert(n_ia32_Test_left == n_ia32_Test8Bit_left - && n_ia32_Test_right == n_ia32_Test8Bit_right); - if (left == right) { /* we need a test for 0 */ ir_node *block = get_nodes_block(node); int pn = pn_ia32_res; + ir_node *op = left; ir_node *flags_proj; ir_mode *flags_mode; + ir_mode *op_mode; ir_node *schedpoint; - const ir_edge_t *edge; + produces_flag_t produced; if (get_nodes_block(left) != block) return; - if (is_Proj(left)) { - pn = get_Proj_proj(left); - left = get_Proj_pred(left); + if (is_Proj(op)) { + pn = get_Proj_proj(op); + op = get_Proj_pred(op); } - /* happens rarely, but if it does code will panic' */ - if (is_ia32_Unknown_GP(left)) - return; - - /* walk schedule up and abort when we find left or some other node destroys - the flags */ + /* walk schedule up and abort when we find left or some other node + * destroys the flags */ schedpoint = node; for (;;) { schedpoint = sched_prev(schedpoint); - if (schedpoint == left) + if (schedpoint == op) break; if (arch_irn_is(schedpoint, modify_flags)) return; @@ -249,56 +209,63 @@ static void peephole_ia32_Test(ir_node *node) panic("couldn't find left"); } - /* make sure only Lg/Eq tests are used */ + produced = check_produces_zero_sign(op, pn); + if (produced == produces_no_flag) + return; + + /* make sure users only look at the sign/zero flag */ foreach_out_edge(node, edge) { - ir_node *user = get_edge_src_irn(edge); - int pnc = get_ia32_condcode(user); + ir_node *user = get_edge_src_irn(edge); + ia32_condition_code_t cc = get_ia32_condcode(user); - if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) { - return; + if (cc == ia32_cc_equal || cc == ia32_cc_not_equal) + continue; + if (produced == produces_zero_sign + && (cc == ia32_cc_sign || cc == ia32_cc_not_sign)) { + continue; } + return; } - switch (produces_test_flag(left, pn)) { - case produces_flag_zero: - break; + op_mode = get_ia32_ls_mode(op); + if (op_mode == NULL) + op_mode = get_irn_mode(op); - case produces_flag_carry: - foreach_out_edge(node, edge) { - ir_node *user = get_edge_src_irn(edge); - int pnc = get_ia32_condcode(user); - - switch (pnc) { - case pn_Cmp_Eq: pnc = pn_Cmp_Ge | ia32_pn_Cmp_unsigned; break; - case pn_Cmp_Lg: pnc = pn_Cmp_Lt | ia32_pn_Cmp_unsigned; break; - default: panic("unexpected pn"); - } - set_ia32_condcode(user, pnc); - } - break; + /* Make sure we operate on the same bit size */ + if (get_mode_size_bits(op_mode) != get_mode_size_bits(get_ia32_ls_mode(node))) + return; - default: - return; + if (produced == produces_zero_in_carry) { + /* patch users to look at the carry instead of the zero flag */ + foreach_out_edge(node, edge) { + ir_node *user = get_edge_src_irn(edge); + ia32_condition_code_t cc = get_ia32_condcode(user); + + switch (cc) { + case ia32_cc_equal: cc = ia32_cc_above_equal; break; + case ia32_cc_not_equal: cc = ia32_cc_below; break; + default: panic("unexpected pn"); + } + set_ia32_condcode(user, cc); + } } - if (get_irn_mode(left) != mode_T) { - set_irn_mode(left, mode_T); + if (get_irn_mode(op) != mode_T) { + set_irn_mode(op, mode_T); /* If there are other users, reroute them to result proj */ - if (get_irn_n_edges(left) != 2) { - ir_node *res = new_r_Proj(current_ir_graph, block, left, - mode_Iu, pn_ia32_res); - - edges_reroute(left, res, current_ir_graph); - /* Reattach the result proj to left */ - set_Proj_pred(res, left); + if (get_irn_n_edges(op) != 2) { + ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res); + edges_reroute_except(op, res, res); } + } else { + if (get_irn_n_edges(left) == 2) + kill_node(left); } flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode; - flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode, - pn_ia32_flags); - arch_set_irn_register(flags_proj, &ia32_flags_regs[REG_EFLAGS]); + flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags); + arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]); assert(get_irn_mode(node) != mode_T); @@ -313,21 +280,22 @@ static void peephole_ia32_Test(ir_node *node) offset = imm->offset; if (get_ia32_op_type(node) == ia32_AddrModeS) { - ia32_attr_t *const attr = get_irn_generic_attr(node); + ia32_attr_t *const attr = get_ia32_attr(node); + ir_graph *const irg = get_irn_irg(node); if ((offset & 0xFFFFFF00) == 0) { /* attr->am_offs += 0; */ } else if ((offset & 0xFFFF00FF) == 0) { - ir_node *imm = create_Immediate(NULL, 0, offset >> 8); - set_irn_n(node, n_ia32_Test_right, imm); + ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 8); + set_irn_n(node, n_ia32_Test_right, imm_node); attr->am_offs += 1; } else if ((offset & 0xFF00FFFF) == 0) { - ir_node *imm = create_Immediate(NULL, 0, offset >> 16); - set_irn_n(node, n_ia32_Test_right, imm); + ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 16); + set_irn_n(node, n_ia32_Test_right, imm_node); attr->am_offs += 2; } else if ((offset & 0x00FFFFFF) == 0) { - ir_node *imm = create_Immediate(NULL, 0, offset >> 24); - set_irn_n(node, n_ia32_Test_right, imm); + ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 24); + set_irn_n(node, n_ia32_Test_right, imm_node); attr->am_offs += 3; } else { return; @@ -335,10 +303,10 @@ static void peephole_ia32_Test(ir_node *node) } else if (offset < 256) { arch_register_t const* const reg = arch_get_irn_register(left); - if (reg != &ia32_gp_regs[REG_EAX] && - reg != &ia32_gp_regs[REG_EBX] && - reg != &ia32_gp_regs[REG_ECX] && - reg != &ia32_gp_regs[REG_EDX]) { + if (reg != &ia32_registers[REG_EAX] && + reg != &ia32_registers[REG_EBX] && + reg != &ia32_registers[REG_ECX] && + reg != &ia32_registers[REG_EDX]) { return; } } else { @@ -356,23 +324,15 @@ static void peephole_ia32_Test(ir_node *node) * conditional jump or directly preceded by other jump instruction. * Can be avoided by placing a Rep prefix before the return. */ -static void peephole_ia32_Return(ir_node *node) { - ir_node *block, *irn; - +static void peephole_ia32_Return(ir_node *node) +{ if (!ia32_cg_config.use_pad_return) return; - block = get_nodes_block(node); - /* check if this return is the first on the block */ - sched_foreach_reverse_from(node, irn) { + sched_foreach_reverse_before(node, irn) { switch (get_irn_opcode(irn)) { - case beo_Return: - /* the return node itself, ignore */ - continue; - case iro_Start: - case beo_RegParams: - case beo_Barrier: + case beo_Start: /* ignore no code generated */ continue; case beo_IncSP: @@ -392,7 +352,7 @@ static void peephole_ia32_Return(ir_node *node) { } /* only optimize up to 48 stores behind IncSPs */ -#define MAXPUSH_OPTIMIZE 48 +#define MAXPUSH_OPTIMIZE 48 /** * Tries to create Push's from IncSP, Store combinations. @@ -401,24 +361,18 @@ static void peephole_ia32_Return(ir_node *node) { */ static void peephole_IncSP_Store_to_push(ir_node *irn) { - int i; - int maxslot; - int inc_ofs; - ir_node *node; - ir_node *stores[MAXPUSH_OPTIMIZE]; - ir_node *block; - ir_graph *irg; - ir_node *curr_sp; - ir_mode *spmode; - ir_node *first_push = NULL; - ir_edge_t const *edge; - ir_edge_t const *next; + int i; + int maxslot; + ir_node *stores[MAXPUSH_OPTIMIZE]; + ir_node *block; + ir_graph *irg; + ir_node *curr_sp; + ir_mode *spmode; + ir_node *first_push = NULL; memset(stores, 0, sizeof(stores)); - assert(be_is_IncSP(irn)); - - inc_ofs = be_get_IncSP_offset(irn); + int inc_ofs = be_get_IncSP_offset(irn); if (inc_ofs < 4) return; @@ -429,7 +383,7 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) * attached to the node */ maxslot = -1; - for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) { + sched_foreach_after(irn, node) { ir_node *mem; int offset; int storeslot; @@ -482,40 +436,55 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) /* walk through the Stores and create Pushs for them */ block = get_nodes_block(irn); spmode = get_irn_mode(irn); - irg = cg->irg; + irg = get_irn_irg(irn); for (; i >= 0; --i) { const arch_register_t *spreg; ir_node *push; ir_node *val, *mem, *mem_proj; ir_node *store = stores[i]; - ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *noreg = ia32_new_NoReg_gp(irg); val = get_irn_n(store, n_ia32_unary_op); mem = get_irn_n(store, n_ia32_mem); spreg = arch_get_irn_register(curr_sp); - push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp); + push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, + mem, val, curr_sp); copy_mark(store, push); if (first_push == NULL) first_push = push; - sched_add_after(curr_sp, push); + sched_add_after(skip_Proj(curr_sp), push); /* create stackpointer Proj */ - curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack); + curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack); arch_set_irn_register(curr_sp, spreg); /* create memory Proj */ - mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M); + mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M); + + /* rewire Store Projs */ + foreach_out_edge_safe(store, edge) { + ir_node *proj = get_edge_src_irn(edge); + if (!is_Proj(proj)) + continue; + switch (get_Proj_proj(proj)) { + case pn_ia32_Store_M: + exchange(proj, mem_proj); + break; + default: + panic("unexpected Proj on Store->IncSp"); + } + } /* use the memproj now */ - be_peephole_exchange(store, mem_proj); + be_peephole_exchange(store, push); inc_ofs -= 4; } - foreach_out_edge_safe(irn, edge, next) { + foreach_out_edge_safe(irn, edge) { ir_node *const src = get_edge_src_irn(edge); int const pos = get_edge_src_pos(edge); @@ -528,97 +497,12 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) be_set_IncSP_offset(irn, inc_ofs); } -#if 0 -static void peephole_store_incsp(ir_node *store) -{ - dbg_info *dbgi; - ir_node *node; - ir_node *block; - ir_node *noreg; - ir_node *mem; - ir_node *push; - ir_node *val; - ir_node *base; - ir_node *index; - ir_node *am_base = get_irn_n(store, n_ia32_Store_base); - if (!be_is_IncSP(am_base) - || get_nodes_block(am_base) != get_nodes_block(store)) - return; - mem = get_irn_n(store, n_ia32_Store_mem); - if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index)) - || !is_NoMem(mem)) - return; - - int incsp_offset = be_get_IncSP_offset(am_base); - if (incsp_offset <= 0) - return; - - /* we have to be at offset 0 */ - int my_offset = get_ia32_am_offs_int(store); - if (my_offset != 0) { - /* TODO here: find out wether there is a store with offset 0 before - * us and wether we can move it down to our place */ - return; - } - ir_mode *ls_mode = get_ia32_ls_mode(store); - int my_store_size = get_mode_size_bytes(ls_mode); - - if (my_offset + my_store_size > incsp_offset) - return; - - /* correctness checking: - - noone else must write to that stackslot - (because after translation incsp won't allocate it anymore) - */ - sched_foreach_reverse_from(store, node) { - int i, arity; - - if (node == am_base) - break; - - /* make sure noone else can use the space on the stack */ - arity = get_irn_arity(node); - for (i = 0; i < arity; ++i) { - ir_node *pred = get_irn_n(node, i); - if (pred != am_base) - continue; - - if (i == n_ia32_base && - (get_ia32_op_type(node) == ia32_AddrModeS - || get_ia32_op_type(node) == ia32_AddrModeD)) { - int node_offset = get_ia32_am_offs_int(node); - ir_mode *node_ls_mode = get_ia32_ls_mode(node); - int node_size = get_mode_size_bytes(node_ls_mode); - /* overlapping with our position? abort */ - if (node_offset < my_offset + my_store_size - && node_offset + node_size >= my_offset) - return; - /* otherwise it's fine */ - continue; - } - - /* strange use of esp: abort */ - return; - } - } - - /* all ok, change to push */ - dbgi = get_irn_dbg_info(store); - block = get_nodes_block(store); - noreg = ia32_new_NoReg_gp(cg); - val = get_irn_n(store, n_ia32_Store_val); - - push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem, - - create_push(dbgi, current_ir_graph, block, am_base, store); -} -#endif - /** * Return true if a mode can be stored in the GP register set */ -static inline int mode_needs_gp_reg(ir_mode *mode) { - if (mode == mode_fpcw) +static inline int mode_needs_gp_reg(ir_mode *mode) +{ + if (mode == ia32_mode_fpcw) return 0; if (get_mode_size_bits(mode) > 32) return 0; @@ -632,18 +516,15 @@ static inline int mode_needs_gp_reg(ir_mode *mode) { */ static void peephole_Load_IncSP_to_pop(ir_node *irn) { - const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; - int i, maxslot, inc_ofs, ofs; - ir_node *node, *pred_sp, *block; + const arch_register_t *esp = &ia32_registers[REG_ESP]; + int i, maxslot, ofs; ir_node *loads[MAXPUSH_OPTIMIZE]; - ir_graph *irg; unsigned regmask = 0; unsigned copymask = ~0; memset(loads, 0, sizeof(loads)); - assert(be_is_IncSP(irn)); - inc_ofs = -be_get_IncSP_offset(irn); + int inc_ofs = -be_get_IncSP_offset(irn); if (inc_ofs < 4) return; @@ -654,8 +535,8 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn) * attached to the node */ maxslot = -1; - pred_sp = be_get_IncSP_pred(irn); - for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) { + ir_node *pred_sp = be_get_IncSP_pred(irn); + sched_foreach_reverse_before(irn, node) { int offset; int loadslot; const arch_register_t *sreg, *dreg; @@ -718,7 +599,7 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn) if (loads[loadslot] != NULL) break; - dreg = arch_irn_get_register(node, pn_ia32_Load_res); + dreg = arch_get_irn_register_out(node, pn_ia32_Load_res); if (regmask & (1 << dreg->index)) { /* this register is already used */ break; @@ -745,10 +626,9 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn) inc_ofs = (i+1) * 4; /* create a new IncSP if needed */ - block = get_nodes_block(irn); - irg = cg->irg; + ir_node *const block = get_nodes_block(irn); if (inc_ofs > 0) { - pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn)); + pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn)); sched_add_before(irn, pred_sp); } @@ -756,25 +636,24 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn) for (++i; i <= maxslot; ++i) { ir_node *load = loads[i]; ir_node *mem, *pop; - const ir_edge_t *edge, *tmp; const arch_register_t *reg; mem = get_irn_n(load, n_ia32_mem); - reg = arch_irn_get_register(load, pn_ia32_Load_res); + reg = arch_get_irn_register_out(load, pn_ia32_Load_res); pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp); - arch_irn_set_register(pop, pn_ia32_Load_res, reg); + arch_set_irn_register_out(pop, pn_ia32_Load_res, reg); copy_mark(load, pop); /* create stackpointer Proj */ - pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack); + pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack); arch_set_irn_register(pred_sp, esp); sched_add_before(irn, pop); /* rewire now */ - foreach_out_edge_safe(load, edge, tmp) { + foreach_out_edge_safe(load, edge) { ir_node *proj = get_edge_src_irn(edge); set_Proj_pred(proj, pop); @@ -793,17 +672,18 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn) /** * Find a free GP register if possible, else return NULL. */ -static const arch_register_t *get_free_gp_reg(void) +static const arch_register_t *get_free_gp_reg(ir_graph *irg) { + be_irg_t *birg = be_birg_from_irg(irg); int i; - for(i = 0; i < N_ia32_gp_REGS; ++i) { - const arch_register_t *reg = &ia32_gp_regs[i]; - if(arch_register_type_is(reg, ignore)) + for (i = 0; i < N_ia32_gp_REGS; ++i) { + const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i]; + if (!rbitset_is_set(birg->allocatable_regs, reg->global_index)) continue; - if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL) - return &ia32_gp_regs[i]; + if (be_peephole_get_value(reg->global_index) == NULL) + return reg; } return NULL; @@ -813,7 +693,6 @@ static const arch_register_t *get_free_gp_reg(void) * Creates a Pop instruction before the given schedule point. * * @param dbgi debug info - * @param irg the graph * @param block the block * @param stack the previous stack value * @param schedpoint the new node is added before this node @@ -821,69 +700,40 @@ static const arch_register_t *get_free_gp_reg(void) * * @return the new stack value */ -static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block, +static ir_node *create_pop(dbg_info *dbgi, ir_node *block, ir_node *stack, ir_node *schedpoint, const arch_register_t *reg) { - const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + const arch_register_t *esp = &ia32_registers[REG_ESP]; + ir_graph *irg = get_irn_irg(block); ir_node *pop; ir_node *keep; ir_node *val; ir_node *in[1]; - pop = new_bd_ia32_Pop(dbgi, block, new_NoMem(), stack); + pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack); - stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack); + stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack); arch_set_irn_register(stack, esp); - val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res); + val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res); arch_set_irn_register(val, reg); sched_add_before(schedpoint, pop); in[0] = val; - keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in); + keep = be_new_Keep(block, 1, in); sched_add_before(schedpoint, keep); return stack; } -/** - * Creates a Push instruction before the given schedule point. - * - * @param dbgi debug info - * @param irg the graph - * @param block the block - * @param stack the previous stack value - * @param schedpoint the new node is added before this node - * @param reg the register to pop - * - * @return the new stack value - */ -static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block, - ir_node *stack, ir_node *schedpoint) -{ - const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; - - ir_node *val = ia32_new_Unknown_gp(cg); - ir_node *noreg = ia32_new_NoReg_gp(cg); - ir_node *nomem = get_irg_no_mem(irg); - ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack); - sched_add_before(schedpoint, push); - - stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack); - arch_set_irn_register(stack, esp); - - return stack; -} - /** * Optimize an IncSp by replacing it with Push/Pop. */ static void peephole_be_IncSP(ir_node *node) { - const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + const arch_register_t *esp = &ia32_registers[REG_ESP]; const arch_register_t *reg; - ir_graph *irg = current_ir_graph; dbg_info *dbgi; ir_node *block; ir_node *stack; @@ -911,7 +761,7 @@ static void peephole_be_IncSP(ir_node *node) if (offset < 0) { /* we need a free register for pop */ - reg = get_free_gp_reg(); + reg = get_free_gp_reg(get_irn_irg(node)); if (reg == NULL) return; @@ -919,19 +769,23 @@ static void peephole_be_IncSP(ir_node *node) block = get_nodes_block(node); stack = be_get_IncSP_pred(node); - stack = create_pop(dbgi, irg, block, stack, node, reg); + stack = create_pop(dbgi, block, stack, node, reg); if (offset == -8) { - stack = create_pop(dbgi, irg, block, stack, node, reg); + stack = create_pop(dbgi, block, stack, node, reg); } } else { dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); stack = be_get_IncSP_pred(node); - stack = create_push(dbgi, irg, block, stack, node); + stack = new_bd_ia32_PushEax(dbgi, block, stack); + arch_set_irn_register(stack, esp); + sched_add_before(node, stack); if (offset == +8) { - stack = create_push(dbgi, irg, block, stack, node); + stack = new_bd_ia32_PushEax(dbgi, block, stack); + arch_set_irn_register(stack, esp); + sched_add_before(node, stack); } } @@ -947,9 +801,7 @@ static void peephole_ia32_Const(ir_node *node) const arch_register_t *reg; ir_node *block; dbg_info *dbgi; - ir_node *produceval; - ir_node *xor; - ir_node *noreg; + ir_node *xorn; /* try to transform a mov 0, reg to xor reg reg */ if (attr->offset != 0 || attr->symconst != NULL) @@ -957,42 +809,36 @@ static void peephole_ia32_Const(ir_node *node) if (ia32_cg_config.use_mov_0) return; /* xor destroys the flags, so no-one must be using them */ - if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL) + if (be_peephole_get_value(REG_EFLAGS) != NULL) return; reg = arch_get_irn_register(node); assert(be_peephole_get_reg_value(reg) == NULL); /* create xor(produceval, produceval) */ - block = get_nodes_block(node); - dbgi = get_irn_dbg_info(node); - produceval = new_bd_ia32_ProduceVal(dbgi, block); - arch_set_irn_register(produceval, reg); - - noreg = ia32_new_NoReg_gp(cg); - xor = new_bd_ia32_Xor(dbgi, block, noreg, noreg, new_NoMem(), produceval, - produceval); - arch_set_irn_register(xor, reg); + block = get_nodes_block(node); + dbgi = get_irn_dbg_info(node); + xorn = new_bd_ia32_Xor0(dbgi, block); + arch_set_irn_register(xorn, reg); - sched_add_before(node, produceval); - sched_add_before(node, xor); + sched_add_before(node, xorn); - copy_mark(node, xor); - be_peephole_exchange(node, xor); + copy_mark(node, xorn); + be_peephole_exchange(node, xorn); } -static inline int is_noreg(ia32_code_gen_t *cg, const ir_node *node) +static inline int is_noreg(const ir_node *node) { - return node == cg->noreg_gp; + return is_ia32_NoReg_GP(node); } -static ir_node *create_immediate_from_int(int val) +ir_node *ia32_immediate_from_long(long val) { ir_graph *irg = current_ir_graph; ir_node *start_block = get_irg_start_block(irg); - ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, - val); - arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]); + ir_node *immediate + = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val); + arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]); return immediate; } @@ -1002,11 +848,14 @@ static ir_node *create_immediate_from_am(const ir_node *node) ir_node *block = get_nodes_block(node); int offset = get_ia32_am_offs_int(node); int sc_sign = is_ia32_am_sc_sign(node); + const ia32_attr_t *attr = get_ia32_attr_const(node); + int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust; ir_entity *entity = get_ia32_am_sc(node); ir_node *res; - res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, offset); - arch_set_irn_register(res, &ia32_gp_regs[REG_GP_NOREG]); + res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust, + offset); + arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]); return res; } @@ -1043,32 +892,30 @@ static void peephole_ia32_Lea(ir_node *node) dbg_info *dbgi; ir_node *block; ir_node *res; - ir_node *noreg; - ir_node *nomem; assert(is_ia32_Lea(node)); - /* we can only do this if are allowed to globber the flags */ - if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL) + /* we can only do this if it is allowed to clobber the flags */ + if (be_peephole_get_value(REG_EFLAGS) != NULL) return; base = get_irn_n(node, n_ia32_Lea_base); index = get_irn_n(node, n_ia32_Lea_index); - if(is_noreg(cg, base)) { + if (is_noreg(base)) { base = NULL; base_reg = NULL; } else { base_reg = arch_get_irn_register(base); } - if(is_noreg(cg, index)) { + if (is_noreg(index)) { index = NULL; index_reg = NULL; } else { index_reg = arch_get_irn_register(index); } - if(base == NULL && index == NULL) { + if (base == NULL && index == NULL) { /* we shouldn't construct these in the first place... */ #ifdef DEBUG_libfirm ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n"); @@ -1081,7 +928,7 @@ static void peephole_ia32_Lea(ir_node *node) assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL); /* check if we have immediates values (frame entities should already be * expressed in the offsets) */ - if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) { + if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) { has_immediates = 1; } else { has_immediates = 0; @@ -1089,10 +936,10 @@ static void peephole_ia32_Lea(ir_node *node) /* we can transform leas where the out register is the same as either the * base or index register back to an Add or Shl */ - if(out_reg == base_reg) { - if(index == NULL) { + if (out_reg == base_reg) { + if (index == NULL) { #ifdef DEBUG_libfirm - if(!has_immediates) { + if (!has_immediates) { ir_fprintf(stderr, "Optimisation warning: found lea which is " "just a copy\n"); } @@ -1100,29 +947,29 @@ static void peephole_ia32_Lea(ir_node *node) op1 = base; goto make_add_immediate; } - if(scale == 0 && !has_immediates) { + if (scale == 0 && !has_immediates) { op1 = base; op2 = index; goto make_add; } /* can't create an add */ return; - } else if(out_reg == index_reg) { - if(base == NULL) { - if(has_immediates && scale == 0) { + } else if (out_reg == index_reg) { + if (base == NULL) { + if (has_immediates && scale == 0) { op1 = index; goto make_add_immediate; - } else if(!has_immediates && scale > 0) { + } else if (!has_immediates && scale > 0) { op1 = index; - op2 = create_immediate_from_int(scale); + op2 = ia32_immediate_from_long(scale); goto make_shl; - } else if(!has_immediates) { + } else if (!has_immediates) { #ifdef DEBUG_libfirm ir_fprintf(stderr, "Optimisation warning: found lea which is " "just a copy\n"); #endif } - } else if(scale == 0 && !has_immediates) { + } else if (scale == 0 && !has_immediates) { op1 = index; op2 = base; goto make_add; @@ -1135,15 +982,15 @@ static void peephole_ia32_Lea(ir_node *node) } make_add_immediate: - if(ia32_cg_config.use_incdec) { - if(is_am_one(node)) { + if (ia32_cg_config.use_incdec) { + if (is_am_one(node)) { dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); res = new_bd_ia32_Inc(dbgi, block, op1); arch_set_irn_register(res, out_reg); goto exchange; } - if(is_am_minus_one(node)) { + if (is_am_minus_one(node)) { dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); res = new_bd_ia32_Dec(dbgi, block, op1); @@ -1156,8 +1003,9 @@ make_add_immediate: make_add: dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); - noreg = ia32_new_NoReg_gp(cg); - nomem = new_NoMem(); + ir_graph *irg = get_irn_irg(node); + ir_node *noreg = ia32_new_NoReg_gp(irg); + ir_node *nomem = get_irg_no_mem(irg); res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2); arch_set_irn_register(res, out_reg); set_ia32_commutative(res); @@ -1166,8 +1014,6 @@ make_add: make_shl: dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); - noreg = ia32_new_NoReg_gp(cg); - nomem = new_NoMem(); res = new_bd_ia32_Shl(dbgi, block, op1, op2); arch_set_irn_register(res, out_reg); goto exchange; @@ -1198,69 +1044,101 @@ static void peephole_ia32_Imul_split(ir_node *imul) return; } /* we need a free register */ - reg = get_free_gp_reg(); + reg = get_free_gp_reg(get_irn_irg(imul)); if (reg == NULL) return; /* fine, we can rebuild it */ - res = turn_back_am(imul); + res = ia32_turn_back_am(imul); arch_set_irn_register(res, reg); } /** * Replace xorps r,r and xorpd r,r by pxor r,r */ -static void peephole_ia32_xZero(ir_node *xor) { - set_irn_op(xor, op_ia32_xPzero); +static void peephole_ia32_xZero(ir_node *xorn) +{ + set_irn_op(xorn, op_ia32_xPzero); +} + +/** + * Replace 16bit sign extension from ax to eax by shorter cwtl + */ +static void peephole_ia32_Conv_I2I(ir_node *node) +{ + const arch_register_t *eax = &ia32_registers[REG_EAX]; + ir_mode *smaller_mode = get_ia32_ls_mode(node); + ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val); + dbg_info *dbgi; + ir_node *block; + ir_node *cwtl; + + if (get_mode_size_bits(smaller_mode) != 16 || + !mode_is_signed(smaller_mode) || + eax != arch_get_irn_register(val) || + eax != arch_get_irn_register_out(node, pn_ia32_Conv_I2I_res)) + return; + + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + cwtl = new_bd_ia32_Cwtl(dbgi, block, val); + arch_set_irn_register(cwtl, eax); + sched_add_before(node, cwtl); + be_peephole_exchange(node, cwtl); } /** * Register a peephole optimisation function. */ -static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) { +static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) +{ assert(op->ops.generic == NULL); op->ops.generic = (op_func)func; } /* Perform peephole-optimizations. */ -void ia32_peephole_optimization(ia32_code_gen_t *new_cg) +void ia32_peephole_optimization(ir_graph *irg) { - cg = new_cg; + /* we currently do it in 2 passes because: + * Lea -> Add could be usefull as flag producer for Test later + */ - /* register peephole optimisations */ - clear_irp_opcodes_generic_func(); - register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const); - register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP); - register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea); + /* pass 1 */ + ir_clear_opcodes_generic_func(); register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp); - register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp); - register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test); - register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test); - register_peephole_optimisation(op_be_Return, peephole_ia32_Return); - if (! ia32_cg_config.use_imul_mem_imm32) - register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split); + register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea); + if (ia32_cg_config.use_short_sex_eax) + register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I); if (ia32_cg_config.use_pxor) register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero); - - be_peephole_opt(cg->birg); + if (! ia32_cg_config.use_imul_mem_imm32) + register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split); + be_peephole_opt(irg); + + /* pass 2 */ + ir_clear_opcodes_generic_func(); + register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const); + register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP); + register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test); + register_peephole_optimisation(op_be_Return, peephole_ia32_Return); + be_peephole_opt(irg); } /** * Removes node from schedule if it is not used anymore. If irn is a mode_T node - * all it's Projs are removed as well. + * all its Projs are removed as well. * @param irn The irn to be removed from schedule */ static inline void try_kill(ir_node *node) { - if(get_irn_mode(node) == mode_T) { - const ir_edge_t *edge, *next; - foreach_out_edge_safe(node, edge, next) { + if (get_irn_mode(node) == mode_T) { + foreach_out_edge_safe(node, edge) { ir_node *proj = get_edge_src_irn(edge); try_kill(proj); } } - if(get_irn_n_edges(node) != 0) + if (get_irn_n_edges(node) != 0) return; if (sched_is_scheduled(node)) { @@ -1277,32 +1155,32 @@ static void optimize_conv_store(ir_node *node) ir_mode *conv_mode; ir_mode *store_mode; - if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node)) + if (!is_ia32_Store(node)) return; - assert(n_ia32_Store_val == n_ia32_Store8Bit_val); pred_proj = get_irn_n(node, n_ia32_Store_val); - if(is_Proj(pred_proj)) { + if (is_Proj(pred_proj)) { pred = get_Proj_pred(pred_proj); } else { pred = pred_proj; } - if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred)) + if (!is_ia32_Conv_I2I(pred)) return; - if(get_ia32_op_type(pred) != ia32_Normal) + if (get_ia32_op_type(pred) != ia32_Normal) return; /* the store only stores the lower bits, so we only need the conv * it it shrinks the mode */ conv_mode = get_ia32_ls_mode(pred); store_mode = get_ia32_ls_mode(node); - if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode)) + if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode)) return; + ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Store(Conv) (%+F, %+F)\n", node, pred); set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val)); - if(get_irn_n_edges(pred_proj) == 0) { + if (get_irn_n_edges(pred_proj) == 0) { kill_node(pred_proj); - if(pred != pred_proj) + if (pred != pred_proj) kill_node(pred); } } @@ -1313,30 +1191,29 @@ static void optimize_load_conv(ir_node *node) ir_mode *load_mode; ir_mode *conv_mode; - if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node)) + if (!is_ia32_Conv_I2I(node)) return; - assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val); pred = get_irn_n(node, n_ia32_Conv_I2I_val); - if(!is_Proj(pred)) + if (!is_Proj(pred)) return; predpred = get_Proj_pred(pred); - if(!is_ia32_Load(predpred)) + if (!is_ia32_Load(predpred)) return; /* the load is sign extending the upper bits, so we only need the conv * if it shrinks the mode */ load_mode = get_ia32_ls_mode(predpred); conv_mode = get_ia32_ls_mode(node); - if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode)) + if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode)) return; - if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) { + if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) { /* change the load if it has only 1 user */ - if(get_irn_n_edges(pred) == 1) { + if (get_irn_n_edges(pred) == 1) { ir_mode *newmode; - if(get_mode_sign(conv_mode)) { + if (get_mode_sign(conv_mode)) { newmode = find_signed_mode(load_mode); } else { newmode = find_unsigned_mode(load_mode); @@ -1350,6 +1227,7 @@ static void optimize_load_conv(ir_node *node) } /* kill the conv */ + ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Conv(Load) (%+F, %+F)\n", node, predpred); exchange(node, pred); } @@ -1360,17 +1238,16 @@ static void optimize_conv_conv(ir_node *node) int conv_mode_bits; int pred_mode_bits; - if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node)) + if (!is_ia32_Conv_I2I(node)) return; - assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val); pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val); - if(is_Proj(pred_proj)) + if (is_Proj(pred_proj)) pred = get_Proj_pred(pred_proj); else pred = pred_proj; - if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred)) + if (!is_ia32_Conv_I2I(pred)) return; /* we know that after a conv, the upper bits are sign extended @@ -1380,24 +1257,25 @@ static void optimize_conv_conv(ir_node *node) pred_mode = get_ia32_ls_mode(pred); pred_mode_bits = get_mode_size_bits(pred_mode); - if(conv_mode_bits == pred_mode_bits + if (conv_mode_bits == pred_mode_bits && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) { result_conv = pred_proj; - } else if(conv_mode_bits <= pred_mode_bits) { + } else if (conv_mode_bits <= pred_mode_bits) { /* if 2nd conv is smaller then first conv, then we can always take the * 2nd conv */ - if(get_irn_n_edges(pred_proj) == 1) { + if (get_irn_n_edges(pred_proj) == 1) { result_conv = pred_proj; set_ia32_ls_mode(pred, conv_mode); /* Argh:We must change the opcode to 8bit AND copy the register constraints */ if (get_mode_size_bits(conv_mode) == 8) { - set_irn_op(pred, op_ia32_Conv_I2I8Bit); - set_ia32_in_req_all(pred, get_ia32_in_req_all(node)); + const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node); + set_irn_op(pred, op_ia32_Conv_I2I); + arch_set_irn_register_reqs_in(pred, reqs); } } else { /* we don't want to end up with 2 loads, so we better do nothing */ - if(get_irn_mode(pred) == mode_T) { + if (get_irn_mode(pred) == mode_T) { return; } @@ -1406,17 +1284,18 @@ static void optimize_conv_conv(ir_node *node) /* Argh:We must change the opcode to 8bit AND copy the register constraints */ if (get_mode_size_bits(conv_mode) == 8) { - set_irn_op(result_conv, op_ia32_Conv_I2I8Bit); - set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node)); + const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node); + set_irn_op(result_conv, op_ia32_Conv_I2I); + arch_set_irn_register_reqs_in(result_conv, reqs); } } } else { /* if both convs have the same sign, then we can take the smaller one */ - if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) { + if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) { result_conv = pred_proj; } else { /* no optimisation possible if smaller conv is sign-extend */ - if(mode_is_signed(pred_mode)) { + if (mode_is_signed(pred_mode)) { return; } /* we can take the smaller conv if it is unsigned */ @@ -1424,15 +1303,16 @@ static void optimize_conv_conv(ir_node *node) } } + ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Conv(Conv) (%+F, %+F)\n", node, pred); /* Some user (like Phis) won't be happy if we change the mode. */ set_irn_mode(result_conv, get_irn_mode(node)); /* kill the conv */ exchange(node, result_conv); - if(get_irn_n_edges(pred_proj) == 0) { + if (get_irn_n_edges(pred_proj) == 0) { kill_node(pred_proj); - if(pred != pred_proj) + if (pred != pred_proj) kill_node(pred); } optimize_conv_conv(result_conv); @@ -1450,12 +1330,9 @@ static void optimize_node(ir_node *node, void *env) /** * Performs conv and address mode optimization. */ -void ia32_optimize_graph(ia32_code_gen_t *cg) +void ia32_optimize_graph(ir_graph *irg) { - irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg); - - if (cg->dump) - be_dump(cg->irg, "-opt", dump_ir_block_graph_sched); + irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL); } void ia32_init_optimize(void)