X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=e5056f5e8a3ccd05f5cc48b73a344c9e1bde888d;hb=3b04d44b9763fc30ca4bcbec3dcfe4fec8f3bc5b;hp=1f99048434b1177847e9c03ccb2957dde6b074bc;hpb=d98d4ab0a6cf8e162331f4f908b17ecd874e941d;p=libfirm

diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c
index 1f9904843..e5056f5e8 100644
--- a/ir/be/ia32/ia32_optimize.c
+++ b/ir/be/ia32/ia32_optimize.c
@@ -1,3 +1,13 @@
+/*
+ * Project:     libFIRM
+ * File name:   ir/be/ia32/ia32_optimize.c
+ * Purpose:     Implements several optimizations for IA32
+ * Author:      Christian Wuerdig
+ * CVS-ID:      $Id$
+ * Copyright:   (c) 2006 Universität Karlsruhe
+ * Licence:     This file protected by GPL -  GNU GENERAL PUBLIC LICENSE.
+ */
+
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -9,6 +19,8 @@
 #include "iredges.h"
 #include "tv.h"
 #include "irgmod.h"
+#include "irgwalk.h"
+#include "height.h"
 
 #include "../be_t.h"
 #include "../beabi.h"
@@ -92,7 +104,9 @@ static ir_node *gen_SymConst(ia32_transform_env_t *env) {
 	}
 	else
 		cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode);
+
 	set_ia32_Const_attr(cnst, env->irn);
+
 	return cnst;
 }
 
@@ -371,7 +385,7 @@ static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
 	int same_args = 1;
 
 	for (i = 0; i < n; i++) {
-		if (get_irn_n(cand, i) == get_irn_n(irn, i)) {
+		if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
 			same_args = 0;
 			break;
 		}
@@ -397,7 +411,7 @@ static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
 		DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
 		DBG_OPT_CJMP(irn);
 
-		set_irn_op(irn, op_ia32_CJmp);
+		set_irn_op(irn, op_ia32_CJmpAM);
 
 		DB((cg->mod, LEVEL_1, "%+F\n", irn));
 	}
@@ -440,6 +454,10 @@ static void ia32_create_Push(ir_node *irn, ia32_code_gen_t *cg) {
 	proj_res = new_r_Proj(current_ir_graph, bl, push, get_irn_mode(sp), pn_ia32_Push_stack);
 	proj_M   = new_r_Proj(current_ir_graph, bl, push, mode_M, pn_ia32_Push_M);
 
+	/* copy a possible constant from the store */
+	set_ia32_id_cnst(push, get_ia32_id_cnst(irn));
+	set_ia32_immop_type(push, get_ia32_immop_type(irn));
+
 	/* the push must have SP out register */
 	arch_set_irn_register(cg->arch_env, push, arch_get_irn_register(cg->arch_env, sp));
 
@@ -510,8 +528,6 @@ static void ia32_create_Pop(ir_node *irn, ia32_code_gen_t *cg) {
 	sched_add_before(proj_res,pop);
 }
 
-/**
-
 /**
  * Tries to optimize two following IncSP.
  */
@@ -554,8 +570,11 @@ void ia32_peephole_optimization(ir_node *irn, void *env) {
 		ia32_optimize_TestJmp(irn, cg);
 	else if (is_ia32_CondJmp(irn))
 		ia32_optimize_CondJmp(irn, cg);
-	else if (be_is_IncSP(irn))
-		ia32_optimize_IncSP(irn, cg);
+	/* seems to be buggy when using Pushes */
+//	else if (be_is_IncSP(irn))
+//		ia32_optimize_IncSP(irn, cg);
+	else if (is_ia32_Store(irn))
+		ia32_create_Push(irn, cg);
 }
 
 
@@ -570,6 +589,11 @@ void ia32_peephole_optimization(ir_node *irn, void *env) {
  *
  ******************************************************************/
 
+typedef struct {
+	ia32_code_gen_t *cg;
+	heights_t       *h;
+} ia32_am_opt_env_t;
+
 static int node_is_ia32_comm(const ir_node *irn) {
 	return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
 }
@@ -664,45 +688,95 @@ static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
 	return 0;
 }
 
-
-
 /**
- * Checks if irn is a candidate for address calculation or address mode.
+ * Checks if irn is a candidate for address calculation.
  *
- * address calculation (AC):
  * - none of the operand must be a Load  within the same block OR
  * - all Loads must have more than one user                    OR
  * - the irn has a frame entity (it's a former FrameAddr)
  *
+ * @param block   The block the Loads must/mustnot be in
+ * @param irn     The irn to check
+ * return 1 if irn is a candidate, 0 otherwise
+ */
+static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
+	ir_node *in, *left, *right;
+	int      n, is_cand = 1;
+
+	left  = get_irn_n(irn, 2);
+	right = get_irn_n(irn, 3);
+
+	in = left;
+
+	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
+		n         = ia32_get_irn_n_edges(in);
+		is_cand   = (n == 1) ? 0 : is_cand;  /* load with only one user: don't create LEA */
+	}
+
+	in = right;
+
+	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
+		n         = ia32_get_irn_n_edges(in);
+		is_cand   = (n == 1) ? 0 : is_cand;  /* load with only one user: don't create LEA */
+	}
+
+	is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand;
+
+	return is_cand;
+}
+
+/**
+ * Checks if irn is a candidate for address mode.
+ *
  * address mode (AM):
  * - at least one operand has to be a Load within the same block AND
  * - the load must not have other users than the irn             AND
  * - the irn must not have a frame entity set
  *
- * @param block       The block the Loads must/not be in
+ * @param h           The height information of the irg
+ * @param block       The block the Loads must/mustnot be in
  * @param irn         The irn to check
- * @param check_addr  1 if to check for address calculation, 0 otherwise
- * return 1 if irn is a candidate for AC or AM, 0 otherwise
+ * return 1 if irn is a candidate, 0 otherwise
  */
-static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
-	ir_node *in;
-	int      n, is_cand = check_addr;
+static int is_am_candidate(heights_t *h, const ir_node *block, ir_node *irn) {
+	ir_node *in, *load, *other, *left, *right;
+	int      n, is_cand = 0;
+
+	if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
+		return 0;
+
+	left  = get_irn_n(irn, 2);
+	right = get_irn_n(irn, 3);
 
-	in = get_irn_n(irn, 2);
+	in = left;
 
 	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
 		n         = ia32_get_irn_n_edges(in);
-		is_cand   = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
+		is_cand   = (n == 1) ? 1 : is_cand;  /* load with more than one user: no AM */
+
+		load  = get_Proj_pred(in);
+		other = right;
+
+		/* If there is a data dependency of other irn from load: cannot use AM */
+		if (get_nodes_block(other) == block)
+			is_cand = heights_reachable_in_block(h, load, other) ? 0 : is_cand;
 	}
 
-	in = get_irn_n(irn, 3);
+	in = right;
 
 	if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
 		n         = ia32_get_irn_n_edges(in);
-		is_cand   = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
+		is_cand   = (n == 1) ? 1 : is_cand;  /* load with more than one user: no AM */
+
+		load  = get_Proj_pred(in);
+		other = left;
+
+		/* If there is a data dependency of other irn from load: cannot use load */
+		if (get_nodes_block(other) == block)
+			is_cand = heights_reachable_in_block(h, load, other) ? 0 : is_cand;
 	}
 
-	is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
+	is_cand = get_ia32_frame_ent(irn) ? 0 : is_cand;
 
 	return is_cand;
 }
@@ -1185,32 +1259,33 @@ static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
 }
 
 /**
- * Optimizes a pattern around irn to address mode if possible.
+ * Sets new_right index of irn to right and new_left index to left.
+ * Also exchange left and right
  */
-void ia32_optimize_am(ir_node *irn, void *env) {
-	ia32_code_gen_t   *cg   = env;
-	ir_node           *res  = irn;
-	dbg_info          *dbg;
-	ir_mode           *mode;
-	ir_node           *block, *noreg_gp, *noreg_fp;
-	ir_node           *left, *right, *temp;
-	ir_node           *store, *load, *mem_proj;
-	ir_node           *succ, *addr_b, *addr_i;
-	int                check_am_src = 0;
-	DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
+static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
+	ir_node *temp;
 
-	if (! is_ia32_irn(irn))
-		return;
+	set_irn_n(irn, new_right, *right);
+	set_irn_n(irn, new_left, *left);
 
-	dbg      = get_irn_dbg_info(irn);
-	mode     = get_irn_mode(irn);
-	block    = get_nodes_block(irn);
-	noreg_gp = ia32_new_NoReg_gp(cg);
-	noreg_fp = ia32_new_NoReg_fp(cg);
+	temp   = *left;
+	*left  = *right;
+	*right = temp;
 
-	DBG((mod, LEVEL_1, "checking for AM\n"));
+	/* this is only needed for Compares, but currently ALL nodes
+	 * have this attribute :-) */
+	set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
+}
 
-	/* 1st part: check for address calculations and transform the into Lea */
+/**
+ * Performs address calculation optimization (create LEAs if possible)
+ */
+static void optimize_lea(ir_node *irn, void *env) {
+	ia32_code_gen_t *cg  = env;
+	ir_node         *block, *noreg_gp, *left, *right;
+
+	if (! is_ia32_irn(irn))
+		return;
 
 	/* Following cases can occur:                                  */
 	/* - Sub (l, imm) -> LEA [base - offset]                       */
@@ -1222,25 +1297,75 @@ void ia32_optimize_am(ir_node *irn, void *env) {
 	/*              with scale > 1 iff l/r == shl (1,2,3)          */
 
 	if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
-		left  = get_irn_n(irn, 2);
-		right = get_irn_n(irn, 3);
+		left     = get_irn_n(irn, 2);
+		right    = get_irn_n(irn, 3);
+		block    = get_nodes_block(irn);
+		noreg_gp = ia32_new_NoReg_gp(cg);
 
 	    /* Do not try to create a LEA if one of the operands is a Load. */
 		/* check is irn is a candidate for address calculation */
-		if (is_candidate(block, irn, 1)) {
-			DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
+		if (is_addr_candidate(block, irn)) {
+			ir_node *res;
+
+			DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
 			res = fold_addr(cg, irn, noreg_gp);
 
-			if (res == irn)
-				DB((mod, LEVEL_1, "transformed into %+F\n", res));
+			if (res != irn)
+				DB((cg->mod, LEVEL_1, "transformed into %+F\n", res));
 			else
-				DB((mod, LEVEL_1, "not transformed\n"));
+				DB((cg->mod, LEVEL_1, "not transformed\n"));
 		}
 	}
+	else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
+		/* - Load  -> LEA into Load  } TODO: If the LEA is used by more than one Load/Store */
+		/* - Store -> LEA into Store }       it might be better to keep the LEA             */
+		left = get_irn_n(irn, 0);
+
+		if (is_ia32_Lea(left)) {
+			const ir_edge_t *edge, *ne;
+			ir_node *src;
+
+			/* merge all Loads/Stores connected to this LEA with the LEA */
+			foreach_out_edge_safe(left, edge, ne) {
+				src = get_edge_src_irn(edge);
+
+				if (src && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
+					DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
+					merge_loadstore_lea(src, left);
+				}
+			}
+		}
+	}
+}
+
+
+/**
+ * Checks for address mode patterns and performs the
+ * necessary transformations.
+ * This function is called by a walker.
+ */
+static void optimize_am(ir_node *irn, void *env) {
+	ia32_am_opt_env_t *am_opt_env = env;
+	ia32_code_gen_t   *cg         = am_opt_env->cg;
+	heights_t         *h          = am_opt_env->h;
+	ir_node           *block, *noreg_gp, *noreg_fp;
+	ir_node           *left, *right, *temp;
+	ir_node           *store, *load, *mem_proj;
+	ir_node           *succ, *addr_b, *addr_i;
+	int               check_am_src          = 0;
+	int               need_exchange_on_fail = 0;
+	DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
+
+	if (! is_ia32_irn(irn))
+		return;
 
-	/* 2nd part: fold following patterns:                                               */
-	/* - Load  -> LEA into Load  } TODO: If the LEA is used by more than one Load/Store */
-	/* - Store -> LEA into Store }       it might be better to keep the LEA             */
+	block    = get_nodes_block(irn);
+	noreg_gp = ia32_new_NoReg_gp(cg);
+	noreg_fp = ia32_new_NoReg_fp(cg);
+
+	DBG((mod, LEVEL_1, "checking for AM\n"));
+
+	/* fold following patterns:                                                         */
 	/* - op -> Load into AMop with am_Source                                            */
 	/*   conditions:                                                                    */
 	/*     - op is am_Source capable AND                                                */
@@ -1254,239 +1379,269 @@ void ia32_optimize_am(ir_node *irn, void *env) {
 	/*     - the Load and Store are in the same block AND                               */
 	/*     - nobody else uses the result of the op                                      */
 
-	if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
-		/* 1st: check for Load/Store -> LEA   */
-		if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
-			left = get_irn_n(irn, 0);
-
-			if (is_ia32_Lea(left)) {
-				const ir_edge_t *edge, *ne;
-				ir_node *src;
-
-				/* merge all Loads/Stores connected to this LEA with the LEA */
-				foreach_out_edge_safe(left, edge, ne) {
-					src = get_edge_src_irn(edge);
+	if ((get_ia32_am_support(irn) != ia32_am_None) && ! is_ia32_Lea(irn) && is_am_candidate(h, block, irn)) {
+		DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
 
-					if (src && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
-						DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
-						merge_loadstore_lea(src, left);
-					}
-				}
-			}
+		left  = get_irn_n(irn, 2);
+		if (get_irn_arity(irn) == 4) {
+			/* it's an "unary" operation */
+			right = left;
+		}
+		else {
+			right = get_irn_n(irn, 3);
 		}
-		/* check if the node is an address mode candidate */
-		else if (is_candidate(block, irn, 0)) {
-			DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
-
-			left  = get_irn_n(irn, 2);
-			if (get_irn_arity(irn) == 4) {
-				/* it's an "unary" operation */
-				right = left;
-			}
-			else {
-				right = get_irn_n(irn, 3);
-			}
-
-			/* normalize commutative ops */
-			if (node_is_ia32_comm(irn)) {
-				/* Assure that right operand is always a Load if there is one    */
-				/* because non-commutative ops can only use Dest AM if the right */
-				/* operand is a load, so we only need to check right operand.    */
-				if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
-				{
-					set_irn_n(irn, 2, right);
-					set_irn_n(irn, 3, left);
 
-					temp  = left;
-					left  = right;
-					right = temp;
-				}
+		/* normalize commutative ops */
+		if (node_is_ia32_comm(irn)) {
+			/* Assure that right operand is always a Load if there is one    */
+			/* because non-commutative ops can only use Dest AM if the right */
+			/* operand is a load, so we only need to check right operand.    */
+			if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
+			{
+				exchange_left_right(irn, &left, &right, 3, 2);
+				need_exchange_on_fail = 1;
 			}
+		}
 
-			/* check for Store -> op -> Load */
+		/* check for Store -> op -> Load */
 
-			/* Store -> op -> Load optimization is only possible if supported by op */
-			/* and if right operand is a Load                                       */
-			if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
-				 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
-			{
+		/* Store -> op -> Load optimization is only possible if supported by op */
+		/* and if right operand is a Load                                       */
+		if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
+			 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
+		{
 
-				/* An address mode capable op always has a result Proj.                  */
-				/* If this Proj is used by more than one other node, we don't need to    */
-				/* check further, otherwise we check for Store and remember the address, */
-				/* the Store points to. */
+			/* An address mode capable op always has a result Proj.                  */
+			/* If this Proj is used by more than one other node, we don't need to    */
+			/* check further, otherwise we check for Store and remember the address, */
+			/* the Store points to. */
 
-				succ = get_res_proj(irn);
-				assert(succ && "Couldn't find result proj");
+			succ = get_res_proj(irn);
+			assert(succ && "Couldn't find result proj");
 
-				addr_b = NULL;
-				addr_i = NULL;
-				store  = NULL;
+			addr_b = NULL;
+			addr_i = NULL;
+			store  = NULL;
 
-				/* now check for users and Store */
-				if (ia32_get_irn_n_edges(succ) == 1) {
-					succ = get_edge_src_irn(get_irn_out_edge_first(succ));
+			/* now check for users and Store */
+			if (ia32_get_irn_n_edges(succ) == 1) {
+				succ = get_edge_src_irn(get_irn_out_edge_first(succ));
 
-					if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
-						store  = succ;
-						addr_b = get_irn_n(store, 0);
-						addr_i = get_irn_n(store, 1);
-					}
+				if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
+					store  = succ;
+					addr_b = get_irn_n(store, 0);
+					addr_i = get_irn_n(store, 1);
 				}
+			}
 
-				if (store) {
-					/* we found a Store as single user: Now check for Load */
+			if (store) {
+				/* we found a Store as single user: Now check for Load */
 
-					/* Extra check for commutative ops with two Loads */
-					/* -> put the interesting Load right              */
-					if (node_is_ia32_comm(irn) &&
-						pred_is_specific_nodeblock(block, left, is_ia32_Ld))
+				/* Extra check for commutative ops with two Loads */
+				/* -> put the interesting Load right              */
+				if (node_is_ia32_comm(irn) &&
+					pred_is_specific_nodeblock(block, left, is_ia32_Ld))
+				{
+					if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
+						(addr_i == get_irn_n(get_Proj_pred(left), 1)))
 					{
-						if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
-							(addr_i == get_irn_n(get_Proj_pred(left), 1)))
-						{
-							/* We exchange left and right, so it's easier to kill     */
-							/* the correct Load later and to handle unary operations. */
-							set_irn_n(irn, 2, right);
-							set_irn_n(irn, 3, left);
-
-							temp  = left;
-							left  = right;
-							right = temp;
-						}
+						/* We exchange left and right, so it's easier to kill     */
+						/* the correct Load later and to handle unary operations. */
+						set_irn_n(irn, 2, right);
+						set_irn_n(irn, 3, left);
+
+						temp  = left;
+						left  = right;
+						right = temp;
+
+						/* this is only needed for Compares, but currently ALL nodes
+						 * have this attribute :-) */
+						set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
 					}
+				}
 
-					/* skip the Proj for easier access */
-					load = get_Proj_pred(right);
-
-					/* Compare Load and Store address */
-					if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
-						/* Right Load is from same address, so we can */
-						/* disconnect the Load and Store here        */
-
-						/* set new base, index and attributes */
-						set_irn_n(irn, 0, addr_b);
-						set_irn_n(irn, 1, addr_i);
-						add_ia32_am_offs(irn, get_ia32_am_offs(load));
-						set_ia32_am_scale(irn, get_ia32_am_scale(load));
-						set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
-						set_ia32_op_type(irn, ia32_AddrModeD);
-						set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
-						set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
-
-						set_ia32_am_sc(irn, get_ia32_am_sc(load));
-						if (is_ia32_am_sc_sign(load))
-							set_ia32_am_sc_sign(irn);
-
-						if (is_ia32_use_frame(load))
-							set_ia32_use_frame(irn);
-
-						/* connect to Load memory and disconnect Load */
-						if (get_irn_arity(irn) == 5) {
-							/* binary AMop */
-							set_irn_n(irn, 4, get_irn_n(load, 2));
-							set_irn_n(irn, 3, noreg_gp);
-						}
-						else {
-							/* unary AMop */
-							set_irn_n(irn, 3, get_irn_n(load, 2));
-							set_irn_n(irn, 2, noreg_gp);
-						}
-
-						/* connect the memory Proj of the Store to the op */
-						mem_proj = get_mem_proj(store);
-						set_Proj_pred(mem_proj, irn);
-						set_Proj_proj(mem_proj, 1);
-
-						/* clear remat flag */
-						set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
-
-						DBG_OPT_AM_D(load, store, irn);
-
-						DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
+				/* skip the Proj for easier access */
+				load = get_Proj_pred(right);
+
+				/* Compare Load and Store address */
+				if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
+					/* Right Load is from same address, so we can */
+					/* disconnect the Load and Store here        */
+
+					/* set new base, index and attributes */
+					set_irn_n(irn, 0, addr_b);
+					set_irn_n(irn, 1, addr_i);
+					add_ia32_am_offs(irn, get_ia32_am_offs(load));
+					set_ia32_am_scale(irn, get_ia32_am_scale(load));
+					set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
+					set_ia32_op_type(irn, ia32_AddrModeD);
+					set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
+					set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
+
+					set_ia32_am_sc(irn, get_ia32_am_sc(load));
+					if (is_ia32_am_sc_sign(load))
+						set_ia32_am_sc_sign(irn);
+
+					if (is_ia32_use_frame(load))
+						set_ia32_use_frame(irn);
+
+					/* connect to Load memory and disconnect Load */
+					if (get_irn_arity(irn) == 5) {
+						/* binary AMop */
+						set_irn_n(irn, 4, get_irn_n(load, 2));
+						set_irn_n(irn, 3, noreg_gp);
 					}
-				} /* if (store) */
-				else if (get_ia32_am_support(irn) & ia32_am_Source) {
-					/* There was no store, check if we still can optimize for source address mode */
-					check_am_src = 1;
+					else {
+						/* unary AMop */
+						set_irn_n(irn, 3, get_irn_n(load, 2));
+						set_irn_n(irn, 2, noreg_gp);
+					}
+
+					/* connect the memory Proj of the Store to the op */
+					mem_proj = get_mem_proj(store);
+					set_Proj_pred(mem_proj, irn);
+					set_Proj_proj(mem_proj, 1);
+
+					/* clear remat flag */
+					set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
+
+					DBG_OPT_AM_D(load, store, irn);
+
+					DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
 				}
-			} /* if (support AM Dest) */
+			} /* if (store) */
 			else if (get_ia32_am_support(irn) & ia32_am_Source) {
-				/* op doesn't support am AM Dest -> check for AM Source */
+				/* There was no store, check if we still can optimize for source address mode */
 				check_am_src = 1;
 			}
+		} /* if (support AM Dest) */
+		else if (get_ia32_am_support(irn) & ia32_am_Source) {
+			/* op doesn't support am AM Dest -> check for AM Source */
+			check_am_src = 1;
+		}
 
-			/* normalize commutative ops */
-			if (node_is_ia32_comm(irn)) {
-				/* Assure that left operand is always a Load if there is one */
-				/* because non-commutative ops can only use Source AM if the */
-				/* left operand is a Load, so we only need to check the left */
-				/* operand afterwards.                                       */
-				if (pred_is_specific_nodeblock(block, right, is_ia32_Ld))	{
-					set_irn_n(irn, 2, right);
-					set_irn_n(irn, 3, left);
-
-					temp  = left;
-					left  = right;
-					right = temp;
-				}
+		/* was exchanged but optimize failed: exchange back */
+		if (check_am_src && need_exchange_on_fail)
+			exchange_left_right(irn, &left, &right, 3, 2);
+
+		need_exchange_on_fail = 0;
+
+		/* normalize commutative ops */
+		if (check_am_src && node_is_ia32_comm(irn)) {
+			/* Assure that left operand is always a Load if there is one */
+			/* because non-commutative ops can only use Source AM if the */
+			/* left operand is a Load, so we only need to check the left */
+			/* operand afterwards.                                       */
+			if (pred_is_specific_nodeblock(block, right, is_ia32_Ld))	{
+				exchange_left_right(irn, &left, &right, 3, 2);
+				need_exchange_on_fail = 1;
 			}
+		}
 
-			/* optimize op -> Load iff Load is only used by this op   */
-			/* and left operand is a Load which only used by this irn */
-			if (check_am_src                                        &&
-				pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
-				(ia32_get_irn_n_edges(left) == 1))
-			{
-				left = get_Proj_pred(left);
-
-				addr_b = get_irn_n(left, 0);
-				addr_i = get_irn_n(left, 1);
-
-				/* set new base, index and attributes */
-				set_irn_n(irn, 0, addr_b);
-				set_irn_n(irn, 1, addr_i);
-				add_ia32_am_offs(irn, get_ia32_am_offs(left));
-				set_ia32_am_scale(irn, get_ia32_am_scale(left));
-				set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
-				set_ia32_op_type(irn, ia32_AddrModeS);
-				set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
-				set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
-
-				set_ia32_am_sc(irn, get_ia32_am_sc(left));
-				if (is_ia32_am_sc_sign(left))
-					set_ia32_am_sc_sign(irn);
-
-				/* clear remat flag */
-				set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
-
-				if (is_ia32_use_frame(left))
-					set_ia32_use_frame(irn);
-
-				/* connect to Load memory */
-				if (get_irn_arity(irn) == 5) {
-					/* binary AMop */
-					set_irn_n(irn, 4, get_irn_n(left, 2));
-				}
-				else {
-					/* unary AMop */
-					set_irn_n(irn, 3, get_irn_n(left, 2));
-				}
+		/* optimize op -> Load iff Load is only used by this op   */
+		/* and left operand is a Load which only used by this irn */
+		if (check_am_src                                        &&
+			pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
+			(ia32_get_irn_n_edges(left) == 1))
+		{
+			left = get_Proj_pred(left);
+
+			addr_b = get_irn_n(left, 0);
+			addr_i = get_irn_n(left, 1);
+
+			/* set new base, index and attributes */
+			set_irn_n(irn, 0, addr_b);
+			set_irn_n(irn, 1, addr_i);
+			add_ia32_am_offs(irn, get_ia32_am_offs(left));
+			set_ia32_am_scale(irn, get_ia32_am_scale(left));
+			set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
+			set_ia32_op_type(irn, ia32_AddrModeS);
+			set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
+			set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
+
+			set_ia32_am_sc(irn, get_ia32_am_sc(left));
+			if (is_ia32_am_sc_sign(left))
+				set_ia32_am_sc_sign(irn);
+
+			/* clear remat flag */
+			set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
+
+			if (is_ia32_use_frame(left))
+				set_ia32_use_frame(irn);
+
+			/* connect to Load memory */
+			if (get_irn_arity(irn) == 5) {
+				/* binary AMop */
+				set_irn_n(irn, 4, get_irn_n(left, 2));
+
+				/* this is only needed for Compares, but currently ALL nodes
+				 * have this attribute :-) */
+				set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
 
 				/* disconnect from Load */
-				set_irn_n(irn, 2, noreg_gp);
+				/* (make second op -> first, set second in to noreg) */
+				set_irn_n(irn, 2, get_irn_n(irn, 3));
+				set_irn_n(irn, 3, noreg_gp);
+			}
+			else {
+				/* unary AMop */
+				set_irn_n(irn, 3, get_irn_n(left, 2));
 
-				DBG_OPT_AM_S(left, irn);
+				/* disconnect from Load */
+				set_irn_n(irn, 2, noreg_gp);
+			}
 
-				/* If Load has a memory Proj, connect it to the op */
-				mem_proj = get_mem_proj(left);
-				if (mem_proj) {
-					set_Proj_pred(mem_proj, irn);
-					set_Proj_proj(mem_proj, 1);
-				}
+			DBG_OPT_AM_S(left, irn);
 
-				DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));
+			/* If Load has a memory Proj, connect it to the op */
+			mem_proj = get_mem_proj(left);
+			if (mem_proj) {
+				set_Proj_pred(mem_proj, irn);
+				set_Proj_proj(mem_proj, 1);
 			}
+
+			DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));
+		}
+		else {
+			/* was exchanged but optimize failed: exchange back */
+			if (need_exchange_on_fail)
+				exchange_left_right(irn, &left, &right, 3, 2);
 		}
 	}
 }
+
+/**
+ * Performs address mode optimization.
+ */
+void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
+	/* if we are supposed to do AM or LEA optimization: recalculate edges */
+	if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
+		edges_deactivate(cg->irg);
+		edges_activate(cg->irg);
+	}
+	else {
+		/* no optimizations at all */
+		return;
+	}
+
+	/* beware: we cannot optimize LEA and AM in one run because */
+	/*         LEA optimization adds new nodes to the irg which */
+	/*         invalidates the phase data                       */
+
+	if (cg->opt & IA32_OPT_LEA) {
+		irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg);
+	}
+
+	if (cg->opt & IA32_OPT_DOAM) {
+		/* we need height information for am optimization */
+		heights_t *h = heights_new(cg->irg);
+		ia32_am_opt_env_t env;
+
+		env.cg = cg;
+		env.h  = h;
+
+		irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);
+
+		heights_free(h);
+	}
+}