X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=c6e2f76b38f01223e01e9b001f40b6fe3fc5f441;hb=08fe790a5784b31964a8783f6af1d14d62c366c4;hp=e897c0f495a154b5d4611b65b79aa786b99075db;hpb=c4d69cc79c5d2039545890d580584eb707500b87;p=libfirm diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c index e897c0f49..c6e2f76b3 100644 --- a/ir/be/ia32/ia32_optimize.c +++ b/ir/be/ia32/ia32_optimize.c @@ -18,20 +18,37 @@ #include "ia32_new_nodes.h" #include "bearch_ia32_t.h" #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */ +#include "ia32_transform.h" #undef is_NoMem #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem) -static int be_is_NoReg(be_abi_irg_t *babi, const ir_node *irn) { - if (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_XXX]) == irn || - be_abi_get_callee_save_irn(babi, &ia32_fp_regs[REG_XXXX]) == irn) - { - return 1; - } +typedef int is_op_func_t(const ir_node *n); - return 0; +/** + * checks if a node represents the NOREG value + */ +static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) { + be_abi_irg_t *babi = cg->birg->abi; + const arch_register_t *fp_noreg = USE_SSE2(cg) ? + &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]; + + return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) || + (be_abi_get_callee_save_irn(babi, fp_noreg) == irn); } + + +/************************************************* + * _____ _ _ + * / ____| | | | | + * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___ + * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __| + * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \ + * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/ + * + *************************************************/ + /** * creates a unique ident by adding a number to a tag * @@ -65,7 +82,15 @@ static ir_node *gen_SymConst(ia32_transform_env_t *env) { ir_graph *irg = env->irg; ir_node *block = env->block; - cnst = new_rd_ia32_Const(dbg, irg, block, mode); + if (mode_is_float(mode)) { + if (USE_SSE2(env->cg)) + cnst = new_rd_ia32_fConst(dbg, irg, block, mode); + else + cnst = new_rd_ia32_vfConst(dbg, irg, block, mode); + } + else { + cnst = new_rd_ia32_Const(dbg, irg, block, mode); + } set_ia32_Const_attr(cnst, env->irn); return cnst; } @@ -95,7 +120,7 @@ static ir_type *get_prim_type(pmap *types, ir_mode *mode) static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst) { tarval *tv = get_Const_tarval(cnst); - pmap_entry *e = pmap_find(cg->tv_ent, tv); + pmap_entry *e = pmap_find(cg->isa->tv_ent, tv); entity *res; ir_graph *rem; @@ -103,7 +128,7 @@ static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst) ir_mode *mode = get_irn_mode(cnst); ir_type *tp = get_Const_type(cnst); if (tp == firm_unknown_type) - tp = get_prim_type(cg->types, mode); + tp = get_prim_type(cg->isa->types, mode); res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp); @@ -118,6 +143,8 @@ static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst) current_ir_graph = get_const_code_irg(); set_atomic_ent_value(res, new_Const_type(tv, tp)); current_ir_graph = rem; + + pmap_insert(cg->isa->tv_ent, tv, res); } else res = e->value; @@ -143,6 +170,14 @@ static ir_node *gen_Const(ia32_transform_env_t *env) { ir_mode *mode = env->mode; if (mode_is_float(mode)) { + if (! USE_SSE2(env->cg)) { + cnst_classify_t clss = classify_Const(node); + + if (clss == CNST_NULL) + return new_rd_ia32_vfldz(dbg, irg, block, mode); + else if (clss == CNST_ONE) + return new_rd_ia32_vfld1(dbg, irg, block, mode); + } sym.entity_p = get_entity_for_tv(env->cg, node); cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent); @@ -161,7 +196,7 @@ static ir_node *gen_Const(ia32_transform_env_t *env) { /** * Transforms (all) Const's into ia32_Const and places them in the * block where they are used (or in the cfg-pred Block in case of Phi's). - * Additionally all mode_P nodes are changed into mode_Is nodes. + * Additionally all reference nodes are changed into mode_Is nodes. */ void ia32_place_consts_set_modes(ir_node *irn, void *env) { ia32_code_gen_t *cg = env; @@ -176,16 +211,16 @@ void ia32_place_consts_set_modes(ir_node *irn, void *env) { mode = get_irn_mode(irn); - /* transform all mode_P nodes into mode_Is nodes */ - if (mode == mode_P) { - set_irn_mode(irn, mode_Is); + /* transform all reference nodes into mode_Is nodes */ + if (mode_is_reference(mode)) { mode = mode_Is; + set_irn_mode(irn, mode); } tenv.block = get_nodes_block(irn); tenv.cg = cg; tenv.irg = cg->irg; - tenv.mod = cg->mod; + DEBUG_ONLY(tenv.mod = cg->mod;) /* Loop over all predecessors and check for Sym/Const nodes */ for (i = get_irn_arity(irn) - 1; i >= 0; --i) { @@ -226,6 +261,190 @@ void ia32_place_consts_set_modes(ir_node *irn, void *env) { } + +/******************************************************************************************************** + * _____ _ _ ____ _ _ _ _ _ + * | __ \ | | | | / __ \ | | (_) (_) | | (_) + * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __ + * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \ + * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | | + * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_| + * | | | | + * |_| |_| + ********************************************************************************************************/ + +/** + * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION. + */ + +static int ia32_cnst_compare(ir_node *n1, ir_node *n2) { + return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2); +} + +/** + * Checks for potential CJmp/CJmpAM optimization candidates. + */ +static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) { + ir_node *cand = NULL; + ir_node *prev = sched_prev(irn); + + if (is_Block(prev)) { + if (get_Block_n_cfgpreds(prev) == 1) + prev = get_Block_cfgpred(prev, 0); + else + prev = NULL; + } + + /* The predecessor must be a ProjX. */ + if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) { + prev = get_Proj_pred(prev); + + if (is_op_func(prev)) + cand = prev; + } + + return cand; +} + +static int is_TestJmp_cand(const ir_node *irn) { + return is_ia32_TestJmp(irn) || is_ia32_And(irn); +} + +/** + * Checks if two consecutive arguments of cand matches + * the two arguments of irn (TestJmp). + */ +static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) { + ir_node *in1 = get_irn_n(irn, 0); + ir_node *in2 = get_irn_n(irn, 1); + int i, n = get_irn_arity(cand); + int same_args = 0; + + for (i = 0; i < n - 1; i++) { + if (get_irn_n(cand, i) == in1 && + get_irn_n(cand, i + 1) == in2) + { + same_args = 1; + break; + } + } + + if (same_args) + return ia32_cnst_compare(cand, irn); + + return 0; +} + +/** + * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And) + */ +static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) { + ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand); + int replace = 0; + + /* we found a possible candidate */ + replace = cand ? is_TestJmp_replacement(cand, irn) : 0; + + if (replace) { + DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn)); + + if (is_ia32_And(cand)) + set_irn_op(irn, op_ia32_CJmpAM); + else + set_irn_op(irn, op_ia32_CJmp); + + DB((cg->mod, LEVEL_1, "%+F\n", irn)); + } +} + +static int is_CondJmp_cand(const ir_node *irn) { + return is_ia32_CondJmp(irn) || is_ia32_Sub(irn); +} + +/** + * Checks if the arguments of cand are the same of irn. + */ +static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) { + int i, n = get_irn_arity(cand); + int same_args = 1; + + for (i = 0; i < n; i++) { + if (get_irn_n(cand, i) == get_irn_n(irn, i)) { + same_args = 0; + break; + } + } + + if (same_args) + return ia32_cnst_compare(cand, irn); + + return 0; +} + +/** + * Tries to replace a CondJmp by a CJmpAM + */ +static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) { + ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand); + int replace = 0; + + /* we found a possible candidate */ + replace = cand ? is_CondJmp_replacement(cand, irn) : 0; + + if (replace) { + DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn)); + + set_irn_op(irn, op_ia32_CJmp); + + DB((cg->mod, LEVEL_1, "%+F\n", irn)); + } +} + +/** + * Tries to optimize two following IncSP. + */ +static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) { + ir_node *prev = be_get_IncSP_pred(irn); + int real_uses = get_irn_n_edges(prev); + + if (be_is_IncSP(prev) && real_uses == 1) { + /* first IncSP has only one IncSP user, kill the first one */ + unsigned prev_offs = be_get_IncSP_offset(prev); + be_stack_dir_t prev_dir = be_get_IncSP_direction(prev); + unsigned curr_offs = be_get_IncSP_offset(irn); + be_stack_dir_t curr_dir = be_get_IncSP_direction(irn); + + int new_ofs = prev_offs * (prev_dir == be_stack_dir_expand ? -1 : +1) + + curr_offs * (curr_dir == be_stack_dir_expand ? -1 : +1); + + if (new_ofs < 0) { + new_ofs = -new_ofs; + curr_dir = be_stack_dir_expand; + } + else + curr_dir = be_stack_dir_shrink; + be_set_IncSP_offset(prev, 0); + be_set_IncSP_offset(irn, (unsigned)new_ofs); + be_set_IncSP_direction(irn, curr_dir); + } +} + +/** + * Performs Peephole Optimizations. + */ +void ia32_peephole_optimization(ir_node *irn, void *env) { + ia32_code_gen_t *cg = env; + + if (is_ia32_TestJmp(irn)) + ia32_optimize_TestJmp(irn, cg); + else if (is_ia32_CondJmp(irn)) + ia32_optimize_CondJmp(irn, cg); + else if (be_is_IncSP(irn)) + ia32_optimize_IncSP(irn, cg); +} + + + /****************************************************************** * _ _ __ __ _ * /\ | | | | | \/ | | | @@ -236,7 +455,7 @@ void ia32_place_consts_set_modes(ir_node *irn, void *env) { * ******************************************************************/ -static int node_is_comm(const ir_node *irn) { +static int node_is_ia32_comm(const ir_node *irn) { return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0; } @@ -300,7 +519,7 @@ static ir_node *get_res_proj(const ir_node *irn) { * @param is_op_func The check-function * @return 1 if conditions are fulfilled, 0 otherwise */ -static int pred_is_specific_node(const ir_node *pred, int (*is_op_func)(const ir_node *n)) { +static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) { if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) { return 1; } @@ -383,12 +602,25 @@ static int load_store_addr_is_equal(const ir_node *load, const ir_node *store, int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1)); entity *lent = get_ia32_frame_ent(load); entity *sent = get_ia32_frame_ent(store); + ident *lid = get_ia32_am_sc(load); + ident *sid = get_ia32_am_sc(store); + char *loffs = get_ia32_am_offs(load); + char *soffs = get_ia32_am_offs(store); /* are both entities set and equal? */ - is_equal = lent && sent && (lent == sent); + if (is_equal && (lent || sent)) + is_equal = lent && sent && (lent == sent); + + /* are address mode idents set and equal? */ + if (is_equal && (lid || sid)) + is_equal = lid && sid && (lid == sid); + + /* are offsets set and equal */ + if (is_equal && (loffs || soffs)) + is_equal = loffs && soffs && strcmp(loffs, soffs) == 0; /* are the load and the store of the same mode? */ - is_equal = get_ia32_ls_mode(load) == get_ia32_ls_mode(store); + is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0; return is_equal; } @@ -398,20 +630,24 @@ static int load_store_addr_is_equal(const ir_node *load, const ir_node *store, /** * Folds Add or Sub to LEA if possible */ -static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) { - ir_graph *irg = get_irn_irg(irn); - dbg_info *dbg = get_irn_dbg_info(irn); - ir_node *block = get_nodes_block(irn); - ir_node *res = irn; - char *offs = NULL; - char *offs_cnst = NULL; - char *offs_lea = NULL; - int scale = 0; - int isadd = 0; - int dolea = 0; - ir_node *left, *right, *temp; - ir_node *base, *index; +static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) { + ir_graph *irg = get_irn_irg(irn); + dbg_info *dbg = get_irn_dbg_info(irn); + ir_node *block = get_nodes_block(irn); + ir_node *res = irn; + char *offs = NULL; + const char *offs_cnst = NULL; + char *offs_lea = NULL; + int scale = 0; + int isadd = 0; + int dolea = 0; + int have_am_sc = 0; + int am_sc_sign = 0; + ident *am_sc = NULL; + ir_node *left, *right, *temp; + ir_node *base, *index; ia32_am_flavour_t am_flav; + DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;) if (is_ia32_Add(irn)) isadd = 1; @@ -420,7 +656,7 @@ static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *m right = get_irn_n(irn, 3); /* "normalize" arguments in case of add with two operands */ - if (isadd && ! be_is_NoReg(babi, right)) { + if (isadd && ! be_is_NoReg(cg, right)) { /* put LEA == ia32_am_O as right operand */ if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) { set_irn_n(irn, 2, right); @@ -455,28 +691,41 @@ static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *m scale = 0; am_flav = 0; - /* check if operand is either const */ - if (get_ia32_cnst(irn)) { - DBG((mod, LEVEL_1, "\tfound op with imm")); + /* check for operation with immediate */ + if (is_ia32_ImmConst(irn)) { + DBG((mod, LEVEL_1, "\tfound op with imm const")); offs_cnst = get_ia32_cnst(irn); dolea = 1; } + else if (is_ia32_ImmSymConst(irn)) { + DBG((mod, LEVEL_1, "\tfound op with imm symconst")); + + have_am_sc = 1; + dolea = 1; + am_sc = get_ia32_id_cnst(irn); + am_sc_sign = is_ia32_am_sc_sign(irn); + } /* determine the operand which needs to be checked */ - if (be_is_NoReg(babi, right)) { + if (be_is_NoReg(cg, right)) { temp = left; } else { temp = right; } - /* check if right operand is AMConst (LEA with ia32_am_O) */ - if (is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) { + /* check if right operand is AMConst (LEA with ia32_am_O) */ + /* but we can only eat it up if there is no other symconst */ + /* because the linker won't accept two symconsts */ + if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) { DBG((mod, LEVEL_1, "\tgot op with LEA am_O")); - offs_lea = get_ia32_am_offs(temp); - dolea = 1; + offs_lea = get_ia32_am_offs(temp); + am_sc = get_ia32_am_sc(temp); + am_sc_sign = is_ia32_am_sc_sign(temp); + have_am_sc = 1; + dolea = 1; } if (isadd) { @@ -508,7 +757,7 @@ static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *m } /* fix base */ - if (! be_is_NoReg(babi, index)) { + if (! be_is_NoReg(cg, index)) { /* if we have index, but left == right -> no base */ if (left == right) { base = noreg; @@ -524,24 +773,44 @@ static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *m /* Try to assimilate a LEA as left operand */ if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) { - am_flav = get_ia32_am_flavour(left); + ir_node *assim_lea_idx, *assim_lea_base; + + am_flav = get_ia32_am_flavour(left); + assim_lea_base = get_irn_n(left, 0); + assim_lea_idx = get_irn_n(left, 1); + /* If we have an Add with a real right operand (not NoReg) and */ /* the LEA contains already an index calculation then we create */ /* a new LEA. */ /* If the LEA contains already a frame_entity then we also */ /* create a new one otherwise we would loose it. */ - if ((isadd && !be_is_NoReg(babi, index) && (am_flav & ia32_am_I)) || - get_ia32_frame_ent(left)) + if ((isadd && ! be_is_NoReg(cg, index) && (am_flav & ia32_I)) || /* no new LEA if index already set */ + get_ia32_frame_ent(left) || /* no new LEA if stack access */ + (have_am_sc && get_ia32_am_sc(left)) || /* no new LEA if AM symconst already present */ + /* at least on of the LEA operands must be NOREG */ + (!be_is_NoReg(cg, assim_lea_base) && !be_is_NoReg(cg, assim_lea_idx))) { DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n")); } else { DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n")); - offs = get_ia32_am_offs(left); - base = get_irn_n(left, 0); - index = get_irn_n(left, 1); - scale = get_ia32_am_scale(left); + offs = get_ia32_am_offs(left); + am_sc = have_am_sc ? am_sc : get_ia32_am_sc(left); + have_am_sc = am_sc ? 1 : 0; + am_sc_sign = is_ia32_am_sc_sign(left); + scale = get_ia32_am_scale(left); + + if (be_is_NoReg(cg, assim_lea_base) && ! be_is_NoReg(cg, assim_lea_idx)) { + /* assimilate index */ + assert(be_is_NoReg(cg, index) && ! be_is_NoReg(cg, base) && "operand mismatch for LEA assimilation"); + index = assim_lea_idx; + } + else if (! be_is_NoReg(cg, assim_lea_base) && be_is_NoReg(cg, assim_lea_idx)) { + /* assimilate base */ + assert(! be_is_NoReg(cg, index) && (base == left) && "operand mismatch for LEA assimilation"); + base = assim_lea_base; + } } } @@ -577,6 +846,13 @@ static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *m } } + /* set the address mode symconst */ + if (have_am_sc) { + set_ia32_am_sc(res, am_sc); + if (am_sc_sign) + set_ia32_am_sc_sign(res); + } + /* copy the frame entity (could be set in case of Add */ /* which was a FrameAddr) */ set_ia32_frame_ent(res, get_ia32_frame_ent(irn)); @@ -592,10 +868,10 @@ static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *m if (offs || offs_cnst || offs_lea) { am_flav |= ia32_O; } - if (! be_is_NoReg(babi, base)) { + if (! be_is_NoReg(cg, base)) { am_flav |= ia32_B; } - if (! be_is_NoReg(babi, index)) { + if (! be_is_NoReg(cg, index)) { am_flav |= ia32_I; } if (scale > 0) { @@ -605,6 +881,8 @@ static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *m set_ia32_op_type(res, ia32_AddrModeS); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn)); + DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res))); /* get the result Proj of the Add/Sub */ @@ -624,9 +902,7 @@ static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *m */ void ia32_optimize_am(ir_node *irn, void *env) { ia32_code_gen_t *cg = env; - firm_dbg_module_t *mod = cg->mod; ir_node *res = irn; - be_abi_irg_t *babi = cg->birg->abi; dbg_info *dbg; ir_mode *mode; ir_node *block, *noreg_gp, *noreg_fp; @@ -634,6 +910,7 @@ void ia32_optimize_am(ir_node *irn, void *env) { ir_node *store, *load, *mem_proj; ir_node *succ, *addr_b, *addr_i; int check_am_src = 0; + DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;) if (! is_ia32_irn(irn)) return; @@ -665,7 +942,7 @@ void ia32_optimize_am(ir_node *irn, void *env) { /* check is irn is a candidate for address calculation */ if (is_candidate(block, irn, 1)) { DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn)); - res = fold_addr(babi, irn, mod, noreg_gp); + res = fold_addr(cg, irn, noreg_gp); if (res == irn) DB((mod, LEVEL_1, "transformed into %+F\n", res)); @@ -703,11 +980,18 @@ void ia32_optimize_am(ir_node *irn, void *env) { set_ia32_am_scale(irn, get_ia32_am_scale(left)); set_ia32_am_flavour(irn, get_ia32_am_flavour(left)); + set_ia32_am_sc(irn, get_ia32_am_sc(left)); + if (is_ia32_am_sc_sign(left)) + set_ia32_am_sc_sign(irn); + set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD); /* set base and index */ set_irn_n(irn, 0, get_irn_n(left, 0)); set_irn_n(irn, 1, get_irn_n(left, 1)); + + /* clear remat flag */ + set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable); } } /* check if the node is an address mode candidate */ @@ -724,7 +1008,7 @@ void ia32_optimize_am(ir_node *irn, void *env) { } /* normalize commutative ops */ - if (node_is_comm(irn)) { + if (node_is_ia32_comm(irn)) { /* Assure that right operand is always a Load if there is one */ /* because non-commutative ops can only use Dest AM if the right */ /* operand is a load, so we only need to check right operand. */ @@ -785,7 +1069,7 @@ void ia32_optimize_am(ir_node *irn, void *env) { /* Extra check for commutative ops with two Loads */ /* -> put the interesting Load right */ - if (node_is_comm(irn) && + if (node_is_ia32_comm(irn) && pred_is_specific_nodeblock(block, left, is_ia32_Ld)) { if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) && @@ -820,6 +1104,10 @@ void ia32_optimize_am(ir_node *irn, void *env) { set_ia32_frame_ent(irn, get_ia32_frame_ent(load)); set_ia32_ls_mode(irn, get_ia32_ls_mode(load)); + set_ia32_am_sc(irn, get_ia32_am_sc(load)); + if (is_ia32_am_sc_sign(load)) + set_ia32_am_sc_sign(irn); + if (is_ia32_use_frame(load)) set_ia32_use_frame(irn); @@ -840,6 +1128,9 @@ void ia32_optimize_am(ir_node *irn, void *env) { set_Proj_pred(mem_proj, irn); set_Proj_proj(mem_proj, 1); + /* clear remat flag */ + set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable); + DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store)); } } /* if (store) */ @@ -854,7 +1145,7 @@ void ia32_optimize_am(ir_node *irn, void *env) { } /* normalize commutative ops */ - if (node_is_comm(irn)) { + if (node_is_ia32_comm(irn)) { /* Assure that left operand is always a Load if there is one */ /* because non-commutative ops can only use Source AM if the */ /* left operand is a Load, so we only need to check the left */ @@ -890,6 +1181,13 @@ void ia32_optimize_am(ir_node *irn, void *env) { set_ia32_frame_ent(irn, get_ia32_frame_ent(left)); set_ia32_ls_mode(irn, get_ia32_ls_mode(left)); + set_ia32_am_sc(irn, get_ia32_am_sc(left)); + if (is_ia32_am_sc_sign(left)) + set_ia32_am_sc_sign(irn); + + /* clear remat flag */ + set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable); + if (is_ia32_use_frame(left)) set_ia32_use_frame(irn);