X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=7ea0a654dbf19d29d42c55084b900eca0b09b7a8;hb=5297678b46a3f2610756dc4c4ff62bc989334dc0;hp=8dd663a501230765a7fc813eec7426fa21bac658;hpb=80856828546f1fbf56f46f642e9a952fe46f2c0b;p=libfirm diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c index 8dd663a50..7ea0a654d 100644 --- a/ir/be/ia32/ia32_optimize.c +++ b/ir/be/ia32/ia32_optimize.c @@ -1,13 +1,28 @@ -/** - * Project: libFIRM - * File name: ir/be/ia32/ia32_optimize.c - * Purpose: Implements several optimizations for IA32 - * Author: Christian Wuerdig - * CVS-ID: $Id$ - * Copyright: (c) 2006 Universität Karlsruhe - * Licence: This file protected by GPL - GNU GENERAL PUBLIC LICENSE. +/* + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. + * + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. + * + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. */ +/** + * @file + * @brief Implements several optimizations for IA32. + * @author Matthias Braun, Christian Wuerdig + * @version $Id$ + */ #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -15,6 +30,7 @@ #include "irnode.h" #include "irprog_t.h" #include "ircons.h" +#include "irtools.h" #include "firm_types.h" #include "iredges.h" #include "tv.h" @@ -22,429 +38,259 @@ #include "irgwalk.h" #include "height.h" #include "irbitset.h" +#include "irprintf.h" +#include "error.h" #include "../be_t.h" #include "../beabi.h" #include "../benode_t.h" #include "../besched_t.h" +#include "../bepeephole.h" #include "ia32_new_nodes.h" +#include "ia32_optimize.h" #include "bearch_ia32_t.h" -#include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */ +#include "gen_ia32_regalloc_if.h" #include "ia32_transform.h" #include "ia32_dbg_stat.h" #include "ia32_util.h" +#include "ia32_architecture.h" -typedef enum { - IA32_AM_CAND_NONE = 0, - IA32_AM_CAND_LEFT = 1, - IA32_AM_CAND_RIGHT = 2, - IA32_AM_CAND_BOTH = 3 -} ia32_am_cand_t; +DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) -#undef is_NoMem -#define is_NoMem(irn) (get_irn_op(irn) == op_NoMem) - -typedef int is_op_func_t(const ir_node *n); -typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem); - -/** - * checks if a node represents the NOREG value - */ -static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) { - be_abi_irg_t *babi = cg->birg->abi; - const arch_register_t *fp_noreg = USE_SSE2(cg) ? - &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]; - - return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) || - (be_abi_get_callee_save_irn(babi, fp_noreg) == irn); -} +static const arch_env_t *arch_env; +static ia32_code_gen_t *cg; +static void peephole_IncSP_IncSP(ir_node *node); - -/************************************************* - * _____ _ _ - * / ____| | | | | - * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___ - * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __| - * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \ - * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/ - * - *************************************************/ - -/** - * creates a unique ident by adding a number to a tag - * - * @param tag the tag string, must contain a %d if a number - * should be added - */ -static ident *unique_id(const char *tag) +#if 0 +static void peephole_ia32_Store_IncSP_to_push(ir_node *node) { - static unsigned id = 0; - char str[256]; - - snprintf(str, sizeof(str), tag, ++id); - return new_id_from_str(str); -} + ir_node *base = get_irn_n(node, n_ia32_Store_base); + ir_node *index = get_irn_n(node, n_ia32_Store_index); + ir_node *mem = get_irn_n(node, n_ia32_Store_mem); + ir_node *incsp = base; + ir_node *val; + ir_node *noreg; + ir_graph *irg; + ir_node *block; + dbg_info *dbgi; + ir_mode *mode; + ir_node *push; + ir_node *proj; + int offset; + int node_offset; + + /* nomem inidicates the store doesn't alias with anything else */ + if(!is_NoMem(mem)) + return; -/** - * Transforms a SymConst. - * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir SymConst node - * @param mode mode of the SymConst - * @return the created ia32 Const node - */ -static ir_node *gen_SymConst(ia32_transform_env_t *env) { - dbg_info *dbg = env->dbg; - ir_mode *mode = env->mode; - ir_graph *irg = env->irg; - ir_node *block = env->block; - ir_node *cnst; - - if (mode_is_float(mode)) { - FP_USED(env->cg); - if (USE_SSE2(env->cg)) - cnst = new_rd_ia32_xConst(dbg, irg, block, get_irg_no_mem(irg), mode); - else - cnst = new_rd_ia32_vfConst(dbg, irg, block, get_irg_no_mem(irg), mode); + /* find an IncSP in front of us, we might have to skip barriers for this */ + while(is_Proj(incsp)) { + ir_node *proj_pred = get_Proj_pred(incsp); + if(!be_is_Barrier(proj_pred)) + return; + incsp = get_irn_n(proj_pred, get_Proj_proj(incsp)); } - else - cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode); + if(!be_is_IncSP(incsp)) + return; - set_ia32_Const_attr(cnst, env->irn); + peephole_IncSP_IncSP(incsp); - return cnst; -} + /* must be in the same block */ + if(get_nodes_block(incsp) != get_nodes_block(node)) + return; -/** - * Get a primitive type for a mode. - */ -static ir_type *get_prim_type(pmap *types, ir_mode *mode) -{ - pmap_entry *e = pmap_find(types, mode); - ir_type *res; - - if (! e) { - char buf[64]; - snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode)); - res = new_type_primitive(new_id_from_str(buf), mode); - pmap_insert(types, mode, res); + if(!is_ia32_NoReg_GP(index) || get_ia32_am_sc(node) != NULL) { + panic("Invalid storeAM found (%+F)", node); } - else - res = e->value; - return res; -} - -/** - * Get an entity that is initialized with a tarval - */ -static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst) -{ - tarval *tv = get_Const_tarval(cnst); - pmap_entry *e = pmap_find(cg->isa->tv_ent, tv); - entity *res; - ir_graph *rem; - - if (! e) { - ir_mode *mode = get_irn_mode(cnst); - ir_type *tp = get_Const_type(cnst); - if (tp == firm_unknown_type) - tp = get_prim_type(cg->isa->types, mode); - - res = new_entity(get_glob_type(), unique_id(".LC%u"), tp); - - set_entity_ld_ident(res, get_entity_ident(res)); - set_entity_visibility(res, visibility_local); - set_entity_variability(res, variability_constant); - set_entity_allocation(res, allocation_static); - - /* we create a new entity here: It's initialization must resist on the - const code irg */ - rem = current_ir_graph; - current_ir_graph = get_const_code_irg(); - set_atomic_ent_value(res, new_Const_type(tv, tp)); - current_ir_graph = rem; - - pmap_insert(cg->isa->tv_ent, tv, res); - } - else - res = e->value; - return res; -} - -/** - * Transforms a Const. - * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Const node - * @param mode mode of the Const - * @return the created ia32 Const node - */ -static ir_node *gen_Const(ia32_transform_env_t *env) { - ir_node *cnst, *load; - symconst_symbol sym; - ir_graph *irg = env->irg; - ir_node *block = env->block; - ir_node *node = env->irn; - dbg_info *dbg = env->dbg; - ir_mode *mode = env->mode; - - if (mode_is_float(mode)) { - FP_USED(env->cg); - if (! USE_SSE2(env->cg)) { - cnst_classify_t clss = classify_Const(node); - - if (clss == CNST_NULL) - return new_rd_ia32_vfldz(dbg, irg, block, mode); - else if (clss == CNST_ONE) - return new_rd_ia32_vfld1(dbg, irg, block, mode); - } - sym.entity_p = get_entity_for_tv(env->cg, node); + /* we should be the store to the end of the stackspace */ + offset = be_get_IncSP_offset(incsp); + mode = get_ia32_ls_mode(node); + node_offset = get_ia32_am_offs_int(node); + if(node_offset != offset - get_mode_size_bytes(mode)) + return; - cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent); - load = new_r_Load(irg, block, get_irg_no_mem(irg), cnst, mode); - load = new_r_Proj(irg, block, load, mode, pn_Load_res); - env->irn = cnst; - env->mode = mode_P; - cnst = gen_SymConst(env); - set_Load_ptr(get_Proj_pred(load), cnst); - cnst = load; - } - else { - cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), get_irn_mode(node)); - set_ia32_Const_attr(cnst, node); - } - return cnst; -} + /* we can use a push instead of the store */ + irg = current_ir_graph; + block = get_nodes_block(node); + dbgi = get_irn_dbg_info(node); + noreg = ia32_new_NoReg_gp(cg); + base = be_get_IncSP_pred(incsp); + val = get_irn_n(node, n_ia32_Store_val); + push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, base, val); -/** - * Transforms (all) Const's into ia32_Const and places them in the - * block where they are used (or in the cfg-pred Block in case of Phi's). - * Additionally all reference nodes are changed into mode_Is nodes. - * NOTE: irn must be a firm constant! - */ -static void ia32_transform_const(ir_node *irn, void *env) { - ia32_code_gen_t *cg = env; - ir_node *cnst = NULL; - ia32_transform_env_t tenv; - - tenv.cg = cg; - tenv.irg = cg->irg; - tenv.mode = get_irn_mode(irn); - tenv.dbg = get_irn_dbg_info(irn); - tenv.irn = irn; - DEBUG_ONLY(tenv.mod = cg->mod;) - - /* place const either in the smallest dominator of all its users or the original block */ - if (cg->opt & IA32_OPT_PLACECNST) - tenv.block = node_users_smallest_common_dominator(irn, 1); - else - tenv.block = get_nodes_block(irn); + proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M); - switch (get_irn_opcode(irn)) { - case iro_Const: - cnst = gen_Const(&tenv); - break; - case iro_SymConst: - cnst = gen_SymConst(&tenv); - break; - default: - assert(0 && "Wrong usage of ia32_transform_const!"); - } + be_set_IncSP_offset(incsp, offset - get_mode_size_bytes(mode)); - assert(cnst && "Could not create ia32 Const"); + sched_add_before(node, push); + sched_remove(node); - /* set the new ia32 const */ - exchange(irn, cnst); + be_peephole_before_exchange(node, proj); + exchange(node, proj); + be_peephole_after_exchange(proj); } -/** - * Transform all firm consts and assure, we visit each const only once. - */ -static void ia32_place_consts_walker(ir_node *irn, void *env) { - ia32_code_gen_t *cg = env; - - if(!is_Const(irn) && !is_SymConst(irn)) - return; - - ia32_transform_const(irn, cg); +static void peephole_ia32_Store(ir_node *node) +{ + peephole_ia32_Store_IncSP_to_push(node); } +#endif -/** - * Replace reference modes with mode_Iu and preserve store value modes. - */ -static void ia32_set_modes(ir_node *irn, void *env) { - if (is_Block(irn)) - return; - - /* transform all reference nodes into mode_Iu nodes */ - if (mode_is_reference(get_irn_mode(irn))) { - set_irn_mode(irn, mode_Iu); - } -} +static int produces_zero_flag(ir_node *node, int pn) +{ + ir_node *count; + const ia32_immediate_attr_t *imm_attr; -/** - * Walks over the graph, transforms all firm consts into ia32 consts - * and places them into the "best" block. - * @param cg The ia32 codegenerator object - */ -static void ia32_transform_all_firm_consts(ia32_code_gen_t *cg) { - irg_walk_graph(cg->irg, NULL, ia32_place_consts_walker, cg); -} + if(!is_ia32_irn(node)) + return 0; -/* Place all consts and change pointer arithmetics into unsigned integer arithmetics. */ -void ia32_pre_transform_phase(ia32_code_gen_t *cg) { - /* - We need to transform the consts twice: - - the psi condition tree transformer needs existing constants to be ia32 constants - - the psi condition tree transformer inserts new firm constants which need to be transformed - */ - ia32_transform_all_firm_consts(cg); - irg_walk_graph(cg->irg, ia32_set_modes, ia32_transform_psi_cond_tree, cg); - ia32_transform_all_firm_consts(cg); -} + if(pn >= 0) { + if(pn != pn_ia32_res) + return 0; + } -/******************************************************************************************************** - * _____ _ _ ____ _ _ _ _ _ - * | __ \ | | | | / __ \ | | (_) (_) | | (_) - * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __ - * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \ - * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | | - * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_| - * | | | | - * |_| |_| - ********************************************************************************************************/ + switch(get_ia32_irn_opcode(node)) { + case iro_ia32_Add: + case iro_ia32_Adc: + case iro_ia32_And: + case iro_ia32_Or: + case iro_ia32_Xor: + case iro_ia32_Sub: + case iro_ia32_Sbb: + case iro_ia32_Neg: + case iro_ia32_Inc: + case iro_ia32_Dec: + return 1; -/** - * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION. - */ + case iro_ia32_ShlD: + case iro_ia32_ShrD: + case iro_ia32_Shl: + case iro_ia32_Shr: + case iro_ia32_Sar: + assert(n_ia32_ShlD_count == n_ia32_ShrD_count); + assert(n_ia32_Shl_count == n_ia32_Shr_count + && n_ia32_Shl_count == n_ia32_Sar_count); + if(is_ia32_ShlD(node) || is_ia32_ShrD(node)) { + count = get_irn_n(node, n_ia32_ShlD_count); + } else { + count = get_irn_n(node, n_ia32_Shl_count); + } + /* when shift count is zero the flags are not affected, so we can only + * do this for constants != 0 */ + if(!is_ia32_Immediate(count)) + return 0; + + imm_attr = get_ia32_immediate_attr_const(count); + if(imm_attr->symconst != NULL) + return 0; + if((imm_attr->offset & 0x1f) == 0) + return 0; + return 1; -static int ia32_cnst_compare(ir_node *n1, ir_node *n2) { - return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2); + default: + break; + } + return 0; } -/** - * Checks for potential CJmp/CJmpAM optimization candidates. - */ -static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) { - ir_node *cand = NULL; - ir_node *prev = sched_prev(irn); - - if (is_Block(prev)) { - if (get_Block_n_cfgpreds(prev) == 1) - prev = get_Block_cfgpred(prev, 0); - else - prev = NULL; - } +static ir_node *turn_into_mode_t(ir_node *node) +{ + ir_node *block; + ir_node *res_proj; + ir_node *new_node; + const arch_register_t *reg; - /* The predecessor must be a ProjX. */ - if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) { - prev = get_Proj_pred(prev); + if(get_irn_mode(node) == mode_T) + return node; - if (is_op_func(prev)) - cand = prev; - } + assert(get_irn_mode(node) == mode_Iu); - return cand; -} + new_node = exact_copy(node); + set_irn_mode(new_node, mode_T); -static int is_TestJmp_cand(const ir_node *irn) { - return is_ia32_TestJmp(irn) || is_ia32_And(irn); -} + block = get_nodes_block(new_node); + res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu, + pn_ia32_res); -/** - * Checks if two consecutive arguments of cand matches - * the two arguments of irn (TestJmp). - */ -static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) { - ir_node *in1 = get_irn_n(irn, 0); - ir_node *in2 = get_irn_n(irn, 1); - int i, n = get_irn_arity(cand); - int same_args = 0; - - for (i = 0; i < n - 1; i++) { - if (get_irn_n(cand, i) == in1 && - get_irn_n(cand, i + 1) == in2) - { - same_args = 1; - break; - } - } + reg = arch_get_irn_register(arch_env, node); + arch_set_irn_register(arch_env, res_proj, reg); - if (same_args) - return ia32_cnst_compare(cand, irn); + be_peephole_before_exchange(node, res_proj); + sched_add_before(node, new_node); + sched_remove(node); + exchange(node, res_proj); + be_peephole_after_exchange(res_proj); - return 0; + return new_node; } -/** - * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And) - */ -static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) { - ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand); - int replace = 0; - - /* we found a possible candidate */ - replace = cand ? is_TestJmp_replacement(cand, irn) : 0; +static void peephole_ia32_Test(ir_node *node) +{ + ir_node *left = get_irn_n(node, n_ia32_Test_left); + ir_node *right = get_irn_n(node, n_ia32_Test_right); + ir_node *flags_proj; + ir_node *block; + ir_mode *flags_mode; + int pn = -1; + ir_node *schedpoint; + const ir_edge_t *edge; + + assert(n_ia32_Test_left == n_ia32_Test8Bit_left + && n_ia32_Test_right == n_ia32_Test8Bit_right); + + /* we need a test for 0 */ + if(left != right) + return; - if (replace) { - DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn)); + block = get_nodes_block(node); + if(get_nodes_block(left) != block) + return; - if (is_ia32_And(cand)) - set_irn_op(irn, op_ia32_CJmpAM); - else - set_irn_op(irn, op_ia32_CJmp); + if(is_Proj(left)) { + pn = get_Proj_proj(left); + left = get_Proj_pred(left); + } - DB((cg->mod, LEVEL_1, "%+F\n", irn)); + /* walk schedule up and abort when we find left or some other node destroys + the flags */ + schedpoint = sched_prev(node); + while(schedpoint != left) { + schedpoint = sched_prev(schedpoint); + if(arch_irn_is(arch_env, schedpoint, modify_flags)) + return; + if(schedpoint == block) + panic("couldn't find left"); } -} -static int is_CondJmp_cand(const ir_node *irn) { - return is_ia32_CondJmp(irn) || is_ia32_Sub(irn); -} + /* make sure only Lg/Eq tests are used */ + foreach_out_edge(node, edge) { + ir_node *user = get_edge_src_irn(edge); + int pnc = get_ia32_condcode(user); -/** - * Checks if the arguments of cand are the same of irn. - */ -static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) { - int i, n = get_irn_arity(cand); - int same_args = 1; - - for (i = 0; i < n; i++) { - if (get_irn_n(cand, i) != get_irn_n(irn, i)) { - same_args = 0; - break; + if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) { + return; } } - if (same_args) - return ia32_cnst_compare(cand, irn); - - return 0; -} - -/** - * Tries to replace a CondJmp by a CJmpAM - */ -static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) { - ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand); - int replace = 0; + if(!produces_zero_flag(left, pn)) + return; - /* we found a possible candidate */ - replace = cand ? is_CondJmp_replacement(cand, irn) : 0; + left = turn_into_mode_t(left); - if (replace) { - DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn)); - DBG_OPT_CJMP(irn); + flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode; + flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode, + pn_ia32_flags); + arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]); - set_irn_op(irn, op_ia32_CJmpAM); + assert(get_irn_mode(node) != mode_T); - DB((cg->mod, LEVEL_1, "%+F\n", irn)); - } + be_peephole_before_exchange(node, flags_proj); + exchange(node, flags_proj); + sched_remove(node); + be_peephole_after_exchange(flags_proj); } // only optimize up to 48 stores behind IncSPs @@ -453,7 +299,8 @@ static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) { /** * Tries to create pushs from IncSP,Store combinations */ -static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) { +static void peephole_IncSP_Store_to_push(ir_node *irn) +{ int i; int offset; ir_node *node; @@ -478,10 +325,8 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) { * attached to the node */ for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) { - const char *am_offs; ir_node *mem; - int offset = -1; - int n; + int offset; int storeslot; // it has to be a store @@ -489,29 +334,20 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) { break; // it has to use our sp value - if(get_irn_n(node, 0) != irn) + if(get_irn_n(node, n_ia32_base) != irn) continue; // store has to be attached to NoMem - mem = get_irn_n(node, 3); + mem = get_irn_n(node, n_ia32_mem); if(!is_NoMem(mem)) { continue; } - if( (get_ia32_am_flavour(node) & ia32_am_IS) != 0) + /* unfortunately we can't support the full AMs possible for push at the + * moment. TODO: fix this */ + if(get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index))) break; - am_offs = get_ia32_am_offs(node); - if(am_offs == NULL) { - offset = 0; - } else { - // the am_offs has to be of the form "+NUMBER" - if(sscanf(am_offs, "+%d%n", &offset, &n) != 1 || am_offs[n] != '\0') { - // we shouldn't have any cases in the compiler at the moment - // that produce something different from esp+XX - assert(0); - break; - } - } + offset = get_ia32_am_offs_int(node); storeslot = offset / 4; if(storeslot >= MAXPUSH_OPTIMIZE) @@ -528,7 +364,7 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) { stores[storeslot] = node; } - curr_sp = get_irn_n(irn, 0); + curr_sp = be_get_IncSP_pred(irn); // walk the stores in inverse order and create pushs for them i = (offset / 4) - 1; @@ -537,1235 +373,663 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) { } for( ; i >= 0; --i) { - const ir_edge_t *edge, *next; const arch_register_t *spreg; ir_node *push; - ir_node *val, *mem; + ir_node *val, *mem, *mem_proj; ir_node *store = stores[i]; + ir_node *noreg = ia32_new_NoReg_gp(cg); if(store == NULL || is_Bad(store)) break; - val = get_irn_n(store, 2); - mem = get_irn_n(store, 3); + val = get_irn_n(store, n_ia32_unary_op); + mem = get_irn_n(store, n_ia32_mem); spreg = arch_get_irn_register(cg->arch_env, curr_sp); - // create a push - push = new_rd_ia32_Push(NULL, irg, block, curr_sp, val, mem); - if(get_ia32_immop_type(store) != ia32_ImmNone) { - copy_ia32_Immop_attr(push, store); - } + push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, curr_sp, val); + sched_add_before(irn, push); // create stackpointer proj curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack); arch_set_irn_register(cg->arch_env, curr_sp, spreg); - sched_add_before(irn, curr_sp); - // rewire memprojs of the store - foreach_out_edge_safe(store, edge, next) { - ir_node *succ = get_edge_src_irn(edge); + // create memory proj + mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M); - assert(is_Proj(succ) && get_Proj_proj(succ) == pn_ia32_Store_M); - set_irn_n(succ, 0, push); - } + // use the memproj now + exchange(store, mem_proj); // we can remove the store now - set_irn_n(store, 0, new_Bad()); - set_irn_n(store, 1, new_Bad()); - set_irn_n(store, 2, new_Bad()); - set_irn_n(store, 3, new_Bad()); sched_remove(store); offset -= 4; } be_set_IncSP_offset(irn, offset); - - // can we remove the IncSP now? - if(offset == 0) { - const ir_edge_t *edge, *next; - - foreach_out_edge_safe(irn, edge, next) { - ir_node *arg = get_edge_src_irn(edge); - int pos = get_edge_src_pos(edge); - - set_irn_n(arg, pos, curr_sp); - } - - set_irn_n(irn, 0, new_Bad()); - sched_remove(irn); - } else { - set_irn_n(irn, 0, curr_sp); - } + be_set_IncSP_pred(irn, curr_sp); } /** * Tries to optimize two following IncSP. */ -static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) { - ir_node *prev = be_get_IncSP_pred(irn); - int real_uses = get_irn_n_edges(prev); - - if (be_is_IncSP(prev) && real_uses == 1) { - /* first IncSP has only one IncSP user, kill the first one */ - int prev_offs = be_get_IncSP_offset(prev); - int curr_offs = be_get_IncSP_offset(irn); - - be_set_IncSP_offset(prev, prev_offs + curr_offs); +static void peephole_IncSP_IncSP(ir_node *node) +{ + int pred_offs; + int curr_offs; + int offs; + ir_node *pred = be_get_IncSP_pred(node); + ir_node *predpred; - /* Omit the optimized IncSP */ - be_set_IncSP_pred(irn, be_get_IncSP_pred(prev)); + if(!be_is_IncSP(pred)) + return; - set_irn_n(prev, 0, new_Bad()); - sched_remove(prev); - } -} + if(get_irn_n_edges(pred) > 1) + return; -/** - * Performs Peephole Optimizations. - */ -static void ia32_peephole_optimize_node(ir_node *irn, void *env) { - ia32_code_gen_t *cg = env; - - /* AMD CPUs want explicit compare before conditional jump */ - if (! ARCH_AMD(cg->opt_arch)) { - if (is_ia32_TestJmp(irn)) - ia32_optimize_TestJmp(irn, cg); - else if (is_ia32_CondJmp(irn)) - ia32_optimize_CondJmp(irn, cg); - } + pred_offs = be_get_IncSP_offset(pred); + curr_offs = be_get_IncSP_offset(node); - if (be_is_IncSP(irn)) { - // optimize_IncSP doesn't respect dependency edges yet... - //ia32_optimize_IncSP(irn, cg); - (void) ia32_optimize_IncSP; - ia32_create_Pushs(irn, cg); + if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) { + if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) { + return; + } + offs = 0; + } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) { + if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) { + return; + } + offs = 0; + } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND + || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) { + return; + } else { + offs = curr_offs + pred_offs; } -} -void ia32_peephole_optimization(ir_graph *irg, ia32_code_gen_t *cg) { - irg_walk_graph(irg, ia32_peephole_optimize_node, NULL, cg); -} + /* add pred offset to ours and remove pred IncSP */ + be_set_IncSP_offset(node, offs); -/****************************************************************** - * _ _ __ __ _ - * /\ | | | | | \/ | | | - * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___ - * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \ - * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/ - * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___| - * - ******************************************************************/ + predpred = be_get_IncSP_pred(pred); + be_peephole_before_exchange(pred, predpred); -typedef struct { - ia32_code_gen_t *cg; - heights_t *h; -} ia32_am_opt_env_t; + /* rewire dependency edges */ + edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph); + be_set_IncSP_pred(node, predpred); + sched_remove(pred); + be_kill_node(pred); -static int node_is_ia32_comm(const ir_node *irn) { - return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0; + be_peephole_after_exchange(predpred); } -static int ia32_get_irn_n_edges(const ir_node *irn) { - const ir_edge_t *edge; - int cnt = 0; - - foreach_out_edge(irn, edge) { - cnt++; - } +static const arch_register_t *get_free_gp_reg(void) +{ + int i; - return cnt; -} + for(i = 0; i < N_ia32_gp_REGS; ++i) { + const arch_register_t *reg = &ia32_gp_regs[i]; + if(arch_register_type_is(reg, ignore)) + continue; -/** - * Determines if pred is a Proj and if is_op_func returns true for it's predecessor. - * - * @param pred The node to be checked - * @param is_op_func The check-function - * @return 1 if conditions are fulfilled, 0 otherwise - */ -static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) { - if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) { - return 1; + if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL) + return &ia32_gp_regs[i]; } - return 0; + return NULL; } -/** - * Determines if pred is a Proj and if is_op_func returns true for it's predecessor - * and if the predecessor is in block bl. - * - * @param bl The block - * @param pred The node to be checked - * @param is_op_func The check-function - * @return 1 if conditions are fulfilled, 0 otherwise - */ -static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred, - int (*is_op_func)(const ir_node *n)) +static void peephole_be_IncSP(ir_node *node) { - if (is_Proj(pred)) { - pred = get_Proj_pred(pred); - if ((bl == get_nodes_block(pred)) && is_op_func(pred)) { - return 1; - } - } - - return 0; -} - -/** - * Checks if irn is a candidate for address calculation. - * - * - none of the operand must be a Load within the same block OR - * - all Loads must have more than one user OR - * - the irn has a frame entity (it's a former FrameAddr) - * - * @param block The block the Loads must/mustnot be in - * @param irn The irn to check - * return 1 if irn is a candidate, 0 otherwise - */ -static int is_addr_candidate(const ir_node *block, const ir_node *irn) { - ir_node *in, *left, *right; - int n, is_cand = 1; - - left = get_irn_n(irn, 2); - right = get_irn_n(irn, 3); - - in = left; + const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + const arch_register_t *reg; + ir_graph *irg; + dbg_info *dbgi; + ir_node *block; + ir_node *keep; + ir_node *val; + ir_node *pop; + ir_node *noreg; + ir_node *stack; + int offset; + + /* first optimize incsp->incsp combinations */ + peephole_IncSP_IncSP(node); + + /* transform IncSP->Store combinations to Push where possible */ + peephole_IncSP_Store_to_push(node); + + /* replace IncSP -4 by Pop freereg when possible */ + offset = be_get_IncSP_offset(node); + if(offset != -4) + return; - if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) { - n = ia32_get_irn_n_edges(in); - is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */ - } + if(arch_get_irn_register(arch_env, node) != esp) + return; - in = right; + reg = get_free_gp_reg(); + if(reg == NULL) + return; - if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) { - n = ia32_get_irn_n_edges(in); - is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */ + irg = current_ir_graph; + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + noreg = ia32_new_NoReg_gp(cg); + stack = be_get_IncSP_pred(node); + pop = new_rd_ia32_Pop(dbgi, irg, block, noreg, noreg, new_NoMem(), stack); + + stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack); + arch_set_irn_register(arch_env, stack, esp); + val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res); + arch_set_irn_register(arch_env, val, reg); + + sched_add_before(node, pop); + + keep = sched_next(node); + if(!be_is_Keep(keep)) { + ir_node *in[1]; + in[0] = val; + keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in); + sched_add_before(node, keep); + } else { + be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val); } - is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand; - - return is_cand; + be_peephole_before_exchange(node, stack); + sched_remove(node); + exchange(node, stack); + be_peephole_after_exchange(stack); } /** - * Checks if irn is a candidate for address mode. - * - * address mode (AM): - * - at least one operand has to be a Load within the same block AND - * - the load must not have other users than the irn AND - * - the irn must not have a frame entity set - * - * @param cg The ia32 code generator - * @param h The height information of the irg - * @param block The block the Loads must/mustnot be in - * @param irn The irn to check - * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both + * Peephole optimisation for ia32_Const's */ -static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const ir_node *block, ir_node *irn) { - ir_node *in, *load, *other, *left, *right; - int n, is_cand = 0, cand; - - if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) || - is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn)) - return 0; - - left = get_irn_n(irn, 2); - right = get_irn_n(irn, 3); - - in = left; - - if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) { - n = ia32_get_irn_n_edges(in); - is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */ - - load = get_Proj_pred(in); - other = right; - - /* 8bit Loads are not supported, they cannot be used with every register */ - if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16) - is_cand = 0; - - /* If there is a data dependency of other irn from load: cannot use AM */ - if (is_cand && get_nodes_block(other) == block) { - other = skip_Proj(other); - is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand; - /* this could happen in loops */ - is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand; - } - } +static void peephole_ia32_Const(ir_node *node) +{ + const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node); + const arch_register_t *reg; + ir_graph *irg = current_ir_graph; + ir_node *block; + dbg_info *dbgi; + ir_node *produceval; + ir_node *xor; + ir_node *noreg; + + /* try to transform a mov 0, reg to xor reg reg */ + if(attr->offset != 0 || attr->symconst != NULL) + return; + /* xor destroys the flags, so no-one must be using them */ + if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL) + return; - cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE; - in = right; - is_cand = 0; + reg = arch_get_irn_register(arch_env, node); + assert(be_peephole_get_reg_value(reg) == NULL); - if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) { - n = ia32_get_irn_n_edges(in); - is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */ + /* create xor(produceval, produceval) */ + block = get_nodes_block(node); + dbgi = get_irn_dbg_info(node); + produceval = new_rd_ia32_ProduceVal(dbgi, irg, block); + arch_set_irn_register(arch_env, produceval, reg); - load = get_Proj_pred(in); - other = left; + noreg = ia32_new_NoReg_gp(cg); + xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(), + produceval, produceval); + arch_set_irn_register(arch_env, xor, reg); - /* 8bit Loads are not supported, they cannot be used with every register */ - if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16) - is_cand = 0; + sched_add_before(node, produceval); + sched_add_before(node, xor); - /* If there is a data dependency of other irn from load: cannot use load */ - if (is_cand && get_nodes_block(other) == block) { - other = skip_Proj(other); - is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand; - /* this could happen in loops */ - is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand; - } - } + be_peephole_before_exchange(node, xor); + exchange(node, xor); + sched_remove(node); + be_peephole_after_exchange(xor); +} - cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand; +static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node) +{ + return node == cg->noreg_gp; +} - /* check some special cases */ - if (USE_SSE2(cg) && is_ia32_Conv_I2FP(irn)) { - /* SSE Conv I -> FP cvtsi2s(s|d) can only load 32 bit values */ - if (get_mode_size_bits(get_ia32_tgt_mode(irn)) != 32) - cand = IA32_AM_CAND_NONE; - } - else if (is_ia32_Conv_I2I(irn)) { - /* we cannot load an N bit value and implicitly convert it into an M bit value if N > M */ - if (get_mode_size_bits(get_ia32_src_mode(irn)) > get_mode_size_bits(get_ia32_tgt_mode(irn))) - cand = IA32_AM_CAND_NONE; - } +static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val) +{ + ir_graph *irg = current_ir_graph; + ir_node *start_block = get_irg_start_block(irg); + ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, + 0, val); + arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]); - /* if the irn has a frame entity: we do not use address mode */ - return get_ia32_frame_ent(irn) ? IA32_AM_CAND_NONE : cand; + return immediate; } -/** - * Compares the base and index addr and the load/store entities - * and returns 1 if they are equal. - */ -static int load_store_addr_is_equal(const ir_node *load, const ir_node *store, - const ir_node *addr_b, const ir_node *addr_i) +static ir_node *create_immediate_from_am(ia32_code_gen_t *cg, + const ir_node *node) { - int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1)); - entity *lent = get_ia32_frame_ent(load); - entity *sent = get_ia32_frame_ent(store); - ident *lid = get_ia32_am_sc(load); - ident *sid = get_ia32_am_sc(store); - char *loffs = get_ia32_am_offs(load); - char *soffs = get_ia32_am_offs(store); - - /* are both entities set and equal? */ - if (is_equal && (lent || sent)) - is_equal = lent && sent && (lent == sent); - - /* are address mode idents set and equal? */ - if (is_equal && (lid || sid)) - is_equal = lid && sid && (lid == sid); - - /* are offsets set and equal */ - if (is_equal && (loffs || soffs)) - is_equal = loffs && soffs && strcmp(loffs, soffs) == 0; - - /* are the load and the store of the same mode? */ - is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0; - - return is_equal; + ir_graph *irg = get_irn_irg(node); + ir_node *block = get_nodes_block(node); + int offset = get_ia32_am_offs_int(node); + int sc_sign = is_ia32_am_sc_sign(node); + ir_entity *entity = get_ia32_am_sc(node); + ir_node *res; + + res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset); + arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]); + return res; } -typedef enum _ia32_take_lea_attr { - IA32_LEA_ATTR_NONE = 0, - IA32_LEA_ATTR_BASE = (1 << 0), - IA32_LEA_ATTR_INDEX = (1 << 1), - IA32_LEA_ATTR_OFFS = (1 << 2), - IA32_LEA_ATTR_SCALE = (1 << 3), - IA32_LEA_ATTR_AMSC = (1 << 4), - IA32_LEA_ATTR_FENT = (1 << 5) -} ia32_take_lea_attr; - -/** - * Decides if we have to keep the LEA operand or if we can assimilate it. - */ -static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea, - int have_am_sc, ia32_code_gen_t *cg) +static int is_am_one(const ir_node *node) { - entity *irn_ent = get_ia32_frame_ent(irn); - entity *lea_ent = get_ia32_frame_ent(lea); - int ret_val = 0; - int is_noreg_base = be_is_NoReg(cg, base); - int is_noreg_index = be_is_NoReg(cg, index); - ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea); - - /* If the Add and the LEA both have a different frame entity set: keep */ - if (irn_ent && lea_ent && (irn_ent != lea_ent)) - return IA32_LEA_ATTR_NONE; - else if (! irn_ent && lea_ent) - ret_val |= IA32_LEA_ATTR_FENT; - - /* If the Add and the LEA both have already an address mode symconst: keep */ - if (have_am_sc && get_ia32_am_sc(lea)) - return IA32_LEA_ATTR_NONE; - else if (get_ia32_am_sc(lea)) - ret_val |= IA32_LEA_ATTR_AMSC; - - /* Check the different base-index combinations */ - - if (! is_noreg_base && ! is_noreg_index) { - /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */ - if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) { - if (am_flav & ia32_O) - ret_val |= IA32_LEA_ATTR_OFFS; - - ret_val |= IA32_LEA_ATTR_BASE; - } - else - return IA32_LEA_ATTR_NONE; - } - else if (! is_noreg_base && is_noreg_index) { - /* Base is set but index not */ - if (base == lea) { - /* Base points to LEA: assimilate everything */ - if (am_flav & ia32_O) - ret_val |= IA32_LEA_ATTR_OFFS; - if (am_flav & ia32_S) - ret_val |= IA32_LEA_ATTR_SCALE; - if (am_flav & ia32_I) - ret_val |= IA32_LEA_ATTR_INDEX; - - ret_val |= IA32_LEA_ATTR_BASE; - } - else if (am_flav & ia32_B ? 0 : 1) { - /* Base is not the LEA but the LEA is an index only calculation: assimilate */ - if (am_flav & ia32_O) - ret_val |= IA32_LEA_ATTR_OFFS; - if (am_flav & ia32_S) - ret_val |= IA32_LEA_ATTR_SCALE; - - ret_val |= IA32_LEA_ATTR_INDEX; - } - else - return IA32_LEA_ATTR_NONE; - } - else if (is_noreg_base && ! is_noreg_index) { - /* Index is set but not base */ - if (index == lea) { - /* Index points to LEA: assimilate everything */ - if (am_flav & ia32_O) - ret_val |= IA32_LEA_ATTR_OFFS; - if (am_flav & ia32_S) - ret_val |= IA32_LEA_ATTR_SCALE; - if (am_flav & ia32_B) - ret_val |= IA32_LEA_ATTR_BASE; - - ret_val |= IA32_LEA_ATTR_INDEX; - } - else if (am_flav & ia32_I ? 0 : 1) { - /* Index is not the LEA but the LEA is a base only calculation: assimilate */ - if (am_flav & ia32_O) - ret_val |= IA32_LEA_ATTR_OFFS; - if (am_flav & ia32_S) - ret_val |= IA32_LEA_ATTR_SCALE; - - ret_val |= IA32_LEA_ATTR_BASE; - } - else - return IA32_LEA_ATTR_NONE; - } - else { - assert(0 && "There must have been set base or index"); - } + int offset = get_ia32_am_offs_int(node); + ir_entity *entity = get_ia32_am_sc(node); - return ret_val; + return offset == 1 && entity == NULL; } -/** - * Adds res before irn into schedule if irn was scheduled. - * @param irn The schedule point - * @param res The node to be scheduled - */ -static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) { - if (sched_is_scheduled(irn)) - sched_add_before(irn, res); -} - -/** - * Removes irn from schedule if it was scheduled. If irn is a mode_T node - * all it's Projs are removed as well. - * @param irn The irn to be removed from schedule - */ -static INLINE void try_remove_from_sched(ir_node *irn) { - int i, arity; - - if (sched_is_scheduled(irn)) { - if (get_irn_mode(irn) == mode_T) { - const ir_edge_t *edge; - foreach_out_edge(irn, edge) { - ir_node *proj = get_edge_src_irn(edge); - if (sched_is_scheduled(proj)) { - set_irn_n(proj, 0, new_Bad()); - sched_remove(proj); - } - } - } +static int is_am_minus_one(const ir_node *node) +{ + int offset = get_ia32_am_offs_int(node); + ir_entity *entity = get_ia32_am_sc(node); - arity = get_irn_arity(irn); - for(i = 0; i < arity; ++i) { - set_irn_n(irn, i, new_Bad()); - } - sched_remove(irn); - } + return offset == -1 && entity == NULL; } /** - * Folds Add or Sub to LEA if possible + * Transforms a LEA into an Add or SHL if possible. */ -static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) { - ir_graph *irg = get_irn_irg(irn); - dbg_info *dbg = get_irn_dbg_info(irn); - ir_node *block = get_nodes_block(irn); - ir_node *res = irn; - ir_node *shift = NULL; - ir_node *lea_o = NULL; - ir_node *lea = NULL; - char *offs = NULL; - const char *offs_cnst = NULL; - char *offs_lea = NULL; - int scale = 0; - int isadd = 0; - int dolea = 0; - int have_am_sc = 0; - int am_sc_sign = 0; - ident *am_sc = NULL; - entity *lea_ent = NULL; - ir_node *left, *right, *temp; - ir_node *base, *index; - int consumed_left_shift; - ia32_am_flavour_t am_flav; - DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;) - - if (is_ia32_Add(irn)) - isadd = 1; - - left = get_irn_n(irn, 2); - right = get_irn_n(irn, 3); - - /* "normalize" arguments in case of add with two operands */ - if (isadd && ! be_is_NoReg(cg, right)) { - /* put LEA == ia32_am_O as right operand */ - if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) { - set_irn_n(irn, 2, right); - set_irn_n(irn, 3, left); - temp = left; - left = right; - right = temp; - } +static void peephole_ia32_Lea(ir_node *node) +{ + const arch_env_t *arch_env = cg->arch_env; + ir_graph *irg = current_ir_graph; + ir_node *base; + ir_node *index; + const arch_register_t *base_reg; + const arch_register_t *index_reg; + const arch_register_t *out_reg; + int scale; + int has_immediates; + ir_node *op1; + ir_node *op2; + dbg_info *dbgi; + ir_node *block; + ir_node *res; + ir_node *noreg; + ir_node *nomem; + + assert(is_ia32_Lea(node)); + + /* we can only do this if are allowed to globber the flags */ + if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL) + return; - /* put LEA != ia32_am_O as left operand */ - if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) { - set_irn_n(irn, 2, right); - set_irn_n(irn, 3, left); - temp = left; - left = right; - right = temp; - } + base = get_irn_n(node, n_ia32_Lea_base); + index = get_irn_n(node, n_ia32_Lea_index); - /* put SHL as left operand iff left is NOT a LEA */ - if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) { - set_irn_n(irn, 2, right); - set_irn_n(irn, 3, left); - temp = left; - left = right; - right = temp; - } + if(is_noreg(cg, base)) { + base = NULL; + base_reg = NULL; + } else { + base_reg = arch_get_irn_register(arch_env, base); } - - base = left; - index = noreg; - offs = NULL; - scale = 0; - am_flav = 0; - - /* check for operation with immediate */ - if (is_ia32_ImmConst(irn)) { - DBG((mod, LEVEL_1, "\tfound op with imm const")); - - offs_cnst = get_ia32_cnst(irn); - dolea = 1; + if(is_noreg(cg, index)) { + index = NULL; + index_reg = NULL; + } else { + index_reg = arch_get_irn_register(arch_env, index); } - else if (is_ia32_ImmSymConst(irn)) { - DBG((mod, LEVEL_1, "\tfound op with imm symconst")); - have_am_sc = 1; - dolea = 1; - am_sc = get_ia32_id_cnst(irn); - am_sc_sign = is_ia32_am_sc_sign(irn); + if(base == NULL && index == NULL) { + /* we shouldn't construct these in the first place... */ +#ifdef DEBUG_libfirm + ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n"); +#endif + return; } - /* determine the operand which needs to be checked */ - temp = be_is_NoReg(cg, right) ? left : right; - - /* check if right operand is AMConst (LEA with ia32_am_O) */ - /* but we can only eat it up if there is no other symconst */ - /* because the linker won't accept two symconsts */ - if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) { - DBG((mod, LEVEL_1, "\tgot op with LEA am_O")); - - offs_lea = get_ia32_am_offs(temp); - am_sc = get_ia32_am_sc(temp); - am_sc_sign = is_ia32_am_sc_sign(temp); - have_am_sc = 1; - dolea = 1; - lea_o = temp; - - if (temp == base) - base = noreg; - else if (temp == right) - right = noreg; + out_reg = arch_get_irn_register(arch_env, node); + scale = get_ia32_am_scale(node); + assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL); + /* check if we have immediates values (frame entities should already be + * expressed in the offsets) */ + if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) { + has_immediates = 1; + } else { + has_immediates = 0; } - if (isadd) { - /* default for add -> make right operand to index */ - index = right; - dolea = 1; - consumed_left_shift = -1; - - DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index)); - - /* determine the operand which needs to be checked */ - temp = left; - if (is_ia32_Lea(left)) { - temp = right; - consumed_left_shift = 0; - } - - /* check for SHL 1,2,3 */ - if (pred_is_specific_node(temp, is_ia32_Shl)) { - temp = get_Proj_pred(temp); - shift = temp; - - if (get_ia32_Immop_tarval(temp)) { - scale = get_tarval_long(get_ia32_Immop_tarval(temp)); - - if (scale <= 3) { - index = get_irn_n(temp, 2); - consumed_left_shift = consumed_left_shift < 0 ? 1 : 0; - - DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index)); - } - else { - scale = 0; - shift = NULL; - } - } - } - - /* fix base */ - if (! be_is_NoReg(cg, index)) { - /* if we have index, but left == right -> no base */ - if (left == right) { - base = noreg; - } - else if (consumed_left_shift == 1) { - /* -> base is right operand */ - base = (right == lea_o) ? noreg : right; + /* we can transform leas where the out register is the same as either the + * base or index register back to an Add or Shl */ + if(out_reg == base_reg) { + if(index == NULL) { +#ifdef DEBUG_libfirm + if(!has_immediates) { + ir_fprintf(stderr, "Optimisation warning: found lea which is " + "just a copy\n"); } +#endif + op1 = base; + goto make_add_immediate; } - } - - /* Try to assimilate a LEA as left operand */ - if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) { - /* check if we can assimilate the LEA */ - int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg); - - if (take_attr == IA32_LEA_ATTR_NONE) { - DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n")); + if(scale == 0 && !has_immediates) { + op1 = base; + op2 = index; + goto make_add; } - else { - DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n")); - lea = left; /* for statistics */ - - if (take_attr & IA32_LEA_ATTR_OFFS) - offs = get_ia32_am_offs(left); - - if (take_attr & IA32_LEA_ATTR_AMSC) { - am_sc = get_ia32_am_sc(left); - have_am_sc = 1; - am_sc_sign = is_ia32_am_sc_sign(left); + /* can't create an add */ + return; + } else if(out_reg == index_reg) { + if(base == NULL) { + if(has_immediates && scale == 0) { + op1 = index; + goto make_add_immediate; + } else if(!has_immediates && scale > 0) { + op1 = index; + op2 = create_immediate_from_int(cg, scale); + goto make_shl; + } else if(!has_immediates) { +#ifdef DEBUG_libfirm + ir_fprintf(stderr, "Optimisation warning: found lea which is " + "just a copy\n"); +#endif } - - if (take_attr & IA32_LEA_ATTR_SCALE) - scale = get_ia32_am_scale(left); - - if (take_attr & IA32_LEA_ATTR_BASE) - base = get_irn_n(left, 0); - - if (take_attr & IA32_LEA_ATTR_INDEX) - index = get_irn_n(left, 1); - - if (take_attr & IA32_LEA_ATTR_FENT) - lea_ent = get_ia32_frame_ent(left); + } else if(scale == 0 && !has_immediates) { + op1 = index; + op2 = base; + goto make_add; } + /* can't create an add */ + return; + } else { + /* can't create an add */ + return; } - /* ok, we can create a new LEA */ - if (dolea) { - res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is); - - /* add the old offset of a previous LEA */ - if (offs) { - add_ia32_am_offs(res, offs); +make_add_immediate: + if(ia32_cg_config.use_incdec) { + if(is_am_one(node)) { + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + res = new_rd_ia32_Inc(dbgi, irg, block, op1); + arch_set_irn_register(arch_env, res, out_reg); + goto exchange; } - - /* add the new offset */ - if (isadd) { - if (offs_cnst) { - add_ia32_am_offs(res, offs_cnst); - } - if (offs_lea) { - add_ia32_am_offs(res, offs_lea); - } - } - else { - /* either lea_O-cnst, -cnst or -lea_O */ - if (offs_cnst) { - if (offs_lea) { - add_ia32_am_offs(res, offs_lea); - } - - sub_ia32_am_offs(res, offs_cnst); - } - else { - sub_ia32_am_offs(res, offs_lea); - } + if(is_am_minus_one(node)) { + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + res = new_rd_ia32_Dec(dbgi, irg, block, op1); + arch_set_irn_register(arch_env, res, out_reg); + goto exchange; } - - /* set the address mode symconst */ - if (have_am_sc) { - set_ia32_am_sc(res, am_sc); - if (am_sc_sign) - set_ia32_am_sc_sign(res); - } - - /* copy the frame entity (could be set in case of Add */ - /* which was a FrameAddr) */ - if (lea_ent) - set_ia32_frame_ent(res, lea_ent); - else - set_ia32_frame_ent(res, get_ia32_frame_ent(irn)); - - if (get_ia32_frame_ent(res)) - set_ia32_use_frame(res); - - /* set scale */ - set_ia32_am_scale(res, scale); - - am_flav = ia32_am_N; - /* determine new am flavour */ - if (offs || offs_cnst || offs_lea || have_am_sc) { - am_flav |= ia32_O; - } - if (! be_is_NoReg(cg, base)) { - am_flav |= ia32_B; - } - if (! be_is_NoReg(cg, index)) { - am_flav |= ia32_I; - } - if (scale > 0) { - am_flav |= ia32_S; - } - set_ia32_am_flavour(res, am_flav); - - set_ia32_op_type(res, ia32_AddrModeS); - - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn)); - - DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res))); - - /* we will exchange it, report here before the Proj is created */ - if (shift && lea && lea_o) { - try_remove_from_sched(shift); - try_remove_from_sched(lea); - try_remove_from_sched(lea_o); - DBG_OPT_LEA4(irn, lea_o, lea, shift, res); - } - else if (shift && lea) { - try_remove_from_sched(shift); - try_remove_from_sched(lea); - DBG_OPT_LEA3(irn, lea, shift, res); - } - else if (shift && lea_o) { - try_remove_from_sched(shift); - try_remove_from_sched(lea_o); - DBG_OPT_LEA3(irn, lea_o, shift, res); - } - else if (lea && lea_o) { - try_remove_from_sched(lea); - try_remove_from_sched(lea_o); - DBG_OPT_LEA3(irn, lea_o, lea, res); - } - else if (shift) { - try_remove_from_sched(shift); - DBG_OPT_LEA2(irn, shift, res); - } - else if (lea) { - try_remove_from_sched(lea); - DBG_OPT_LEA2(irn, lea, res); - } - else if (lea_o) { - try_remove_from_sched(lea_o); - DBG_OPT_LEA2(irn, lea_o, res); - } - else - DBG_OPT_LEA1(irn, res); - - /* get the result Proj of the Add/Sub */ - try_add_to_sched(irn, res); - try_remove_from_sched(irn); - irn = ia32_get_res_proj(irn); - - assert(irn && "Couldn't find result proj"); - - /* exchange the old op with the new LEA */ - exchange(irn, res); } - - return res; + op2 = create_immediate_from_am(cg, node); + +make_add: + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + noreg = ia32_new_NoReg_gp(cg); + nomem = new_NoMem(); + res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2); + arch_set_irn_register(arch_env, res, out_reg); + set_ia32_commutative(res); + goto exchange; + +make_shl: + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + noreg = ia32_new_NoReg_gp(cg); + nomem = new_NoMem(); + res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2); + arch_set_irn_register(arch_env, res, out_reg); + goto exchange; + +exchange: + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node)); + + /* add new ADD/SHL to schedule */ + DBG_OPT_LEA2ADD(node, res); + + /* exchange the Add and the LEA */ + be_peephole_before_exchange(node, res); + sched_add_before(node, res); + sched_remove(node); + exchange(node, res); + be_peephole_after_exchange(res); } - /** - * Merges a Load/Store node with a LEA. - * @param irn The Load/Store node - * @param lea The LEA + * Register a peephole optimisation function. */ -static void merge_loadstore_lea(ir_node *irn, ir_node *lea) { - entity *irn_ent = get_ia32_frame_ent(irn); - entity *lea_ent = get_ia32_frame_ent(lea); - - /* If the irn and the LEA both have a different frame entity set: do not merge */ - if (irn_ent && lea_ent && (irn_ent != lea_ent)) - return; - else if (! irn_ent && lea_ent) { - set_ia32_frame_ent(irn, lea_ent); - set_ia32_use_frame(irn); - } - - /* get the AM attributes from the LEA */ - add_ia32_am_offs(irn, get_ia32_am_offs(lea)); - set_ia32_am_scale(irn, get_ia32_am_scale(lea)); - set_ia32_am_flavour(irn, get_ia32_am_flavour(lea)); - - set_ia32_am_sc(irn, get_ia32_am_sc(lea)); - if (is_ia32_am_sc_sign(lea)) - set_ia32_am_sc_sign(irn); - - set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD); - - /* set base and index */ - set_irn_n(irn, 0, get_irn_n(lea, 0)); - set_irn_n(irn, 1, get_irn_n(lea, 1)); - - try_remove_from_sched(lea); - - /* clear remat flag */ - set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable); - - if (is_ia32_Ld(irn)) - DBG_OPT_LOAD_LEA(lea, irn); - else - DBG_OPT_STORE_LEA(lea, irn); - +static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) { + assert(op->ops.generic == NULL); + op->ops.generic = (void*) func; } -/** - * Sets new_right index of irn to right and new_left index to left. - * Also exchange left and right - */ -static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) { - ir_node *temp; - - set_irn_n(irn, new_right, *right); - set_irn_n(irn, new_left, *left); - - temp = *left; - *left = *right; - *right = temp; - - /* this is only needed for Compares, but currently ALL nodes - * have this attribute :-) */ - set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn))); +/* Perform peephole-optimizations. */ +void ia32_peephole_optimization(ia32_code_gen_t *new_cg) +{ + cg = new_cg; + arch_env = cg->arch_env; + + /* register peephole optimisations */ + clear_irp_opcodes_generic_func(); + register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const); + //register_peephole_optimisation(op_ia32_Store, peephole_ia32_Store); + register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP); + register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea); + register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test); + register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test); + + be_peephole_opt(cg->birg); } /** - * Performs address calculation optimization (create LEAs if possible) + * Removes node from schedule if it is not used anymore. If irn is a mode_T node + * all it's Projs are removed as well. + * @param irn The irn to be removed from schedule */ -static void optimize_lea(ir_node *irn, void *env) { - ia32_code_gen_t *cg = env; - ir_node *block, *noreg_gp, *left, *right; +static INLINE void try_kill(ir_node *node) +{ + if(get_irn_mode(node) == mode_T) { + const ir_edge_t *edge, *next; + foreach_out_edge_safe(node, edge, next) { + ir_node *proj = get_edge_src_irn(edge); + try_kill(proj); + } + } - if (! is_ia32_irn(irn)) + if(get_irn_n_edges(node) != 0) return; - /* Following cases can occur: */ - /* - Sub (l, imm) -> LEA [base - offset] */ - /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */ - /* - Add (l, imm) -> LEA [base + offset] */ - /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */ - /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */ - /* - Add (l, r) -> LEA [base + index * scale] */ - /* with scale > 1 iff l/r == shl (1,2,3) */ - - if (is_ia32_Sub(irn) || is_ia32_Add(irn)) { - left = get_irn_n(irn, 2); - right = get_irn_n(irn, 3); - block = get_nodes_block(irn); - noreg_gp = ia32_new_NoReg_gp(cg); - - /* Do not try to create a LEA if one of the operands is a Load. */ - /* check is irn is a candidate for address calculation */ - if (is_addr_candidate(block, irn)) { - ir_node *res; - - DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn)); - res = fold_addr(cg, irn, noreg_gp); - - if (res != irn) - DB((cg->mod, LEVEL_1, "transformed into %+F\n", res)); - else - DB((cg->mod, LEVEL_1, "not transformed\n")); - } - } - else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) { - /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */ - /* - Store -> LEA into Store } it might be better to keep the LEA */ - left = get_irn_n(irn, 0); - - if (is_ia32_Lea(left)) { - const ir_edge_t *edge, *ne; - ir_node *src; - - /* merge all Loads/Stores connected to this LEA with the LEA */ - foreach_out_edge_safe(left, edge, ne) { - src = get_edge_src_irn(edge); - - if (src && (get_edge_src_pos(edge) == 0) && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) { - DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn)); - if (! is_ia32_got_lea(src)) - merge_loadstore_lea(src, left); - set_ia32_got_lea(src); - } - } - } + if (sched_is_scheduled(node)) { + sched_remove(node); } + + be_kill_node(node); } +static void optimize_conv_store(ir_node *node) +{ + ir_node *pred; + ir_node *pred_proj; + ir_mode *conv_mode; + ir_mode *store_mode; -/** - * Checks for address mode patterns and performs the - * necessary transformations. - * This function is called by a walker. - */ -static void optimize_am(ir_node *irn, void *env) { - ia32_am_opt_env_t *am_opt_env = env; - ia32_code_gen_t *cg = am_opt_env->cg; - heights_t *h = am_opt_env->h; - ir_node *block, *noreg_gp, *noreg_fp; - ir_node *left, *right; - ir_node *store, *load, *mem_proj; - ir_node *succ, *addr_b, *addr_i; - int check_am_src = 0; - int need_exchange_on_fail = 0; - DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;) - - if (! is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) + if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node)) return; - block = get_nodes_block(irn); - noreg_gp = ia32_new_NoReg_gp(cg); - noreg_fp = ia32_new_NoReg_fp(cg); - - DBG((mod, LEVEL_1, "checking for AM\n")); - - /* fold following patterns: */ - /* - op -> Load into AMop with am_Source */ - /* conditions: */ - /* - op is am_Source capable AND */ - /* - the Load is only used by this op AND */ - /* - the Load is in the same block */ - /* - Store -> op -> Load into AMop with am_Dest */ - /* conditions: */ - /* - op is am_Dest capable AND */ - /* - the Store uses the same address as the Load AND */ - /* - the Load is only used by this op AND */ - /* - the Load and Store are in the same block AND */ - /* - nobody else uses the result of the op */ - - if ((get_ia32_am_support(irn) != ia32_am_None) && ! is_ia32_Lea(irn)) { - ia32_am_cand_t cand = is_am_candidate(cg, h, block, irn); - ia32_am_cand_t orig_cand = cand; - - /* cand == 1: load is left; cand == 2: load is right; */ - - if (cand == IA32_AM_CAND_NONE) - return; + assert(n_ia32_Store_val == n_ia32_Store8Bit_val); + pred_proj = get_irn_n(node, n_ia32_Store_val); + if(is_Proj(pred_proj)) { + pred = get_Proj_pred(pred_proj); + } else { + pred = pred_proj; + } + if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred)) + return; + if(get_ia32_op_type(pred) != ia32_Normal) + return; - DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn)); + /* the store only stores the lower bits, so we only need the conv + * it it shrinks the mode */ + conv_mode = get_ia32_ls_mode(pred); + store_mode = get_ia32_ls_mode(node); + if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode)) + return; - left = get_irn_n(irn, 2); - if (get_irn_arity(irn) == 4) { - /* it's an "unary" operation */ - right = left; - } - else { - right = get_irn_n(irn, 3); - } + set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val)); + if(get_irn_n_edges(pred_proj) == 0) { + be_kill_node(pred_proj); + if(pred != pred_proj) + be_kill_node(pred); + } +} - /* normalize commutative ops */ - if (node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_RIGHT)) { +static void optimize_load_conv(ir_node *node) +{ + ir_node *pred, *predpred; + ir_mode *load_mode; + ir_mode *conv_mode; - /* Assure that left operand is always a Load if there is one */ - /* because non-commutative ops can only use Dest AM if the left */ - /* operand is a load, so we only need to check left operand. */ + if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node)) + return; - exchange_left_right(irn, &left, &right, 3, 2); - need_exchange_on_fail = 1; + assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val); + pred = get_irn_n(node, n_ia32_Conv_I2I_val); + if(!is_Proj(pred)) + return; - /* now: load is right */ - cand = IA32_AM_CAND_LEFT; - } + predpred = get_Proj_pred(pred); + if(!is_ia32_Load(predpred)) + return; - /* check for Store -> op -> Load */ - - /* Store -> op -> Load optimization is only possible if supported by op */ - /* and if right operand is a Load */ - if ((get_ia32_am_support(irn) & ia32_am_Dest) && (cand & IA32_AM_CAND_LEFT)) - { - /* An address mode capable op always has a result Proj. */ - /* If this Proj is used by more than one other node, we don't need to */ - /* check further, otherwise we check for Store and remember the address, */ - /* the Store points to. */ - - succ = ia32_get_res_proj(irn); - assert(succ && "Couldn't find result proj"); - - addr_b = NULL; - addr_i = NULL; - store = NULL; - - /* now check for users and Store */ - if (ia32_get_irn_n_edges(succ) == 1) { - succ = get_edge_src_irn(get_irn_out_edge_first(succ)); - - if (is_ia32_xStore(succ) || is_ia32_Store(succ)) { - store = succ; - addr_b = get_irn_n(store, 0); - addr_i = get_irn_n(store, 1); - } - } + /* the load is sign extending the upper bits, so we only need the conv + * if it shrinks the mode */ + load_mode = get_ia32_ls_mode(predpred); + conv_mode = get_ia32_ls_mode(node); + if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode)) + return; - if (store) { - /* we found a Store as single user: Now check for Load */ - - /* skip the Proj for easier access */ - load = is_Proj(right) ? (is_ia32_Load(get_Proj_pred(right)) ? get_Proj_pred(right) : NULL) : NULL; - - /* Extra check for commutative ops with two Loads */ - /* -> put the interesting Load left */ - if (load && node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_BOTH)) { - if (load_store_addr_is_equal(load, store, addr_b, addr_i)) { - /* We exchange left and right, so it's easier to kill */ - /* the correct Load later and to handle unary operations. */ - exchange_left_right(irn, &left, &right, 3, 2); - need_exchange_on_fail ^= 1; - } - } - - /* skip the Proj for easier access */ - load = get_Proj_pred(left); - - /* Compare Load and Store address */ - if (load_store_addr_is_equal(load, store, addr_b, addr_i)) { - /* Left Load is from same address, so we can */ - /* disconnect the Load and Store here */ - - /* set new base, index and attributes */ - set_irn_n(irn, 0, addr_b); - set_irn_n(irn, 1, addr_i); - add_ia32_am_offs(irn, get_ia32_am_offs(load)); - set_ia32_am_scale(irn, get_ia32_am_scale(load)); - set_ia32_am_flavour(irn, get_ia32_am_flavour(load)); - set_ia32_op_type(irn, ia32_AddrModeD); - set_ia32_frame_ent(irn, get_ia32_frame_ent(load)); - set_ia32_ls_mode(irn, get_ia32_ls_mode(load)); - - set_ia32_am_sc(irn, get_ia32_am_sc(load)); - if (is_ia32_am_sc_sign(load)) - set_ia32_am_sc_sign(irn); - - if (is_ia32_use_frame(load)) - set_ia32_use_frame(irn); - - /* connect to Load memory and disconnect Load */ - if (get_irn_arity(irn) == 5) { - /* binary AMop */ - set_irn_n(irn, 4, get_irn_n(load, 2)); - set_irn_n(irn, 2, noreg_gp); - } - else { - /* unary AMop */ - set_irn_n(irn, 3, get_irn_n(load, 2)); - set_irn_n(irn, 2, noreg_gp); - } - - /* connect the memory Proj of the Store to the op */ - mem_proj = ia32_get_proj_for_mode(store, mode_M); - set_Proj_pred(mem_proj, irn); - set_Proj_proj(mem_proj, 1); - - /* clear remat flag */ - set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable); - - try_remove_from_sched(load); - try_remove_from_sched(store); - DBG_OPT_AM_D(load, store, irn); - - DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store)); - - need_exchange_on_fail = 0; - } - } /* if (store) */ - else if (get_ia32_am_support(irn) & ia32_am_Source) { - /* There was no store, check if we still can optimize for source address mode */ - check_am_src = 1; + if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) { + /* change the load if it has only 1 user */ + if(get_irn_n_edges(pred) == 1) { + ir_mode *newmode; + if(get_mode_sign(conv_mode)) { + newmode = find_signed_mode(load_mode); + } else { + newmode = find_unsigned_mode(load_mode); } - } /* if (support AM Dest) */ - else if (get_ia32_am_support(irn) & ia32_am_Source) { - /* op doesn't support am AM Dest -> check for AM Source */ - check_am_src = 1; - } - - /* was exchanged but optimize failed: exchange back */ - if (need_exchange_on_fail) { - exchange_left_right(irn, &left, &right, 3, 2); - cand = orig_cand; + assert(newmode != NULL); + set_ia32_ls_mode(predpred, newmode); + } else { + /* otherwise we have to keep the conv */ + return; } + } - need_exchange_on_fail = 0; + /* kill the conv */ + exchange(node, pred); +} - /* normalize commutative ops */ - if (check_am_src && node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_LEFT)) { +static void optimize_conv_conv(ir_node *node) +{ + ir_node *pred_proj, *pred, *result_conv; + ir_mode *pred_mode, *conv_mode; + int conv_mode_bits; + int pred_mode_bits; - /* Assure that right operand is always a Load if there is one */ - /* because non-commutative ops can only use Source AM if the */ - /* right operand is a Load, so we only need to check the right */ - /* operand afterwards. */ + if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node)) + return; - exchange_left_right(irn, &left, &right, 3, 2); - need_exchange_on_fail = 1; + assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val); + pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val); + if(is_Proj(pred_proj)) + pred = get_Proj_pred(pred_proj); + else + pred = pred_proj; - /* now: load is left */ - cand = IA32_AM_CAND_RIGHT; - } + if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred)) + return; - /* optimize op -> Load iff Load is only used by this op */ - /* and right operand is a Load which only used by this irn */ - if (check_am_src && - (cand & IA32_AM_CAND_RIGHT) && - (get_irn_arity(irn) == 5) && - (ia32_get_irn_n_edges(right) == 1)) - { - right = get_Proj_pred(right); - - addr_b = get_irn_n(right, 0); - addr_i = get_irn_n(right, 1); - - /* set new base, index and attributes */ - set_irn_n(irn, 0, addr_b); - set_irn_n(irn, 1, addr_i); - add_ia32_am_offs(irn, get_ia32_am_offs(right)); - set_ia32_am_scale(irn, get_ia32_am_scale(right)); - set_ia32_am_flavour(irn, get_ia32_am_flavour(right)); - set_ia32_op_type(irn, ia32_AddrModeS); - set_ia32_frame_ent(irn, get_ia32_frame_ent(right)); - set_ia32_ls_mode(irn, get_ia32_ls_mode(right)); - - set_ia32_am_sc(irn, get_ia32_am_sc(right)); - if (is_ia32_am_sc_sign(right)) - set_ia32_am_sc_sign(irn); - - /* clear remat flag */ - set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable); - - if (is_ia32_use_frame(right)) - set_ia32_use_frame(irn); - - /* connect to Load memory */ - set_irn_n(irn, 4, get_irn_n(right, 2)); - - /* this is only needed for Compares, but currently ALL nodes - * have this attribute :-) */ - set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn))); - - /* disconnect from Load */ - set_irn_n(irn, 3, noreg_gp); - - DBG_OPT_AM_S(right, irn); - - /* If Load has a memory Proj, connect it to the op */ - mem_proj = ia32_get_proj_for_mode(right, mode_M); - if (mem_proj) { - set_Proj_pred(mem_proj, irn); - set_Proj_proj(mem_proj, 1); + /* we know that after a conv, the upper bits are sign extended + * so we only need the 2nd conv if it shrinks the mode */ + conv_mode = get_ia32_ls_mode(node); + conv_mode_bits = get_mode_size_bits(conv_mode); + pred_mode = get_ia32_ls_mode(pred); + pred_mode_bits = get_mode_size_bits(pred_mode); + + if(conv_mode_bits == pred_mode_bits + && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) { + result_conv = pred_proj; + } else if(conv_mode_bits <= pred_mode_bits) { + /* if 2nd conv is smaller then first conv, then we can always take the + * 2nd conv */ + if(get_irn_n_edges(pred_proj) == 1) { + result_conv = pred_proj; + set_ia32_ls_mode(pred, conv_mode); + + /* Argh:We must change the opcode to 8bit AND copy the register constraints */ + if (get_mode_size_bits(conv_mode) == 8) { + set_irn_op(pred, op_ia32_Conv_I2I8Bit); + set_ia32_in_req_all(pred, get_ia32_in_req_all(node)); + } + } else { + /* we don't want to end up with 2 loads, so we better do nothing */ + if(get_irn_mode(pred) == mode_T) { + return; } - try_remove_from_sched(right); + result_conv = exact_copy(pred); + set_ia32_ls_mode(result_conv, conv_mode); - DB((mod, LEVEL_1, "merged with %+F into source AM\n", right)); + /* Argh:We must change the opcode to 8bit AND copy the register constraints */ + if (get_mode_size_bits(conv_mode) == 8) { + set_irn_op(result_conv, op_ia32_Conv_I2I8Bit); + set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node)); + } } - else { - /* was exchanged but optimize failed: exchange back */ - if (need_exchange_on_fail) - exchange_left_right(irn, &left, &right, 3, 2); + } else { + /* if both convs have the same sign, then we can take the smaller one */ + if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) { + result_conv = pred_proj; + } else { + /* no optimisation possible if smaller conv is sign-extend */ + if(mode_is_signed(pred_mode)) { + return; + } + /* we can take the smaller conv if it is unsigned */ + result_conv = pred_proj; } } -} - -/** - * Performs address mode optimization. - */ -void ia32_optimize_addressmode(ia32_code_gen_t *cg) { - /* if we are supposed to do AM or LEA optimization: recalculate edges */ - if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) { - edges_deactivate(cg->irg); - edges_activate(cg->irg); - } - else { - /* no optimizations at all */ - return; - } - /* beware: we cannot optimize LEA and AM in one run because */ - /* LEA optimization adds new nodes to the irg which */ - /* invalidates the phase data */ + /* kill the conv */ + exchange(node, result_conv); - if (cg->opt & IA32_OPT_LEA) { - irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg); + if(get_irn_n_edges(pred_proj) == 0) { + be_kill_node(pred_proj); + if(pred != pred_proj) + be_kill_node(pred); } + optimize_conv_conv(result_conv); +} - if (cg->dump) - be_dump(cg->irg, "-lea", dump_ir_block_graph_sched); +static void optimize_node(ir_node *node, void *env) +{ + (void) env; - if (cg->opt & IA32_OPT_DOAM) { - /* we need height information for am optimization */ - heights_t *h = heights_new(cg->irg); - ia32_am_opt_env_t env; + optimize_load_conv(node); + optimize_conv_store(node); + optimize_conv_conv(node); +} - env.cg = cg; - env.h = h; +/** + * Performs conv and address mode optimization. + */ +void ia32_optimize_graph(ia32_code_gen_t *cg) +{ + irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg); - irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env); + if (cg->dump) + be_dump(cg->irg, "-opt", dump_ir_block_graph_sched); +} - heights_free(h); - } +void ia32_init_optimize(void) +{ + FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize"); }