X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=73ff3ba4ef4327a5bf697c9ac60d5f801dbdede8;hb=87fea9e1e34fcdd7b43ab60cb03b08c716f69571;hp=fcf1e85e336040d2b567d8d56c6785ac940a8245;hpb=4f67f5ba5f49cab46c94b121041ada16c240e7d0;p=libfirm diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c index fcf1e85e3..73ff3ba4e 100644 --- a/ir/be/ia32/ia32_optimize.c +++ b/ir/be/ia32/ia32_optimize.c @@ -61,8 +61,6 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) static const arch_env_t *arch_env; static ia32_code_gen_t *cg; -static void peephole_IncSP_IncSP(ir_node *node); - #if 0 static void peephole_ia32_Store_IncSP_to_push(ir_node *node) { @@ -95,7 +93,7 @@ static void peephole_ia32_Store_IncSP_to_push(ir_node *node) if(!be_is_IncSP(incsp)) return; - peephole_IncSP_IncSP(incsp); + be_peephole_IncSP_IncSP(incsp); /* must be in the same block */ if(get_nodes_block(incsp) != get_nodes_block(node)) @@ -303,7 +301,7 @@ static void peephole_ia32_Test(ir_node *node) * Can be avoided by placing a Rep prefix before the return. */ static void peephole_ia32_Return(ir_node *node) { - ir_node *block, *irn, *rep; + ir_node *block, *irn; if (!ia32_cg_config.use_pad_return) return; @@ -326,7 +324,7 @@ static void peephole_ia32_Return(ir_node *node) { /* check if this return is the first on the block */ sched_foreach_reverse_from(node, irn) { - switch (be_get_irn_opcode(irn)) { + switch (get_irn_opcode(irn)) { case beo_Return: /* the return node itself, ignore */ continue; @@ -338,18 +336,20 @@ static void peephole_ia32_Return(ir_node *node) { if (be_get_IncSP_offset(irn) == 0) continue; return; + case iro_Phi: + continue; default: - if (is_Phi(irn)) - continue; return; } } /* yep, return is the first real instruction in this block */ #if 0 - /* add an rep prefix to the return */ - rep = new_rd_ia32_RepPrefix(get_irn_dbg_info(node), current_ir_graph, block); - keep_alive(rep); - sched_add_before(node, rep); + { + /* add an rep prefix to the return */ + ir_node *rep = new_rd_ia32_RepPrefix(get_irn_dbg_info(node), current_ir_graph, block); + keep_alive(rep); + sched_add_before(node, rep); + } #else /* ensure, that the 3 byte return is generated */ be_Return_set_emit_pop(node, 1); @@ -476,91 +476,111 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) } /** - * Tries to optimize two following IncSP. + * Find a free GP register if possible, else return NULL. */ -static void peephole_IncSP_IncSP(ir_node *node) +static const arch_register_t *get_free_gp_reg(void) { - int pred_offs; - int curr_offs; - int offs; - ir_node *pred = be_get_IncSP_pred(node); - ir_node *predpred; + int i; - if(!be_is_IncSP(pred)) - return; + for(i = 0; i < N_ia32_gp_REGS; ++i) { + const arch_register_t *reg = &ia32_gp_regs[i]; + if(arch_register_type_is(reg, ignore)) + continue; - if(get_irn_n_edges(pred) > 1) - return; + if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL) + return &ia32_gp_regs[i]; + } - pred_offs = be_get_IncSP_offset(pred); - curr_offs = be_get_IncSP_offset(node); + return NULL; +} - if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) { - if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) { - return; - } - offs = 0; - } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) { - if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) { - return; - } - offs = 0; - } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND - || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) { - return; - } else { - offs = curr_offs + pred_offs; - } +/** + * Creates a Pop instruction before the given schedule point. + * + * @param dbgi debug info + * @param irg the graph + * @param block the block + * @param stack the previous stack value + * @param schedpoint the new node is added before this node + * @param reg the register to pop + * + * @return the new stack value + */ +static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block, + ir_node *stack, ir_node *schedpoint, + const arch_register_t *reg) +{ + const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + ir_node *pop; + ir_node *keep; + ir_node *val; + ir_node *in[1]; - /* add pred offset to ours and remove pred IncSP */ - be_set_IncSP_offset(node, offs); + pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack); - predpred = be_get_IncSP_pred(pred); - be_peephole_before_exchange(pred, predpred); + stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack); + arch_set_irn_register(arch_env, stack, esp); + val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res); + arch_set_irn_register(arch_env, val, reg); - /* rewire dependency edges */ - edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph); - be_set_IncSP_pred(node, predpred); - sched_remove(pred); - be_kill_node(pred); + sched_add_before(schedpoint, pop); - be_peephole_after_exchange(predpred); + in[0] = val; + keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in); + sched_add_before(schedpoint, keep); + + return stack; } /** - * Find a free GP register if possible, else return NULL. + * Creates a Push instruction before the given schedule point. + * + * @param dbgi debug info + * @param irg the graph + * @param block the block + * @param stack the previous stack value + * @param schedpoint the new node is added before this node + * @param reg the register to pop + * + * @return the new stack value */ -static const arch_register_t *get_free_gp_reg(void) +static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block, + ir_node *stack, ir_node *schedpoint, + const arch_register_t *reg) { - int i; + const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + ir_node *noreg, *nomem, *push, *val; - for(i = 0; i < N_ia32_gp_REGS; ++i) { - const arch_register_t *reg = &ia32_gp_regs[i]; - if(arch_register_type_is(reg, ignore)) - continue; + val = new_rd_ia32_ProduceVal(NULL, irg, block); + arch_set_irn_register(arch_env, val, reg); + sched_add_before(schedpoint, val); - if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL) - return &ia32_gp_regs[i]; - } + noreg = ia32_new_NoReg_gp(cg); + nomem = get_irg_no_mem(irg); + push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack); + sched_add_before(schedpoint, push); - return NULL; + stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack); + arch_set_irn_register(arch_env, stack, esp); + + return stack; } +/** + * Optimize an IncSp by replacing it with push/pop + */ static void peephole_be_IncSP(ir_node *node) { const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; const arch_register_t *reg; - ir_graph *irg; + ir_graph *irg = current_ir_graph; dbg_info *dbgi; ir_node *block; - ir_node *keep; - ir_node *val; - ir_node *pop, *pop2; ir_node *stack; int offset; /* first optimize incsp->incsp combinations */ - peephole_IncSP_IncSP(node); + be_peephole_IncSP_IncSP(node); /* transform IncSP->Store combinations to Push where possible */ peephole_IncSP_Store_to_push(node); @@ -570,55 +590,38 @@ static void peephole_be_IncSP(ir_node *node) /* replace IncSP -4 by Pop freereg when possible */ offset = be_get_IncSP_offset(node); - if ((offset != -8 || !ia32_cg_config.use_add_esp_8) && - (offset != -4 || !ia32_cg_config.use_add_esp_4) && - (offset != +4 || !ia32_cg_config.use_sub_esp_4) && - (offset != +8 || !ia32_cg_config.use_sub_esp_8)) + if ((offset != -8 || ia32_cg_config.use_add_esp_8) && + (offset != -4 || ia32_cg_config.use_add_esp_4) && + (offset != +4 || ia32_cg_config.use_sub_esp_4) && + (offset != +8 || ia32_cg_config.use_sub_esp_8)) return; if (offset < 0) { /* we need a free register for pop */ reg = get_free_gp_reg(); - if(reg == NULL) + if (reg == NULL) return; - irg = current_ir_graph; dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); stack = be_get_IncSP_pred(node); - pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack); - - stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack); - arch_set_irn_register(arch_env, stack, esp); - val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res); - arch_set_irn_register(arch_env, val, reg); - sched_add_before(node, pop); - - keep = sched_next(node); - if (!be_is_Keep(keep)) { - ir_node *in[1]; - in[0] = val; - keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in); - sched_add_before(node, keep); - } else { - be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val); - } + stack = create_pop(dbgi, irg, block, stack, node, reg); if (offset == -8) { - pop2 = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack); + stack = create_pop(dbgi, irg, block, stack, node, reg); + } + } else { + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + stack = be_get_IncSP_pred(node); + reg = &ia32_gp_regs[REG_EAX]; - stack = new_r_Proj(irg, block, pop2, mode_Iu, pn_ia32_Pop_stack); - arch_set_irn_register(arch_env, stack, esp); - val = new_r_Proj(irg, block, pop2, mode_Iu, pn_ia32_Pop_res); - arch_set_irn_register(arch_env, val, reg); + stack = create_push(dbgi, irg, block, stack, node, reg); - sched_add_after(pop, pop2); - be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val); + if (offset == +8) { + stack = create_push(dbgi, irg, block, stack, node, reg); } - } else { - /* NIY */ - return; } be_peephole_before_exchange(node, stack); @@ -938,6 +941,13 @@ static void peephole_ia32_Imul_split(ir_node *imul) { set_ia32_op_type(imul, ia32_Normal); } +/** + * Replace xorps r,r and xorpd r,r by pxor r,r + */ +static void peephole_ia32_xZero(ir_node *xor) { + set_irn_op(xor, op_ia32_xPzero); +} + /** * Register a peephole optimisation function. */ @@ -963,6 +973,8 @@ void ia32_peephole_optimization(ia32_code_gen_t *new_cg) register_peephole_optimisation(op_be_Return, peephole_ia32_Return); if (! ia32_cg_config.use_imul_mem_imm32) register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split); + if (ia32_cg_config.use_pxor) + register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero); be_peephole_opt(cg->birg); }